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dmaengine: replace dma_async_client_register with dmaengine_get
[mirror_ubuntu-artful-kernel.git] / drivers / dma / mv_xor.c
CommitLineData
ff7b0479
SB		 1/*
2 * offload engine driver for the Marvell XOR engine
3 * Copyright (C) 2007, 2008, Marvell International Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
ff7b0479
SB		 21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
23#include <linux/spinlock.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
26#include <linux/memory.h>
6f088f1d 27#include <plat/mv_xor.h>
ff7b0479
SB		 28#include "mv_xor.h"
29
30static void mv_xor_issue_pending(struct dma_chan *chan);
31
32#define to_mv_xor_chan(chan) \
33 container_of(chan, struct mv_xor_chan, common)
34
35#define to_mv_xor_device(dev) \
36 container_of(dev, struct mv_xor_device, common)
37
38#define to_mv_xor_slot(tx) \
39 container_of(tx, struct mv_xor_desc_slot, async_tx)
40
41static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags)
42{
43 struct mv_xor_desc *hw_desc = desc->hw_desc;
44
45 hw_desc->status = (1 << 31);
46 hw_desc->phy_next_desc = 0;
47 hw_desc->desc_command = (1 << 31);
48}
49
50static u32 mv_desc_get_dest_addr(struct mv_xor_desc_slot *desc)
51{
52 struct mv_xor_desc *hw_desc = desc->hw_desc;
53 return hw_desc->phy_dest_addr;
54}
55
56static u32 mv_desc_get_src_addr(struct mv_xor_desc_slot *desc,
57 int src_idx)
58{
59 struct mv_xor_desc *hw_desc = desc->hw_desc;
60 return hw_desc->phy_src_addr[src_idx];
61}
62
63
64static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc,
65 u32 byte_count)
66{
67 struct mv_xor_desc *hw_desc = desc->hw_desc;
68 hw_desc->byte_count = byte_count;
69}
70
71static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
72 u32 next_desc_addr)
73{
74 struct mv_xor_desc *hw_desc = desc->hw_desc;
75 BUG_ON(hw_desc->phy_next_desc);
76 hw_desc->phy_next_desc = next_desc_addr;
77}
78
79static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc)
80{
81 struct mv_xor_desc *hw_desc = desc->hw_desc;
82 hw_desc->phy_next_desc = 0;
83}
84
85static void mv_desc_set_block_fill_val(struct mv_xor_desc_slot *desc, u32 val)
86{
87 desc->value = val;
88}
89
90static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc,
91 dma_addr_t addr)
92{
93 struct mv_xor_desc *hw_desc = desc->hw_desc;
94 hw_desc->phy_dest_addr = addr;
95}
96
97static int mv_chan_memset_slot_count(size_t len)
98{
99 return 1;
100}
101
102#define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
103
104static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
105 int index, dma_addr_t addr)
106{
107 struct mv_xor_desc *hw_desc = desc->hw_desc;
108 hw_desc->phy_src_addr[index] = addr;
109 if (desc->type == DMA_XOR)
110 hw_desc->desc_command |= (1 << index);
111}
112
113static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
114{
115 return __raw_readl(XOR_CURR_DESC(chan));
116}
117
118static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
119 u32 next_desc_addr)
120{
121 __raw_writel(next_desc_addr, XOR_NEXT_DESC(chan));
122}
123
124static void mv_chan_set_dest_pointer(struct mv_xor_chan *chan, u32 desc_addr)
125{
126 __raw_writel(desc_addr, XOR_DEST_POINTER(chan));
127}
128
129static void mv_chan_set_block_size(struct mv_xor_chan *chan, u32 block_size)
130{
131 __raw_writel(block_size, XOR_BLOCK_SIZE(chan));
132}
133
134static void mv_chan_set_value(struct mv_xor_chan *chan, u32 value)
135{
136 __raw_writel(value, XOR_INIT_VALUE_LOW(chan));
137 __raw_writel(value, XOR_INIT_VALUE_HIGH(chan));
138}
139
140static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
141{
142 u32 val = __raw_readl(XOR_INTR_MASK(chan));
143 val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
144 __raw_writel(val, XOR_INTR_MASK(chan));
145}
146
147static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
148{
149 u32 intr_cause = __raw_readl(XOR_INTR_CAUSE(chan));
150 intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
151 return intr_cause;
152}
153
154static int mv_is_err_intr(u32 intr_cause)
155{
156 if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
157 return 1;
158
159 return 0;
160}
161
162static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
163{
164 u32 val = (1 << (1 + (chan->idx * 16)));
165 dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val);
166 __raw_writel(val, XOR_INTR_CAUSE(chan));
167}
168
169static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan)
170{
171 u32 val = 0xFFFF0000 >> (chan->idx * 16);
172 __raw_writel(val, XOR_INTR_CAUSE(chan));
173}
174
175static int mv_can_chain(struct mv_xor_desc_slot *desc)
176{
177 struct mv_xor_desc_slot *chain_old_tail = list_entry(
178 desc->chain_node.prev, struct mv_xor_desc_slot, chain_node);
179
180 if (chain_old_tail->type != desc->type)
181 return 0;
182 if (desc->type == DMA_MEMSET)
183 return 0;
184
185 return 1;
186}
187
188static void mv_set_mode(struct mv_xor_chan *chan,
189 enum dma_transaction_type type)
190{
191 u32 op_mode;
192 u32 config = __raw_readl(XOR_CONFIG(chan));
193
194 switch (type) {
195 case DMA_XOR:
196 op_mode = XOR_OPERATION_MODE_XOR;
197 break;
198 case DMA_MEMCPY:
199 op_mode = XOR_OPERATION_MODE_MEMCPY;
200 break;
201 case DMA_MEMSET:
202 op_mode = XOR_OPERATION_MODE_MEMSET;
203 break;
204 default:
205 dev_printk(KERN_ERR, chan->device->common.dev,
206 "error: unsupported operation %d.\n",
207 type);
208 BUG();
209 return;
210 }
211
212 config &= ~0x7;
213 config |= op_mode;
214 __raw_writel(config, XOR_CONFIG(chan));
215 chan->current_type = type;
216}
217
218static void mv_chan_activate(struct mv_xor_chan *chan)
219{
220 u32 activation;
221
222 dev_dbg(chan->device->common.dev, " activate chan.\n");
223 activation = __raw_readl(XOR_ACTIVATION(chan));
224 activation |= 0x1;
225 __raw_writel(activation, XOR_ACTIVATION(chan));
226}
227
228static char mv_chan_is_busy(struct mv_xor_chan *chan)
229{
230 u32 state = __raw_readl(XOR_ACTIVATION(chan));
231
232 state = (state >> 4) & 0x3;
233
234 return (state == 1) ? 1 : 0;
235}
236
237static int mv_chan_xor_slot_count(size_t len, int src_cnt)
238{
239 return 1;
240}
241
242/**
243 * mv_xor_free_slots - flags descriptor slots for reuse
244 * @slot: Slot to free
245 * Caller must hold &mv_chan->lock while calling this function
246 */
247static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
248 struct mv_xor_desc_slot *slot)
249{
250 dev_dbg(mv_chan->device->common.dev, "%s %d slot %p\n",
251 __func__, __LINE__, slot);
252
253 slot->slots_per_op = 0;
254
255}
256
257/*
258 * mv_xor_start_new_chain - program the engine to operate on new chain headed by
259 * sw_desc
260 * Caller must hold &mv_chan->lock while calling this function
261 */
262static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
263 struct mv_xor_desc_slot *sw_desc)
264{
265 dev_dbg(mv_chan->device->common.dev, "%s %d: sw_desc %p\n",
266 __func__, __LINE__, sw_desc);
267 if (sw_desc->type != mv_chan->current_type)
268 mv_set_mode(mv_chan, sw_desc->type);
269
270 if (sw_desc->type == DMA_MEMSET) {
271 /* for memset requests we need to program the engine, no
272 * descriptors used.
273 */
274 struct mv_xor_desc *hw_desc = sw_desc->hw_desc;
275 mv_chan_set_dest_pointer(mv_chan, hw_desc->phy_dest_addr);
276 mv_chan_set_block_size(mv_chan, sw_desc->unmap_len);
277 mv_chan_set_value(mv_chan, sw_desc->value);
278 } else {
279 /* set the hardware chain */
280 mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
281 }
282 mv_chan->pending += sw_desc->slot_cnt;
283 mv_xor_issue_pending(&mv_chan->common);
284}
285
286static dma_cookie_t
287mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
288 struct mv_xor_chan *mv_chan, dma_cookie_t cookie)
289{
290 BUG_ON(desc->async_tx.cookie < 0);
291
292 if (desc->async_tx.cookie > 0) {
293 cookie = desc->async_tx.cookie;
294
295 /* call the callback (must not sleep or submit new
296 * operations to this channel)
297 */
298 if (desc->async_tx.callback)
299 desc->async_tx.callback(
300 desc->async_tx.callback_param);
301
302 /* unmap dma addresses
303 * (unmap_single vs unmap_page?)
304 */
305 if (desc->group_head && desc->unmap_len) {
306 struct mv_xor_desc_slot *unmap = desc->group_head;
307 struct device *dev =
308 &mv_chan->device->pdev->dev;
309 u32 len = unmap->unmap_len;
e1d181ef
DW		 310 enum dma_ctrl_flags flags = desc->async_tx.flags;
311 u32 src_cnt;
312 dma_addr_t addr;
a06d568f 313 dma_addr_t dest;
ff7b0479 314
a06d568f
DW		 315 src_cnt = unmap->unmap_src_cnt;
316 dest = mv_desc_get_dest_addr(unmap);
e1d181ef 317 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
a06d568f
DW		 318 enum dma_data_direction dir;
319
320 if (src_cnt > 1) /* is xor ? */
321 dir = DMA_BIDIRECTIONAL;
322 else
323 dir = DMA_FROM_DEVICE;
324 dma_unmap_page(dev, dest, len, dir);
e1d181ef
DW		 325 }
326
327 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
e1d181ef
DW		 328 while (src_cnt--) {
329 addr = mv_desc_get_src_addr(unmap,
330 src_cnt);
a06d568f
DW		 331 if (addr == dest)
332 continue;
e1d181ef
DW		 333 dma_unmap_page(dev, addr, len,
334 DMA_TO_DEVICE);
335 }
ff7b0479
SB		 336 }
337 desc->group_head = NULL;
338 }
339 }
340
341 /* run dependent operations */
07f2211e 342 dma_run_dependencies(&desc->async_tx);
ff7b0479
SB		 343
344 return cookie;
345}
346
347static int
348mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan)
349{
350 struct mv_xor_desc_slot *iter, *_iter;
351
352 dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
353 list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
354 completed_node) {
355
356 if (async_tx_test_ack(&iter->async_tx)) {
357 list_del(&iter->completed_node);
358 mv_xor_free_slots(mv_chan, iter);
359 }
360 }
361 return 0;
362}
363
364static int
365mv_xor_clean_slot(struct mv_xor_desc_slot *desc,
366 struct mv_xor_chan *mv_chan)
367{
368 dev_dbg(mv_chan->device->common.dev, "%s %d: desc %p flags %d\n",
369 __func__, __LINE__, desc, desc->async_tx.flags);
370 list_del(&desc->chain_node);
371 /* the client is allowed to attach dependent operations
372 * until 'ack' is set
373 */
374 if (!async_tx_test_ack(&desc->async_tx)) {
375 /* move this slot to the completed_slots */
376 list_add_tail(&desc->completed_node, &mv_chan->completed_slots);
377 return 0;
378 }
379
380 mv_xor_free_slots(mv_chan, desc);
381 return 0;
382}
383
384static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
385{
386 struct mv_xor_desc_slot *iter, *_iter;
387 dma_cookie_t cookie = 0;
388 int busy = mv_chan_is_busy(mv_chan);
389 u32 current_desc = mv_chan_get_current_desc(mv_chan);
390 int seen_current = 0;
391
392 dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
393 dev_dbg(mv_chan->device->common.dev, "current_desc %x\n", current_desc);
394 mv_xor_clean_completed_slots(mv_chan);
395
396 /* free completed slots from the chain starting with
397 * the oldest descriptor
398 */
399
400 list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
401 chain_node) {
402 prefetch(_iter);
403 prefetch(&_iter->async_tx);
404
405 /* do not advance past the current descriptor loaded into the
406 * hardware channel, subsequent descriptors are either in
407 * process or have not been submitted
408 */
409 if (seen_current)
410 break;
411
412 /* stop the search if we reach the current descriptor and the
413 * channel is busy
414 */
415 if (iter->async_tx.phys == current_desc) {
416 seen_current = 1;
417 if (busy)
418 break;
419 }
420
421 cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie);
422
423 if (mv_xor_clean_slot(iter, mv_chan))
424 break;
425 }
426
427 if ((busy == 0) && !list_empty(&mv_chan->chain)) {
428 struct mv_xor_desc_slot *chain_head;
429 chain_head = list_entry(mv_chan->chain.next,
430 struct mv_xor_desc_slot,
431 chain_node);
432
433 mv_xor_start_new_chain(mv_chan, chain_head);
434 }
435
436 if (cookie > 0)
437 mv_chan->completed_cookie = cookie;
438}
439
440static void
441mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
442{
443 spin_lock_bh(&mv_chan->lock);
444 __mv_xor_slot_cleanup(mv_chan);
445 spin_unlock_bh(&mv_chan->lock);
446}
447
448static void mv_xor_tasklet(unsigned long data)
449{
450 struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
451 __mv_xor_slot_cleanup(chan);
452}
453
454static struct mv_xor_desc_slot *
455mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
456 int slots_per_op)
457{
458 struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL;
459 LIST_HEAD(chain);
460 int slots_found, retry = 0;
461
462 /* start search from the last allocated descrtiptor
463 * if a contiguous allocation can not be found start searching
464 * from the beginning of the list
465 */
466retry:
467 slots_found = 0;
468 if (retry == 0)
469 iter = mv_chan->last_used;
470 else
471 iter = list_entry(&mv_chan->all_slots,
472 struct mv_xor_desc_slot,
473 slot_node);
474
475 list_for_each_entry_safe_continue(
476 iter, _iter, &mv_chan->all_slots, slot_node) {
477 prefetch(_iter);
478 prefetch(&_iter->async_tx);
479 if (iter->slots_per_op) {
480 /* give up after finding the first busy slot
481 * on the second pass through the list
482 */
483 if (retry)
484 break;
485
486 slots_found = 0;
487 continue;
488 }
489
490 /* start the allocation if the slot is correctly aligned */
491 if (!slots_found++)
492 alloc_start = iter;
493
494 if (slots_found == num_slots) {
495 struct mv_xor_desc_slot *alloc_tail = NULL;
496 struct mv_xor_desc_slot *last_used = NULL;
497 iter = alloc_start;
498 while (num_slots) {
499 int i;
500
501 /* pre-ack all but the last descriptor */
502 async_tx_ack(&iter->async_tx);
503
504 list_add_tail(&iter->chain_node, &chain);
505 alloc_tail = iter;
506 iter->async_tx.cookie = 0;
507 iter->slot_cnt = num_slots;
508 iter->xor_check_result = NULL;
509 for (i = 0; i < slots_per_op; i++) {
510 iter->slots_per_op = slots_per_op - i;
511 last_used = iter;
512 iter = list_entry(iter->slot_node.next,
513 struct mv_xor_desc_slot,
514 slot_node);
515 }
516 num_slots -= slots_per_op;
517 }
518 alloc_tail->group_head = alloc_start;
519 alloc_tail->async_tx.cookie = -EBUSY;
520 list_splice(&chain, &alloc_tail->async_tx.tx_list);
521 mv_chan->last_used = last_used;
522 mv_desc_clear_next_desc(alloc_start);
523 mv_desc_clear_next_desc(alloc_tail);
524 return alloc_tail;
525 }
526 }
527 if (!retry++)
528 goto retry;
529
530 /* try to free some slots if the allocation fails */
531 tasklet_schedule(&mv_chan->irq_tasklet);
532
533 return NULL;
534}
535
536static dma_cookie_t
537mv_desc_assign_cookie(struct mv_xor_chan *mv_chan,
538 struct mv_xor_desc_slot *desc)
539{
540 dma_cookie_t cookie = mv_chan->common.cookie;
541
542 if (++cookie < 0)
543 cookie = 1;
544 mv_chan->common.cookie = desc->async_tx.cookie = cookie;
545 return cookie;
546}
547
548/************************ DMA engine API functions ****************************/
549static dma_cookie_t
550mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
551{
552 struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
553 struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
554 struct mv_xor_desc_slot *grp_start, *old_chain_tail;
555 dma_cookie_t cookie;
556 int new_hw_chain = 1;
557
558 dev_dbg(mv_chan->device->common.dev,
559 "%s sw_desc %p: async_tx %p\n",
560 __func__, sw_desc, &sw_desc->async_tx);
561
562 grp_start = sw_desc->group_head;
563
564 spin_lock_bh(&mv_chan->lock);
565 cookie = mv_desc_assign_cookie(mv_chan, sw_desc);
566
567 if (list_empty(&mv_chan->chain))
568 list_splice_init(&sw_desc->async_tx.tx_list, &mv_chan->chain);
569 else {
570 new_hw_chain = 0;
571
572 old_chain_tail = list_entry(mv_chan->chain.prev,
573 struct mv_xor_desc_slot,
574 chain_node);
575 list_splice_init(&grp_start->async_tx.tx_list,
576 &old_chain_tail->chain_node);
577
578 if (!mv_can_chain(grp_start))
579 goto submit_done;
580
581 dev_dbg(mv_chan->device->common.dev, "Append to last desc %x\n",
582 old_chain_tail->async_tx.phys);
583
584 /* fix up the hardware chain */
585 mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
586
587 /* if the channel is not busy */
588 if (!mv_chan_is_busy(mv_chan)) {
589 u32 current_desc = mv_chan_get_current_desc(mv_chan);
590 /*
591 * and the curren desc is the end of the chain before
592 * the append, then we need to start the channel
593 */
594 if (current_desc == old_chain_tail->async_tx.phys)
595 new_hw_chain = 1;
596 }
597 }
598
599 if (new_hw_chain)
600 mv_xor_start_new_chain(mv_chan, grp_start);
601
602submit_done:
603 spin_unlock_bh(&mv_chan->lock);
604
605 return cookie;
606}
607
608/* returns the number of allocated descriptors */
848c536a
HS		 609static int mv_xor_alloc_chan_resources(struct dma_chan *chan,
610 struct dma_client *client)
ff7b0479
SB		 611{
612 char *hw_desc;
613 int idx;
614 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
615 struct mv_xor_desc_slot *slot = NULL;
616 struct mv_xor_platform_data *plat_data =
617 mv_chan->device->pdev->dev.platform_data;
618 int num_descs_in_pool = plat_data->pool_size/MV_XOR_SLOT_SIZE;
619
620 /* Allocate descriptor slots */
621 idx = mv_chan->slots_allocated;
622 while (idx < num_descs_in_pool) {
623 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
624 if (!slot) {
625 printk(KERN_INFO "MV XOR Channel only initialized"
626 " %d descriptor slots", idx);
627 break;
628 }
629 hw_desc = (char *) mv_chan->device->dma_desc_pool_virt;
630 slot->hw_desc = (void *) &hw_desc[idx * MV_XOR_SLOT_SIZE];
631
632 dma_async_tx_descriptor_init(&slot->async_tx, chan);
633 slot->async_tx.tx_submit = mv_xor_tx_submit;
634 INIT_LIST_HEAD(&slot->chain_node);
635 INIT_LIST_HEAD(&slot->slot_node);
636 INIT_LIST_HEAD(&slot->async_tx.tx_list);
637 hw_desc = (char *) mv_chan->device->dma_desc_pool;
638 slot->async_tx.phys =
639 (dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE];
640 slot->idx = idx++;
641
642 spin_lock_bh(&mv_chan->lock);
643 mv_chan->slots_allocated = idx;
644 list_add_tail(&slot->slot_node, &mv_chan->all_slots);
645 spin_unlock_bh(&mv_chan->lock);
646 }
647
648 if (mv_chan->slots_allocated && !mv_chan->last_used)
649 mv_chan->last_used = list_entry(mv_chan->all_slots.next,
650 struct mv_xor_desc_slot,
651 slot_node);
652
653 dev_dbg(mv_chan->device->common.dev,
654 "allocated %d descriptor slots last_used: %p\n",
655 mv_chan->slots_allocated, mv_chan->last_used);
656
657 return mv_chan->slots_allocated ? : -ENOMEM;
658}
659
660static struct dma_async_tx_descriptor *
661mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
662 size_t len, unsigned long flags)
663{
664 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
665 struct mv_xor_desc_slot *sw_desc, *grp_start;
666 int slot_cnt;
667
668 dev_dbg(mv_chan->device->common.dev,
669 "%s dest: %x src %x len: %u flags: %ld\n",
670 __func__, dest, src, len, flags);
671 if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
672 return NULL;
673
674 BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
675
676 spin_lock_bh(&mv_chan->lock);
677 slot_cnt = mv_chan_memcpy_slot_count(len);
678 sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
679 if (sw_desc) {
680 sw_desc->type = DMA_MEMCPY;
681 sw_desc->async_tx.flags = flags;
682 grp_start = sw_desc->group_head;
683 mv_desc_init(grp_start, flags);
684 mv_desc_set_byte_count(grp_start, len);
685 mv_desc_set_dest_addr(sw_desc->group_head, dest);
686 mv_desc_set_src_addr(grp_start, 0, src);
687 sw_desc->unmap_src_cnt = 1;
688 sw_desc->unmap_len = len;
689 }
690 spin_unlock_bh(&mv_chan->lock);
691
692 dev_dbg(mv_chan->device->common.dev,
693 "%s sw_desc %p async_tx %p\n",
694 __func__, sw_desc, sw_desc ? &sw_desc->async_tx : 0);
695
696 return sw_desc ? &sw_desc->async_tx : NULL;
697}
698
699static struct dma_async_tx_descriptor *
700mv_xor_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
701 size_t len, unsigned long flags)
702{
703 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
704 struct mv_xor_desc_slot *sw_desc, *grp_start;
705 int slot_cnt;
706
707 dev_dbg(mv_chan->device->common.dev,
708 "%s dest: %x len: %u flags: %ld\n",
709 __func__, dest, len, flags);
710 if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
711 return NULL;
712
713 BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
714
715 spin_lock_bh(&mv_chan->lock);
716 slot_cnt = mv_chan_memset_slot_count(len);
717 sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
718 if (sw_desc) {
719 sw_desc->type = DMA_MEMSET;
720 sw_desc->async_tx.flags = flags;
721 grp_start = sw_desc->group_head;
722 mv_desc_init(grp_start, flags);
723 mv_desc_set_byte_count(grp_start, len);
724 mv_desc_set_dest_addr(sw_desc->group_head, dest);
725 mv_desc_set_block_fill_val(grp_start, value);
726 sw_desc->unmap_src_cnt = 1;
727 sw_desc->unmap_len = len;
728 }
729 spin_unlock_bh(&mv_chan->lock);
730 dev_dbg(mv_chan->device->common.dev,
731 "%s sw_desc %p async_tx %p \n",
732 __func__, sw_desc, &sw_desc->async_tx);
733 return sw_desc ? &sw_desc->async_tx : NULL;
734}
735
736static struct dma_async_tx_descriptor *
737mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
738 unsigned int src_cnt, size_t len, unsigned long flags)
739{
740 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
741 struct mv_xor_desc_slot *sw_desc, *grp_start;
742 int slot_cnt;
743
744 if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
745 return NULL;
746
747 BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
748
749 dev_dbg(mv_chan->device->common.dev,
750 "%s src_cnt: %d len: dest %x %u flags: %ld\n",
751 __func__, src_cnt, len, dest, flags);
752
753 spin_lock_bh(&mv_chan->lock);
754 slot_cnt = mv_chan_xor_slot_count(len, src_cnt);
755 sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
756 if (sw_desc) {
757 sw_desc->type = DMA_XOR;
758 sw_desc->async_tx.flags = flags;
759 grp_start = sw_desc->group_head;
760 mv_desc_init(grp_start, flags);
761 /* the byte count field is the same as in memcpy desc*/
762 mv_desc_set_byte_count(grp_start, len);
763 mv_desc_set_dest_addr(sw_desc->group_head, dest);
764 sw_desc->unmap_src_cnt = src_cnt;
765 sw_desc->unmap_len = len;
766 while (src_cnt--)
767 mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]);
768 }
769 spin_unlock_bh(&mv_chan->lock);
770 dev_dbg(mv_chan->device->common.dev,
771 "%s sw_desc %p async_tx %p \n",
772 __func__, sw_desc, &sw_desc->async_tx);
773 return sw_desc ? &sw_desc->async_tx : NULL;
774}
775
776static void mv_xor_free_chan_resources(struct dma_chan *chan)
777{
778 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
779 struct mv_xor_desc_slot *iter, *_iter;
780 int in_use_descs = 0;
781
782 mv_xor_slot_cleanup(mv_chan);
783
784 spin_lock_bh(&mv_chan->lock);
785 list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
786 chain_node) {
787 in_use_descs++;
788 list_del(&iter->chain_node);
789 }
790 list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
791 completed_node) {
792 in_use_descs++;
793 list_del(&iter->completed_node);
794 }
795 list_for_each_entry_safe_reverse(
796 iter, _iter, &mv_chan->all_slots, slot_node) {
797 list_del(&iter->slot_node);
798 kfree(iter);
799 mv_chan->slots_allocated--;
800 }
801 mv_chan->last_used = NULL;
802
803 dev_dbg(mv_chan->device->common.dev, "%s slots_allocated %d\n",
804 __func__, mv_chan->slots_allocated);
805 spin_unlock_bh(&mv_chan->lock);
806
807 if (in_use_descs)
808 dev_err(mv_chan->device->common.dev,
809 "freeing %d in use descriptors!\n", in_use_descs);
810}
811
812/**
813 * mv_xor_is_complete - poll the status of an XOR transaction
814 * @chan: XOR channel handle
815 * @cookie: XOR transaction identifier
816 */
817static enum dma_status mv_xor_is_complete(struct dma_chan *chan,
818 dma_cookie_t cookie,
819 dma_cookie_t *done,
820 dma_cookie_t *used)
821{
822 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
823 dma_cookie_t last_used;
824 dma_cookie_t last_complete;
825 enum dma_status ret;
826
827 last_used = chan->cookie;
828 last_complete = mv_chan->completed_cookie;
829 mv_chan->is_complete_cookie = cookie;
830 if (done)
831 *done = last_complete;
832 if (used)
833 *used = last_used;
834
835 ret = dma_async_is_complete(cookie, last_complete, last_used);
836 if (ret == DMA_SUCCESS) {
837 mv_xor_clean_completed_slots(mv_chan);
838 return ret;
839 }
840 mv_xor_slot_cleanup(mv_chan);
841
842 last_used = chan->cookie;
843 last_complete = mv_chan->completed_cookie;
844
845 if (done)
846 *done = last_complete;
847 if (used)
848 *used = last_used;
849
850 return dma_async_is_complete(cookie, last_complete, last_used);
851}
852
853static void mv_dump_xor_regs(struct mv_xor_chan *chan)
854{
855 u32 val;
856
857 val = __raw_readl(XOR_CONFIG(chan));
858 dev_printk(KERN_ERR, chan->device->common.dev,
859 "config 0x%08x.\n", val);
860
861 val = __raw_readl(XOR_ACTIVATION(chan));
862 dev_printk(KERN_ERR, chan->device->common.dev,
863 "activation 0x%08x.\n", val);
864
865 val = __raw_readl(XOR_INTR_CAUSE(chan));
866 dev_printk(KERN_ERR, chan->device->common.dev,
867 "intr cause 0x%08x.\n", val);
868
869 val = __raw_readl(XOR_INTR_MASK(chan));
870 dev_printk(KERN_ERR, chan->device->common.dev,
871 "intr mask 0x%08x.\n", val);
872
873 val = __raw_readl(XOR_ERROR_CAUSE(chan));
874 dev_printk(KERN_ERR, chan->device->common.dev,
875 "error cause 0x%08x.\n", val);
876
877 val = __raw_readl(XOR_ERROR_ADDR(chan));
878 dev_printk(KERN_ERR, chan->device->common.dev,
879 "error addr 0x%08x.\n", val);
880}
881
882static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,
883 u32 intr_cause)
884{
885 if (intr_cause & (1 << 4)) {
886 dev_dbg(chan->device->common.dev,
887 "ignore this error\n");
888 return;
889 }
890
891 dev_printk(KERN_ERR, chan->device->common.dev,
892 "error on chan %d. intr cause 0x%08x.\n",
893 chan->idx, intr_cause);
894
895 mv_dump_xor_regs(chan);
896 BUG();
897}
898
899static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
900{
901 struct mv_xor_chan *chan = data;
902 u32 intr_cause = mv_chan_get_intr_cause(chan);
903
904 dev_dbg(chan->device->common.dev, "intr cause %x\n", intr_cause);
905
906 if (mv_is_err_intr(intr_cause))
907 mv_xor_err_interrupt_handler(chan, intr_cause);
908
909 tasklet_schedule(&chan->irq_tasklet);
910
911 mv_xor_device_clear_eoc_cause(chan);
912
913 return IRQ_HANDLED;
914}
915
916static void mv_xor_issue_pending(struct dma_chan *chan)
917{
918 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
919
920 if (mv_chan->pending >= MV_XOR_THRESHOLD) {
921 mv_chan->pending = 0;
922 mv_chan_activate(mv_chan);
923 }
924}
925
926/*
927 * Perform a transaction to verify the HW works.
928 */
929#define MV_XOR_TEST_SIZE 2000
930
931static int __devinit mv_xor_memcpy_self_test(struct mv_xor_device *device)
932{
933 int i;
934 void *src, *dest;
935 dma_addr_t src_dma, dest_dma;
936 struct dma_chan *dma_chan;
937 dma_cookie_t cookie;
938 struct dma_async_tx_descriptor *tx;
939 int err = 0;
940 struct mv_xor_chan *mv_chan;
941
942 src = kmalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
943 if (!src)
944 return -ENOMEM;
945
946 dest = kzalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
947 if (!dest) {
948 kfree(src);
949 return -ENOMEM;
950 }
951
952 /* Fill in src buffer */
953 for (i = 0; i < MV_XOR_TEST_SIZE; i++)
954 ((u8 *) src)[i] = (u8)i;
955
956 /* Start copy, using first DMA channel */
957 dma_chan = container_of(device->common.channels.next,
958 struct dma_chan,
959 device_node);
848c536a 960 if (mv_xor_alloc_chan_resources(dma_chan, NULL) < 1) {
ff7b0479
SB		 961 err = -ENODEV;
962 goto out;
963 }
964
965 dest_dma = dma_map_single(dma_chan->device->dev, dest,
966 MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
967
968 src_dma = dma_map_single(dma_chan->device->dev, src,
969 MV_XOR_TEST_SIZE, DMA_TO_DEVICE);
970
971 tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
972 MV_XOR_TEST_SIZE, 0);
973 cookie = mv_xor_tx_submit(tx);
974 mv_xor_issue_pending(dma_chan);
975 async_tx_ack(tx);
976 msleep(1);
977
978 if (mv_xor_is_complete(dma_chan, cookie, NULL, NULL) !=
979 DMA_SUCCESS) {
980 dev_printk(KERN_ERR, dma_chan->device->dev,
981 "Self-test copy timed out, disabling\n");
982 err = -ENODEV;
983 goto free_resources;
984 }
985
986 mv_chan = to_mv_xor_chan(dma_chan);
987 dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
988 MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
989 if (memcmp(src, dest, MV_XOR_TEST_SIZE)) {
990 dev_printk(KERN_ERR, dma_chan->device->dev,
991 "Self-test copy failed compare, disabling\n");
992 err = -ENODEV;
993 goto free_resources;
994 }
995
996free_resources:
997 mv_xor_free_chan_resources(dma_chan);
998out:
999 kfree(src);
1000 kfree(dest);
1001 return err;
1002}
1003
1004#define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
1005static int __devinit
1006mv_xor_xor_self_test(struct mv_xor_device *device)
1007{
1008 int i, src_idx;
1009 struct page *dest;
1010 struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
1011 dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
1012 dma_addr_t dest_dma;
1013 struct dma_async_tx_descriptor *tx;
1014 struct dma_chan *dma_chan;
1015 dma_cookie_t cookie;
1016 u8 cmp_byte = 0;
1017 u32 cmp_word;
1018 int err = 0;
1019 struct mv_xor_chan *mv_chan;
1020
1021 for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
1022 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
1023 if (!xor_srcs[src_idx])
1024 while (src_idx--) {
1025 __free_page(xor_srcs[src_idx]);
1026 return -ENOMEM;
1027 }
1028 }
1029
1030 dest = alloc_page(GFP_KERNEL);
1031 if (!dest)
1032 while (src_idx--) {
1033 __free_page(xor_srcs[src_idx]);
1034 return -ENOMEM;
1035 }
1036
1037 /* Fill in src buffers */
1038 for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
1039 u8 *ptr = page_address(xor_srcs[src_idx]);
1040 for (i = 0; i < PAGE_SIZE; i++)
1041 ptr[i] = (1 << src_idx);
1042 }
1043
1044 for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++)
1045 cmp_byte ^= (u8) (1 << src_idx);
1046
1047 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
1048 (cmp_byte << 8) | cmp_byte;
1049
1050 memset(page_address(dest), 0, PAGE_SIZE);
1051
1052 dma_chan = container_of(device->common.channels.next,
1053 struct dma_chan,
1054 device_node);
848c536a 1055 if (mv_xor_alloc_chan_resources(dma_chan, NULL) < 1) {
ff7b0479
SB		 1056 err = -ENODEV;
1057 goto out;
1058 }
1059
1060 /* test xor */
1061 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
1062 DMA_FROM_DEVICE);
1063
1064 for (i = 0; i < MV_XOR_NUM_SRC_TEST; i++)
1065 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
1066 0, PAGE_SIZE, DMA_TO_DEVICE);
1067
1068 tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
1069 MV_XOR_NUM_SRC_TEST, PAGE_SIZE, 0);
1070
1071 cookie = mv_xor_tx_submit(tx);
1072 mv_xor_issue_pending(dma_chan);
1073 async_tx_ack(tx);
1074 msleep(8);
1075
1076 if (mv_xor_is_complete(dma_chan, cookie, NULL, NULL) !=
1077 DMA_SUCCESS) {
1078 dev_printk(KERN_ERR, dma_chan->device->dev,
1079 "Self-test xor timed out, disabling\n");
1080 err = -ENODEV;
1081 goto free_resources;
1082 }
1083
1084 mv_chan = to_mv_xor_chan(dma_chan);
1085 dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
1086 PAGE_SIZE, DMA_FROM_DEVICE);
1087 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1088 u32 *ptr = page_address(dest);
1089 if (ptr[i] != cmp_word) {
1090 dev_printk(KERN_ERR, dma_chan->device->dev,
1091 "Self-test xor failed compare, disabling."
1092 " index %d, data %x, expected %x\n", i,
1093 ptr[i], cmp_word);
1094 err = -ENODEV;
1095 goto free_resources;
1096 }
1097 }
1098
1099free_resources:
1100 mv_xor_free_chan_resources(dma_chan);
1101out:
1102 src_idx = MV_XOR_NUM_SRC_TEST;
1103 while (src_idx--)
1104 __free_page(xor_srcs[src_idx]);
1105 __free_page(dest);
1106 return err;
1107}
1108
1109static int __devexit mv_xor_remove(struct platform_device *dev)
1110{
1111 struct mv_xor_device *device = platform_get_drvdata(dev);
1112 struct dma_chan *chan, *_chan;
1113 struct mv_xor_chan *mv_chan;
1114 struct mv_xor_platform_data *plat_data = dev->dev.platform_data;
1115
1116 dma_async_device_unregister(&device->common);
1117
1118 dma_free_coherent(&dev->dev, plat_data->pool_size,
1119 device->dma_desc_pool_virt, device->dma_desc_pool);
1120
1121 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1122 device_node) {
1123 mv_chan = to_mv_xor_chan(chan);
1124 list_del(&chan->device_node);
1125 }
1126
1127 return 0;
1128}
1129
1130static int __devinit mv_xor_probe(struct platform_device *pdev)
1131{
1132 int ret = 0;
1133 int irq;
1134 struct mv_xor_device *adev;
1135 struct mv_xor_chan *mv_chan;
1136 struct dma_device *dma_dev;
1137 struct mv_xor_platform_data *plat_data = pdev->dev.platform_data;
1138
1139
1140 adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
1141 if (!adev)
1142 return -ENOMEM;
1143
1144 dma_dev = &adev->common;
1145
1146 /* allocate coherent memory for hardware descriptors
1147 * note: writecombine gives slightly better performance, but
1148 * requires that we explicitly flush the writes
1149 */
1150 adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1151 plat_data->pool_size,
1152 &adev->dma_desc_pool,
1153 GFP_KERNEL);
1154 if (!adev->dma_desc_pool_virt)
1155 return -ENOMEM;
1156
1157 adev->id = plat_data->hw_id;
1158
1159 /* discover transaction capabilites from the platform data */
1160 dma_dev->cap_mask = plat_data->cap_mask;
1161 adev->pdev = pdev;
1162 platform_set_drvdata(pdev, adev);
1163
1164 adev->shared = platform_get_drvdata(plat_data->shared);
1165
1166 INIT_LIST_HEAD(&dma_dev->channels);
1167
1168 /* set base routines */
1169 dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
1170 dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
1171 dma_dev->device_is_tx_complete = mv_xor_is_complete;
1172 dma_dev->device_issue_pending = mv_xor_issue_pending;
1173 dma_dev->dev = &pdev->dev;
1174
1175 /* set prep routines based on capability */
1176 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1177 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
1178 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1179 dma_dev->device_prep_dma_memset = mv_xor_prep_dma_memset;
1180 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1181 dma_dev->max_xor = 8; ;
1182 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
1183 }
1184
1185 mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
1186 if (!mv_chan) {
1187 ret = -ENOMEM;
1188 goto err_free_dma;
1189 }
1190 mv_chan->device = adev;
1191 mv_chan->idx = plat_data->hw_id;
1192 mv_chan->mmr_base = adev->shared->xor_base;
1193
1194 if (!mv_chan->mmr_base) {
1195 ret = -ENOMEM;
1196 goto err_free_dma;
1197 }
1198 tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
1199 mv_chan);
1200
1201 /* clear errors before enabling interrupts */
1202 mv_xor_device_clear_err_status(mv_chan);
1203
1204 irq = platform_get_irq(pdev, 0);
1205 if (irq < 0) {
1206 ret = irq;
1207 goto err_free_dma;
1208 }
1209 ret = devm_request_irq(&pdev->dev, irq,
1210 mv_xor_interrupt_handler,
1211 0, dev_name(&pdev->dev), mv_chan);
1212 if (ret)
1213 goto err_free_dma;
1214
1215 mv_chan_unmask_interrupts(mv_chan);
1216
1217 mv_set_mode(mv_chan, DMA_MEMCPY);
1218
1219 spin_lock_init(&mv_chan->lock);
1220 INIT_LIST_HEAD(&mv_chan->chain);
1221 INIT_LIST_HEAD(&mv_chan->completed_slots);
1222 INIT_LIST_HEAD(&mv_chan->all_slots);
1223 INIT_RCU_HEAD(&mv_chan->common.rcu);
1224 mv_chan->common.device = dma_dev;
1225
1226 list_add_tail(&mv_chan->common.device_node, &dma_dev->channels);
1227
1228 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1229 ret = mv_xor_memcpy_self_test(adev);
1230 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1231 if (ret)
1232 goto err_free_dma;
1233 }
1234
1235 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1236 ret = mv_xor_xor_self_test(adev);
1237 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1238 if (ret)
1239 goto err_free_dma;
1240 }
1241
1242 dev_printk(KERN_INFO, &pdev->dev, "Marvell XOR: "
1243 "( %s%s%s%s)\n",
1244 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1245 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
1246 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1247 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1248
1249 dma_async_device_register(dma_dev);
1250 goto out;
1251
1252 err_free_dma:
1253 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1254 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1255 out:
1256 return ret;
1257}
1258
1259static void
1260mv_xor_conf_mbus_windows(struct mv_xor_shared_private *msp,
1261 struct mbus_dram_target_info *dram)
1262{
1263 void __iomem *base = msp->xor_base;
1264 u32 win_enable = 0;
1265 int i;
1266
1267 for (i = 0; i < 8; i++) {
1268 writel(0, base + WINDOW_BASE(i));
1269 writel(0, base + WINDOW_SIZE(i));
1270 if (i < 4)
1271 writel(0, base + WINDOW_REMAP_HIGH(i));
1272 }
1273
1274 for (i = 0; i < dram->num_cs; i++) {
1275 struct mbus_dram_window *cs = dram->cs + i;
1276
1277 writel((cs->base & 0xffff0000) |
1278 (cs->mbus_attr << 8) |
1279 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1280 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1281
1282 win_enable |= (1 << i);
1283 win_enable |= 3 << (16 + (2 * i));
1284 }
1285
1286 writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1287 writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1288}
1289
1290static struct platform_driver mv_xor_driver = {
1291 .probe = mv_xor_probe,
1292 .remove = mv_xor_remove,
1293 .driver = {
1294 .owner = THIS_MODULE,
1295 .name = MV_XOR_NAME,
1296 },
1297};
1298
1299static int mv_xor_shared_probe(struct platform_device *pdev)
1300{
1301 struct mv_xor_platform_shared_data *msd = pdev->dev.platform_data;
1302 struct mv_xor_shared_private *msp;
1303 struct resource *res;
1304
1305 dev_printk(KERN_NOTICE, &pdev->dev, "Marvell shared XOR driver\n");
1306
1307 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
1308 if (!msp)
1309 return -ENOMEM;
1310
1311 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1312 if (!res)
1313 return -ENODEV;
1314
1315 msp->xor_base = devm_ioremap(&pdev->dev, res->start,
1316 res->end - res->start + 1);
1317 if (!msp->xor_base)
1318 return -EBUSY;
1319
1320 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1321 if (!res)
1322 return -ENODEV;
1323
1324 msp->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1325 res->end - res->start + 1);
1326 if (!msp->xor_high_base)
1327 return -EBUSY;
1328
1329 platform_set_drvdata(pdev, msp);
1330
1331 /*
1332 * (Re-)program MBUS remapping windows if we are asked to.
1333 */
1334 if (msd != NULL && msd->dram != NULL)
1335 mv_xor_conf_mbus_windows(msp, msd->dram);
1336
1337 return 0;
1338}
1339
1340static int mv_xor_shared_remove(struct platform_device *pdev)
1341{
1342 return 0;
1343}
1344
1345static struct platform_driver mv_xor_shared_driver = {
1346 .probe = mv_xor_shared_probe,
1347 .remove = mv_xor_shared_remove,
1348 .driver = {
1349 .owner = THIS_MODULE,
1350 .name = MV_XOR_SHARED_NAME,
1351 },
1352};
1353
1354
1355static int __init mv_xor_init(void)
1356{
1357 int rc;
1358
1359 rc = platform_driver_register(&mv_xor_shared_driver);
1360 if (!rc) {
1361 rc = platform_driver_register(&mv_xor_driver);
1362 if (rc)
1363 platform_driver_unregister(&mv_xor_shared_driver);
1364 }
1365 return rc;
1366}
1367module_init(mv_xor_init);
1368
1369/* it's currently unsafe to unload this module */
1370#if 0
1371static void __exit mv_xor_exit(void)
1372{
1373 platform_driver_unregister(&mv_xor_driver);
1374 platform_driver_unregister(&mv_xor_shared_driver);
1375 return;
1376}
1377
1378module_exit(mv_xor_exit);
1379#endif
1380
1381MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1382MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1383MODULE_LICENSE("GPL");
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