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a580b8c5 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * Refer to drivers/dma/imx-sdma.c | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/wait.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/semaphore.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/dmaengine.h> | |
24 | #include <linux/delay.h> | |
25 | ||
26 | #include <asm/irq.h> | |
27 | #include <mach/mxs.h> | |
28 | #include <mach/dma.h> | |
29 | #include <mach/common.h> | |
30 | ||
31 | /* | |
32 | * NOTE: The term "PIO" throughout the mxs-dma implementation means | |
33 | * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, | |
34 | * dma can program the controller registers of peripheral devices. | |
35 | */ | |
36 | ||
37 | #define MXS_DMA_APBH 0 | |
38 | #define MXS_DMA_APBX 1 | |
39 | #define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH) | |
40 | ||
41 | #define APBH_VERSION_LATEST 3 | |
42 | #define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST) | |
43 | ||
44 | #define HW_APBHX_CTRL0 0x000 | |
45 | #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) | |
46 | #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) | |
47 | #define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 | |
48 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 | |
49 | #define HW_APBHX_CTRL1 0x010 | |
50 | #define HW_APBHX_CTRL2 0x020 | |
51 | #define HW_APBHX_CHANNEL_CTRL 0x030 | |
52 | #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 | |
53 | #define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800) | |
54 | #define HW_APBX_VERSION 0x800 | |
55 | #define BP_APBHX_VERSION_MAJOR 24 | |
56 | #define HW_APBHX_CHn_NXTCMDAR(n) \ | |
57 | (((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70) | |
58 | #define HW_APBHX_CHn_SEMA(n) \ | |
59 | (((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70) | |
60 | ||
61 | /* | |
62 | * ccw bits definitions | |
63 | * | |
64 | * COMMAND: 0..1 (2) | |
65 | * CHAIN: 2 (1) | |
66 | * IRQ: 3 (1) | |
67 | * NAND_LOCK: 4 (1) - not implemented | |
68 | * NAND_WAIT4READY: 5 (1) - not implemented | |
69 | * DEC_SEM: 6 (1) | |
70 | * WAIT4END: 7 (1) | |
71 | * HALT_ON_TERMINATE: 8 (1) | |
72 | * TERMINATE_FLUSH: 9 (1) | |
73 | * RESERVED: 10..11 (2) | |
74 | * PIO_NUM: 12..15 (4) | |
75 | */ | |
76 | #define BP_CCW_COMMAND 0 | |
77 | #define BM_CCW_COMMAND (3 << 0) | |
78 | #define CCW_CHAIN (1 << 2) | |
79 | #define CCW_IRQ (1 << 3) | |
80 | #define CCW_DEC_SEM (1 << 6) | |
81 | #define CCW_WAIT4END (1 << 7) | |
82 | #define CCW_HALT_ON_TERM (1 << 8) | |
83 | #define CCW_TERM_FLUSH (1 << 9) | |
84 | #define BP_CCW_PIO_NUM 12 | |
85 | #define BM_CCW_PIO_NUM (0xf << 12) | |
86 | ||
87 | #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) | |
88 | ||
89 | #define MXS_DMA_CMD_NO_XFER 0 | |
90 | #define MXS_DMA_CMD_WRITE 1 | |
91 | #define MXS_DMA_CMD_READ 2 | |
92 | #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ | |
93 | ||
94 | struct mxs_dma_ccw { | |
95 | u32 next; | |
96 | u16 bits; | |
97 | u16 xfer_bytes; | |
98 | #define MAX_XFER_BYTES 0xff00 | |
99 | u32 bufaddr; | |
100 | #define MXS_PIO_WORDS 16 | |
101 | u32 pio_words[MXS_PIO_WORDS]; | |
102 | }; | |
103 | ||
104 | #define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw)) | |
105 | ||
106 | struct mxs_dma_chan { | |
107 | struct mxs_dma_engine *mxs_dma; | |
108 | struct dma_chan chan; | |
109 | struct dma_async_tx_descriptor desc; | |
110 | struct tasklet_struct tasklet; | |
111 | int chan_irq; | |
112 | struct mxs_dma_ccw *ccw; | |
113 | dma_addr_t ccw_phys; | |
114 | dma_cookie_t last_completed; | |
115 | enum dma_status status; | |
116 | unsigned int flags; | |
117 | #define MXS_DMA_SG_LOOP (1 << 0) | |
118 | }; | |
119 | ||
120 | #define MXS_DMA_CHANNELS 16 | |
121 | #define MXS_DMA_CHANNELS_MASK 0xffff | |
122 | ||
123 | struct mxs_dma_engine { | |
124 | int dev_id; | |
125 | unsigned int version; | |
126 | void __iomem *base; | |
127 | struct clk *clk; | |
128 | struct dma_device dma_device; | |
129 | struct device_dma_parameters dma_parms; | |
130 | struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; | |
131 | }; | |
132 | ||
133 | static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) | |
134 | { | |
135 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
136 | int chan_id = mxs_chan->chan.chan_id; | |
137 | ||
138 | if (dma_is_apbh() && apbh_is_old()) | |
139 | writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), | |
140 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
141 | else | |
142 | writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), | |
143 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); | |
144 | } | |
145 | ||
146 | static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) | |
147 | { | |
148 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
149 | int chan_id = mxs_chan->chan.chan_id; | |
150 | ||
151 | /* set cmd_addr up */ | |
152 | writel(mxs_chan->ccw_phys, | |
153 | mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id)); | |
154 | ||
155 | /* enable apbh channel clock */ | |
156 | if (dma_is_apbh()) { | |
157 | if (apbh_is_old()) | |
158 | writel(1 << (chan_id + BP_APBH_CTRL0_CLKGATE_CHANNEL), | |
159 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR); | |
160 | else | |
161 | writel(1 << chan_id, | |
162 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR); | |
163 | } | |
164 | ||
165 | /* write 1 to SEMA to kick off the channel */ | |
166 | writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id)); | |
167 | } | |
168 | ||
169 | static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) | |
170 | { | |
171 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
172 | int chan_id = mxs_chan->chan.chan_id; | |
173 | ||
174 | /* disable apbh channel clock */ | |
175 | if (dma_is_apbh()) { | |
176 | if (apbh_is_old()) | |
177 | writel(1 << (chan_id + BP_APBH_CTRL0_CLKGATE_CHANNEL), | |
178 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
179 | else | |
180 | writel(1 << chan_id, | |
181 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
182 | } | |
183 | ||
184 | mxs_chan->status = DMA_SUCCESS; | |
185 | } | |
186 | ||
187 | static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) | |
188 | { | |
189 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
190 | int chan_id = mxs_chan->chan.chan_id; | |
191 | ||
192 | /* freeze the channel */ | |
193 | if (dma_is_apbh() && apbh_is_old()) | |
194 | writel(1 << chan_id, | |
195 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
196 | else | |
197 | writel(1 << chan_id, | |
198 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); | |
199 | ||
200 | mxs_chan->status = DMA_PAUSED; | |
201 | } | |
202 | ||
203 | static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) | |
204 | { | |
205 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
206 | int chan_id = mxs_chan->chan.chan_id; | |
207 | ||
208 | /* unfreeze the channel */ | |
209 | if (dma_is_apbh() && apbh_is_old()) | |
210 | writel(1 << chan_id, | |
211 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR); | |
212 | else | |
213 | writel(1 << chan_id, | |
214 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR); | |
215 | ||
216 | mxs_chan->status = DMA_IN_PROGRESS; | |
217 | } | |
218 | ||
219 | static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan) | |
220 | { | |
221 | dma_cookie_t cookie = mxs_chan->chan.cookie; | |
222 | ||
223 | if (++cookie < 0) | |
224 | cookie = 1; | |
225 | ||
226 | mxs_chan->chan.cookie = cookie; | |
227 | mxs_chan->desc.cookie = cookie; | |
228 | ||
229 | return cookie; | |
230 | } | |
231 | ||
232 | static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) | |
233 | { | |
234 | return container_of(chan, struct mxs_dma_chan, chan); | |
235 | } | |
236 | ||
237 | static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) | |
238 | { | |
239 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan); | |
240 | ||
241 | mxs_dma_enable_chan(mxs_chan); | |
242 | ||
243 | return mxs_dma_assign_cookie(mxs_chan); | |
244 | } | |
245 | ||
246 | static void mxs_dma_tasklet(unsigned long data) | |
247 | { | |
248 | struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; | |
249 | ||
250 | if (mxs_chan->desc.callback) | |
251 | mxs_chan->desc.callback(mxs_chan->desc.callback_param); | |
252 | } | |
253 | ||
254 | static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) | |
255 | { | |
256 | struct mxs_dma_engine *mxs_dma = dev_id; | |
257 | u32 stat1, stat2; | |
258 | ||
259 | /* completion status */ | |
260 | stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1); | |
261 | stat1 &= MXS_DMA_CHANNELS_MASK; | |
262 | writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR); | |
263 | ||
264 | /* error status */ | |
265 | stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2); | |
266 | writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR); | |
267 | ||
268 | /* | |
269 | * When both completion and error of termination bits set at the | |
270 | * same time, we do not take it as an error. IOW, it only becomes | |
271 | * an error we need to handler here in case of ether it's (1) an bus | |
272 | * error or (2) a termination error with no completion. | |
273 | */ | |
274 | stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */ | |
275 | (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */ | |
276 | ||
277 | /* combine error and completion status for checking */ | |
278 | stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1; | |
279 | while (stat1) { | |
280 | int channel = fls(stat1) - 1; | |
281 | struct mxs_dma_chan *mxs_chan = | |
282 | &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS]; | |
283 | ||
284 | if (channel >= MXS_DMA_CHANNELS) { | |
285 | dev_dbg(mxs_dma->dma_device.dev, | |
286 | "%s: error in channel %d\n", __func__, | |
287 | channel - MXS_DMA_CHANNELS); | |
288 | mxs_chan->status = DMA_ERROR; | |
289 | mxs_dma_reset_chan(mxs_chan); | |
290 | } else { | |
291 | if (mxs_chan->flags & MXS_DMA_SG_LOOP) | |
292 | mxs_chan->status = DMA_IN_PROGRESS; | |
293 | else | |
294 | mxs_chan->status = DMA_SUCCESS; | |
295 | } | |
296 | ||
297 | stat1 &= ~(1 << channel); | |
298 | ||
299 | if (mxs_chan->status == DMA_SUCCESS) | |
300 | mxs_chan->last_completed = mxs_chan->desc.cookie; | |
301 | ||
302 | /* schedule tasklet on this channel */ | |
303 | tasklet_schedule(&mxs_chan->tasklet); | |
304 | } | |
305 | ||
306 | return IRQ_HANDLED; | |
307 | } | |
308 | ||
309 | static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) | |
310 | { | |
311 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
312 | struct mxs_dma_data *data = chan->private; | |
313 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
314 | int ret; | |
315 | ||
316 | if (!data) | |
317 | return -EINVAL; | |
318 | ||
319 | mxs_chan->chan_irq = data->chan_irq; | |
320 | ||
321 | mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, | |
322 | &mxs_chan->ccw_phys, GFP_KERNEL); | |
323 | if (!mxs_chan->ccw) { | |
324 | ret = -ENOMEM; | |
325 | goto err_alloc; | |
326 | } | |
327 | ||
328 | memset(mxs_chan->ccw, 0, PAGE_SIZE); | |
329 | ||
95bfea16 SG |
330 | if (mxs_chan->chan_irq != NO_IRQ) { |
331 | ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, | |
332 | 0, "mxs-dma", mxs_dma); | |
333 | if (ret) | |
334 | goto err_irq; | |
335 | } | |
a580b8c5 SG |
336 | |
337 | ret = clk_enable(mxs_dma->clk); | |
338 | if (ret) | |
339 | goto err_clk; | |
340 | ||
341 | mxs_dma_reset_chan(mxs_chan); | |
342 | ||
343 | dma_async_tx_descriptor_init(&mxs_chan->desc, chan); | |
344 | mxs_chan->desc.tx_submit = mxs_dma_tx_submit; | |
345 | ||
346 | /* the descriptor is ready */ | |
347 | async_tx_ack(&mxs_chan->desc); | |
348 | ||
349 | return 0; | |
350 | ||
351 | err_clk: | |
352 | free_irq(mxs_chan->chan_irq, mxs_dma); | |
353 | err_irq: | |
354 | dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, | |
355 | mxs_chan->ccw, mxs_chan->ccw_phys); | |
356 | err_alloc: | |
357 | return ret; | |
358 | } | |
359 | ||
360 | static void mxs_dma_free_chan_resources(struct dma_chan *chan) | |
361 | { | |
362 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
363 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
364 | ||
365 | mxs_dma_disable_chan(mxs_chan); | |
366 | ||
367 | free_irq(mxs_chan->chan_irq, mxs_dma); | |
368 | ||
369 | dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, | |
370 | mxs_chan->ccw, mxs_chan->ccw_phys); | |
371 | ||
372 | clk_disable(mxs_dma->clk); | |
373 | } | |
374 | ||
375 | static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( | |
376 | struct dma_chan *chan, struct scatterlist *sgl, | |
377 | unsigned int sg_len, enum dma_data_direction direction, | |
378 | unsigned long append) | |
379 | { | |
380 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
381 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
382 | struct mxs_dma_ccw *ccw; | |
383 | struct scatterlist *sg; | |
384 | int i, j; | |
385 | u32 *pio; | |
386 | static int idx; | |
387 | ||
388 | if (mxs_chan->status == DMA_IN_PROGRESS && !append) | |
389 | return NULL; | |
390 | ||
391 | if (sg_len + (append ? idx : 0) > NUM_CCW) { | |
392 | dev_err(mxs_dma->dma_device.dev, | |
393 | "maximum number of sg exceeded: %d > %d\n", | |
394 | sg_len, NUM_CCW); | |
395 | goto err_out; | |
396 | } | |
397 | ||
398 | mxs_chan->status = DMA_IN_PROGRESS; | |
399 | mxs_chan->flags = 0; | |
400 | ||
401 | /* | |
402 | * If the sg is prepared with append flag set, the sg | |
403 | * will be appended to the last prepared sg. | |
404 | */ | |
405 | if (append) { | |
406 | BUG_ON(idx < 1); | |
407 | ccw = &mxs_chan->ccw[idx - 1]; | |
408 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; | |
409 | ccw->bits |= CCW_CHAIN; | |
410 | ccw->bits &= ~CCW_IRQ; | |
411 | ccw->bits &= ~CCW_DEC_SEM; | |
412 | ccw->bits &= ~CCW_WAIT4END; | |
413 | } else { | |
414 | idx = 0; | |
415 | } | |
416 | ||
417 | if (direction == DMA_NONE) { | |
418 | ccw = &mxs_chan->ccw[idx++]; | |
419 | pio = (u32 *) sgl; | |
420 | ||
421 | for (j = 0; j < sg_len;) | |
422 | ccw->pio_words[j++] = *pio++; | |
423 | ||
424 | ccw->bits = 0; | |
425 | ccw->bits |= CCW_IRQ; | |
426 | ccw->bits |= CCW_DEC_SEM; | |
427 | ccw->bits |= CCW_WAIT4END; | |
428 | ccw->bits |= CCW_HALT_ON_TERM; | |
429 | ccw->bits |= CCW_TERM_FLUSH; | |
430 | ccw->bits |= BF_CCW(sg_len, PIO_NUM); | |
431 | ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); | |
432 | } else { | |
433 | for_each_sg(sgl, sg, sg_len, i) { | |
434 | if (sg->length > MAX_XFER_BYTES) { | |
435 | dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", | |
436 | sg->length, MAX_XFER_BYTES); | |
437 | goto err_out; | |
438 | } | |
439 | ||
440 | ccw = &mxs_chan->ccw[idx++]; | |
441 | ||
442 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; | |
443 | ccw->bufaddr = sg->dma_address; | |
444 | ccw->xfer_bytes = sg->length; | |
445 | ||
446 | ccw->bits = 0; | |
447 | ccw->bits |= CCW_CHAIN; | |
448 | ccw->bits |= CCW_HALT_ON_TERM; | |
449 | ccw->bits |= CCW_TERM_FLUSH; | |
450 | ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ? | |
451 | MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, | |
452 | COMMAND); | |
453 | ||
454 | if (i + 1 == sg_len) { | |
455 | ccw->bits &= ~CCW_CHAIN; | |
456 | ccw->bits |= CCW_IRQ; | |
457 | ccw->bits |= CCW_DEC_SEM; | |
458 | ccw->bits |= CCW_WAIT4END; | |
459 | } | |
460 | } | |
461 | } | |
462 | ||
463 | return &mxs_chan->desc; | |
464 | ||
465 | err_out: | |
466 | mxs_chan->status = DMA_ERROR; | |
467 | return NULL; | |
468 | } | |
469 | ||
470 | static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( | |
471 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
472 | size_t period_len, enum dma_data_direction direction) | |
473 | { | |
474 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
475 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
476 | int num_periods = buf_len / period_len; | |
477 | int i = 0, buf = 0; | |
478 | ||
479 | if (mxs_chan->status == DMA_IN_PROGRESS) | |
480 | return NULL; | |
481 | ||
482 | mxs_chan->status = DMA_IN_PROGRESS; | |
483 | mxs_chan->flags |= MXS_DMA_SG_LOOP; | |
484 | ||
485 | if (num_periods > NUM_CCW) { | |
486 | dev_err(mxs_dma->dma_device.dev, | |
487 | "maximum number of sg exceeded: %d > %d\n", | |
488 | num_periods, NUM_CCW); | |
489 | goto err_out; | |
490 | } | |
491 | ||
492 | if (period_len > MAX_XFER_BYTES) { | |
493 | dev_err(mxs_dma->dma_device.dev, | |
494 | "maximum period size exceeded: %d > %d\n", | |
495 | period_len, MAX_XFER_BYTES); | |
496 | goto err_out; | |
497 | } | |
498 | ||
499 | while (buf < buf_len) { | |
500 | struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; | |
501 | ||
502 | if (i + 1 == num_periods) | |
503 | ccw->next = mxs_chan->ccw_phys; | |
504 | else | |
505 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); | |
506 | ||
507 | ccw->bufaddr = dma_addr; | |
508 | ccw->xfer_bytes = period_len; | |
509 | ||
510 | ccw->bits = 0; | |
511 | ccw->bits |= CCW_CHAIN; | |
512 | ccw->bits |= CCW_IRQ; | |
513 | ccw->bits |= CCW_HALT_ON_TERM; | |
514 | ccw->bits |= CCW_TERM_FLUSH; | |
515 | ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ? | |
516 | MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); | |
517 | ||
518 | dma_addr += period_len; | |
519 | buf += period_len; | |
520 | ||
521 | i++; | |
522 | } | |
523 | ||
524 | return &mxs_chan->desc; | |
525 | ||
526 | err_out: | |
527 | mxs_chan->status = DMA_ERROR; | |
528 | return NULL; | |
529 | } | |
530 | ||
531 | static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
532 | unsigned long arg) | |
533 | { | |
534 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
535 | int ret = 0; | |
536 | ||
537 | switch (cmd) { | |
538 | case DMA_TERMINATE_ALL: | |
539 | mxs_dma_disable_chan(mxs_chan); | |
a62bae98 | 540 | mxs_dma_reset_chan(mxs_chan); |
a580b8c5 SG |
541 | break; |
542 | case DMA_PAUSE: | |
543 | mxs_dma_pause_chan(mxs_chan); | |
544 | break; | |
545 | case DMA_RESUME: | |
546 | mxs_dma_resume_chan(mxs_chan); | |
547 | break; | |
548 | default: | |
549 | ret = -ENOSYS; | |
550 | } | |
551 | ||
552 | return ret; | |
553 | } | |
554 | ||
555 | static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, | |
556 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
557 | { | |
558 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
559 | dma_cookie_t last_used; | |
560 | ||
561 | last_used = chan->cookie; | |
562 | dma_set_tx_state(txstate, mxs_chan->last_completed, last_used, 0); | |
563 | ||
564 | return mxs_chan->status; | |
565 | } | |
566 | ||
567 | static void mxs_dma_issue_pending(struct dma_chan *chan) | |
568 | { | |
569 | /* | |
570 | * Nothing to do. We only have a single descriptor. | |
571 | */ | |
572 | } | |
573 | ||
574 | static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) | |
575 | { | |
576 | int ret; | |
577 | ||
578 | ret = clk_enable(mxs_dma->clk); | |
579 | if (ret) | |
580 | goto err_out; | |
581 | ||
582 | ret = mxs_reset_block(mxs_dma->base); | |
583 | if (ret) | |
584 | goto err_out; | |
585 | ||
586 | /* only major version matters */ | |
587 | mxs_dma->version = readl(mxs_dma->base + | |
588 | ((mxs_dma->dev_id == MXS_DMA_APBX) ? | |
589 | HW_APBX_VERSION : HW_APBH_VERSION)) >> | |
590 | BP_APBHX_VERSION_MAJOR; | |
591 | ||
592 | /* enable apbh burst */ | |
593 | if (dma_is_apbh()) { | |
594 | writel(BM_APBH_CTRL0_APB_BURST_EN, | |
595 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
596 | writel(BM_APBH_CTRL0_APB_BURST8_EN, | |
597 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
598 | } | |
599 | ||
600 | /* enable irq for all the channels */ | |
601 | writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, | |
602 | mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR); | |
603 | ||
604 | clk_disable(mxs_dma->clk); | |
605 | ||
606 | return 0; | |
607 | ||
608 | err_out: | |
609 | return ret; | |
610 | } | |
611 | ||
612 | static int __init mxs_dma_probe(struct platform_device *pdev) | |
613 | { | |
614 | const struct platform_device_id *id_entry = | |
615 | platform_get_device_id(pdev); | |
616 | struct mxs_dma_engine *mxs_dma; | |
617 | struct resource *iores; | |
618 | int ret, i; | |
619 | ||
620 | mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL); | |
621 | if (!mxs_dma) | |
622 | return -ENOMEM; | |
623 | ||
624 | mxs_dma->dev_id = id_entry->driver_data; | |
625 | ||
626 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
627 | ||
628 | if (!request_mem_region(iores->start, resource_size(iores), | |
629 | pdev->name)) { | |
630 | ret = -EBUSY; | |
631 | goto err_request_region; | |
632 | } | |
633 | ||
634 | mxs_dma->base = ioremap(iores->start, resource_size(iores)); | |
635 | if (!mxs_dma->base) { | |
636 | ret = -ENOMEM; | |
637 | goto err_ioremap; | |
638 | } | |
639 | ||
640 | mxs_dma->clk = clk_get(&pdev->dev, NULL); | |
641 | if (IS_ERR(mxs_dma->clk)) { | |
642 | ret = PTR_ERR(mxs_dma->clk); | |
643 | goto err_clk; | |
644 | } | |
645 | ||
646 | dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); | |
647 | dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); | |
648 | ||
649 | INIT_LIST_HEAD(&mxs_dma->dma_device.channels); | |
650 | ||
651 | /* Initialize channel parameters */ | |
652 | for (i = 0; i < MXS_DMA_CHANNELS; i++) { | |
653 | struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; | |
654 | ||
655 | mxs_chan->mxs_dma = mxs_dma; | |
656 | mxs_chan->chan.device = &mxs_dma->dma_device; | |
657 | ||
658 | tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, | |
659 | (unsigned long) mxs_chan); | |
660 | ||
661 | ||
662 | /* Add the channel to mxs_chan list */ | |
663 | list_add_tail(&mxs_chan->chan.device_node, | |
664 | &mxs_dma->dma_device.channels); | |
665 | } | |
666 | ||
667 | ret = mxs_dma_init(mxs_dma); | |
668 | if (ret) | |
669 | goto err_init; | |
670 | ||
671 | mxs_dma->dma_device.dev = &pdev->dev; | |
672 | ||
673 | /* mxs_dma gets 65535 bytes maximum sg size */ | |
674 | mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; | |
675 | dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); | |
676 | ||
677 | mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; | |
678 | mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; | |
679 | mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; | |
680 | mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; | |
681 | mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; | |
682 | mxs_dma->dma_device.device_control = mxs_dma_control; | |
683 | mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending; | |
684 | ||
685 | ret = dma_async_device_register(&mxs_dma->dma_device); | |
686 | if (ret) { | |
687 | dev_err(mxs_dma->dma_device.dev, "unable to register\n"); | |
688 | goto err_init; | |
689 | } | |
690 | ||
691 | dev_info(mxs_dma->dma_device.dev, "initialized\n"); | |
692 | ||
693 | return 0; | |
694 | ||
695 | err_init: | |
696 | clk_put(mxs_dma->clk); | |
697 | err_clk: | |
698 | iounmap(mxs_dma->base); | |
699 | err_ioremap: | |
700 | release_mem_region(iores->start, resource_size(iores)); | |
701 | err_request_region: | |
702 | kfree(mxs_dma); | |
703 | return ret; | |
704 | } | |
705 | ||
706 | static struct platform_device_id mxs_dma_type[] = { | |
707 | { | |
708 | .name = "mxs-dma-apbh", | |
709 | .driver_data = MXS_DMA_APBH, | |
710 | }, { | |
711 | .name = "mxs-dma-apbx", | |
712 | .driver_data = MXS_DMA_APBX, | |
2a9778ed AL |
713 | }, { |
714 | /* end of list */ | |
a580b8c5 SG |
715 | } |
716 | }; | |
717 | ||
718 | static struct platform_driver mxs_dma_driver = { | |
719 | .driver = { | |
720 | .name = "mxs-dma", | |
721 | }, | |
722 | .id_table = mxs_dma_type, | |
723 | }; | |
724 | ||
725 | static int __init mxs_dma_module_init(void) | |
726 | { | |
727 | return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); | |
728 | } | |
729 | subsys_initcall(mxs_dma_module_init); |