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Commit | Line | Data |
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a580b8c5 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * Refer to drivers/dma/imx-sdma.c | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/wait.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/semaphore.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/dmaengine.h> | |
24 | #include <linux/delay.h> | |
25 | ||
26 | #include <asm/irq.h> | |
27 | #include <mach/mxs.h> | |
28 | #include <mach/dma.h> | |
29 | #include <mach/common.h> | |
30 | ||
d2ebfb33 RKAL |
31 | #include "dmaengine.h" |
32 | ||
a580b8c5 SG |
33 | /* |
34 | * NOTE: The term "PIO" throughout the mxs-dma implementation means | |
35 | * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, | |
36 | * dma can program the controller registers of peripheral devices. | |
37 | */ | |
38 | ||
39 | #define MXS_DMA_APBH 0 | |
40 | #define MXS_DMA_APBX 1 | |
41 | #define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH) | |
42 | ||
43 | #define APBH_VERSION_LATEST 3 | |
44 | #define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST) | |
45 | ||
46 | #define HW_APBHX_CTRL0 0x000 | |
47 | #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) | |
48 | #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) | |
a580b8c5 SG |
49 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 |
50 | #define HW_APBHX_CTRL1 0x010 | |
51 | #define HW_APBHX_CTRL2 0x020 | |
52 | #define HW_APBHX_CHANNEL_CTRL 0x030 | |
53 | #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 | |
54 | #define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800) | |
55 | #define HW_APBX_VERSION 0x800 | |
56 | #define BP_APBHX_VERSION_MAJOR 24 | |
57 | #define HW_APBHX_CHn_NXTCMDAR(n) \ | |
58 | (((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70) | |
59 | #define HW_APBHX_CHn_SEMA(n) \ | |
60 | (((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70) | |
61 | ||
62 | /* | |
63 | * ccw bits definitions | |
64 | * | |
65 | * COMMAND: 0..1 (2) | |
66 | * CHAIN: 2 (1) | |
67 | * IRQ: 3 (1) | |
68 | * NAND_LOCK: 4 (1) - not implemented | |
69 | * NAND_WAIT4READY: 5 (1) - not implemented | |
70 | * DEC_SEM: 6 (1) | |
71 | * WAIT4END: 7 (1) | |
72 | * HALT_ON_TERMINATE: 8 (1) | |
73 | * TERMINATE_FLUSH: 9 (1) | |
74 | * RESERVED: 10..11 (2) | |
75 | * PIO_NUM: 12..15 (4) | |
76 | */ | |
77 | #define BP_CCW_COMMAND 0 | |
78 | #define BM_CCW_COMMAND (3 << 0) | |
79 | #define CCW_CHAIN (1 << 2) | |
80 | #define CCW_IRQ (1 << 3) | |
81 | #define CCW_DEC_SEM (1 << 6) | |
82 | #define CCW_WAIT4END (1 << 7) | |
83 | #define CCW_HALT_ON_TERM (1 << 8) | |
84 | #define CCW_TERM_FLUSH (1 << 9) | |
85 | #define BP_CCW_PIO_NUM 12 | |
86 | #define BM_CCW_PIO_NUM (0xf << 12) | |
87 | ||
88 | #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) | |
89 | ||
90 | #define MXS_DMA_CMD_NO_XFER 0 | |
91 | #define MXS_DMA_CMD_WRITE 1 | |
92 | #define MXS_DMA_CMD_READ 2 | |
93 | #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ | |
94 | ||
95 | struct mxs_dma_ccw { | |
96 | u32 next; | |
97 | u16 bits; | |
98 | u16 xfer_bytes; | |
99 | #define MAX_XFER_BYTES 0xff00 | |
100 | u32 bufaddr; | |
101 | #define MXS_PIO_WORDS 16 | |
102 | u32 pio_words[MXS_PIO_WORDS]; | |
103 | }; | |
104 | ||
105 | #define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw)) | |
106 | ||
107 | struct mxs_dma_chan { | |
108 | struct mxs_dma_engine *mxs_dma; | |
109 | struct dma_chan chan; | |
110 | struct dma_async_tx_descriptor desc; | |
111 | struct tasklet_struct tasklet; | |
112 | int chan_irq; | |
113 | struct mxs_dma_ccw *ccw; | |
114 | dma_addr_t ccw_phys; | |
6d23ea4b | 115 | int desc_count; |
a580b8c5 SG |
116 | enum dma_status status; |
117 | unsigned int flags; | |
118 | #define MXS_DMA_SG_LOOP (1 << 0) | |
119 | }; | |
120 | ||
121 | #define MXS_DMA_CHANNELS 16 | |
122 | #define MXS_DMA_CHANNELS_MASK 0xffff | |
123 | ||
124 | struct mxs_dma_engine { | |
125 | int dev_id; | |
126 | unsigned int version; | |
127 | void __iomem *base; | |
128 | struct clk *clk; | |
129 | struct dma_device dma_device; | |
130 | struct device_dma_parameters dma_parms; | |
131 | struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; | |
132 | }; | |
133 | ||
134 | static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) | |
135 | { | |
136 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
137 | int chan_id = mxs_chan->chan.chan_id; | |
138 | ||
139 | if (dma_is_apbh() && apbh_is_old()) | |
140 | writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), | |
141 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
142 | else | |
143 | writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), | |
144 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); | |
145 | } | |
146 | ||
147 | static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) | |
148 | { | |
149 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
150 | int chan_id = mxs_chan->chan.chan_id; | |
151 | ||
152 | /* set cmd_addr up */ | |
153 | writel(mxs_chan->ccw_phys, | |
154 | mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id)); | |
155 | ||
a580b8c5 SG |
156 | /* write 1 to SEMA to kick off the channel */ |
157 | writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id)); | |
158 | } | |
159 | ||
160 | static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) | |
161 | { | |
a580b8c5 SG |
162 | mxs_chan->status = DMA_SUCCESS; |
163 | } | |
164 | ||
165 | static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) | |
166 | { | |
167 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
168 | int chan_id = mxs_chan->chan.chan_id; | |
169 | ||
170 | /* freeze the channel */ | |
171 | if (dma_is_apbh() && apbh_is_old()) | |
172 | writel(1 << chan_id, | |
173 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
174 | else | |
175 | writel(1 << chan_id, | |
176 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); | |
177 | ||
178 | mxs_chan->status = DMA_PAUSED; | |
179 | } | |
180 | ||
181 | static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) | |
182 | { | |
183 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
184 | int chan_id = mxs_chan->chan.chan_id; | |
185 | ||
186 | /* unfreeze the channel */ | |
187 | if (dma_is_apbh() && apbh_is_old()) | |
188 | writel(1 << chan_id, | |
189 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR); | |
190 | else | |
191 | writel(1 << chan_id, | |
192 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR); | |
193 | ||
194 | mxs_chan->status = DMA_IN_PROGRESS; | |
195 | } | |
196 | ||
a580b8c5 SG |
197 | static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) |
198 | { | |
199 | return container_of(chan, struct mxs_dma_chan, chan); | |
200 | } | |
201 | ||
202 | static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) | |
203 | { | |
204 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan); | |
205 | ||
206 | mxs_dma_enable_chan(mxs_chan); | |
207 | ||
884485e1 | 208 | return dma_cookie_assign(tx); |
a580b8c5 SG |
209 | } |
210 | ||
211 | static void mxs_dma_tasklet(unsigned long data) | |
212 | { | |
213 | struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; | |
214 | ||
215 | if (mxs_chan->desc.callback) | |
216 | mxs_chan->desc.callback(mxs_chan->desc.callback_param); | |
217 | } | |
218 | ||
219 | static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) | |
220 | { | |
221 | struct mxs_dma_engine *mxs_dma = dev_id; | |
222 | u32 stat1, stat2; | |
223 | ||
224 | /* completion status */ | |
225 | stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1); | |
226 | stat1 &= MXS_DMA_CHANNELS_MASK; | |
227 | writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR); | |
228 | ||
229 | /* error status */ | |
230 | stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2); | |
231 | writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR); | |
232 | ||
233 | /* | |
234 | * When both completion and error of termination bits set at the | |
235 | * same time, we do not take it as an error. IOW, it only becomes | |
40031220 | 236 | * an error we need to handle here in case of either it's (1) a bus |
a580b8c5 SG |
237 | * error or (2) a termination error with no completion. |
238 | */ | |
239 | stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */ | |
240 | (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */ | |
241 | ||
242 | /* combine error and completion status for checking */ | |
243 | stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1; | |
244 | while (stat1) { | |
245 | int channel = fls(stat1) - 1; | |
246 | struct mxs_dma_chan *mxs_chan = | |
247 | &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS]; | |
248 | ||
249 | if (channel >= MXS_DMA_CHANNELS) { | |
250 | dev_dbg(mxs_dma->dma_device.dev, | |
251 | "%s: error in channel %d\n", __func__, | |
252 | channel - MXS_DMA_CHANNELS); | |
253 | mxs_chan->status = DMA_ERROR; | |
254 | mxs_dma_reset_chan(mxs_chan); | |
255 | } else { | |
256 | if (mxs_chan->flags & MXS_DMA_SG_LOOP) | |
257 | mxs_chan->status = DMA_IN_PROGRESS; | |
258 | else | |
259 | mxs_chan->status = DMA_SUCCESS; | |
260 | } | |
261 | ||
262 | stat1 &= ~(1 << channel); | |
263 | ||
264 | if (mxs_chan->status == DMA_SUCCESS) | |
f7fbce07 | 265 | dma_cookie_complete(&mxs_chan->desc); |
a580b8c5 SG |
266 | |
267 | /* schedule tasklet on this channel */ | |
268 | tasklet_schedule(&mxs_chan->tasklet); | |
269 | } | |
270 | ||
271 | return IRQ_HANDLED; | |
272 | } | |
273 | ||
274 | static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) | |
275 | { | |
276 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
277 | struct mxs_dma_data *data = chan->private; | |
278 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
279 | int ret; | |
280 | ||
281 | if (!data) | |
282 | return -EINVAL; | |
283 | ||
284 | mxs_chan->chan_irq = data->chan_irq; | |
285 | ||
286 | mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, | |
287 | &mxs_chan->ccw_phys, GFP_KERNEL); | |
288 | if (!mxs_chan->ccw) { | |
289 | ret = -ENOMEM; | |
290 | goto err_alloc; | |
291 | } | |
292 | ||
293 | memset(mxs_chan->ccw, 0, PAGE_SIZE); | |
294 | ||
95bfea16 SG |
295 | if (mxs_chan->chan_irq != NO_IRQ) { |
296 | ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, | |
297 | 0, "mxs-dma", mxs_dma); | |
298 | if (ret) | |
299 | goto err_irq; | |
300 | } | |
a580b8c5 | 301 | |
759a2e30 | 302 | ret = clk_prepare_enable(mxs_dma->clk); |
a580b8c5 SG |
303 | if (ret) |
304 | goto err_clk; | |
305 | ||
306 | mxs_dma_reset_chan(mxs_chan); | |
307 | ||
308 | dma_async_tx_descriptor_init(&mxs_chan->desc, chan); | |
309 | mxs_chan->desc.tx_submit = mxs_dma_tx_submit; | |
310 | ||
311 | /* the descriptor is ready */ | |
312 | async_tx_ack(&mxs_chan->desc); | |
313 | ||
314 | return 0; | |
315 | ||
316 | err_clk: | |
317 | free_irq(mxs_chan->chan_irq, mxs_dma); | |
318 | err_irq: | |
319 | dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, | |
320 | mxs_chan->ccw, mxs_chan->ccw_phys); | |
321 | err_alloc: | |
322 | return ret; | |
323 | } | |
324 | ||
325 | static void mxs_dma_free_chan_resources(struct dma_chan *chan) | |
326 | { | |
327 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
328 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
329 | ||
330 | mxs_dma_disable_chan(mxs_chan); | |
331 | ||
332 | free_irq(mxs_chan->chan_irq, mxs_dma); | |
333 | ||
334 | dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, | |
335 | mxs_chan->ccw, mxs_chan->ccw_phys); | |
336 | ||
759a2e30 | 337 | clk_disable_unprepare(mxs_dma->clk); |
a580b8c5 SG |
338 | } |
339 | ||
340 | static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( | |
341 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 342 | unsigned int sg_len, enum dma_transfer_direction direction, |
a580b8c5 SG |
343 | unsigned long append) |
344 | { | |
345 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
346 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
347 | struct mxs_dma_ccw *ccw; | |
348 | struct scatterlist *sg; | |
349 | int i, j; | |
350 | u32 *pio; | |
6d23ea4b | 351 | int idx = append ? mxs_chan->desc_count : 0; |
a580b8c5 SG |
352 | |
353 | if (mxs_chan->status == DMA_IN_PROGRESS && !append) | |
354 | return NULL; | |
355 | ||
356 | if (sg_len + (append ? idx : 0) > NUM_CCW) { | |
357 | dev_err(mxs_dma->dma_device.dev, | |
358 | "maximum number of sg exceeded: %d > %d\n", | |
359 | sg_len, NUM_CCW); | |
360 | goto err_out; | |
361 | } | |
362 | ||
363 | mxs_chan->status = DMA_IN_PROGRESS; | |
364 | mxs_chan->flags = 0; | |
365 | ||
366 | /* | |
367 | * If the sg is prepared with append flag set, the sg | |
368 | * will be appended to the last prepared sg. | |
369 | */ | |
370 | if (append) { | |
371 | BUG_ON(idx < 1); | |
372 | ccw = &mxs_chan->ccw[idx - 1]; | |
373 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; | |
374 | ccw->bits |= CCW_CHAIN; | |
375 | ccw->bits &= ~CCW_IRQ; | |
376 | ccw->bits &= ~CCW_DEC_SEM; | |
377 | ccw->bits &= ~CCW_WAIT4END; | |
378 | } else { | |
379 | idx = 0; | |
380 | } | |
381 | ||
62268ce9 | 382 | if (direction == DMA_TRANS_NONE) { |
a580b8c5 SG |
383 | ccw = &mxs_chan->ccw[idx++]; |
384 | pio = (u32 *) sgl; | |
385 | ||
386 | for (j = 0; j < sg_len;) | |
387 | ccw->pio_words[j++] = *pio++; | |
388 | ||
389 | ccw->bits = 0; | |
390 | ccw->bits |= CCW_IRQ; | |
391 | ccw->bits |= CCW_DEC_SEM; | |
392 | ccw->bits |= CCW_WAIT4END; | |
393 | ccw->bits |= CCW_HALT_ON_TERM; | |
394 | ccw->bits |= CCW_TERM_FLUSH; | |
395 | ccw->bits |= BF_CCW(sg_len, PIO_NUM); | |
396 | ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); | |
397 | } else { | |
398 | for_each_sg(sgl, sg, sg_len, i) { | |
399 | if (sg->length > MAX_XFER_BYTES) { | |
400 | dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", | |
401 | sg->length, MAX_XFER_BYTES); | |
402 | goto err_out; | |
403 | } | |
404 | ||
405 | ccw = &mxs_chan->ccw[idx++]; | |
406 | ||
407 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; | |
408 | ccw->bufaddr = sg->dma_address; | |
409 | ccw->xfer_bytes = sg->length; | |
410 | ||
411 | ccw->bits = 0; | |
412 | ccw->bits |= CCW_CHAIN; | |
413 | ccw->bits |= CCW_HALT_ON_TERM; | |
414 | ccw->bits |= CCW_TERM_FLUSH; | |
db8196df | 415 | ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? |
a580b8c5 SG |
416 | MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, |
417 | COMMAND); | |
418 | ||
419 | if (i + 1 == sg_len) { | |
420 | ccw->bits &= ~CCW_CHAIN; | |
421 | ccw->bits |= CCW_IRQ; | |
422 | ccw->bits |= CCW_DEC_SEM; | |
423 | ccw->bits |= CCW_WAIT4END; | |
424 | } | |
425 | } | |
426 | } | |
6d23ea4b | 427 | mxs_chan->desc_count = idx; |
a580b8c5 SG |
428 | |
429 | return &mxs_chan->desc; | |
430 | ||
431 | err_out: | |
432 | mxs_chan->status = DMA_ERROR; | |
433 | return NULL; | |
434 | } | |
435 | ||
436 | static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( | |
437 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
db8196df | 438 | size_t period_len, enum dma_transfer_direction direction) |
a580b8c5 SG |
439 | { |
440 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
441 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
442 | int num_periods = buf_len / period_len; | |
443 | int i = 0, buf = 0; | |
444 | ||
445 | if (mxs_chan->status == DMA_IN_PROGRESS) | |
446 | return NULL; | |
447 | ||
448 | mxs_chan->status = DMA_IN_PROGRESS; | |
449 | mxs_chan->flags |= MXS_DMA_SG_LOOP; | |
450 | ||
451 | if (num_periods > NUM_CCW) { | |
452 | dev_err(mxs_dma->dma_device.dev, | |
453 | "maximum number of sg exceeded: %d > %d\n", | |
454 | num_periods, NUM_CCW); | |
455 | goto err_out; | |
456 | } | |
457 | ||
458 | if (period_len > MAX_XFER_BYTES) { | |
459 | dev_err(mxs_dma->dma_device.dev, | |
460 | "maximum period size exceeded: %d > %d\n", | |
461 | period_len, MAX_XFER_BYTES); | |
462 | goto err_out; | |
463 | } | |
464 | ||
465 | while (buf < buf_len) { | |
466 | struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; | |
467 | ||
468 | if (i + 1 == num_periods) | |
469 | ccw->next = mxs_chan->ccw_phys; | |
470 | else | |
471 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); | |
472 | ||
473 | ccw->bufaddr = dma_addr; | |
474 | ccw->xfer_bytes = period_len; | |
475 | ||
476 | ccw->bits = 0; | |
477 | ccw->bits |= CCW_CHAIN; | |
478 | ccw->bits |= CCW_IRQ; | |
479 | ccw->bits |= CCW_HALT_ON_TERM; | |
480 | ccw->bits |= CCW_TERM_FLUSH; | |
db8196df | 481 | ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? |
a580b8c5 SG |
482 | MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); |
483 | ||
484 | dma_addr += period_len; | |
485 | buf += period_len; | |
486 | ||
487 | i++; | |
488 | } | |
6d23ea4b | 489 | mxs_chan->desc_count = i; |
a580b8c5 SG |
490 | |
491 | return &mxs_chan->desc; | |
492 | ||
493 | err_out: | |
494 | mxs_chan->status = DMA_ERROR; | |
495 | return NULL; | |
496 | } | |
497 | ||
498 | static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
499 | unsigned long arg) | |
500 | { | |
501 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
502 | int ret = 0; | |
503 | ||
504 | switch (cmd) { | |
505 | case DMA_TERMINATE_ALL: | |
a62bae98 | 506 | mxs_dma_reset_chan(mxs_chan); |
7ad7a345 | 507 | mxs_dma_disable_chan(mxs_chan); |
a580b8c5 SG |
508 | break; |
509 | case DMA_PAUSE: | |
510 | mxs_dma_pause_chan(mxs_chan); | |
511 | break; | |
512 | case DMA_RESUME: | |
513 | mxs_dma_resume_chan(mxs_chan); | |
514 | break; | |
515 | default: | |
516 | ret = -ENOSYS; | |
517 | } | |
518 | ||
519 | return ret; | |
520 | } | |
521 | ||
522 | static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, | |
523 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
524 | { | |
525 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
526 | dma_cookie_t last_used; | |
527 | ||
528 | last_used = chan->cookie; | |
4d4e58de | 529 | dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0); |
a580b8c5 SG |
530 | |
531 | return mxs_chan->status; | |
532 | } | |
533 | ||
534 | static void mxs_dma_issue_pending(struct dma_chan *chan) | |
535 | { | |
536 | /* | |
537 | * Nothing to do. We only have a single descriptor. | |
538 | */ | |
539 | } | |
540 | ||
541 | static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) | |
542 | { | |
543 | int ret; | |
544 | ||
759a2e30 | 545 | ret = clk_prepare_enable(mxs_dma->clk); |
a580b8c5 | 546 | if (ret) |
feb397de | 547 | return ret; |
a580b8c5 SG |
548 | |
549 | ret = mxs_reset_block(mxs_dma->base); | |
550 | if (ret) | |
551 | goto err_out; | |
552 | ||
553 | /* only major version matters */ | |
554 | mxs_dma->version = readl(mxs_dma->base + | |
555 | ((mxs_dma->dev_id == MXS_DMA_APBX) ? | |
556 | HW_APBX_VERSION : HW_APBH_VERSION)) >> | |
557 | BP_APBHX_VERSION_MAJOR; | |
558 | ||
559 | /* enable apbh burst */ | |
560 | if (dma_is_apbh()) { | |
561 | writel(BM_APBH_CTRL0_APB_BURST_EN, | |
562 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
563 | writel(BM_APBH_CTRL0_APB_BURST8_EN, | |
564 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
565 | } | |
566 | ||
567 | /* enable irq for all the channels */ | |
568 | writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, | |
569 | mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR); | |
570 | ||
a580b8c5 | 571 | err_out: |
57f2685c | 572 | clk_disable_unprepare(mxs_dma->clk); |
a580b8c5 SG |
573 | return ret; |
574 | } | |
575 | ||
576 | static int __init mxs_dma_probe(struct platform_device *pdev) | |
577 | { | |
578 | const struct platform_device_id *id_entry = | |
579 | platform_get_device_id(pdev); | |
580 | struct mxs_dma_engine *mxs_dma; | |
581 | struct resource *iores; | |
582 | int ret, i; | |
583 | ||
584 | mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL); | |
585 | if (!mxs_dma) | |
586 | return -ENOMEM; | |
587 | ||
588 | mxs_dma->dev_id = id_entry->driver_data; | |
589 | ||
590 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
591 | ||
592 | if (!request_mem_region(iores->start, resource_size(iores), | |
593 | pdev->name)) { | |
594 | ret = -EBUSY; | |
595 | goto err_request_region; | |
596 | } | |
597 | ||
598 | mxs_dma->base = ioremap(iores->start, resource_size(iores)); | |
599 | if (!mxs_dma->base) { | |
600 | ret = -ENOMEM; | |
601 | goto err_ioremap; | |
602 | } | |
603 | ||
604 | mxs_dma->clk = clk_get(&pdev->dev, NULL); | |
605 | if (IS_ERR(mxs_dma->clk)) { | |
606 | ret = PTR_ERR(mxs_dma->clk); | |
607 | goto err_clk; | |
608 | } | |
609 | ||
610 | dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); | |
611 | dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); | |
612 | ||
613 | INIT_LIST_HEAD(&mxs_dma->dma_device.channels); | |
614 | ||
615 | /* Initialize channel parameters */ | |
616 | for (i = 0; i < MXS_DMA_CHANNELS; i++) { | |
617 | struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; | |
618 | ||
619 | mxs_chan->mxs_dma = mxs_dma; | |
620 | mxs_chan->chan.device = &mxs_dma->dma_device; | |
8ac69546 | 621 | dma_cookie_init(&mxs_chan->chan); |
a580b8c5 SG |
622 | |
623 | tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, | |
624 | (unsigned long) mxs_chan); | |
625 | ||
626 | ||
627 | /* Add the channel to mxs_chan list */ | |
628 | list_add_tail(&mxs_chan->chan.device_node, | |
629 | &mxs_dma->dma_device.channels); | |
630 | } | |
631 | ||
632 | ret = mxs_dma_init(mxs_dma); | |
633 | if (ret) | |
634 | goto err_init; | |
635 | ||
636 | mxs_dma->dma_device.dev = &pdev->dev; | |
637 | ||
638 | /* mxs_dma gets 65535 bytes maximum sg size */ | |
639 | mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; | |
640 | dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); | |
641 | ||
642 | mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; | |
643 | mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; | |
644 | mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; | |
645 | mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; | |
646 | mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; | |
647 | mxs_dma->dma_device.device_control = mxs_dma_control; | |
648 | mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending; | |
649 | ||
650 | ret = dma_async_device_register(&mxs_dma->dma_device); | |
651 | if (ret) { | |
652 | dev_err(mxs_dma->dma_device.dev, "unable to register\n"); | |
653 | goto err_init; | |
654 | } | |
655 | ||
656 | dev_info(mxs_dma->dma_device.dev, "initialized\n"); | |
657 | ||
658 | return 0; | |
659 | ||
660 | err_init: | |
661 | clk_put(mxs_dma->clk); | |
662 | err_clk: | |
663 | iounmap(mxs_dma->base); | |
664 | err_ioremap: | |
665 | release_mem_region(iores->start, resource_size(iores)); | |
666 | err_request_region: | |
667 | kfree(mxs_dma); | |
668 | return ret; | |
669 | } | |
670 | ||
671 | static struct platform_device_id mxs_dma_type[] = { | |
672 | { | |
673 | .name = "mxs-dma-apbh", | |
674 | .driver_data = MXS_DMA_APBH, | |
675 | }, { | |
676 | .name = "mxs-dma-apbx", | |
677 | .driver_data = MXS_DMA_APBX, | |
2a9778ed AL |
678 | }, { |
679 | /* end of list */ | |
a580b8c5 SG |
680 | } |
681 | }; | |
682 | ||
683 | static struct platform_driver mxs_dma_driver = { | |
684 | .driver = { | |
685 | .name = "mxs-dma", | |
686 | }, | |
687 | .id_table = mxs_dma_type, | |
688 | }; | |
689 | ||
690 | static int __init mxs_dma_module_init(void) | |
691 | { | |
692 | return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); | |
693 | } | |
694 | subsys_initcall(mxs_dma_module_init); |