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Commit | Line | Data |
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a580b8c5 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * Refer to drivers/dma/imx-sdma.c | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/wait.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/semaphore.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/dmaengine.h> | |
24 | #include <linux/delay.h> | |
25 | ||
26 | #include <asm/irq.h> | |
27 | #include <mach/mxs.h> | |
28 | #include <mach/dma.h> | |
29 | #include <mach/common.h> | |
30 | ||
31 | /* | |
32 | * NOTE: The term "PIO" throughout the mxs-dma implementation means | |
33 | * PIO mode of mxs apbh-dma and apbx-dma. With this working mode, | |
34 | * dma can program the controller registers of peripheral devices. | |
35 | */ | |
36 | ||
37 | #define MXS_DMA_APBH 0 | |
38 | #define MXS_DMA_APBX 1 | |
39 | #define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH) | |
40 | ||
41 | #define APBH_VERSION_LATEST 3 | |
42 | #define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST) | |
43 | ||
44 | #define HW_APBHX_CTRL0 0x000 | |
45 | #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) | |
46 | #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) | |
a580b8c5 SG |
47 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 |
48 | #define HW_APBHX_CTRL1 0x010 | |
49 | #define HW_APBHX_CTRL2 0x020 | |
50 | #define HW_APBHX_CHANNEL_CTRL 0x030 | |
51 | #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16 | |
52 | #define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800) | |
53 | #define HW_APBX_VERSION 0x800 | |
54 | #define BP_APBHX_VERSION_MAJOR 24 | |
55 | #define HW_APBHX_CHn_NXTCMDAR(n) \ | |
56 | (((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70) | |
57 | #define HW_APBHX_CHn_SEMA(n) \ | |
58 | (((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70) | |
59 | ||
60 | /* | |
61 | * ccw bits definitions | |
62 | * | |
63 | * COMMAND: 0..1 (2) | |
64 | * CHAIN: 2 (1) | |
65 | * IRQ: 3 (1) | |
66 | * NAND_LOCK: 4 (1) - not implemented | |
67 | * NAND_WAIT4READY: 5 (1) - not implemented | |
68 | * DEC_SEM: 6 (1) | |
69 | * WAIT4END: 7 (1) | |
70 | * HALT_ON_TERMINATE: 8 (1) | |
71 | * TERMINATE_FLUSH: 9 (1) | |
72 | * RESERVED: 10..11 (2) | |
73 | * PIO_NUM: 12..15 (4) | |
74 | */ | |
75 | #define BP_CCW_COMMAND 0 | |
76 | #define BM_CCW_COMMAND (3 << 0) | |
77 | #define CCW_CHAIN (1 << 2) | |
78 | #define CCW_IRQ (1 << 3) | |
79 | #define CCW_DEC_SEM (1 << 6) | |
80 | #define CCW_WAIT4END (1 << 7) | |
81 | #define CCW_HALT_ON_TERM (1 << 8) | |
82 | #define CCW_TERM_FLUSH (1 << 9) | |
83 | #define BP_CCW_PIO_NUM 12 | |
84 | #define BM_CCW_PIO_NUM (0xf << 12) | |
85 | ||
86 | #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field) | |
87 | ||
88 | #define MXS_DMA_CMD_NO_XFER 0 | |
89 | #define MXS_DMA_CMD_WRITE 1 | |
90 | #define MXS_DMA_CMD_READ 2 | |
91 | #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */ | |
92 | ||
93 | struct mxs_dma_ccw { | |
94 | u32 next; | |
95 | u16 bits; | |
96 | u16 xfer_bytes; | |
97 | #define MAX_XFER_BYTES 0xff00 | |
98 | u32 bufaddr; | |
99 | #define MXS_PIO_WORDS 16 | |
100 | u32 pio_words[MXS_PIO_WORDS]; | |
101 | }; | |
102 | ||
103 | #define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw)) | |
104 | ||
105 | struct mxs_dma_chan { | |
106 | struct mxs_dma_engine *mxs_dma; | |
107 | struct dma_chan chan; | |
108 | struct dma_async_tx_descriptor desc; | |
109 | struct tasklet_struct tasklet; | |
110 | int chan_irq; | |
111 | struct mxs_dma_ccw *ccw; | |
112 | dma_addr_t ccw_phys; | |
6d23ea4b | 113 | int desc_count; |
a580b8c5 SG |
114 | enum dma_status status; |
115 | unsigned int flags; | |
116 | #define MXS_DMA_SG_LOOP (1 << 0) | |
117 | }; | |
118 | ||
119 | #define MXS_DMA_CHANNELS 16 | |
120 | #define MXS_DMA_CHANNELS_MASK 0xffff | |
121 | ||
122 | struct mxs_dma_engine { | |
123 | int dev_id; | |
124 | unsigned int version; | |
125 | void __iomem *base; | |
126 | struct clk *clk; | |
127 | struct dma_device dma_device; | |
128 | struct device_dma_parameters dma_parms; | |
129 | struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; | |
130 | }; | |
131 | ||
132 | static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) | |
133 | { | |
134 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
135 | int chan_id = mxs_chan->chan.chan_id; | |
136 | ||
137 | if (dma_is_apbh() && apbh_is_old()) | |
138 | writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), | |
139 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
140 | else | |
141 | writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), | |
142 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); | |
143 | } | |
144 | ||
145 | static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) | |
146 | { | |
147 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
148 | int chan_id = mxs_chan->chan.chan_id; | |
149 | ||
150 | /* set cmd_addr up */ | |
151 | writel(mxs_chan->ccw_phys, | |
152 | mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id)); | |
153 | ||
a580b8c5 SG |
154 | /* write 1 to SEMA to kick off the channel */ |
155 | writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id)); | |
156 | } | |
157 | ||
158 | static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) | |
159 | { | |
a580b8c5 SG |
160 | mxs_chan->status = DMA_SUCCESS; |
161 | } | |
162 | ||
163 | static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) | |
164 | { | |
165 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
166 | int chan_id = mxs_chan->chan.chan_id; | |
167 | ||
168 | /* freeze the channel */ | |
169 | if (dma_is_apbh() && apbh_is_old()) | |
170 | writel(1 << chan_id, | |
171 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
172 | else | |
173 | writel(1 << chan_id, | |
174 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); | |
175 | ||
176 | mxs_chan->status = DMA_PAUSED; | |
177 | } | |
178 | ||
179 | static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) | |
180 | { | |
181 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
182 | int chan_id = mxs_chan->chan.chan_id; | |
183 | ||
184 | /* unfreeze the channel */ | |
185 | if (dma_is_apbh() && apbh_is_old()) | |
186 | writel(1 << chan_id, | |
187 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR); | |
188 | else | |
189 | writel(1 << chan_id, | |
190 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR); | |
191 | ||
192 | mxs_chan->status = DMA_IN_PROGRESS; | |
193 | } | |
194 | ||
195 | static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan) | |
196 | { | |
197 | dma_cookie_t cookie = mxs_chan->chan.cookie; | |
198 | ||
199 | if (++cookie < 0) | |
200 | cookie = 1; | |
201 | ||
202 | mxs_chan->chan.cookie = cookie; | |
203 | mxs_chan->desc.cookie = cookie; | |
204 | ||
205 | return cookie; | |
206 | } | |
207 | ||
208 | static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan) | |
209 | { | |
210 | return container_of(chan, struct mxs_dma_chan, chan); | |
211 | } | |
212 | ||
213 | static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) | |
214 | { | |
215 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan); | |
216 | ||
217 | mxs_dma_enable_chan(mxs_chan); | |
218 | ||
219 | return mxs_dma_assign_cookie(mxs_chan); | |
220 | } | |
221 | ||
222 | static void mxs_dma_tasklet(unsigned long data) | |
223 | { | |
224 | struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data; | |
225 | ||
226 | if (mxs_chan->desc.callback) | |
227 | mxs_chan->desc.callback(mxs_chan->desc.callback_param); | |
228 | } | |
229 | ||
230 | static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) | |
231 | { | |
232 | struct mxs_dma_engine *mxs_dma = dev_id; | |
233 | u32 stat1, stat2; | |
234 | ||
235 | /* completion status */ | |
236 | stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1); | |
237 | stat1 &= MXS_DMA_CHANNELS_MASK; | |
238 | writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR); | |
239 | ||
240 | /* error status */ | |
241 | stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2); | |
242 | writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR); | |
243 | ||
244 | /* | |
245 | * When both completion and error of termination bits set at the | |
246 | * same time, we do not take it as an error. IOW, it only becomes | |
40031220 | 247 | * an error we need to handle here in case of either it's (1) a bus |
a580b8c5 SG |
248 | * error or (2) a termination error with no completion. |
249 | */ | |
250 | stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */ | |
251 | (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */ | |
252 | ||
253 | /* combine error and completion status for checking */ | |
254 | stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1; | |
255 | while (stat1) { | |
256 | int channel = fls(stat1) - 1; | |
257 | struct mxs_dma_chan *mxs_chan = | |
258 | &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS]; | |
259 | ||
260 | if (channel >= MXS_DMA_CHANNELS) { | |
261 | dev_dbg(mxs_dma->dma_device.dev, | |
262 | "%s: error in channel %d\n", __func__, | |
263 | channel - MXS_DMA_CHANNELS); | |
264 | mxs_chan->status = DMA_ERROR; | |
265 | mxs_dma_reset_chan(mxs_chan); | |
266 | } else { | |
267 | if (mxs_chan->flags & MXS_DMA_SG_LOOP) | |
268 | mxs_chan->status = DMA_IN_PROGRESS; | |
269 | else | |
270 | mxs_chan->status = DMA_SUCCESS; | |
271 | } | |
272 | ||
273 | stat1 &= ~(1 << channel); | |
274 | ||
275 | if (mxs_chan->status == DMA_SUCCESS) | |
4d4e58de | 276 | mxs_chan->chan.completed_cookie = mxs_chan->desc.cookie; |
a580b8c5 SG |
277 | |
278 | /* schedule tasklet on this channel */ | |
279 | tasklet_schedule(&mxs_chan->tasklet); | |
280 | } | |
281 | ||
282 | return IRQ_HANDLED; | |
283 | } | |
284 | ||
285 | static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) | |
286 | { | |
287 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
288 | struct mxs_dma_data *data = chan->private; | |
289 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
290 | int ret; | |
291 | ||
292 | if (!data) | |
293 | return -EINVAL; | |
294 | ||
295 | mxs_chan->chan_irq = data->chan_irq; | |
296 | ||
297 | mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, | |
298 | &mxs_chan->ccw_phys, GFP_KERNEL); | |
299 | if (!mxs_chan->ccw) { | |
300 | ret = -ENOMEM; | |
301 | goto err_alloc; | |
302 | } | |
303 | ||
304 | memset(mxs_chan->ccw, 0, PAGE_SIZE); | |
305 | ||
95bfea16 SG |
306 | if (mxs_chan->chan_irq != NO_IRQ) { |
307 | ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler, | |
308 | 0, "mxs-dma", mxs_dma); | |
309 | if (ret) | |
310 | goto err_irq; | |
311 | } | |
a580b8c5 | 312 | |
759a2e30 | 313 | ret = clk_prepare_enable(mxs_dma->clk); |
a580b8c5 SG |
314 | if (ret) |
315 | goto err_clk; | |
316 | ||
317 | mxs_dma_reset_chan(mxs_chan); | |
318 | ||
319 | dma_async_tx_descriptor_init(&mxs_chan->desc, chan); | |
320 | mxs_chan->desc.tx_submit = mxs_dma_tx_submit; | |
321 | ||
322 | /* the descriptor is ready */ | |
323 | async_tx_ack(&mxs_chan->desc); | |
324 | ||
325 | return 0; | |
326 | ||
327 | err_clk: | |
328 | free_irq(mxs_chan->chan_irq, mxs_dma); | |
329 | err_irq: | |
330 | dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, | |
331 | mxs_chan->ccw, mxs_chan->ccw_phys); | |
332 | err_alloc: | |
333 | return ret; | |
334 | } | |
335 | ||
336 | static void mxs_dma_free_chan_resources(struct dma_chan *chan) | |
337 | { | |
338 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
339 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
340 | ||
341 | mxs_dma_disable_chan(mxs_chan); | |
342 | ||
343 | free_irq(mxs_chan->chan_irq, mxs_dma); | |
344 | ||
345 | dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE, | |
346 | mxs_chan->ccw, mxs_chan->ccw_phys); | |
347 | ||
759a2e30 | 348 | clk_disable_unprepare(mxs_dma->clk); |
a580b8c5 SG |
349 | } |
350 | ||
351 | static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( | |
352 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 353 | unsigned int sg_len, enum dma_transfer_direction direction, |
a580b8c5 SG |
354 | unsigned long append) |
355 | { | |
356 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
357 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
358 | struct mxs_dma_ccw *ccw; | |
359 | struct scatterlist *sg; | |
360 | int i, j; | |
361 | u32 *pio; | |
6d23ea4b | 362 | int idx = append ? mxs_chan->desc_count : 0; |
a580b8c5 SG |
363 | |
364 | if (mxs_chan->status == DMA_IN_PROGRESS && !append) | |
365 | return NULL; | |
366 | ||
367 | if (sg_len + (append ? idx : 0) > NUM_CCW) { | |
368 | dev_err(mxs_dma->dma_device.dev, | |
369 | "maximum number of sg exceeded: %d > %d\n", | |
370 | sg_len, NUM_CCW); | |
371 | goto err_out; | |
372 | } | |
373 | ||
374 | mxs_chan->status = DMA_IN_PROGRESS; | |
375 | mxs_chan->flags = 0; | |
376 | ||
377 | /* | |
378 | * If the sg is prepared with append flag set, the sg | |
379 | * will be appended to the last prepared sg. | |
380 | */ | |
381 | if (append) { | |
382 | BUG_ON(idx < 1); | |
383 | ccw = &mxs_chan->ccw[idx - 1]; | |
384 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; | |
385 | ccw->bits |= CCW_CHAIN; | |
386 | ccw->bits &= ~CCW_IRQ; | |
387 | ccw->bits &= ~CCW_DEC_SEM; | |
388 | ccw->bits &= ~CCW_WAIT4END; | |
389 | } else { | |
390 | idx = 0; | |
391 | } | |
392 | ||
62268ce9 | 393 | if (direction == DMA_TRANS_NONE) { |
a580b8c5 SG |
394 | ccw = &mxs_chan->ccw[idx++]; |
395 | pio = (u32 *) sgl; | |
396 | ||
397 | for (j = 0; j < sg_len;) | |
398 | ccw->pio_words[j++] = *pio++; | |
399 | ||
400 | ccw->bits = 0; | |
401 | ccw->bits |= CCW_IRQ; | |
402 | ccw->bits |= CCW_DEC_SEM; | |
403 | ccw->bits |= CCW_WAIT4END; | |
404 | ccw->bits |= CCW_HALT_ON_TERM; | |
405 | ccw->bits |= CCW_TERM_FLUSH; | |
406 | ccw->bits |= BF_CCW(sg_len, PIO_NUM); | |
407 | ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); | |
408 | } else { | |
409 | for_each_sg(sgl, sg, sg_len, i) { | |
410 | if (sg->length > MAX_XFER_BYTES) { | |
411 | dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", | |
412 | sg->length, MAX_XFER_BYTES); | |
413 | goto err_out; | |
414 | } | |
415 | ||
416 | ccw = &mxs_chan->ccw[idx++]; | |
417 | ||
418 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; | |
419 | ccw->bufaddr = sg->dma_address; | |
420 | ccw->xfer_bytes = sg->length; | |
421 | ||
422 | ccw->bits = 0; | |
423 | ccw->bits |= CCW_CHAIN; | |
424 | ccw->bits |= CCW_HALT_ON_TERM; | |
425 | ccw->bits |= CCW_TERM_FLUSH; | |
db8196df | 426 | ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? |
a580b8c5 SG |
427 | MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, |
428 | COMMAND); | |
429 | ||
430 | if (i + 1 == sg_len) { | |
431 | ccw->bits &= ~CCW_CHAIN; | |
432 | ccw->bits |= CCW_IRQ; | |
433 | ccw->bits |= CCW_DEC_SEM; | |
434 | ccw->bits |= CCW_WAIT4END; | |
435 | } | |
436 | } | |
437 | } | |
6d23ea4b | 438 | mxs_chan->desc_count = idx; |
a580b8c5 SG |
439 | |
440 | return &mxs_chan->desc; | |
441 | ||
442 | err_out: | |
443 | mxs_chan->status = DMA_ERROR; | |
444 | return NULL; | |
445 | } | |
446 | ||
447 | static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( | |
448 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
db8196df | 449 | size_t period_len, enum dma_transfer_direction direction) |
a580b8c5 SG |
450 | { |
451 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
452 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | |
453 | int num_periods = buf_len / period_len; | |
454 | int i = 0, buf = 0; | |
455 | ||
456 | if (mxs_chan->status == DMA_IN_PROGRESS) | |
457 | return NULL; | |
458 | ||
459 | mxs_chan->status = DMA_IN_PROGRESS; | |
460 | mxs_chan->flags |= MXS_DMA_SG_LOOP; | |
461 | ||
462 | if (num_periods > NUM_CCW) { | |
463 | dev_err(mxs_dma->dma_device.dev, | |
464 | "maximum number of sg exceeded: %d > %d\n", | |
465 | num_periods, NUM_CCW); | |
466 | goto err_out; | |
467 | } | |
468 | ||
469 | if (period_len > MAX_XFER_BYTES) { | |
470 | dev_err(mxs_dma->dma_device.dev, | |
471 | "maximum period size exceeded: %d > %d\n", | |
472 | period_len, MAX_XFER_BYTES); | |
473 | goto err_out; | |
474 | } | |
475 | ||
476 | while (buf < buf_len) { | |
477 | struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i]; | |
478 | ||
479 | if (i + 1 == num_periods) | |
480 | ccw->next = mxs_chan->ccw_phys; | |
481 | else | |
482 | ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1); | |
483 | ||
484 | ccw->bufaddr = dma_addr; | |
485 | ccw->xfer_bytes = period_len; | |
486 | ||
487 | ccw->bits = 0; | |
488 | ccw->bits |= CCW_CHAIN; | |
489 | ccw->bits |= CCW_IRQ; | |
490 | ccw->bits |= CCW_HALT_ON_TERM; | |
491 | ccw->bits |= CCW_TERM_FLUSH; | |
db8196df | 492 | ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ? |
a580b8c5 SG |
493 | MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); |
494 | ||
495 | dma_addr += period_len; | |
496 | buf += period_len; | |
497 | ||
498 | i++; | |
499 | } | |
6d23ea4b | 500 | mxs_chan->desc_count = i; |
a580b8c5 SG |
501 | |
502 | return &mxs_chan->desc; | |
503 | ||
504 | err_out: | |
505 | mxs_chan->status = DMA_ERROR; | |
506 | return NULL; | |
507 | } | |
508 | ||
509 | static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
510 | unsigned long arg) | |
511 | { | |
512 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
513 | int ret = 0; | |
514 | ||
515 | switch (cmd) { | |
516 | case DMA_TERMINATE_ALL: | |
a62bae98 | 517 | mxs_dma_reset_chan(mxs_chan); |
7ad7a345 | 518 | mxs_dma_disable_chan(mxs_chan); |
a580b8c5 SG |
519 | break; |
520 | case DMA_PAUSE: | |
521 | mxs_dma_pause_chan(mxs_chan); | |
522 | break; | |
523 | case DMA_RESUME: | |
524 | mxs_dma_resume_chan(mxs_chan); | |
525 | break; | |
526 | default: | |
527 | ret = -ENOSYS; | |
528 | } | |
529 | ||
530 | return ret; | |
531 | } | |
532 | ||
533 | static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, | |
534 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
535 | { | |
536 | struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); | |
537 | dma_cookie_t last_used; | |
538 | ||
539 | last_used = chan->cookie; | |
4d4e58de | 540 | dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0); |
a580b8c5 SG |
541 | |
542 | return mxs_chan->status; | |
543 | } | |
544 | ||
545 | static void mxs_dma_issue_pending(struct dma_chan *chan) | |
546 | { | |
547 | /* | |
548 | * Nothing to do. We only have a single descriptor. | |
549 | */ | |
550 | } | |
551 | ||
552 | static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) | |
553 | { | |
554 | int ret; | |
555 | ||
759a2e30 | 556 | ret = clk_prepare_enable(mxs_dma->clk); |
a580b8c5 | 557 | if (ret) |
feb397de | 558 | return ret; |
a580b8c5 SG |
559 | |
560 | ret = mxs_reset_block(mxs_dma->base); | |
561 | if (ret) | |
562 | goto err_out; | |
563 | ||
564 | /* only major version matters */ | |
565 | mxs_dma->version = readl(mxs_dma->base + | |
566 | ((mxs_dma->dev_id == MXS_DMA_APBX) ? | |
567 | HW_APBX_VERSION : HW_APBH_VERSION)) >> | |
568 | BP_APBHX_VERSION_MAJOR; | |
569 | ||
570 | /* enable apbh burst */ | |
571 | if (dma_is_apbh()) { | |
572 | writel(BM_APBH_CTRL0_APB_BURST_EN, | |
573 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
574 | writel(BM_APBH_CTRL0_APB_BURST8_EN, | |
575 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | |
576 | } | |
577 | ||
578 | /* enable irq for all the channels */ | |
579 | writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, | |
580 | mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR); | |
581 | ||
a580b8c5 | 582 | err_out: |
57f2685c | 583 | clk_disable_unprepare(mxs_dma->clk); |
a580b8c5 SG |
584 | return ret; |
585 | } | |
586 | ||
587 | static int __init mxs_dma_probe(struct platform_device *pdev) | |
588 | { | |
589 | const struct platform_device_id *id_entry = | |
590 | platform_get_device_id(pdev); | |
591 | struct mxs_dma_engine *mxs_dma; | |
592 | struct resource *iores; | |
593 | int ret, i; | |
594 | ||
595 | mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL); | |
596 | if (!mxs_dma) | |
597 | return -ENOMEM; | |
598 | ||
599 | mxs_dma->dev_id = id_entry->driver_data; | |
600 | ||
601 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
602 | ||
603 | if (!request_mem_region(iores->start, resource_size(iores), | |
604 | pdev->name)) { | |
605 | ret = -EBUSY; | |
606 | goto err_request_region; | |
607 | } | |
608 | ||
609 | mxs_dma->base = ioremap(iores->start, resource_size(iores)); | |
610 | if (!mxs_dma->base) { | |
611 | ret = -ENOMEM; | |
612 | goto err_ioremap; | |
613 | } | |
614 | ||
615 | mxs_dma->clk = clk_get(&pdev->dev, NULL); | |
616 | if (IS_ERR(mxs_dma->clk)) { | |
617 | ret = PTR_ERR(mxs_dma->clk); | |
618 | goto err_clk; | |
619 | } | |
620 | ||
621 | dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask); | |
622 | dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask); | |
623 | ||
624 | INIT_LIST_HEAD(&mxs_dma->dma_device.channels); | |
625 | ||
626 | /* Initialize channel parameters */ | |
627 | for (i = 0; i < MXS_DMA_CHANNELS; i++) { | |
628 | struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; | |
629 | ||
630 | mxs_chan->mxs_dma = mxs_dma; | |
631 | mxs_chan->chan.device = &mxs_dma->dma_device; | |
632 | ||
633 | tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, | |
634 | (unsigned long) mxs_chan); | |
635 | ||
636 | ||
637 | /* Add the channel to mxs_chan list */ | |
638 | list_add_tail(&mxs_chan->chan.device_node, | |
639 | &mxs_dma->dma_device.channels); | |
640 | } | |
641 | ||
642 | ret = mxs_dma_init(mxs_dma); | |
643 | if (ret) | |
644 | goto err_init; | |
645 | ||
646 | mxs_dma->dma_device.dev = &pdev->dev; | |
647 | ||
648 | /* mxs_dma gets 65535 bytes maximum sg size */ | |
649 | mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; | |
650 | dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); | |
651 | ||
652 | mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; | |
653 | mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; | |
654 | mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status; | |
655 | mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg; | |
656 | mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic; | |
657 | mxs_dma->dma_device.device_control = mxs_dma_control; | |
658 | mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending; | |
659 | ||
660 | ret = dma_async_device_register(&mxs_dma->dma_device); | |
661 | if (ret) { | |
662 | dev_err(mxs_dma->dma_device.dev, "unable to register\n"); | |
663 | goto err_init; | |
664 | } | |
665 | ||
666 | dev_info(mxs_dma->dma_device.dev, "initialized\n"); | |
667 | ||
668 | return 0; | |
669 | ||
670 | err_init: | |
671 | clk_put(mxs_dma->clk); | |
672 | err_clk: | |
673 | iounmap(mxs_dma->base); | |
674 | err_ioremap: | |
675 | release_mem_region(iores->start, resource_size(iores)); | |
676 | err_request_region: | |
677 | kfree(mxs_dma); | |
678 | return ret; | |
679 | } | |
680 | ||
681 | static struct platform_device_id mxs_dma_type[] = { | |
682 | { | |
683 | .name = "mxs-dma-apbh", | |
684 | .driver_data = MXS_DMA_APBH, | |
685 | }, { | |
686 | .name = "mxs-dma-apbx", | |
687 | .driver_data = MXS_DMA_APBX, | |
2a9778ed AL |
688 | }, { |
689 | /* end of list */ | |
a580b8c5 SG |
690 | } |
691 | }; | |
692 | ||
693 | static struct platform_driver mxs_dma_driver = { | |
694 | .driver = { | |
695 | .name = "mxs-dma", | |
696 | }, | |
697 | .id_table = mxs_dma_type, | |
698 | }; | |
699 | ||
700 | static int __init mxs_dma_module_init(void) | |
701 | { | |
702 | return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); | |
703 | } | |
704 | subsys_initcall(mxs_dma_module_init); |