[mirror_ubuntu-artful-kernel.git] / drivers / dma / mxs-dma.c

/*
 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * Refer to drivers/dma/imx-sdma.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/semaphore.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/delay.h>

#include <asm/irq.h>
#include <mach/mxs.h>
#include <mach/dma.h>
#include <mach/common.h>

/*
 * NOTE: The term "PIO" throughout the mxs-dma implementation means
 * PIO mode of mxs apbh-dma and apbx-dma.  With this working mode,
 * dma can program the controller registers of peripheral devices.
 */

#define MXS_DMA_APBH		0
#define MXS_DMA_APBX		1
#define dma_is_apbh()		(mxs_dma->dev_id == MXS_DMA_APBH)

#define APBH_VERSION_LATEST	3
#define apbh_is_old()		(mxs_dma->version < APBH_VERSION_LATEST)

#define HW_APBHX_CTRL0				0x000
#define BM_APBH_CTRL0_APB_BURST8_EN		(1 << 29)
#define BM_APBH_CTRL0_APB_BURST_EN		(1 << 28)
#define BP_APBH_CTRL0_CLKGATE_CHANNEL		8
#define BP_APBH_CTRL0_RESET_CHANNEL		16
#define HW_APBHX_CTRL1				0x010
#define HW_APBHX_CTRL2				0x020
#define HW_APBHX_CHANNEL_CTRL			0x030
#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL	16
#define HW_APBH_VERSION				(cpu_is_mx23() ? 0x3f0 : 0x800)
#define HW_APBX_VERSION				0x800
#define BP_APBHX_VERSION_MAJOR			24
#define HW_APBHX_CHn_NXTCMDAR(n) \
	(((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70)
#define HW_APBHX_CHn_SEMA(n) \
	(((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70)

/*
 * ccw bits definitions
 *
 * COMMAND:		0..1	(2)
 * CHAIN:		2	(1)
 * IRQ:			3	(1)
 * NAND_LOCK:		4	(1) - not implemented
 * NAND_WAIT4READY:	5	(1) - not implemented
 * DEC_SEM:		6	(1)
 * WAIT4END:		7	(1)
 * HALT_ON_TERMINATE:	8	(1)
 * TERMINATE_FLUSH:	9	(1)
 * RESERVED:		10..11	(2)
 * PIO_NUM:		12..15	(4)
 */
#define BP_CCW_COMMAND		0
#define BM_CCW_COMMAND		(3 << 0)
#define CCW_CHAIN		(1 << 2)
#define CCW_IRQ			(1 << 3)
#define CCW_DEC_SEM		(1 << 6)
#define CCW_WAIT4END		(1 << 7)
#define CCW_HALT_ON_TERM	(1 << 8)
#define CCW_TERM_FLUSH		(1 << 9)
#define BP_CCW_PIO_NUM		12
#define BM_CCW_PIO_NUM		(0xf << 12)

#define BF_CCW(value, field)	(((value) << BP_CCW_##field) & BM_CCW_##field)

#define MXS_DMA_CMD_NO_XFER	0
#define MXS_DMA_CMD_WRITE	1
#define MXS_DMA_CMD_READ	2
#define MXS_DMA_CMD_DMA_SENSE	3	/* not implemented */

struct mxs_dma_ccw {
	u32		next;
	u16		bits;
	u16		xfer_bytes;
#define MAX_XFER_BYTES	0xff00
	u32		bufaddr;
#define MXS_PIO_WORDS	16
	u32		pio_words[MXS_PIO_WORDS];
};

#define NUM_CCW	(int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))

struct mxs_dma_chan {
	struct mxs_dma_engine		*mxs_dma;
	struct dma_chan			chan;
	struct dma_async_tx_descriptor	desc;
	struct tasklet_struct		tasklet;
	int				chan_irq;
	struct mxs_dma_ccw		*ccw;
	dma_addr_t			ccw_phys;
	int				desc_count;
	dma_cookie_t			last_completed;
	enum dma_status			status;
	unsigned int			flags;
#define MXS_DMA_SG_LOOP			(1 << 0)
};

#define MXS_DMA_CHANNELS		16
#define MXS_DMA_CHANNELS_MASK		0xffff

struct mxs_dma_engine {
	int				dev_id;
	unsigned int			version;
	void __iomem			*base;
	struct clk			*clk;
	struct dma_device		dma_device;
	struct device_dma_parameters	dma_parms;
	struct mxs_dma_chan		mxs_chans[MXS_DMA_CHANNELS];
};

static inline void mxs_dma_clkgate(struct mxs_dma_chan *mxs_chan, int enable)
{
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int chan_id = mxs_chan->chan.chan_id;
	int set_clr = enable ? MXS_CLR_ADDR : MXS_SET_ADDR;

	/* enable apbh channel clock */
	if (dma_is_apbh()) {
		if (apbh_is_old())
			writel(1 << (chan_id + BP_APBH_CTRL0_CLKGATE_CHANNEL),
				mxs_dma->base + HW_APBHX_CTRL0 + set_clr);
		else
			writel(1 << chan_id,
				mxs_dma->base + HW_APBHX_CTRL0 + set_clr);
	}
}

static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
{
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int chan_id = mxs_chan->chan.chan_id;

	if (dma_is_apbh() && apbh_is_old())
		writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
			mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	else
		writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
			mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
}

static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
{
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int chan_id = mxs_chan->chan.chan_id;

	/* clkgate needs to be enabled before writing other registers */
	mxs_dma_clkgate(mxs_chan, 1);

	/* set cmd_addr up */
	writel(mxs_chan->ccw_phys,
		mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id));

	/* write 1 to SEMA to kick off the channel */
	writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id));
}

static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
{
	/* disable apbh channel clock */
	mxs_dma_clkgate(mxs_chan, 0);

	mxs_chan->status = DMA_SUCCESS;
}

static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
{
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int chan_id = mxs_chan->chan.chan_id;

	/* freeze the channel */
	if (dma_is_apbh() && apbh_is_old())
		writel(1 << chan_id,
			mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	else
		writel(1 << chan_id,
			mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);

	mxs_chan->status = DMA_PAUSED;
}

static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
{
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int chan_id = mxs_chan->chan.chan_id;

	/* unfreeze the channel */
	if (dma_is_apbh() && apbh_is_old())
		writel(1 << chan_id,
			mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
	else
		writel(1 << chan_id,
			mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);

	mxs_chan->status = DMA_IN_PROGRESS;
}

static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan)
{
	dma_cookie_t cookie = mxs_chan->chan.cookie;

	if (++cookie < 0)
		cookie = 1;

	mxs_chan->chan.cookie = cookie;
	mxs_chan->desc.cookie = cookie;

	return cookie;
}

static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct mxs_dma_chan, chan);
}

static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan);

	mxs_dma_enable_chan(mxs_chan);

	return mxs_dma_assign_cookie(mxs_chan);
}

static void mxs_dma_tasklet(unsigned long data)
{
	struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;

	if (mxs_chan->desc.callback)
		mxs_chan->desc.callback(mxs_chan->desc.callback_param);
}

static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
{
	struct mxs_dma_engine *mxs_dma = dev_id;
	u32 stat1, stat2;

	/* completion status */
	stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
	stat1 &= MXS_DMA_CHANNELS_MASK;
	writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);

	/* error status */
	stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
	writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);

	/*
	 * When both completion and error of termination bits set at the
	 * same time, we do not take it as an error.  IOW, it only becomes
	 * an error we need to handle here in case of either it's (1) a bus
	 * error or (2) a termination error with no completion.
	 */
	stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */
		(~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */

	/* combine error and completion status for checking */
	stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1;
	while (stat1) {
		int channel = fls(stat1) - 1;
		struct mxs_dma_chan *mxs_chan =
			&mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS];

		if (channel >= MXS_DMA_CHANNELS) {
			dev_dbg(mxs_dma->dma_device.dev,
				"%s: error in channel %d\n", __func__,
				channel - MXS_DMA_CHANNELS);
			mxs_chan->status = DMA_ERROR;
			mxs_dma_reset_chan(mxs_chan);
		} else {
			if (mxs_chan->flags & MXS_DMA_SG_LOOP)
				mxs_chan->status = DMA_IN_PROGRESS;
			else
				mxs_chan->status = DMA_SUCCESS;
		}

		stat1 &= ~(1 << channel);

		if (mxs_chan->status == DMA_SUCCESS)
			mxs_chan->last_completed = mxs_chan->desc.cookie;

		/* schedule tasklet on this channel */
		tasklet_schedule(&mxs_chan->tasklet);
	}

	return IRQ_HANDLED;
}

static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	struct mxs_dma_data *data = chan->private;
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int ret;

	if (!data)
		return -EINVAL;

	mxs_chan->chan_irq = data->chan_irq;

	mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
				&mxs_chan->ccw_phys, GFP_KERNEL);
	if (!mxs_chan->ccw) {
		ret = -ENOMEM;
		goto err_alloc;
	}

	memset(mxs_chan->ccw, 0, PAGE_SIZE);

	if (mxs_chan->chan_irq != NO_IRQ) {
		ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
					0, "mxs-dma", mxs_dma);
		if (ret)
			goto err_irq;
	}

	ret = clk_enable(mxs_dma->clk);
	if (ret)
		goto err_clk;

	/* clkgate needs to be enabled for reset to finish */
	mxs_dma_clkgate(mxs_chan, 1);
	mxs_dma_reset_chan(mxs_chan);
	mxs_dma_clkgate(mxs_chan, 0);

	dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
	mxs_chan->desc.tx_submit = mxs_dma_tx_submit;

	/* the descriptor is ready */
	async_tx_ack(&mxs_chan->desc);

	return 0;

err_clk:
	free_irq(mxs_chan->chan_irq, mxs_dma);
err_irq:
	dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
			mxs_chan->ccw, mxs_chan->ccw_phys);
err_alloc:
	return ret;
}

static void mxs_dma_free_chan_resources(struct dma_chan *chan)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;

	mxs_dma_disable_chan(mxs_chan);

	free_irq(mxs_chan->chan_irq, mxs_dma);

	dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
			mxs_chan->ccw, mxs_chan->ccw_phys);

	clk_disable(mxs_dma->clk);
}

static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_transfer_direction direction,
		unsigned long append)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	struct mxs_dma_ccw *ccw;
	struct scatterlist *sg;
	int i, j;
	u32 *pio;
	int idx = append ? mxs_chan->desc_count : 0;

	if (mxs_chan->status == DMA_IN_PROGRESS && !append)
		return NULL;

	if (sg_len + (append ? idx : 0) > NUM_CCW) {
		dev_err(mxs_dma->dma_device.dev,
				"maximum number of sg exceeded: %d > %d\n",
				sg_len, NUM_CCW);
		goto err_out;
	}

	mxs_chan->status = DMA_IN_PROGRESS;
	mxs_chan->flags = 0;

	/*
	 * If the sg is prepared with append flag set, the sg
	 * will be appended to the last prepared sg.
	 */
	if (append) {
		BUG_ON(idx < 1);
		ccw = &mxs_chan->ccw[idx - 1];
		ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
		ccw->bits |= CCW_CHAIN;
		ccw->bits &= ~CCW_IRQ;
		ccw->bits &= ~CCW_DEC_SEM;
		ccw->bits &= ~CCW_WAIT4END;
	} else {
		idx = 0;
	}

	if (direction == DMA_NONE) {
		ccw = &mxs_chan->ccw[idx++];
		pio = (u32 *) sgl;

		for (j = 0; j < sg_len;)
			ccw->pio_words[j++] = *pio++;

		ccw->bits = 0;
		ccw->bits |= CCW_IRQ;
		ccw->bits |= CCW_DEC_SEM;
		ccw->bits |= CCW_WAIT4END;
		ccw->bits |= CCW_HALT_ON_TERM;
		ccw->bits |= CCW_TERM_FLUSH;
		ccw->bits |= BF_CCW(sg_len, PIO_NUM);
		ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
	} else {
		for_each_sg(sgl, sg, sg_len, i) {
			if (sg->length > MAX_XFER_BYTES) {
				dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
						sg->length, MAX_XFER_BYTES);
				goto err_out;
			}

			ccw = &mxs_chan->ccw[idx++];

			ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
			ccw->bufaddr = sg->dma_address;
			ccw->xfer_bytes = sg->length;

			ccw->bits = 0;
			ccw->bits |= CCW_CHAIN;
			ccw->bits |= CCW_HALT_ON_TERM;
			ccw->bits |= CCW_TERM_FLUSH;
			ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
					MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
					COMMAND);

			if (i + 1 == sg_len) {
				ccw->bits &= ~CCW_CHAIN;
				ccw->bits |= CCW_IRQ;
				ccw->bits |= CCW_DEC_SEM;
				ccw->bits |= CCW_WAIT4END;
			}
		}
	}
	mxs_chan->desc_count = idx;

	return &mxs_chan->desc;

err_out:
	mxs_chan->status = DMA_ERROR;
	return NULL;
}

static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
		size_t period_len, enum dma_transfer_direction direction)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int num_periods = buf_len / period_len;
	int i = 0, buf = 0;

	if (mxs_chan->status == DMA_IN_PROGRESS)
		return NULL;

	mxs_chan->status = DMA_IN_PROGRESS;
	mxs_chan->flags |= MXS_DMA_SG_LOOP;

	if (num_periods > NUM_CCW) {
		dev_err(mxs_dma->dma_device.dev,
				"maximum number of sg exceeded: %d > %d\n",
				num_periods, NUM_CCW);
		goto err_out;
	}

	if (period_len > MAX_XFER_BYTES) {
		dev_err(mxs_dma->dma_device.dev,
				"maximum period size exceeded: %d > %d\n",
				period_len, MAX_XFER_BYTES);
		goto err_out;
	}

	while (buf < buf_len) {
		struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];

		if (i + 1 == num_periods)
			ccw->next = mxs_chan->ccw_phys;
		else
			ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);

		ccw->bufaddr = dma_addr;
		ccw->xfer_bytes = period_len;

		ccw->bits = 0;
		ccw->bits |= CCW_CHAIN;
		ccw->bits |= CCW_IRQ;
		ccw->bits |= CCW_HALT_ON_TERM;
		ccw->bits |= CCW_TERM_FLUSH;
		ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
				MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);

		dma_addr += period_len;
		buf += period_len;

		i++;
	}
	mxs_chan->desc_count = i;

	return &mxs_chan->desc;

err_out:
	mxs_chan->status = DMA_ERROR;
	return NULL;
}

static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
		unsigned long arg)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	int ret = 0;

	switch (cmd) {
	case DMA_TERMINATE_ALL:
		mxs_dma_disable_chan(mxs_chan);
		mxs_dma_reset_chan(mxs_chan);
		break;
	case DMA_PAUSE:
		mxs_dma_pause_chan(mxs_chan);
		break;
	case DMA_RESUME:
		mxs_dma_resume_chan(mxs_chan);
		break;
	default:
		ret = -ENOSYS;
	}

	return ret;
}

static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
			dma_cookie_t cookie, struct dma_tx_state *txstate)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	dma_cookie_t last_used;

	last_used = chan->cookie;
	dma_set_tx_state(txstate, mxs_chan->last_completed, last_used, 0);

	return mxs_chan->status;
}

static void mxs_dma_issue_pending(struct dma_chan *chan)
{
	/*
	 * Nothing to do. We only have a single descriptor.
	 */
}

static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
{
	int ret;

	ret = clk_enable(mxs_dma->clk);
	if (ret)
		return ret;

	ret = mxs_reset_block(mxs_dma->base);
	if (ret)
		goto err_out;

	/* only major version matters */
	mxs_dma->version = readl(mxs_dma->base +
				((mxs_dma->dev_id == MXS_DMA_APBX) ?
				HW_APBX_VERSION : HW_APBH_VERSION)) >>
				BP_APBHX_VERSION_MAJOR;

	/* enable apbh burst */
	if (dma_is_apbh()) {
		writel(BM_APBH_CTRL0_APB_BURST_EN,
			mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
		writel(BM_APBH_CTRL0_APB_BURST8_EN,
			mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	}

	/* enable irq for all the channels */
	writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
		mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);

err_out:
	clk_disable(mxs_dma->clk);
	return ret;
}

static int __init mxs_dma_probe(struct platform_device *pdev)
{
	const struct platform_device_id *id_entry =
				platform_get_device_id(pdev);
	struct mxs_dma_engine *mxs_dma;
	struct resource *iores;
	int ret, i;

	mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL);
	if (!mxs_dma)
		return -ENOMEM;

	mxs_dma->dev_id = id_entry->driver_data;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!request_mem_region(iores->start, resource_size(iores),
				pdev->name)) {
		ret = -EBUSY;
		goto err_request_region;
	}

	mxs_dma->base = ioremap(iores->start, resource_size(iores));
	if (!mxs_dma->base) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	mxs_dma->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(mxs_dma->clk)) {
		ret = PTR_ERR(mxs_dma->clk);
		goto err_clk;
	}

	dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
	dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);

	INIT_LIST_HEAD(&mxs_dma->dma_device.channels);

	/* Initialize channel parameters */
	for (i = 0; i < MXS_DMA_CHANNELS; i++) {
		struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];

		mxs_chan->mxs_dma = mxs_dma;
		mxs_chan->chan.device = &mxs_dma->dma_device;

		tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
			     (unsigned long) mxs_chan);


		/* Add the channel to mxs_chan list */
		list_add_tail(&mxs_chan->chan.device_node,
			&mxs_dma->dma_device.channels);
	}

	ret = mxs_dma_init(mxs_dma);
	if (ret)
		goto err_init;

	mxs_dma->dma_device.dev = &pdev->dev;

	/* mxs_dma gets 65535 bytes maximum sg size */
	mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
	dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);

	mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
	mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
	mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
	mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
	mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
	mxs_dma->dma_device.device_control = mxs_dma_control;
	mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;

	ret = dma_async_device_register(&mxs_dma->dma_device);
	if (ret) {
		dev_err(mxs_dma->dma_device.dev, "unable to register\n");
		goto err_init;
	}

	dev_info(mxs_dma->dma_device.dev, "initialized\n");

	return 0;

err_init:
	clk_put(mxs_dma->clk);
err_clk:
	iounmap(mxs_dma->base);
err_ioremap:
	release_mem_region(iores->start, resource_size(iores));
err_request_region:
	kfree(mxs_dma);
	return ret;
}

static struct platform_device_id mxs_dma_type[] = {
	{
		.name = "mxs-dma-apbh",
		.driver_data = MXS_DMA_APBH,
	}, {
		.name = "mxs-dma-apbx",
		.driver_data = MXS_DMA_APBX,
	}, {
		/* end of list */
	}
};

static struct platform_driver mxs_dma_driver = {
	.driver		= {
		.name	= "mxs-dma",
	},
	.id_table	= mxs_dma_type,
};

static int __init mxs_dma_module_init(void)
{
	return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
}
subsys_initcall(mxs_dma_module_init);
Commit	Line	Data
a580b8c5 SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* Refer to drivers/dma/imx-sdma.c
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/types.h>
	13	#include <linux/mm.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/clk.h>
	16	#include <linux/wait.h>
	17	#include <linux/sched.h>
	18	#include <linux/semaphore.h>
	19	#include <linux/device.h>
	20	#include <linux/dma-mapping.h>
	21	#include <linux/slab.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/dmaengine.h>
	24	#include <linux/delay.h>
	25
	26	#include <asm/irq.h>
	27	#include <mach/mxs.h>
	28	#include <mach/dma.h>
	29	#include <mach/common.h>
	30
	31	/*
	32	* NOTE: The term "PIO" throughout the mxs-dma implementation means
	33	* PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
	34	* dma can program the controller registers of peripheral devices.
	35	*/
	36
	37	#define MXS_DMA_APBH 0
	38	#define MXS_DMA_APBX 1
	39	#define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH)
	40
	41	#define APBH_VERSION_LATEST 3
	42	#define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST)
	43
	44	#define HW_APBHX_CTRL0 0x000
	45	#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
	46	#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
	47	#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8
	48	#define BP_APBH_CTRL0_RESET_CHANNEL 16
	49	#define HW_APBHX_CTRL1 0x010
	50	#define HW_APBHX_CTRL2 0x020
	51	#define HW_APBHX_CHANNEL_CTRL 0x030
	52	#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
	53	#define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800)
	54	#define HW_APBX_VERSION 0x800
	55	#define BP_APBHX_VERSION_MAJOR 24
	56	#define HW_APBHX_CHn_NXTCMDAR(n) \
	57	(((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70)
	58	#define HW_APBHX_CHn_SEMA(n) \
	59	(((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70)
	60
	61	/*
	62	* ccw bits definitions
	63	*
	64	* COMMAND: 0..1 (2)
65	* CHAIN: 2 (1)
66	* IRQ: 3 (1)
67	* NAND_LOCK: 4 (1) - not implemented
68	* NAND_WAIT4READY: 5 (1) - not implemented
69	* DEC_SEM: 6 (1)
70	* WAIT4END: 7 (1)
71	* HALT_ON_TERMINATE: 8 (1)
72	* TERMINATE_FLUSH: 9 (1)
73	* RESERVED: 10..11 (2)
74	* PIO_NUM: 12..15 (4)
75	*/
76	#define BP_CCW_COMMAND 0
77	#define BM_CCW_COMMAND (3 << 0)
78	#define CCW_CHAIN (1 << 2)
79	#define CCW_IRQ (1 << 3)
80	#define CCW_DEC_SEM (1 << 6)
81	#define CCW_WAIT4END (1 << 7)
82	#define CCW_HALT_ON_TERM (1 << 8)
83	#define CCW_TERM_FLUSH (1 << 9)
84	#define BP_CCW_PIO_NUM 12
85	#define BM_CCW_PIO_NUM (0xf << 12)
86
87	#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
88
89	#define MXS_DMA_CMD_NO_XFER 0
90	#define MXS_DMA_CMD_WRITE 1
91	#define MXS_DMA_CMD_READ 2
92	#define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
93
94	struct mxs_dma_ccw {
95	u32 next;
96	u16 bits;
97	u16 xfer_bytes;
98	#define MAX_XFER_BYTES 0xff00
99	u32 bufaddr;
100	#define MXS_PIO_WORDS 16
101	u32 pio_words[MXS_PIO_WORDS];
102	};
103
104	#define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))
105
106	struct mxs_dma_chan {
107	struct mxs_dma_engine *mxs_dma;
108	struct dma_chan chan;
109	struct dma_async_tx_descriptor desc;
110	struct tasklet_struct tasklet;
111	int chan_irq;
112	struct mxs_dma_ccw *ccw;
113	dma_addr_t ccw_phys;
6d23ea4b	114	int desc_count;
a580b8c5 SG	115	dma_cookie_t last_completed;
	116	enum dma_status status;
	117	unsigned int flags;
	118	#define MXS_DMA_SG_LOOP (1 << 0)
	119	};
	120
	121	#define MXS_DMA_CHANNELS 16
	122	#define MXS_DMA_CHANNELS_MASK 0xffff
	123
	124	struct mxs_dma_engine {
	125	int dev_id;
	126	unsigned int version;
	127	void __iomem *base;
	128	struct clk *clk;
	129	struct dma_device dma_device;
	130	struct device_dma_parameters dma_parms;
	131	struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
	132	};
	133
ef298c21 LW	134	static inline void mxs_dma_clkgate(struct mxs_dma_chan *mxs_chan, int enable)
	135	{
	136	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	137	int chan_id = mxs_chan->chan.chan_id;
	138	int set_clr = enable ? MXS_CLR_ADDR : MXS_SET_ADDR;
	139
	140	/* enable apbh channel clock */
	141	if (dma_is_apbh()) {
	142	if (apbh_is_old())
	143	writel(1 << (chan_id + BP_APBH_CTRL0_CLKGATE_CHANNEL),
	144	mxs_dma->base + HW_APBHX_CTRL0 + set_clr);
	145	else
	146	writel(1 << chan_id,
	147	mxs_dma->base + HW_APBHX_CTRL0 + set_clr);
	148	}
	149	}
	150
a580b8c5 SG	151	static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
	152	{
	153	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	154	int chan_id = mxs_chan->chan.chan_id;
	155
	156	if (dma_is_apbh() && apbh_is_old())
	157	writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
	158	mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	159	else
	160	writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
	161	mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
	162	}
	163
	164	static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
	165	{
	166	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	167	int chan_id = mxs_chan->chan.chan_id;
	168
ef298c21 LW	169	/* clkgate needs to be enabled before writing other registers */
	170	mxs_dma_clkgate(mxs_chan, 1);
	171
a580b8c5 SG	172	/* set cmd_addr up */
	173	writel(mxs_chan->ccw_phys,
	174	mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id));
	175
a580b8c5 SG	176	/* write 1 to SEMA to kick off the channel */
	177	writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id));
	178	}
	179
	180	static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
	181	{
a580b8c5	182	/* disable apbh channel clock */
ef298c21	183	mxs_dma_clkgate(mxs_chan, 0);
a580b8c5 SG	184
	185	mxs_chan->status = DMA_SUCCESS;
	186	}
	187
	188	static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
	189	{
	190	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	191	int chan_id = mxs_chan->chan.chan_id;
	192
	193	/* freeze the channel */
	194	if (dma_is_apbh() && apbh_is_old())
	195	writel(1 << chan_id,
	196	mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	197	else
	198	writel(1 << chan_id,
	199	mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
	200
	201	mxs_chan->status = DMA_PAUSED;
	202	}
	203
	204	static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
	205	{
	206	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	207	int chan_id = mxs_chan->chan.chan_id;
	208
	209	/* unfreeze the channel */
	210	if (dma_is_apbh() && apbh_is_old())
	211	writel(1 << chan_id,
	212	mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
	213	else
	214	writel(1 << chan_id,
	215	mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);
	216
	217	mxs_chan->status = DMA_IN_PROGRESS;
	218	}
	219
	220	static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan)
	221	{
	222	dma_cookie_t cookie = mxs_chan->chan.cookie;
	223
	224	if (++cookie < 0)
	225	cookie = 1;
	226
	227	mxs_chan->chan.cookie = cookie;
	228	mxs_chan->desc.cookie = cookie;
	229
	230	return cookie;
	231	}
	232
	233	static struct mxs_dma_chan to_mxs_dma_chan(struct dma_chan chan)
	234	{
	235	return container_of(chan, struct mxs_dma_chan, chan);
	236	}
	237
	238	static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
	239	{
	240	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan);
	241
	242	mxs_dma_enable_chan(mxs_chan);
	243
	244	return mxs_dma_assign_cookie(mxs_chan);
	245	}
	246
	247	static void mxs_dma_tasklet(unsigned long data)
248	{
249	struct mxs_dma_chan mxs_chan = (struct mxs_dma_chan ) data;
250
251	if (mxs_chan->desc.callback)
252	mxs_chan->desc.callback(mxs_chan->desc.callback_param);
253	}
254
255	static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
256	{
257	struct mxs_dma_engine *mxs_dma = dev_id;
258	u32 stat1, stat2;
259
260	/* completion status */
261	stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
262	stat1 &= MXS_DMA_CHANNELS_MASK;
263	writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);
264
265	/* error status */
266	stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
267	writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);
268
269	/*
270	* When both completion and error of termination bits set at the
271	* same time, we do not take it as an error. IOW, it only becomes
40031220	272	* an error we need to handle here in case of either it's (1) a bus
a580b8c5 SG	273	* error or (2) a termination error with no completion.
	274	*/
	275	stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) \| /* (1) */
	276	(~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */
	277
	278	/* combine error and completion status for checking */
	279	stat1 = (stat2 << MXS_DMA_CHANNELS) \| stat1;
	280	while (stat1) {
	281	int channel = fls(stat1) - 1;
	282	struct mxs_dma_chan *mxs_chan =
	283	&mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS];
	284
	285	if (channel >= MXS_DMA_CHANNELS) {
	286	dev_dbg(mxs_dma->dma_device.dev,
	287	"%s: error in channel %d\n", __func__,
	288	channel - MXS_DMA_CHANNELS);
	289	mxs_chan->status = DMA_ERROR;
	290	mxs_dma_reset_chan(mxs_chan);
	291	} else {
	292	if (mxs_chan->flags & MXS_DMA_SG_LOOP)
	293	mxs_chan->status = DMA_IN_PROGRESS;
	294	else
	295	mxs_chan->status = DMA_SUCCESS;
	296	}
	297
	298	stat1 &= ~(1 << channel);
	299
	300	if (mxs_chan->status == DMA_SUCCESS)
	301	mxs_chan->last_completed = mxs_chan->desc.cookie;
	302
	303	/* schedule tasklet on this channel */
	304	tasklet_schedule(&mxs_chan->tasklet);
	305	}
	306
	307	return IRQ_HANDLED;
	308	}
	309
	310	static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
	311	{
	312	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	313	struct mxs_dma_data *data = chan->private;
	314	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	315	int ret;
	316
	317	if (!data)
	318	return -EINVAL;
	319
	320	mxs_chan->chan_irq = data->chan_irq;
	321
	322	mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
	323	&mxs_chan->ccw_phys, GFP_KERNEL);
	324	if (!mxs_chan->ccw) {
	325	ret = -ENOMEM;
	326	goto err_alloc;
	327	}
	328
	329	memset(mxs_chan->ccw, 0, PAGE_SIZE);
	330
95bfea16 SG	331	if (mxs_chan->chan_irq != NO_IRQ) {
	332	ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
	333	0, "mxs-dma", mxs_dma);
	334	if (ret)
	335	goto err_irq;
	336	}
a580b8c5 SG	337
	338	ret = clk_enable(mxs_dma->clk);
	339	if (ret)
	340	goto err_clk;
	341
ef298c21 LW	342	/* clkgate needs to be enabled for reset to finish */
ef298c21 LW	343	mxs_dma_clkgate(mxs_chan, 1);
a580b8c5	344	mxs_dma_reset_chan(mxs_chan);
ef298c21	345	mxs_dma_clkgate(mxs_chan, 0);
a580b8c5 SG	346
	347	dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
	348	mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
	349
	350	/* the descriptor is ready */
	351	async_tx_ack(&mxs_chan->desc);
	352
	353	return 0;
	354
	355	err_clk:
	356	free_irq(mxs_chan->chan_irq, mxs_dma);
	357	err_irq:
	358	dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
	359	mxs_chan->ccw, mxs_chan->ccw_phys);
	360	err_alloc:
	361	return ret;
	362	}
	363
	364	static void mxs_dma_free_chan_resources(struct dma_chan *chan)
	365	{
	366	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	367	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	368
	369	mxs_dma_disable_chan(mxs_chan);
	370
	371	free_irq(mxs_chan->chan_irq, mxs_dma);
	372
	373	dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
	374	mxs_chan->ccw, mxs_chan->ccw_phys);
	375
	376	clk_disable(mxs_dma->clk);
	377	}
	378
	379	static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
	380	struct dma_chan chan, struct scatterlist sgl,
db8196df	381	unsigned int sg_len, enum dma_transfer_direction direction,
a580b8c5 SG	382	unsigned long append)
	383	{
	384	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	385	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	386	struct mxs_dma_ccw *ccw;
	387	struct scatterlist *sg;
	388	int i, j;
	389	u32 *pio;
6d23ea4b	390	int idx = append ? mxs_chan->desc_count : 0;
a580b8c5 SG	391
	392	if (mxs_chan->status == DMA_IN_PROGRESS && !append)
	393	return NULL;
	394
	395	if (sg_len + (append ? idx : 0) > NUM_CCW) {
	396	dev_err(mxs_dma->dma_device.dev,
	397	"maximum number of sg exceeded: %d > %d\n",
	398	sg_len, NUM_CCW);
	399	goto err_out;
	400	}
	401
	402	mxs_chan->status = DMA_IN_PROGRESS;
	403	mxs_chan->flags = 0;
	404
	405	/*
	406	* If the sg is prepared with append flag set, the sg
	407	* will be appended to the last prepared sg.
	408	*/
	409	if (append) {
	410	BUG_ON(idx < 1);
	411	ccw = &mxs_chan->ccw[idx - 1];
	412	ccw->next = mxs_chan->ccw_phys + sizeof(ccw) idx;
	413	ccw->bits \|= CCW_CHAIN;
	414	ccw->bits &= ~CCW_IRQ;
	415	ccw->bits &= ~CCW_DEC_SEM;
	416	ccw->bits &= ~CCW_WAIT4END;
	417	} else {
	418	idx = 0;
	419	}
	420
	421	if (direction == DMA_NONE) {
	422	ccw = &mxs_chan->ccw[idx++];
	423	pio = (u32 *) sgl;
	424
	425	for (j = 0; j < sg_len;)
	426	ccw->pio_words[j++] = *pio++;
	427
	428	ccw->bits = 0;
	429	ccw->bits \|= CCW_IRQ;
	430	ccw->bits \|= CCW_DEC_SEM;
	431	ccw->bits \|= CCW_WAIT4END;
	432	ccw->bits \|= CCW_HALT_ON_TERM;
	433	ccw->bits \|= CCW_TERM_FLUSH;
	434	ccw->bits \|= BF_CCW(sg_len, PIO_NUM);
	435	ccw->bits \|= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
	436	} else {
	437	for_each_sg(sgl, sg, sg_len, i) {
	438	if (sg->length > MAX_XFER_BYTES) {
	439	dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
	440	sg->length, MAX_XFER_BYTES);
	441	goto err_out;
	442	}
	443
	444	ccw = &mxs_chan->ccw[idx++];
	445
	446	ccw->next = mxs_chan->ccw_phys + sizeof(ccw) idx;
	447	ccw->bufaddr = sg->dma_address;
	448	ccw->xfer_bytes = sg->length;
	449
	450	ccw->bits = 0;
	451	ccw->bits \|= CCW_CHAIN;
	452	ccw->bits \|= CCW_HALT_ON_TERM;
	453	ccw->bits \|= CCW_TERM_FLUSH;
db8196df	454	ccw->bits \|= BF_CCW(direction == DMA_DEV_TO_MEM ?
a580b8c5 SG	455	MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
	456	COMMAND);
	457
	458	if (i + 1 == sg_len) {
	459	ccw->bits &= ~CCW_CHAIN;
	460	ccw->bits \|= CCW_IRQ;
	461	ccw->bits \|= CCW_DEC_SEM;
	462	ccw->bits \|= CCW_WAIT4END;
	463	}
	464	}
	465	}
6d23ea4b	466	mxs_chan->desc_count = idx;
a580b8c5 SG	467
	468	return &mxs_chan->desc;
	469
	470	err_out:
	471	mxs_chan->status = DMA_ERROR;
	472	return NULL;
	473	}
	474
	475	static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
	476	struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
db8196df	477	size_t period_len, enum dma_transfer_direction direction)
a580b8c5 SG	478	{
	479	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	480	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	481	int num_periods = buf_len / period_len;
	482	int i = 0, buf = 0;
	483
	484	if (mxs_chan->status == DMA_IN_PROGRESS)
	485	return NULL;
	486
	487	mxs_chan->status = DMA_IN_PROGRESS;
	488	mxs_chan->flags \|= MXS_DMA_SG_LOOP;
	489
	490	if (num_periods > NUM_CCW) {
	491	dev_err(mxs_dma->dma_device.dev,
	492	"maximum number of sg exceeded: %d > %d\n",
	493	num_periods, NUM_CCW);
	494	goto err_out;
	495	}
	496
	497	if (period_len > MAX_XFER_BYTES) {
	498	dev_err(mxs_dma->dma_device.dev,
	499	"maximum period size exceeded: %d > %d\n",
	500	period_len, MAX_XFER_BYTES);
	501	goto err_out;
	502	}
	503
	504	while (buf < buf_len) {
	505	struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
	506
	507	if (i + 1 == num_periods)
	508	ccw->next = mxs_chan->ccw_phys;
	509	else
	510	ccw->next = mxs_chan->ccw_phys + sizeof(ccw) (i + 1);
	511
	512	ccw->bufaddr = dma_addr;
	513	ccw->xfer_bytes = period_len;
	514
	515	ccw->bits = 0;
	516	ccw->bits \|= CCW_CHAIN;
	517	ccw->bits \|= CCW_IRQ;
	518	ccw->bits \|= CCW_HALT_ON_TERM;
	519	ccw->bits \|= CCW_TERM_FLUSH;
db8196df	520	ccw->bits \|= BF_CCW(direction == DMA_DEV_TO_MEM ?
a580b8c5 SG	521	MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
	522
	523	dma_addr += period_len;
	524	buf += period_len;
	525
	526	i++;
	527	}
6d23ea4b	528	mxs_chan->desc_count = i;
a580b8c5 SG	529
	530	return &mxs_chan->desc;
	531
	532	err_out:
	533	mxs_chan->status = DMA_ERROR;
	534	return NULL;
	535	}
	536
	537	static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
	538	unsigned long arg)
	539	{
	540	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	541	int ret = 0;
	542
	543	switch (cmd) {
	544	case DMA_TERMINATE_ALL:
	545	mxs_dma_disable_chan(mxs_chan);
a62bae98	546	mxs_dma_reset_chan(mxs_chan);
a580b8c5 SG	547	break;
	548	case DMA_PAUSE:
	549	mxs_dma_pause_chan(mxs_chan);
	550	break;
	551	case DMA_RESUME:
	552	mxs_dma_resume_chan(mxs_chan);
	553	break;
	554	default:
	555	ret = -ENOSYS;
	556	}
	557
	558	return ret;
	559	}
	560
	561	static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
	562	dma_cookie_t cookie, struct dma_tx_state *txstate)
	563	{
	564	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	565	dma_cookie_t last_used;
	566
	567	last_used = chan->cookie;
	568	dma_set_tx_state(txstate, mxs_chan->last_completed, last_used, 0);
	569
	570	return mxs_chan->status;
	571	}
	572
	573	static void mxs_dma_issue_pending(struct dma_chan *chan)
	574	{
	575	/*
	576	* Nothing to do. We only have a single descriptor.
	577	*/
	578	}
	579
	580	static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
	581	{
	582	int ret;
	583
	584	ret = clk_enable(mxs_dma->clk);
	585	if (ret)
feb397de	586	return ret;
a580b8c5 SG	587
	588	ret = mxs_reset_block(mxs_dma->base);
	589	if (ret)
	590	goto err_out;
	591
	592	/* only major version matters */
	593	mxs_dma->version = readl(mxs_dma->base +
	594	((mxs_dma->dev_id == MXS_DMA_APBX) ?
	595	HW_APBX_VERSION : HW_APBH_VERSION)) >>
	596	BP_APBHX_VERSION_MAJOR;
	597
	598	/* enable apbh burst */
	599	if (dma_is_apbh()) {
	600	writel(BM_APBH_CTRL0_APB_BURST_EN,
	601	mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	602	writel(BM_APBH_CTRL0_APB_BURST8_EN,
	603	mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	604	}
	605
	606	/* enable irq for all the channels */
	607	writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
	608	mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);
	609
a580b8c5	610	err_out:
feb397de	611	clk_disable(mxs_dma->clk);
a580b8c5 SG	612	return ret;
	613	}
	614
	615	static int __init mxs_dma_probe(struct platform_device *pdev)
	616	{
	617	const struct platform_device_id *id_entry =
	618	platform_get_device_id(pdev);
	619	struct mxs_dma_engine *mxs_dma;
	620	struct resource *iores;
	621	int ret, i;
	622
	623	mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL);
	624	if (!mxs_dma)
	625	return -ENOMEM;
	626
	627	mxs_dma->dev_id = id_entry->driver_data;
	628
	629	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	630
	631	if (!request_mem_region(iores->start, resource_size(iores),
	632	pdev->name)) {
	633	ret = -EBUSY;
	634	goto err_request_region;
	635	}
	636
	637	mxs_dma->base = ioremap(iores->start, resource_size(iores));
	638	if (!mxs_dma->base) {
	639	ret = -ENOMEM;
	640	goto err_ioremap;
	641	}
	642
	643	mxs_dma->clk = clk_get(&pdev->dev, NULL);
	644	if (IS_ERR(mxs_dma->clk)) {
	645	ret = PTR_ERR(mxs_dma->clk);
	646	goto err_clk;
	647	}
	648
	649	dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
	650	dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
	651
	652	INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
	653
	654	/* Initialize channel parameters */
	655	for (i = 0; i < MXS_DMA_CHANNELS; i++) {
	656	struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
	657
	658	mxs_chan->mxs_dma = mxs_dma;
	659	mxs_chan->chan.device = &mxs_dma->dma_device;
	660
	661	tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
	662	(unsigned long) mxs_chan);
	663
	664
	665	/* Add the channel to mxs_chan list */
	666	list_add_tail(&mxs_chan->chan.device_node,
	667	&mxs_dma->dma_device.channels);
	668	}
	669
	670	ret = mxs_dma_init(mxs_dma);
	671	if (ret)
	672	goto err_init;
	673
	674	mxs_dma->dma_device.dev = &pdev->dev;
	675
676	/* mxs_dma gets 65535 bytes maximum sg size */
677	mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
678	dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
679
680	mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
681	mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
682	mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
683	mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
684	mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
685	mxs_dma->dma_device.device_control = mxs_dma_control;
686	mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
687
688	ret = dma_async_device_register(&mxs_dma->dma_device);
689	if (ret) {
690	dev_err(mxs_dma->dma_device.dev, "unable to register\n");
691	goto err_init;
692	}
693
694	dev_info(mxs_dma->dma_device.dev, "initialized\n");
695
696	return 0;
697
698	err_init:
699	clk_put(mxs_dma->clk);
700	err_clk:
701	iounmap(mxs_dma->base);
702	err_ioremap:
703	release_mem_region(iores->start, resource_size(iores));
704	err_request_region:
705	kfree(mxs_dma);
706	return ret;
707	}
708
709	static struct platform_device_id mxs_dma_type[] = {
710	{
711	.name = "mxs-dma-apbh",
712	.driver_data = MXS_DMA_APBH,
713	}, {
714	.name = "mxs-dma-apbx",
715	.driver_data = MXS_DMA_APBX,
2a9778ed AL	716	}, {
2a9778ed AL	717	/* end of list */
a580b8c5 SG	718	}
	719	};
	720
	721	static struct platform_driver mxs_dma_driver = {
	722	.driver = {
	723	.name = "mxs-dma",
	724	},
	725	.id_table = mxs_dma_type,
	726	};
	727
	728	static int __init mxs_dma_module_init(void)
	729	{
	730	return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
	731	}
	732	subsys_initcall(mxs_dma_module_init);