[mirror_ubuntu-hirsute-kernel.git] / drivers / dma / mxs-dma.c

/*
 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * Refer to drivers/dma/imx-sdma.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/semaphore.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/delay.h>
#include <linux/fsl/mxs-dma.h>

#include <asm/irq.h>
#include <mach/mxs.h>
#include <mach/common.h>

#include "dmaengine.h"

/*
 * NOTE: The term "PIO" throughout the mxs-dma implementation means
 * PIO mode of mxs apbh-dma and apbx-dma.  With this working mode,
 * dma can program the controller registers of peripheral devices.
 */

#define MXS_DMA_APBH		0
#define MXS_DMA_APBX		1
#define dma_is_apbh()		(mxs_dma->dev_id == MXS_DMA_APBH)

#define APBH_VERSION_LATEST	3
#define apbh_is_old()		(mxs_dma->version < APBH_VERSION_LATEST)

#define HW_APBHX_CTRL0				0x000
#define BM_APBH_CTRL0_APB_BURST8_EN		(1 << 29)
#define BM_APBH_CTRL0_APB_BURST_EN		(1 << 28)
#define BP_APBH_CTRL0_RESET_CHANNEL		16
#define HW_APBHX_CTRL1				0x010
#define HW_APBHX_CTRL2				0x020
#define HW_APBHX_CHANNEL_CTRL			0x030
#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL	16
#define HW_APBH_VERSION				(cpu_is_mx23() ? 0x3f0 : 0x800)
#define HW_APBX_VERSION				0x800
#define BP_APBHX_VERSION_MAJOR			24
#define HW_APBHX_CHn_NXTCMDAR(n) \
	(((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70)
#define HW_APBHX_CHn_SEMA(n) \
	(((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70)

/*
 * ccw bits definitions
 *
 * COMMAND:		0..1	(2)
 * CHAIN:		2	(1)
 * IRQ:			3	(1)
 * NAND_LOCK:		4	(1) - not implemented
 * NAND_WAIT4READY:	5	(1) - not implemented
 * DEC_SEM:		6	(1)
 * WAIT4END:		7	(1)
 * HALT_ON_TERMINATE:	8	(1)
 * TERMINATE_FLUSH:	9	(1)
 * RESERVED:		10..11	(2)
 * PIO_NUM:		12..15	(4)
 */
#define BP_CCW_COMMAND		0
#define BM_CCW_COMMAND		(3 << 0)
#define CCW_CHAIN		(1 << 2)
#define CCW_IRQ			(1 << 3)
#define CCW_DEC_SEM		(1 << 6)
#define CCW_WAIT4END		(1 << 7)
#define CCW_HALT_ON_TERM	(1 << 8)
#define CCW_TERM_FLUSH		(1 << 9)
#define BP_CCW_PIO_NUM		12
#define BM_CCW_PIO_NUM		(0xf << 12)

#define BF_CCW(value, field)	(((value) << BP_CCW_##field) & BM_CCW_##field)

#define MXS_DMA_CMD_NO_XFER	0
#define MXS_DMA_CMD_WRITE	1
#define MXS_DMA_CMD_READ	2
#define MXS_DMA_CMD_DMA_SENSE	3	/* not implemented */

struct mxs_dma_ccw {
	u32		next;
	u16		bits;
	u16		xfer_bytes;
#define MAX_XFER_BYTES	0xff00
	u32		bufaddr;
#define MXS_PIO_WORDS	16
	u32		pio_words[MXS_PIO_WORDS];
};

#define NUM_CCW	(int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))

struct mxs_dma_chan {
	struct mxs_dma_engine		*mxs_dma;
	struct dma_chan			chan;
	struct dma_async_tx_descriptor	desc;
	struct tasklet_struct		tasklet;
	int				chan_irq;
	struct mxs_dma_ccw		*ccw;
	dma_addr_t			ccw_phys;
	int				desc_count;
	enum dma_status			status;
	unsigned int			flags;
#define MXS_DMA_SG_LOOP			(1 << 0)
};

#define MXS_DMA_CHANNELS		16
#define MXS_DMA_CHANNELS_MASK		0xffff

struct mxs_dma_engine {
	int				dev_id;
	unsigned int			version;
	void __iomem			*base;
	struct clk			*clk;
	struct dma_device		dma_device;
	struct device_dma_parameters	dma_parms;
	struct mxs_dma_chan		mxs_chans[MXS_DMA_CHANNELS];
};

static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
{
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int chan_id = mxs_chan->chan.chan_id;

	if (dma_is_apbh() && apbh_is_old())
		writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
			mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	else
		writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
			mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
}

static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
{
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int chan_id = mxs_chan->chan.chan_id;

	/* set cmd_addr up */
	writel(mxs_chan->ccw_phys,
		mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id));

	/* write 1 to SEMA to kick off the channel */
	writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id));
}

static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
{
	mxs_chan->status = DMA_SUCCESS;
}

static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
{
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int chan_id = mxs_chan->chan.chan_id;

	/* freeze the channel */
	if (dma_is_apbh() && apbh_is_old())
		writel(1 << chan_id,
			mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	else
		writel(1 << chan_id,
			mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);

	mxs_chan->status = DMA_PAUSED;
}

static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
{
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int chan_id = mxs_chan->chan.chan_id;

	/* unfreeze the channel */
	if (dma_is_apbh() && apbh_is_old())
		writel(1 << chan_id,
			mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
	else
		writel(1 << chan_id,
			mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);

	mxs_chan->status = DMA_IN_PROGRESS;
}

static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct mxs_dma_chan, chan);
}

static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
{
	return dma_cookie_assign(tx);
}

static void mxs_dma_tasklet(unsigned long data)
{
	struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;

	if (mxs_chan->desc.callback)
		mxs_chan->desc.callback(mxs_chan->desc.callback_param);
}

static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
{
	struct mxs_dma_engine *mxs_dma = dev_id;
	u32 stat1, stat2;

	/* completion status */
	stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
	stat1 &= MXS_DMA_CHANNELS_MASK;
	writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);

	/* error status */
	stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
	writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);

	/*
	 * When both completion and error of termination bits set at the
	 * same time, we do not take it as an error.  IOW, it only becomes
	 * an error we need to handle here in case of either it's (1) a bus
	 * error or (2) a termination error with no completion.
	 */
	stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */
		(~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */

	/* combine error and completion status for checking */
	stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1;
	while (stat1) {
		int channel = fls(stat1) - 1;
		struct mxs_dma_chan *mxs_chan =
			&mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS];

		if (channel >= MXS_DMA_CHANNELS) {
			dev_dbg(mxs_dma->dma_device.dev,
				"%s: error in channel %d\n", __func__,
				channel - MXS_DMA_CHANNELS);
			mxs_chan->status = DMA_ERROR;
			mxs_dma_reset_chan(mxs_chan);
		} else {
			if (mxs_chan->flags & MXS_DMA_SG_LOOP)
				mxs_chan->status = DMA_IN_PROGRESS;
			else
				mxs_chan->status = DMA_SUCCESS;
		}

		stat1 &= ~(1 << channel);

		if (mxs_chan->status == DMA_SUCCESS)
			dma_cookie_complete(&mxs_chan->desc);

		/* schedule tasklet on this channel */
		tasklet_schedule(&mxs_chan->tasklet);
	}

	return IRQ_HANDLED;
}

static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	struct mxs_dma_data *data = chan->private;
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int ret;

	if (!data)
		return -EINVAL;

	mxs_chan->chan_irq = data->chan_irq;

	mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
				&mxs_chan->ccw_phys, GFP_KERNEL);
	if (!mxs_chan->ccw) {
		ret = -ENOMEM;
		goto err_alloc;
	}

	memset(mxs_chan->ccw, 0, PAGE_SIZE);

	if (mxs_chan->chan_irq != NO_IRQ) {
		ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
					0, "mxs-dma", mxs_dma);
		if (ret)
			goto err_irq;
	}

	ret = clk_prepare_enable(mxs_dma->clk);
	if (ret)
		goto err_clk;

	mxs_dma_reset_chan(mxs_chan);

	dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
	mxs_chan->desc.tx_submit = mxs_dma_tx_submit;

	/* the descriptor is ready */
	async_tx_ack(&mxs_chan->desc);

	return 0;

err_clk:
	free_irq(mxs_chan->chan_irq, mxs_dma);
err_irq:
	dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
			mxs_chan->ccw, mxs_chan->ccw_phys);
err_alloc:
	return ret;
}

static void mxs_dma_free_chan_resources(struct dma_chan *chan)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;

	mxs_dma_disable_chan(mxs_chan);

	free_irq(mxs_chan->chan_irq, mxs_dma);

	dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
			mxs_chan->ccw, mxs_chan->ccw_phys);

	clk_disable_unprepare(mxs_dma->clk);
}

/*
 * How to use the flags for ->device_prep_slave_sg() :
 *    [1] If there is only one DMA command in the DMA chain, the code should be:
 *            ......
 *            ->device_prep_slave_sg(DMA_CTRL_ACK);
 *            ......
 *    [2] If there are two DMA commands in the DMA chain, the code should be
 *            ......
 *            ->device_prep_slave_sg(0);
 *            ......
 *            ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 *            ......
 *    [3] If there are more than two DMA commands in the DMA chain, the code
 *        should be:
 *            ......
 *            ->device_prep_slave_sg(0);                                // First
 *            ......
 *            ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
 *            ......
 *            ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
 *            ......
 */
static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_transfer_direction direction,
		unsigned long flags, void *context)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	struct mxs_dma_ccw *ccw;
	struct scatterlist *sg;
	int i, j;
	u32 *pio;
	bool append = flags & DMA_PREP_INTERRUPT;
	int idx = append ? mxs_chan->desc_count : 0;

	if (mxs_chan->status == DMA_IN_PROGRESS && !append)
		return NULL;

	if (sg_len + (append ? idx : 0) > NUM_CCW) {
		dev_err(mxs_dma->dma_device.dev,
				"maximum number of sg exceeded: %d > %d\n",
				sg_len, NUM_CCW);
		goto err_out;
	}

	mxs_chan->status = DMA_IN_PROGRESS;
	mxs_chan->flags = 0;

	/*
	 * If the sg is prepared with append flag set, the sg
	 * will be appended to the last prepared sg.
	 */
	if (append) {
		BUG_ON(idx < 1);
		ccw = &mxs_chan->ccw[idx - 1];
		ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
		ccw->bits |= CCW_CHAIN;
		ccw->bits &= ~CCW_IRQ;
		ccw->bits &= ~CCW_DEC_SEM;
	} else {
		idx = 0;
	}

	if (direction == DMA_TRANS_NONE) {
		ccw = &mxs_chan->ccw[idx++];
		pio = (u32 *) sgl;

		for (j = 0; j < sg_len;)
			ccw->pio_words[j++] = *pio++;

		ccw->bits = 0;
		ccw->bits |= CCW_IRQ;
		ccw->bits |= CCW_DEC_SEM;
		if (flags & DMA_CTRL_ACK)
			ccw->bits |= CCW_WAIT4END;
		ccw->bits |= CCW_HALT_ON_TERM;
		ccw->bits |= CCW_TERM_FLUSH;
		ccw->bits |= BF_CCW(sg_len, PIO_NUM);
		ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
	} else {
		for_each_sg(sgl, sg, sg_len, i) {
			if (sg->length > MAX_XFER_BYTES) {
				dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
						sg->length, MAX_XFER_BYTES);
				goto err_out;
			}

			ccw = &mxs_chan->ccw[idx++];

			ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
			ccw->bufaddr = sg->dma_address;
			ccw->xfer_bytes = sg->length;

			ccw->bits = 0;
			ccw->bits |= CCW_CHAIN;
			ccw->bits |= CCW_HALT_ON_TERM;
			ccw->bits |= CCW_TERM_FLUSH;
			ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
					MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
					COMMAND);

			if (i + 1 == sg_len) {
				ccw->bits &= ~CCW_CHAIN;
				ccw->bits |= CCW_IRQ;
				ccw->bits |= CCW_DEC_SEM;
				if (flags & DMA_CTRL_ACK)
					ccw->bits |= CCW_WAIT4END;
			}
		}
	}
	mxs_chan->desc_count = idx;

	return &mxs_chan->desc;

err_out:
	mxs_chan->status = DMA_ERROR;
	return NULL;
}

static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
		size_t period_len, enum dma_transfer_direction direction,
		void *context)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	int num_periods = buf_len / period_len;
	int i = 0, buf = 0;

	if (mxs_chan->status == DMA_IN_PROGRESS)
		return NULL;

	mxs_chan->status = DMA_IN_PROGRESS;
	mxs_chan->flags |= MXS_DMA_SG_LOOP;

	if (num_periods > NUM_CCW) {
		dev_err(mxs_dma->dma_device.dev,
				"maximum number of sg exceeded: %d > %d\n",
				num_periods, NUM_CCW);
		goto err_out;
	}

	if (period_len > MAX_XFER_BYTES) {
		dev_err(mxs_dma->dma_device.dev,
				"maximum period size exceeded: %d > %d\n",
				period_len, MAX_XFER_BYTES);
		goto err_out;
	}

	while (buf < buf_len) {
		struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];

		if (i + 1 == num_periods)
			ccw->next = mxs_chan->ccw_phys;
		else
			ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);

		ccw->bufaddr = dma_addr;
		ccw->xfer_bytes = period_len;

		ccw->bits = 0;
		ccw->bits |= CCW_CHAIN;
		ccw->bits |= CCW_IRQ;
		ccw->bits |= CCW_HALT_ON_TERM;
		ccw->bits |= CCW_TERM_FLUSH;
		ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
				MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);

		dma_addr += period_len;
		buf += period_len;

		i++;
	}
	mxs_chan->desc_count = i;

	return &mxs_chan->desc;

err_out:
	mxs_chan->status = DMA_ERROR;
	return NULL;
}

static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
		unsigned long arg)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	int ret = 0;

	switch (cmd) {
	case DMA_TERMINATE_ALL:
		mxs_dma_reset_chan(mxs_chan);
		mxs_dma_disable_chan(mxs_chan);
		break;
	case DMA_PAUSE:
		mxs_dma_pause_chan(mxs_chan);
		break;
	case DMA_RESUME:
		mxs_dma_resume_chan(mxs_chan);
		break;
	default:
		ret = -ENOSYS;
	}

	return ret;
}

static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
			dma_cookie_t cookie, struct dma_tx_state *txstate)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	dma_cookie_t last_used;

	last_used = chan->cookie;
	dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);

	return mxs_chan->status;
}

static void mxs_dma_issue_pending(struct dma_chan *chan)
{
	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);

	mxs_dma_enable_chan(mxs_chan);
}

static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
{
	int ret;

	ret = clk_prepare_enable(mxs_dma->clk);
	if (ret)
		return ret;

	ret = mxs_reset_block(mxs_dma->base);
	if (ret)
		goto err_out;

	/* only major version matters */
	mxs_dma->version = readl(mxs_dma->base +
				((mxs_dma->dev_id == MXS_DMA_APBX) ?
				HW_APBX_VERSION : HW_APBH_VERSION)) >>
				BP_APBHX_VERSION_MAJOR;

	/* enable apbh burst */
	if (dma_is_apbh()) {
		writel(BM_APBH_CTRL0_APB_BURST_EN,
			mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
		writel(BM_APBH_CTRL0_APB_BURST8_EN,
			mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	}

	/* enable irq for all the channels */
	writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
		mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);

err_out:
	clk_disable_unprepare(mxs_dma->clk);
	return ret;
}

static int __init mxs_dma_probe(struct platform_device *pdev)
{
	const struct platform_device_id *id_entry =
				platform_get_device_id(pdev);
	struct mxs_dma_engine *mxs_dma;
	struct resource *iores;
	int ret, i;

	mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL);
	if (!mxs_dma)
		return -ENOMEM;

	mxs_dma->dev_id = id_entry->driver_data;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!request_mem_region(iores->start, resource_size(iores),
				pdev->name)) {
		ret = -EBUSY;
		goto err_request_region;
	}

	mxs_dma->base = ioremap(iores->start, resource_size(iores));
	if (!mxs_dma->base) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	mxs_dma->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(mxs_dma->clk)) {
		ret = PTR_ERR(mxs_dma->clk);
		goto err_clk;
	}

	dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
	dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);

	INIT_LIST_HEAD(&mxs_dma->dma_device.channels);

	/* Initialize channel parameters */
	for (i = 0; i < MXS_DMA_CHANNELS; i++) {
		struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];

		mxs_chan->mxs_dma = mxs_dma;
		mxs_chan->chan.device = &mxs_dma->dma_device;
		dma_cookie_init(&mxs_chan->chan);

		tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
			     (unsigned long) mxs_chan);


		/* Add the channel to mxs_chan list */
		list_add_tail(&mxs_chan->chan.device_node,
			&mxs_dma->dma_device.channels);
	}

	ret = mxs_dma_init(mxs_dma);
	if (ret)
		goto err_init;

	mxs_dma->dma_device.dev = &pdev->dev;

	/* mxs_dma gets 65535 bytes maximum sg size */
	mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
	dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);

	mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
	mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
	mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
	mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
	mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
	mxs_dma->dma_device.device_control = mxs_dma_control;
	mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;

	ret = dma_async_device_register(&mxs_dma->dma_device);
	if (ret) {
		dev_err(mxs_dma->dma_device.dev, "unable to register\n");
		goto err_init;
	}

	dev_info(mxs_dma->dma_device.dev, "initialized\n");

	return 0;

err_init:
	clk_put(mxs_dma->clk);
err_clk:
	iounmap(mxs_dma->base);
err_ioremap:
	release_mem_region(iores->start, resource_size(iores));
err_request_region:
	kfree(mxs_dma);
	return ret;
}

static struct platform_device_id mxs_dma_type[] = {
	{
		.name = "mxs-dma-apbh",
		.driver_data = MXS_DMA_APBH,
	}, {
		.name = "mxs-dma-apbx",
		.driver_data = MXS_DMA_APBX,
	}, {
		/* end of list */
	}
};

static struct platform_driver mxs_dma_driver = {
	.driver		= {
		.name	= "mxs-dma",
	},
	.id_table	= mxs_dma_type,
};

static int __init mxs_dma_module_init(void)
{
	return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
}
subsys_initcall(mxs_dma_module_init);
Commit	Line	Data
a580b8c5 SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* Refer to drivers/dma/imx-sdma.c
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/types.h>
	13	#include <linux/mm.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/clk.h>
	16	#include <linux/wait.h>
	17	#include <linux/sched.h>
	18	#include <linux/semaphore.h>
	19	#include <linux/device.h>
	20	#include <linux/dma-mapping.h>
	21	#include <linux/slab.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/dmaengine.h>
	24	#include <linux/delay.h>
39468604	25	#include <linux/fsl/mxs-dma.h>
a580b8c5 SG	26
	27	#include <asm/irq.h>
	28	#include <mach/mxs.h>
a580b8c5 SG	29	#include <mach/common.h>
a580b8c5 SG	30
d2ebfb33 RKAL	31	#include "dmaengine.h"
d2ebfb33 RKAL	32
a580b8c5 SG	33	/*
	34	* NOTE: The term "PIO" throughout the mxs-dma implementation means
	35	* PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
	36	* dma can program the controller registers of peripheral devices.
	37	*/
	38
	39	#define MXS_DMA_APBH 0
	40	#define MXS_DMA_APBX 1
	41	#define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH)
	42
	43	#define APBH_VERSION_LATEST 3
	44	#define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST)
	45
	46	#define HW_APBHX_CTRL0 0x000
	47	#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
	48	#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
a580b8c5 SG	49	#define BP_APBH_CTRL0_RESET_CHANNEL 16
	50	#define HW_APBHX_CTRL1 0x010
	51	#define HW_APBHX_CTRL2 0x020
	52	#define HW_APBHX_CHANNEL_CTRL 0x030
	53	#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
	54	#define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800)
	55	#define HW_APBX_VERSION 0x800
	56	#define BP_APBHX_VERSION_MAJOR 24
	57	#define HW_APBHX_CHn_NXTCMDAR(n) \
	58	(((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70)
	59	#define HW_APBHX_CHn_SEMA(n) \
	60	(((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70)
	61
	62	/*
	63	* ccw bits definitions
	64	*
	65	* COMMAND: 0..1 (2)
	66	* CHAIN: 2 (1)
	67	* IRQ: 3 (1)
	68	* NAND_LOCK: 4 (1) - not implemented
	69	* NAND_WAIT4READY: 5 (1) - not implemented
	70	* DEC_SEM: 6 (1)
	71	* WAIT4END: 7 (1)
	72	* HALT_ON_TERMINATE: 8 (1)
	73	* TERMINATE_FLUSH: 9 (1)
	74	* RESERVED: 10..11 (2)
	75	* PIO_NUM: 12..15 (4)
	76	*/
	77	#define BP_CCW_COMMAND 0
	78	#define BM_CCW_COMMAND (3 << 0)
	79	#define CCW_CHAIN (1 << 2)
	80	#define CCW_IRQ (1 << 3)
	81	#define CCW_DEC_SEM (1 << 6)
	82	#define CCW_WAIT4END (1 << 7)
	83	#define CCW_HALT_ON_TERM (1 << 8)
	84	#define CCW_TERM_FLUSH (1 << 9)
	85	#define BP_CCW_PIO_NUM 12
	86	#define BM_CCW_PIO_NUM (0xf << 12)
	87
	88	#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
	89
	90	#define MXS_DMA_CMD_NO_XFER 0
	91	#define MXS_DMA_CMD_WRITE 1
	92	#define MXS_DMA_CMD_READ 2
	93	#define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
	94
	95	struct mxs_dma_ccw {
	96	u32 next;
	97	u16 bits;
	98	u16 xfer_bytes;
	99	#define MAX_XFER_BYTES 0xff00
	100	u32 bufaddr;
	101	#define MXS_PIO_WORDS 16
	102	u32 pio_words[MXS_PIO_WORDS];
	103	};
	104
	105	#define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))
	106
	107	struct mxs_dma_chan {
	108	struct mxs_dma_engine *mxs_dma;
	109	struct dma_chan chan;
	110	struct dma_async_tx_descriptor desc;
	111	struct tasklet_struct tasklet;
	112	int chan_irq;
113	struct mxs_dma_ccw *ccw;
114	dma_addr_t ccw_phys;
6d23ea4b	115	int desc_count;
a580b8c5 SG	116	enum dma_status status;
	117	unsigned int flags;
	118	#define MXS_DMA_SG_LOOP (1 << 0)
	119	};
	120
	121	#define MXS_DMA_CHANNELS 16
	122	#define MXS_DMA_CHANNELS_MASK 0xffff
	123
	124	struct mxs_dma_engine {
	125	int dev_id;
	126	unsigned int version;
	127	void __iomem *base;
	128	struct clk *clk;
	129	struct dma_device dma_device;
	130	struct device_dma_parameters dma_parms;
	131	struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
	132	};
	133
	134	static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
	135	{
	136	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	137	int chan_id = mxs_chan->chan.chan_id;
	138
	139	if (dma_is_apbh() && apbh_is_old())
	140	writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
	141	mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	142	else
	143	writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
	144	mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
	145	}
	146
	147	static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
	148	{
	149	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	150	int chan_id = mxs_chan->chan.chan_id;
	151
	152	/* set cmd_addr up */
	153	writel(mxs_chan->ccw_phys,
	154	mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id));
	155
a580b8c5 SG	156	/* write 1 to SEMA to kick off the channel */
	157	writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id));
	158	}
	159
	160	static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
	161	{
a580b8c5 SG	162	mxs_chan->status = DMA_SUCCESS;
	163	}
	164
	165	static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
	166	{
	167	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	168	int chan_id = mxs_chan->chan.chan_id;
	169
	170	/* freeze the channel */
	171	if (dma_is_apbh() && apbh_is_old())
	172	writel(1 << chan_id,
	173	mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	174	else
	175	writel(1 << chan_id,
	176	mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
	177
	178	mxs_chan->status = DMA_PAUSED;
	179	}
	180
	181	static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
	182	{
	183	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	184	int chan_id = mxs_chan->chan.chan_id;
	185
	186	/* unfreeze the channel */
	187	if (dma_is_apbh() && apbh_is_old())
	188	writel(1 << chan_id,
	189	mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
	190	else
	191	writel(1 << chan_id,
	192	mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);
	193
	194	mxs_chan->status = DMA_IN_PROGRESS;
	195	}
	196
a580b8c5 SG	197	static struct mxs_dma_chan to_mxs_dma_chan(struct dma_chan chan)
	198	{
	199	return container_of(chan, struct mxs_dma_chan, chan);
	200	}
	201
	202	static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
	203	{
884485e1	204	return dma_cookie_assign(tx);
a580b8c5 SG	205	}
	206
	207	static void mxs_dma_tasklet(unsigned long data)
	208	{
	209	struct mxs_dma_chan mxs_chan = (struct mxs_dma_chan ) data;
	210
	211	if (mxs_chan->desc.callback)
	212	mxs_chan->desc.callback(mxs_chan->desc.callback_param);
	213	}
	214
	215	static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
	216	{
	217	struct mxs_dma_engine *mxs_dma = dev_id;
	218	u32 stat1, stat2;
	219
	220	/* completion status */
	221	stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
	222	stat1 &= MXS_DMA_CHANNELS_MASK;
	223	writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);
	224
	225	/* error status */
	226	stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
	227	writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);
	228
	229	/*
	230	* When both completion and error of termination bits set at the
	231	* same time, we do not take it as an error. IOW, it only becomes
40031220	232	* an error we need to handle here in case of either it's (1) a bus
a580b8c5 SG	233	* error or (2) a termination error with no completion.
	234	*/
	235	stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) \| /* (1) */
	236	(~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */
	237
	238	/* combine error and completion status for checking */
	239	stat1 = (stat2 << MXS_DMA_CHANNELS) \| stat1;
	240	while (stat1) {
	241	int channel = fls(stat1) - 1;
	242	struct mxs_dma_chan *mxs_chan =
	243	&mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS];
	244
	245	if (channel >= MXS_DMA_CHANNELS) {
	246	dev_dbg(mxs_dma->dma_device.dev,
	247	"%s: error in channel %d\n", __func__,
	248	channel - MXS_DMA_CHANNELS);
	249	mxs_chan->status = DMA_ERROR;
	250	mxs_dma_reset_chan(mxs_chan);
	251	} else {
	252	if (mxs_chan->flags & MXS_DMA_SG_LOOP)
	253	mxs_chan->status = DMA_IN_PROGRESS;
	254	else
	255	mxs_chan->status = DMA_SUCCESS;
	256	}
	257
	258	stat1 &= ~(1 << channel);
	259
	260	if (mxs_chan->status == DMA_SUCCESS)
f7fbce07	261	dma_cookie_complete(&mxs_chan->desc);
a580b8c5 SG	262
	263	/* schedule tasklet on this channel */
	264	tasklet_schedule(&mxs_chan->tasklet);
	265	}
	266
	267	return IRQ_HANDLED;
	268	}
	269
	270	static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
	271	{
	272	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	273	struct mxs_dma_data *data = chan->private;
	274	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	275	int ret;
	276
	277	if (!data)
	278	return -EINVAL;
	279
	280	mxs_chan->chan_irq = data->chan_irq;
	281
	282	mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
	283	&mxs_chan->ccw_phys, GFP_KERNEL);
	284	if (!mxs_chan->ccw) {
	285	ret = -ENOMEM;
	286	goto err_alloc;
	287	}
	288
	289	memset(mxs_chan->ccw, 0, PAGE_SIZE);
	290
95bfea16 SG	291	if (mxs_chan->chan_irq != NO_IRQ) {
	292	ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
	293	0, "mxs-dma", mxs_dma);
	294	if (ret)
	295	goto err_irq;
	296	}
a580b8c5	297
759a2e30	298	ret = clk_prepare_enable(mxs_dma->clk);
a580b8c5 SG	299	if (ret)
	300	goto err_clk;
	301
	302	mxs_dma_reset_chan(mxs_chan);
	303
	304	dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
	305	mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
	306
	307	/* the descriptor is ready */
	308	async_tx_ack(&mxs_chan->desc);
	309
	310	return 0;
	311
	312	err_clk:
	313	free_irq(mxs_chan->chan_irq, mxs_dma);
	314	err_irq:
	315	dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
	316	mxs_chan->ccw, mxs_chan->ccw_phys);
	317	err_alloc:
	318	return ret;
	319	}
	320
	321	static void mxs_dma_free_chan_resources(struct dma_chan *chan)
	322	{
	323	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	324	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	325
	326	mxs_dma_disable_chan(mxs_chan);
	327
	328	free_irq(mxs_chan->chan_irq, mxs_dma);
	329
	330	dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
	331	mxs_chan->ccw, mxs_chan->ccw_phys);
	332
759a2e30	333	clk_disable_unprepare(mxs_dma->clk);
a580b8c5 SG	334	}
a580b8c5 SG	335
921de864 HS	336	/*
	337	* How to use the flags for ->device_prep_slave_sg() :
	338	* [1] If there is only one DMA command in the DMA chain, the code should be:
	339	* ......
	340	* ->device_prep_slave_sg(DMA_CTRL_ACK);
	341	* ......
	342	* [2] If there are two DMA commands in the DMA chain, the code should be
	343	* ......
	344	* ->device_prep_slave_sg(0);
	345	* ......
	346	* ->device_prep_slave_sg(DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	347	* ......
	348	* [3] If there are more than two DMA commands in the DMA chain, the code
	349	* should be:
	350	* ......
	351	* ->device_prep_slave_sg(0); // First
	352	* ......
	353	* ->device_prep_slave_sg(DMA_PREP_INTERRUPT [\| DMA_CTRL_ACK]);
	354	* ......
	355	* ->device_prep_slave_sg(DMA_PREP_INTERRUPT \| DMA_CTRL_ACK); // Last
	356	* ......
	357	*/
a580b8c5 SG	358	static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
a580b8c5 SG	359	struct dma_chan chan, struct scatterlist sgl,
db8196df	360	unsigned int sg_len, enum dma_transfer_direction direction,
623ff773	361	unsigned long flags, void *context)
a580b8c5 SG	362	{
	363	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	364	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	365	struct mxs_dma_ccw *ccw;
	366	struct scatterlist *sg;
	367	int i, j;
	368	u32 *pio;
921de864	369	bool append = flags & DMA_PREP_INTERRUPT;
6d23ea4b	370	int idx = append ? mxs_chan->desc_count : 0;
a580b8c5 SG	371
	372	if (mxs_chan->status == DMA_IN_PROGRESS && !append)
	373	return NULL;
	374
	375	if (sg_len + (append ? idx : 0) > NUM_CCW) {
	376	dev_err(mxs_dma->dma_device.dev,
	377	"maximum number of sg exceeded: %d > %d\n",
	378	sg_len, NUM_CCW);
	379	goto err_out;
	380	}
	381
	382	mxs_chan->status = DMA_IN_PROGRESS;
	383	mxs_chan->flags = 0;
	384
	385	/*
	386	* If the sg is prepared with append flag set, the sg
	387	* will be appended to the last prepared sg.
	388	*/
	389	if (append) {
	390	BUG_ON(idx < 1);
	391	ccw = &mxs_chan->ccw[idx - 1];
	392	ccw->next = mxs_chan->ccw_phys + sizeof(ccw) idx;
	393	ccw->bits \|= CCW_CHAIN;
	394	ccw->bits &= ~CCW_IRQ;
	395	ccw->bits &= ~CCW_DEC_SEM;
a580b8c5 SG	396	} else {
	397	idx = 0;
	398	}
	399
62268ce9	400	if (direction == DMA_TRANS_NONE) {
a580b8c5 SG	401	ccw = &mxs_chan->ccw[idx++];
	402	pio = (u32 *) sgl;
	403
	404	for (j = 0; j < sg_len;)
	405	ccw->pio_words[j++] = *pio++;
	406
	407	ccw->bits = 0;
	408	ccw->bits \|= CCW_IRQ;
	409	ccw->bits \|= CCW_DEC_SEM;
921de864 HS	410	if (flags & DMA_CTRL_ACK)
921de864 HS	411	ccw->bits \|= CCW_WAIT4END;
a580b8c5 SG	412	ccw->bits \|= CCW_HALT_ON_TERM;
	413	ccw->bits \|= CCW_TERM_FLUSH;
	414	ccw->bits \|= BF_CCW(sg_len, PIO_NUM);
	415	ccw->bits \|= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
	416	} else {
	417	for_each_sg(sgl, sg, sg_len, i) {
	418	if (sg->length > MAX_XFER_BYTES) {
	419	dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
	420	sg->length, MAX_XFER_BYTES);
	421	goto err_out;
	422	}
	423
	424	ccw = &mxs_chan->ccw[idx++];
	425
	426	ccw->next = mxs_chan->ccw_phys + sizeof(ccw) idx;
	427	ccw->bufaddr = sg->dma_address;
	428	ccw->xfer_bytes = sg->length;
	429
	430	ccw->bits = 0;
	431	ccw->bits \|= CCW_CHAIN;
	432	ccw->bits \|= CCW_HALT_ON_TERM;
	433	ccw->bits \|= CCW_TERM_FLUSH;
db8196df	434	ccw->bits \|= BF_CCW(direction == DMA_DEV_TO_MEM ?
a580b8c5 SG	435	MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
	436	COMMAND);
	437
	438	if (i + 1 == sg_len) {
	439	ccw->bits &= ~CCW_CHAIN;
	440	ccw->bits \|= CCW_IRQ;
	441	ccw->bits \|= CCW_DEC_SEM;
921de864 HS	442	if (flags & DMA_CTRL_ACK)
921de864 HS	443	ccw->bits \|= CCW_WAIT4END;
a580b8c5 SG	444	}
	445	}
	446	}
6d23ea4b	447	mxs_chan->desc_count = idx;
a580b8c5 SG	448
	449	return &mxs_chan->desc;
	450
	451	err_out:
	452	mxs_chan->status = DMA_ERROR;
	453	return NULL;
	454	}
	455
	456	static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
	457	struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
185ecb5f AB	458	size_t period_len, enum dma_transfer_direction direction,
185ecb5f AB	459	void *context)
a580b8c5 SG	460	{
	461	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	462	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
	463	int num_periods = buf_len / period_len;
	464	int i = 0, buf = 0;
	465
	466	if (mxs_chan->status == DMA_IN_PROGRESS)
	467	return NULL;
	468
	469	mxs_chan->status = DMA_IN_PROGRESS;
	470	mxs_chan->flags \|= MXS_DMA_SG_LOOP;
	471
	472	if (num_periods > NUM_CCW) {
	473	dev_err(mxs_dma->dma_device.dev,
	474	"maximum number of sg exceeded: %d > %d\n",
	475	num_periods, NUM_CCW);
	476	goto err_out;
	477	}
	478
	479	if (period_len > MAX_XFER_BYTES) {
	480	dev_err(mxs_dma->dma_device.dev,
	481	"maximum period size exceeded: %d > %d\n",
	482	period_len, MAX_XFER_BYTES);
	483	goto err_out;
	484	}
	485
	486	while (buf < buf_len) {
	487	struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
	488
	489	if (i + 1 == num_periods)
	490	ccw->next = mxs_chan->ccw_phys;
	491	else
	492	ccw->next = mxs_chan->ccw_phys + sizeof(ccw) (i + 1);
	493
	494	ccw->bufaddr = dma_addr;
	495	ccw->xfer_bytes = period_len;
	496
	497	ccw->bits = 0;
	498	ccw->bits \|= CCW_CHAIN;
	499	ccw->bits \|= CCW_IRQ;
	500	ccw->bits \|= CCW_HALT_ON_TERM;
	501	ccw->bits \|= CCW_TERM_FLUSH;
db8196df	502	ccw->bits \|= BF_CCW(direction == DMA_DEV_TO_MEM ?
a580b8c5 SG	503	MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
	504
	505	dma_addr += period_len;
	506	buf += period_len;
	507
	508	i++;
	509	}
6d23ea4b	510	mxs_chan->desc_count = i;
a580b8c5 SG	511
	512	return &mxs_chan->desc;
	513
	514	err_out:
	515	mxs_chan->status = DMA_ERROR;
	516	return NULL;
	517	}
	518
	519	static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
	520	unsigned long arg)
	521	{
	522	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	523	int ret = 0;
	524
	525	switch (cmd) {
	526	case DMA_TERMINATE_ALL:
a62bae98	527	mxs_dma_reset_chan(mxs_chan);
7ad7a345	528	mxs_dma_disable_chan(mxs_chan);
a580b8c5 SG	529	break;
	530	case DMA_PAUSE:
	531	mxs_dma_pause_chan(mxs_chan);
	532	break;
	533	case DMA_RESUME:
	534	mxs_dma_resume_chan(mxs_chan);
	535	break;
	536	default:
	537	ret = -ENOSYS;
	538	}
	539
	540	return ret;
	541	}
	542
	543	static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
	544	dma_cookie_t cookie, struct dma_tx_state *txstate)
	545	{
	546	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	547	dma_cookie_t last_used;
	548
	549	last_used = chan->cookie;
4d4e58de	550	dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
a580b8c5 SG	551
	552	return mxs_chan->status;
	553	}
	554
	555	static void mxs_dma_issue_pending(struct dma_chan *chan)
	556	{
d04525ed SG	557	struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
	558
	559	mxs_dma_enable_chan(mxs_chan);
a580b8c5 SG	560	}
	561
	562	static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
	563	{
	564	int ret;
	565
759a2e30	566	ret = clk_prepare_enable(mxs_dma->clk);
a580b8c5	567	if (ret)
feb397de	568	return ret;
a580b8c5 SG	569
	570	ret = mxs_reset_block(mxs_dma->base);
	571	if (ret)
	572	goto err_out;
	573
	574	/* only major version matters */
	575	mxs_dma->version = readl(mxs_dma->base +
	576	((mxs_dma->dev_id == MXS_DMA_APBX) ?
	577	HW_APBX_VERSION : HW_APBH_VERSION)) >>
	578	BP_APBHX_VERSION_MAJOR;
	579
	580	/* enable apbh burst */
	581	if (dma_is_apbh()) {
	582	writel(BM_APBH_CTRL0_APB_BURST_EN,
	583	mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	584	writel(BM_APBH_CTRL0_APB_BURST8_EN,
	585	mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
	586	}
	587
	588	/* enable irq for all the channels */
	589	writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
	590	mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);
	591
a580b8c5	592	err_out:
57f2685c	593	clk_disable_unprepare(mxs_dma->clk);
a580b8c5 SG	594	return ret;
	595	}
	596
	597	static int __init mxs_dma_probe(struct platform_device *pdev)
	598	{
	599	const struct platform_device_id *id_entry =
	600	platform_get_device_id(pdev);
	601	struct mxs_dma_engine *mxs_dma;
	602	struct resource *iores;
	603	int ret, i;
	604
	605	mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL);
	606	if (!mxs_dma)
	607	return -ENOMEM;
	608
	609	mxs_dma->dev_id = id_entry->driver_data;
	610
	611	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	612
	613	if (!request_mem_region(iores->start, resource_size(iores),
	614	pdev->name)) {
	615	ret = -EBUSY;
	616	goto err_request_region;
	617	}
	618
	619	mxs_dma->base = ioremap(iores->start, resource_size(iores));
	620	if (!mxs_dma->base) {
	621	ret = -ENOMEM;
	622	goto err_ioremap;
	623	}
	624
	625	mxs_dma->clk = clk_get(&pdev->dev, NULL);
	626	if (IS_ERR(mxs_dma->clk)) {
	627	ret = PTR_ERR(mxs_dma->clk);
	628	goto err_clk;
	629	}
	630
	631	dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
	632	dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
	633
	634	INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
	635
	636	/* Initialize channel parameters */
	637	for (i = 0; i < MXS_DMA_CHANNELS; i++) {
	638	struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
	639
	640	mxs_chan->mxs_dma = mxs_dma;
	641	mxs_chan->chan.device = &mxs_dma->dma_device;
8ac69546	642	dma_cookie_init(&mxs_chan->chan);
a580b8c5 SG	643
	644	tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
	645	(unsigned long) mxs_chan);
	646
	647
	648	/* Add the channel to mxs_chan list */
	649	list_add_tail(&mxs_chan->chan.device_node,
	650	&mxs_dma->dma_device.channels);
	651	}
	652
	653	ret = mxs_dma_init(mxs_dma);
	654	if (ret)
	655	goto err_init;
	656
	657	mxs_dma->dma_device.dev = &pdev->dev;
	658
	659	/* mxs_dma gets 65535 bytes maximum sg size */
	660	mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
	661	dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
	662
	663	mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
	664	mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
	665	mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
	666	mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
	667	mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
	668	mxs_dma->dma_device.device_control = mxs_dma_control;
	669	mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
	670
	671	ret = dma_async_device_register(&mxs_dma->dma_device);
	672	if (ret) {
	673	dev_err(mxs_dma->dma_device.dev, "unable to register\n");
	674	goto err_init;
	675	}
	676
	677	dev_info(mxs_dma->dma_device.dev, "initialized\n");
	678
	679	return 0;
	680
	681	err_init:
	682	clk_put(mxs_dma->clk);
	683	err_clk:
	684	iounmap(mxs_dma->base);
	685	err_ioremap:
	686	release_mem_region(iores->start, resource_size(iores));
	687	err_request_region:
	688	kfree(mxs_dma);
	689	return ret;
	690	}
	691
	692	static struct platform_device_id mxs_dma_type[] = {
	693	{
	694	.name = "mxs-dma-apbh",
	695	.driver_data = MXS_DMA_APBH,
	696	}, {
	697	.name = "mxs-dma-apbx",
	698	.driver_data = MXS_DMA_APBX,
2a9778ed AL	699	}, {
2a9778ed AL	700	/* end of list */
a580b8c5 SG	701	}
	702	};
	703
	704	static struct platform_driver mxs_dma_driver = {
	705	.driver = {
	706	.name = "mxs-dma",
	707	},
	708	.id_table = mxs_dma_type,
	709	};
	710
	711	static int __init mxs_dma_module_init(void)
	712	{
	713	return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
	714	}
	715	subsys_initcall(mxs_dma_module_init);