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7bedaa55 RK |
1 | /* |
2 | * OMAP DMAengine support | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
fa3ad86a | 8 | #include <linux/delay.h> |
7bedaa55 RK |
9 | #include <linux/dmaengine.h> |
10 | #include <linux/dma-mapping.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/omap-dma.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/spinlock.h> | |
8d30662a JH |
20 | #include <linux/of_dma.h> |
21 | #include <linux/of_device.h> | |
7bedaa55 RK |
22 | |
23 | #include "virt-dma.h" | |
7d7e1eba | 24 | |
7bedaa55 RK |
25 | struct omap_dmadev { |
26 | struct dma_device ddev; | |
27 | spinlock_t lock; | |
28 | struct tasklet_struct task; | |
29 | struct list_head pending; | |
1b416c4b | 30 | struct omap_system_dma_plat_info *plat; |
7bedaa55 RK |
31 | }; |
32 | ||
33 | struct omap_chan { | |
34 | struct virt_dma_chan vc; | |
35 | struct list_head node; | |
1b416c4b | 36 | struct omap_system_dma_plat_info *plat; |
7bedaa55 RK |
37 | |
38 | struct dma_slave_config cfg; | |
39 | unsigned dma_sig; | |
3a774ea9 | 40 | bool cyclic; |
2dcdf570 | 41 | bool paused; |
7bedaa55 RK |
42 | |
43 | int dma_ch; | |
44 | struct omap_desc *desc; | |
45 | unsigned sgidx; | |
46 | }; | |
47 | ||
48 | struct omap_sg { | |
49 | dma_addr_t addr; | |
50 | uint32_t en; /* number of elements (24-bit) */ | |
51 | uint32_t fn; /* number of frames (16-bit) */ | |
52 | }; | |
53 | ||
54 | struct omap_desc { | |
55 | struct virt_dma_desc vd; | |
56 | enum dma_transfer_direction dir; | |
57 | dma_addr_t dev_addr; | |
58 | ||
7c836bc7 | 59 | int16_t fi; /* for OMAP_DMA_SYNC_PACKET */ |
9043826d | 60 | uint8_t es; /* CSDP_DATA_TYPE_xxx */ |
3ed4d18f | 61 | uint32_t ccr; /* CCR value */ |
965aeb4d | 62 | uint16_t clnk_ctrl; /* CLNK_CTRL value */ |
fa3ad86a | 63 | uint16_t cicr; /* CICR value */ |
2f0d13bd | 64 | uint32_t csdp; /* CSDP value */ |
7bedaa55 RK |
65 | |
66 | unsigned sglen; | |
67 | struct omap_sg sg[0]; | |
68 | }; | |
69 | ||
9043826d RK |
70 | enum { |
71 | CCR_FS = BIT(5), | |
72 | CCR_READ_PRIORITY = BIT(6), | |
73 | CCR_ENABLE = BIT(7), | |
74 | CCR_AUTO_INIT = BIT(8), /* OMAP1 only */ | |
75 | CCR_REPEAT = BIT(9), /* OMAP1 only */ | |
76 | CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */ | |
77 | CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */ | |
78 | CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */ | |
79 | CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */ | |
80 | CCR_SRC_AMODE_CONSTANT = 0 << 12, | |
81 | CCR_SRC_AMODE_POSTINC = 1 << 12, | |
82 | CCR_SRC_AMODE_SGLIDX = 2 << 12, | |
83 | CCR_SRC_AMODE_DBLIDX = 3 << 12, | |
84 | CCR_DST_AMODE_CONSTANT = 0 << 14, | |
85 | CCR_DST_AMODE_POSTINC = 1 << 14, | |
86 | CCR_DST_AMODE_SGLIDX = 2 << 14, | |
87 | CCR_DST_AMODE_DBLIDX = 3 << 14, | |
88 | CCR_CONSTANT_FILL = BIT(16), | |
89 | CCR_TRANSPARENT_COPY = BIT(17), | |
90 | CCR_BS = BIT(18), | |
91 | CCR_SUPERVISOR = BIT(22), | |
92 | CCR_PREFETCH = BIT(23), | |
93 | CCR_TRIGGER_SRC = BIT(24), | |
94 | CCR_BUFFERING_DISABLE = BIT(25), | |
95 | CCR_WRITE_PRIORITY = BIT(26), | |
96 | CCR_SYNC_ELEMENT = 0, | |
97 | CCR_SYNC_FRAME = CCR_FS, | |
98 | CCR_SYNC_BLOCK = CCR_BS, | |
99 | CCR_SYNC_PACKET = CCR_BS | CCR_FS, | |
100 | ||
101 | CSDP_DATA_TYPE_8 = 0, | |
102 | CSDP_DATA_TYPE_16 = 1, | |
103 | CSDP_DATA_TYPE_32 = 2, | |
104 | CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */ | |
105 | CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */ | |
106 | CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */ | |
107 | CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */ | |
108 | CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */ | |
109 | CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */ | |
110 | CSDP_SRC_PACKED = BIT(6), | |
111 | CSDP_SRC_BURST_1 = 0 << 7, | |
112 | CSDP_SRC_BURST_16 = 1 << 7, | |
113 | CSDP_SRC_BURST_32 = 2 << 7, | |
114 | CSDP_SRC_BURST_64 = 3 << 7, | |
115 | CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */ | |
116 | CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */ | |
117 | CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */ | |
118 | CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */ | |
119 | CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */ | |
120 | CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */ | |
121 | CSDP_DST_PACKED = BIT(13), | |
122 | CSDP_DST_BURST_1 = 0 << 14, | |
123 | CSDP_DST_BURST_16 = 1 << 14, | |
124 | CSDP_DST_BURST_32 = 2 << 14, | |
125 | CSDP_DST_BURST_64 = 3 << 14, | |
126 | ||
127 | CICR_TOUT_IE = BIT(0), /* OMAP1 only */ | |
128 | CICR_DROP_IE = BIT(1), | |
129 | CICR_HALF_IE = BIT(2), | |
130 | CICR_FRAME_IE = BIT(3), | |
131 | CICR_LAST_IE = BIT(4), | |
132 | CICR_BLOCK_IE = BIT(5), | |
133 | CICR_PKT_IE = BIT(7), /* OMAP2+ only */ | |
134 | CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */ | |
135 | CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */ | |
136 | CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */ | |
137 | CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */ | |
138 | CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */ | |
139 | ||
140 | CLNK_CTRL_ENABLE_LNK = BIT(15), | |
141 | }; | |
142 | ||
7bedaa55 | 143 | static const unsigned es_bytes[] = { |
9043826d RK |
144 | [CSDP_DATA_TYPE_8] = 1, |
145 | [CSDP_DATA_TYPE_16] = 2, | |
146 | [CSDP_DATA_TYPE_32] = 4, | |
7bedaa55 RK |
147 | }; |
148 | ||
8d30662a JH |
149 | static struct of_dma_filter_info omap_dma_info = { |
150 | .filter_fn = omap_dma_filter_fn, | |
151 | }; | |
152 | ||
7bedaa55 RK |
153 | static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d) |
154 | { | |
155 | return container_of(d, struct omap_dmadev, ddev); | |
156 | } | |
157 | ||
158 | static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c) | |
159 | { | |
160 | return container_of(c, struct omap_chan, vc.chan); | |
161 | } | |
162 | ||
163 | static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t) | |
164 | { | |
165 | return container_of(t, struct omap_desc, vd.tx); | |
166 | } | |
167 | ||
168 | static void omap_dma_desc_free(struct virt_dma_desc *vd) | |
169 | { | |
170 | kfree(container_of(vd, struct omap_desc, vd)); | |
171 | } | |
172 | ||
470b23f7 RK |
173 | static void omap_dma_clear_csr(struct omap_chan *c) |
174 | { | |
175 | if (dma_omap1()) | |
176 | c->plat->dma_read(CSR, c->dma_ch); | |
177 | else | |
178 | c->plat->dma_write(~0, CSR, c->dma_ch); | |
179 | } | |
180 | ||
fa3ad86a RK |
181 | static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) |
182 | { | |
183 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
fa3ad86a RK |
184 | |
185 | if (__dma_omap15xx(od->plat->dma_attr)) | |
186 | c->plat->dma_write(0, CPC, c->dma_ch); | |
187 | else | |
188 | c->plat->dma_write(0, CDAC, c->dma_ch); | |
189 | ||
470b23f7 | 190 | omap_dma_clear_csr(c); |
fa3ad86a RK |
191 | |
192 | /* Enable interrupts */ | |
193 | c->plat->dma_write(d->cicr, CICR, c->dma_ch); | |
194 | ||
45da7b04 RK |
195 | /* Enable channel */ |
196 | c->plat->dma_write(d->ccr | CCR_ENABLE, CCR, c->dma_ch); | |
fa3ad86a RK |
197 | } |
198 | ||
199 | static void omap_dma_stop(struct omap_chan *c) | |
200 | { | |
201 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
202 | uint32_t val; | |
203 | ||
204 | /* disable irq */ | |
205 | c->plat->dma_write(0, CICR, c->dma_ch); | |
206 | ||
470b23f7 | 207 | omap_dma_clear_csr(c); |
fa3ad86a RK |
208 | |
209 | val = c->plat->dma_read(CCR, c->dma_ch); | |
9043826d | 210 | if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { |
fa3ad86a RK |
211 | uint32_t sysconfig; |
212 | unsigned i; | |
213 | ||
214 | sysconfig = c->plat->dma_read(OCP_SYSCONFIG, c->dma_ch); | |
215 | val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK; | |
216 | val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
217 | c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch); | |
218 | ||
219 | val = c->plat->dma_read(CCR, c->dma_ch); | |
9043826d | 220 | val &= ~CCR_ENABLE; |
fa3ad86a RK |
221 | c->plat->dma_write(val, CCR, c->dma_ch); |
222 | ||
223 | /* Wait for sDMA FIFO to drain */ | |
224 | for (i = 0; ; i++) { | |
225 | val = c->plat->dma_read(CCR, c->dma_ch); | |
9043826d | 226 | if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))) |
fa3ad86a RK |
227 | break; |
228 | ||
229 | if (i > 100) | |
230 | break; | |
231 | ||
232 | udelay(5); | |
233 | } | |
234 | ||
9043826d | 235 | if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)) |
fa3ad86a RK |
236 | dev_err(c->vc.chan.device->dev, |
237 | "DMA drain did not complete on lch %d\n", | |
238 | c->dma_ch); | |
239 | ||
240 | c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch); | |
241 | } else { | |
9043826d | 242 | val &= ~CCR_ENABLE; |
fa3ad86a RK |
243 | c->plat->dma_write(val, CCR, c->dma_ch); |
244 | } | |
245 | ||
246 | mb(); | |
247 | ||
248 | if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) { | |
249 | val = c->plat->dma_read(CLNK_CTRL, c->dma_ch); | |
250 | ||
251 | if (dma_omap1()) | |
252 | val |= 1 << 14; /* set the STOP_LNK bit */ | |
253 | else | |
9043826d | 254 | val &= ~CLNK_CTRL_ENABLE_LNK; |
fa3ad86a RK |
255 | |
256 | c->plat->dma_write(val, CLNK_CTRL, c->dma_ch); | |
257 | } | |
258 | } | |
259 | ||
7bedaa55 RK |
260 | static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, |
261 | unsigned idx) | |
262 | { | |
263 | struct omap_sg *sg = d->sg + idx; | |
893e63e3 | 264 | unsigned cxsa, cxei, cxfi; |
913a2d0c RK |
265 | |
266 | if (d->dir == DMA_DEV_TO_MEM) { | |
893e63e3 RK |
267 | cxsa = CDSA; |
268 | cxei = CDEI; | |
269 | cxfi = CDFI; | |
913a2d0c | 270 | } else { |
893e63e3 RK |
271 | cxsa = CSSA; |
272 | cxei = CSEI; | |
273 | cxfi = CSFI; | |
913a2d0c RK |
274 | } |
275 | ||
893e63e3 RK |
276 | c->plat->dma_write(sg->addr, cxsa, c->dma_ch); |
277 | c->plat->dma_write(0, cxei, c->dma_ch); | |
278 | c->plat->dma_write(0, cxfi, c->dma_ch); | |
913a2d0c RK |
279 | c->plat->dma_write(sg->en, CEN, c->dma_ch); |
280 | c->plat->dma_write(sg->fn, CFN, c->dma_ch); | |
281 | ||
fa3ad86a | 282 | omap_dma_start(c, d); |
913a2d0c RK |
283 | } |
284 | ||
285 | static void omap_dma_start_desc(struct omap_chan *c) | |
286 | { | |
287 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); | |
288 | struct omap_desc *d; | |
893e63e3 | 289 | unsigned cxsa, cxei, cxfi; |
b9e97822 | 290 | |
913a2d0c RK |
291 | if (!vd) { |
292 | c->desc = NULL; | |
293 | return; | |
294 | } | |
295 | ||
296 | list_del(&vd->node); | |
297 | ||
298 | c->desc = d = to_omap_dma_desc(&vd->tx); | |
299 | c->sgidx = 0; | |
300 | ||
59871902 RK |
301 | /* |
302 | * This provides the necessary barrier to ensure data held in | |
303 | * DMA coherent memory is visible to the DMA engine prior to | |
304 | * the transfer starting. | |
305 | */ | |
306 | mb(); | |
307 | ||
3ed4d18f RK |
308 | c->plat->dma_write(d->ccr, CCR, c->dma_ch); |
309 | if (dma_omap1()) | |
310 | c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch); | |
b9e97822 | 311 | |
3ed4d18f | 312 | if (d->dir == DMA_DEV_TO_MEM) { |
893e63e3 RK |
313 | cxsa = CSSA; |
314 | cxei = CSEI; | |
315 | cxfi = CSFI; | |
b9e97822 | 316 | } else { |
893e63e3 RK |
317 | cxsa = CDSA; |
318 | cxei = CDEI; | |
319 | cxfi = CDFI; | |
b9e97822 RK |
320 | } |
321 | ||
893e63e3 RK |
322 | c->plat->dma_write(d->dev_addr, cxsa, c->dma_ch); |
323 | c->plat->dma_write(0, cxei, c->dma_ch); | |
324 | c->plat->dma_write(d->fi, cxfi, c->dma_ch); | |
2f0d13bd | 325 | c->plat->dma_write(d->csdp, CSDP, c->dma_ch); |
965aeb4d | 326 | c->plat->dma_write(d->clnk_ctrl, CLNK_CTRL, c->dma_ch); |
b9e97822 | 327 | |
7bedaa55 RK |
328 | omap_dma_start_sg(c, d, 0); |
329 | } | |
330 | ||
331 | static void omap_dma_callback(int ch, u16 status, void *data) | |
332 | { | |
333 | struct omap_chan *c = data; | |
334 | struct omap_desc *d; | |
335 | unsigned long flags; | |
336 | ||
337 | spin_lock_irqsave(&c->vc.lock, flags); | |
338 | d = c->desc; | |
339 | if (d) { | |
3a774ea9 RK |
340 | if (!c->cyclic) { |
341 | if (++c->sgidx < d->sglen) { | |
342 | omap_dma_start_sg(c, d, c->sgidx); | |
343 | } else { | |
344 | omap_dma_start_desc(c); | |
345 | vchan_cookie_complete(&d->vd); | |
346 | } | |
7bedaa55 | 347 | } else { |
3a774ea9 | 348 | vchan_cyclic_callback(&d->vd); |
7bedaa55 RK |
349 | } |
350 | } | |
351 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
352 | } | |
353 | ||
354 | /* | |
355 | * This callback schedules all pending channels. We could be more | |
356 | * clever here by postponing allocation of the real DMA channels to | |
357 | * this point, and freeing them when our virtual channel becomes idle. | |
358 | * | |
359 | * We would then need to deal with 'all channels in-use' | |
360 | */ | |
361 | static void omap_dma_sched(unsigned long data) | |
362 | { | |
363 | struct omap_dmadev *d = (struct omap_dmadev *)data; | |
364 | LIST_HEAD(head); | |
365 | ||
366 | spin_lock_irq(&d->lock); | |
367 | list_splice_tail_init(&d->pending, &head); | |
368 | spin_unlock_irq(&d->lock); | |
369 | ||
370 | while (!list_empty(&head)) { | |
371 | struct omap_chan *c = list_first_entry(&head, | |
372 | struct omap_chan, node); | |
373 | ||
374 | spin_lock_irq(&c->vc.lock); | |
375 | list_del_init(&c->node); | |
376 | omap_dma_start_desc(c); | |
377 | spin_unlock_irq(&c->vc.lock); | |
378 | } | |
379 | } | |
380 | ||
381 | static int omap_dma_alloc_chan_resources(struct dma_chan *chan) | |
382 | { | |
383 | struct omap_chan *c = to_omap_dma_chan(chan); | |
384 | ||
9e2f7d82 | 385 | dev_dbg(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig); |
7bedaa55 RK |
386 | |
387 | return omap_request_dma(c->dma_sig, "DMA engine", | |
388 | omap_dma_callback, c, &c->dma_ch); | |
389 | } | |
390 | ||
391 | static void omap_dma_free_chan_resources(struct dma_chan *chan) | |
392 | { | |
393 | struct omap_chan *c = to_omap_dma_chan(chan); | |
394 | ||
395 | vchan_free_chan_resources(&c->vc); | |
396 | omap_free_dma(c->dma_ch); | |
397 | ||
9e2f7d82 | 398 | dev_dbg(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig); |
7bedaa55 RK |
399 | } |
400 | ||
3850e22f RK |
401 | static size_t omap_dma_sg_size(struct omap_sg *sg) |
402 | { | |
403 | return sg->en * sg->fn; | |
404 | } | |
405 | ||
406 | static size_t omap_dma_desc_size(struct omap_desc *d) | |
407 | { | |
408 | unsigned i; | |
409 | size_t size; | |
410 | ||
411 | for (size = i = 0; i < d->sglen; i++) | |
412 | size += omap_dma_sg_size(&d->sg[i]); | |
413 | ||
414 | return size * es_bytes[d->es]; | |
415 | } | |
416 | ||
417 | static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr) | |
418 | { | |
419 | unsigned i; | |
420 | size_t size, es_size = es_bytes[d->es]; | |
421 | ||
422 | for (size = i = 0; i < d->sglen; i++) { | |
423 | size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size; | |
424 | ||
425 | if (size) | |
426 | size += this_size; | |
427 | else if (addr >= d->sg[i].addr && | |
428 | addr < d->sg[i].addr + this_size) | |
429 | size += d->sg[i].addr + this_size - addr; | |
430 | } | |
431 | return size; | |
432 | } | |
433 | ||
3997cab3 RK |
434 | static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c) |
435 | { | |
436 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
437 | dma_addr_t addr; | |
438 | ||
439 | if (__dma_omap15xx(od->plat->dma_attr)) | |
440 | addr = c->plat->dma_read(CPC, c->dma_ch); | |
441 | else | |
442 | addr = c->plat->dma_read(CSAC, c->dma_ch); | |
443 | ||
444 | if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0) | |
445 | addr = c->plat->dma_read(CSAC, c->dma_ch); | |
446 | ||
447 | if (!__dma_omap15xx(od->plat->dma_attr)) { | |
448 | /* | |
449 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
450 | * not been started (no data has been transferred so far). | |
451 | * Return the programmed source start address in this case. | |
452 | */ | |
453 | if (c->plat->dma_read(CDAC, c->dma_ch)) | |
454 | addr = c->plat->dma_read(CSAC, c->dma_ch); | |
455 | else | |
456 | addr = c->plat->dma_read(CSSA, c->dma_ch); | |
457 | } | |
458 | ||
459 | if (dma_omap1()) | |
460 | addr |= c->plat->dma_read(CSSA, c->dma_ch) & 0xffff0000; | |
461 | ||
462 | return addr; | |
463 | } | |
464 | ||
465 | static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c) | |
466 | { | |
467 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
468 | dma_addr_t addr; | |
469 | ||
470 | if (__dma_omap15xx(od->plat->dma_attr)) | |
471 | addr = c->plat->dma_read(CPC, c->dma_ch); | |
472 | else | |
473 | addr = c->plat->dma_read(CDAC, c->dma_ch); | |
474 | ||
475 | /* | |
476 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
477 | * read before the DMA controller finished disabling the channel. | |
478 | */ | |
479 | if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) { | |
480 | addr = c->plat->dma_read(CDAC, c->dma_ch); | |
481 | /* | |
482 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
483 | * not been started (no data has been transferred so far). | |
484 | * Return the programmed destination start address in this case. | |
485 | */ | |
486 | if (addr == 0) | |
487 | addr = c->plat->dma_read(CDSA, c->dma_ch); | |
488 | } | |
489 | ||
490 | if (dma_omap1()) | |
491 | addr |= c->plat->dma_read(CDSA, c->dma_ch) & 0xffff0000; | |
492 | ||
493 | return addr; | |
494 | } | |
495 | ||
7bedaa55 RK |
496 | static enum dma_status omap_dma_tx_status(struct dma_chan *chan, |
497 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
498 | { | |
3850e22f RK |
499 | struct omap_chan *c = to_omap_dma_chan(chan); |
500 | struct virt_dma_desc *vd; | |
501 | enum dma_status ret; | |
502 | unsigned long flags; | |
503 | ||
504 | ret = dma_cookie_status(chan, cookie, txstate); | |
7cce5083 | 505 | if (ret == DMA_COMPLETE || !txstate) |
3850e22f RK |
506 | return ret; |
507 | ||
508 | spin_lock_irqsave(&c->vc.lock, flags); | |
509 | vd = vchan_find_desc(&c->vc, cookie); | |
510 | if (vd) { | |
511 | txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx)); | |
512 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { | |
513 | struct omap_desc *d = c->desc; | |
514 | dma_addr_t pos; | |
515 | ||
516 | if (d->dir == DMA_MEM_TO_DEV) | |
3997cab3 | 517 | pos = omap_dma_get_src_pos(c); |
3850e22f | 518 | else if (d->dir == DMA_DEV_TO_MEM) |
3997cab3 | 519 | pos = omap_dma_get_dst_pos(c); |
3850e22f RK |
520 | else |
521 | pos = 0; | |
522 | ||
523 | txstate->residue = omap_dma_desc_size_pos(d, pos); | |
524 | } else { | |
525 | txstate->residue = 0; | |
526 | } | |
527 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
528 | ||
529 | return ret; | |
7bedaa55 RK |
530 | } |
531 | ||
532 | static void omap_dma_issue_pending(struct dma_chan *chan) | |
533 | { | |
534 | struct omap_chan *c = to_omap_dma_chan(chan); | |
535 | unsigned long flags; | |
536 | ||
537 | spin_lock_irqsave(&c->vc.lock, flags); | |
538 | if (vchan_issue_pending(&c->vc) && !c->desc) { | |
76502469 PU |
539 | /* |
540 | * c->cyclic is used only by audio and in this case the DMA need | |
541 | * to be started without delay. | |
542 | */ | |
543 | if (!c->cyclic) { | |
544 | struct omap_dmadev *d = to_omap_dma_dev(chan->device); | |
545 | spin_lock(&d->lock); | |
546 | if (list_empty(&c->node)) | |
547 | list_add_tail(&c->node, &d->pending); | |
548 | spin_unlock(&d->lock); | |
549 | tasklet_schedule(&d->task); | |
550 | } else { | |
551 | omap_dma_start_desc(c); | |
552 | } | |
7bedaa55 RK |
553 | } |
554 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
555 | } | |
556 | ||
557 | static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg( | |
558 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen, | |
559 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) | |
560 | { | |
49ae0b29 | 561 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
562 | struct omap_chan *c = to_omap_dma_chan(chan); |
563 | enum dma_slave_buswidth dev_width; | |
564 | struct scatterlist *sgent; | |
565 | struct omap_desc *d; | |
566 | dma_addr_t dev_addr; | |
3ed4d18f | 567 | unsigned i, j = 0, es, en, frame_bytes; |
7bedaa55 RK |
568 | u32 burst; |
569 | ||
570 | if (dir == DMA_DEV_TO_MEM) { | |
571 | dev_addr = c->cfg.src_addr; | |
572 | dev_width = c->cfg.src_addr_width; | |
573 | burst = c->cfg.src_maxburst; | |
7bedaa55 RK |
574 | } else if (dir == DMA_MEM_TO_DEV) { |
575 | dev_addr = c->cfg.dst_addr; | |
576 | dev_width = c->cfg.dst_addr_width; | |
577 | burst = c->cfg.dst_maxburst; | |
7bedaa55 RK |
578 | } else { |
579 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
580 | return NULL; | |
581 | } | |
582 | ||
583 | /* Bus width translates to the element size (ES) */ | |
584 | switch (dev_width) { | |
585 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 586 | es = CSDP_DATA_TYPE_8; |
7bedaa55 RK |
587 | break; |
588 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 589 | es = CSDP_DATA_TYPE_16; |
7bedaa55 RK |
590 | break; |
591 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 592 | es = CSDP_DATA_TYPE_32; |
7bedaa55 RK |
593 | break; |
594 | default: /* not reached */ | |
595 | return NULL; | |
596 | } | |
597 | ||
598 | /* Now allocate and setup the descriptor. */ | |
599 | d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC); | |
600 | if (!d) | |
601 | return NULL; | |
602 | ||
603 | d->dir = dir; | |
604 | d->dev_addr = dev_addr; | |
605 | d->es = es; | |
3ed4d18f | 606 | |
9043826d | 607 | d->ccr = CCR_SYNC_FRAME; |
3ed4d18f | 608 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 609 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 610 | else |
9043826d | 611 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 612 | |
9043826d | 613 | d->cicr = CICR_DROP_IE | CICR_BLOCK_IE; |
2f0d13bd | 614 | d->csdp = es; |
fa3ad86a | 615 | |
2f0d13bd | 616 | if (dma_omap1()) { |
3ed4d18f | 617 | if (__dma_omap16xx(od->plat->dma_attr)) { |
9043826d | 618 | d->ccr |= CCR_OMAP31_DISABLE; |
3ed4d18f RK |
619 | /* Duplicate what plat-omap/dma.c does */ |
620 | d->ccr |= c->dma_ch + 1; | |
621 | } else { | |
622 | d->ccr |= c->dma_sig & 0x1f; | |
623 | } | |
624 | ||
9043826d | 625 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
626 | |
627 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 628 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB; |
2f0d13bd | 629 | else |
9043826d | 630 | d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 631 | } else { |
3ed4d18f RK |
632 | d->ccr |= (c->dma_sig & ~0x1f) << 14; |
633 | d->ccr |= c->dma_sig & 0x1f; | |
3ed4d18f RK |
634 | |
635 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 636 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 637 | |
9043826d | 638 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
2f0d13bd | 639 | } |
49ae0b29 RK |
640 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
641 | d->ccr |= CCR_BUFFERING_DISABLE; | |
965aeb4d RK |
642 | if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS) |
643 | d->clnk_ctrl = c->dma_ch; | |
7bedaa55 RK |
644 | |
645 | /* | |
646 | * Build our scatterlist entries: each contains the address, | |
647 | * the number of elements (EN) in each frame, and the number of | |
648 | * frames (FN). Number of bytes for this entry = ES * EN * FN. | |
649 | * | |
650 | * Burst size translates to number of elements with frame sync. | |
651 | * Note: DMA engine defines burst to be the number of dev-width | |
652 | * transfers. | |
653 | */ | |
654 | en = burst; | |
655 | frame_bytes = es_bytes[es] * en; | |
656 | for_each_sg(sgl, sgent, sglen, i) { | |
657 | d->sg[j].addr = sg_dma_address(sgent); | |
658 | d->sg[j].en = en; | |
659 | d->sg[j].fn = sg_dma_len(sgent) / frame_bytes; | |
660 | j++; | |
661 | } | |
662 | ||
663 | d->sglen = j; | |
664 | ||
665 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); | |
666 | } | |
667 | ||
3a774ea9 RK |
668 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( |
669 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
ec8b5e48 PU |
670 | size_t period_len, enum dma_transfer_direction dir, unsigned long flags, |
671 | void *context) | |
3a774ea9 | 672 | { |
fa3ad86a | 673 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
3a774ea9 RK |
674 | struct omap_chan *c = to_omap_dma_chan(chan); |
675 | enum dma_slave_buswidth dev_width; | |
676 | struct omap_desc *d; | |
677 | dma_addr_t dev_addr; | |
3ed4d18f | 678 | unsigned es; |
3a774ea9 RK |
679 | u32 burst; |
680 | ||
681 | if (dir == DMA_DEV_TO_MEM) { | |
682 | dev_addr = c->cfg.src_addr; | |
683 | dev_width = c->cfg.src_addr_width; | |
684 | burst = c->cfg.src_maxburst; | |
3a774ea9 RK |
685 | } else if (dir == DMA_MEM_TO_DEV) { |
686 | dev_addr = c->cfg.dst_addr; | |
687 | dev_width = c->cfg.dst_addr_width; | |
688 | burst = c->cfg.dst_maxburst; | |
3a774ea9 RK |
689 | } else { |
690 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
691 | return NULL; | |
692 | } | |
693 | ||
694 | /* Bus width translates to the element size (ES) */ | |
695 | switch (dev_width) { | |
696 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 697 | es = CSDP_DATA_TYPE_8; |
3a774ea9 RK |
698 | break; |
699 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 700 | es = CSDP_DATA_TYPE_16; |
3a774ea9 RK |
701 | break; |
702 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 703 | es = CSDP_DATA_TYPE_32; |
3a774ea9 RK |
704 | break; |
705 | default: /* not reached */ | |
706 | return NULL; | |
707 | } | |
708 | ||
709 | /* Now allocate and setup the descriptor. */ | |
710 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); | |
711 | if (!d) | |
712 | return NULL; | |
713 | ||
714 | d->dir = dir; | |
715 | d->dev_addr = dev_addr; | |
716 | d->fi = burst; | |
717 | d->es = es; | |
3a774ea9 RK |
718 | d->sg[0].addr = buf_addr; |
719 | d->sg[0].en = period_len / es_bytes[es]; | |
720 | d->sg[0].fn = buf_len / period_len; | |
721 | d->sglen = 1; | |
3ed4d18f RK |
722 | |
723 | d->ccr = 0; | |
3ed4d18f | 724 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 725 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 726 | else |
9043826d | 727 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 728 | |
9043826d | 729 | d->cicr = CICR_DROP_IE; |
fa3ad86a | 730 | if (flags & DMA_PREP_INTERRUPT) |
9043826d | 731 | d->cicr |= CICR_FRAME_IE; |
fa3ad86a | 732 | |
2f0d13bd RK |
733 | d->csdp = es; |
734 | ||
735 | if (dma_omap1()) { | |
3ed4d18f | 736 | if (__dma_omap16xx(od->plat->dma_attr)) { |
9043826d | 737 | d->ccr |= CCR_OMAP31_DISABLE; |
3ed4d18f RK |
738 | /* Duplicate what plat-omap/dma.c does */ |
739 | d->ccr |= c->dma_ch + 1; | |
740 | } else { | |
741 | d->ccr |= c->dma_sig & 0x1f; | |
742 | } | |
743 | ||
9043826d | 744 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
745 | |
746 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 747 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI; |
2f0d13bd | 748 | else |
9043826d | 749 | d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 750 | } else { |
3ed4d18f RK |
751 | d->ccr |= (c->dma_sig & ~0x1f) << 14; |
752 | d->ccr |= c->dma_sig & 0x1f; | |
753 | ||
754 | if (burst) | |
9043826d RK |
755 | d->ccr |= CCR_SYNC_PACKET; |
756 | else | |
757 | d->ccr |= CCR_SYNC_ELEMENT; | |
3ed4d18f RK |
758 | |
759 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 760 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 761 | |
9043826d | 762 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
3a774ea9 | 763 | |
9043826d | 764 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
2f0d13bd | 765 | } |
49ae0b29 RK |
766 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
767 | d->ccr |= CCR_BUFFERING_DISABLE; | |
2f0d13bd | 768 | |
965aeb4d RK |
769 | if (__dma_omap15xx(od->plat->dma_attr)) |
770 | d->ccr |= CCR_AUTO_INIT | CCR_REPEAT; | |
771 | else | |
772 | d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK; | |
773 | ||
3ed4d18f | 774 | c->cyclic = true; |
3a774ea9 | 775 | |
2dde5b90 | 776 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
3a774ea9 RK |
777 | } |
778 | ||
7bedaa55 RK |
779 | static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg) |
780 | { | |
781 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
782 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
783 | return -EINVAL; | |
784 | ||
785 | memcpy(&c->cfg, cfg, sizeof(c->cfg)); | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | static int omap_dma_terminate_all(struct omap_chan *c) | |
791 | { | |
792 | struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device); | |
793 | unsigned long flags; | |
794 | LIST_HEAD(head); | |
795 | ||
796 | spin_lock_irqsave(&c->vc.lock, flags); | |
797 | ||
798 | /* Prevent this channel being scheduled */ | |
799 | spin_lock(&d->lock); | |
800 | list_del_init(&c->node); | |
801 | spin_unlock(&d->lock); | |
802 | ||
803 | /* | |
804 | * Stop DMA activity: we assume the callback will not be called | |
fa3ad86a | 805 | * after omap_dma_stop() returns (even if it does, it will see |
7bedaa55 RK |
806 | * c->desc is NULL and exit.) |
807 | */ | |
808 | if (c->desc) { | |
809 | c->desc = NULL; | |
2dcdf570 PU |
810 | /* Avoid stopping the dma twice */ |
811 | if (!c->paused) | |
fa3ad86a | 812 | omap_dma_stop(c); |
7bedaa55 RK |
813 | } |
814 | ||
3a774ea9 RK |
815 | if (c->cyclic) { |
816 | c->cyclic = false; | |
2dcdf570 | 817 | c->paused = false; |
3a774ea9 RK |
818 | } |
819 | ||
7bedaa55 RK |
820 | vchan_get_all_descriptors(&c->vc, &head); |
821 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
822 | vchan_dma_desc_free_list(&c->vc, &head); | |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | static int omap_dma_pause(struct omap_chan *c) | |
828 | { | |
2dcdf570 PU |
829 | /* Pause/Resume only allowed with cyclic mode */ |
830 | if (!c->cyclic) | |
831 | return -EINVAL; | |
832 | ||
833 | if (!c->paused) { | |
fa3ad86a | 834 | omap_dma_stop(c); |
2dcdf570 PU |
835 | c->paused = true; |
836 | } | |
837 | ||
838 | return 0; | |
7bedaa55 RK |
839 | } |
840 | ||
841 | static int omap_dma_resume(struct omap_chan *c) | |
842 | { | |
2dcdf570 PU |
843 | /* Pause/Resume only allowed with cyclic mode */ |
844 | if (!c->cyclic) | |
845 | return -EINVAL; | |
846 | ||
847 | if (c->paused) { | |
fa3ad86a | 848 | omap_dma_start(c, c->desc); |
2dcdf570 PU |
849 | c->paused = false; |
850 | } | |
851 | ||
852 | return 0; | |
7bedaa55 RK |
853 | } |
854 | ||
855 | static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
856 | unsigned long arg) | |
857 | { | |
858 | struct omap_chan *c = to_omap_dma_chan(chan); | |
859 | int ret; | |
860 | ||
861 | switch (cmd) { | |
862 | case DMA_SLAVE_CONFIG: | |
863 | ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg); | |
864 | break; | |
865 | ||
866 | case DMA_TERMINATE_ALL: | |
867 | ret = omap_dma_terminate_all(c); | |
868 | break; | |
869 | ||
870 | case DMA_PAUSE: | |
871 | ret = omap_dma_pause(c); | |
872 | break; | |
873 | ||
874 | case DMA_RESUME: | |
875 | ret = omap_dma_resume(c); | |
876 | break; | |
877 | ||
878 | default: | |
879 | ret = -ENXIO; | |
880 | break; | |
881 | } | |
882 | ||
883 | return ret; | |
884 | } | |
885 | ||
886 | static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig) | |
887 | { | |
888 | struct omap_chan *c; | |
889 | ||
890 | c = kzalloc(sizeof(*c), GFP_KERNEL); | |
891 | if (!c) | |
892 | return -ENOMEM; | |
893 | ||
1b416c4b | 894 | c->plat = od->plat; |
7bedaa55 RK |
895 | c->dma_sig = dma_sig; |
896 | c->vc.desc_free = omap_dma_desc_free; | |
897 | vchan_init(&c->vc, &od->ddev); | |
898 | INIT_LIST_HEAD(&c->node); | |
899 | ||
900 | od->ddev.chancnt++; | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
905 | static void omap_dma_free(struct omap_dmadev *od) | |
906 | { | |
907 | tasklet_kill(&od->task); | |
908 | while (!list_empty(&od->ddev.channels)) { | |
909 | struct omap_chan *c = list_first_entry(&od->ddev.channels, | |
910 | struct omap_chan, vc.chan.device_node); | |
911 | ||
912 | list_del(&c->vc.chan.device_node); | |
913 | tasklet_kill(&c->vc.task); | |
914 | kfree(c); | |
915 | } | |
7bedaa55 RK |
916 | } |
917 | ||
918 | static int omap_dma_probe(struct platform_device *pdev) | |
919 | { | |
920 | struct omap_dmadev *od; | |
921 | int rc, i; | |
922 | ||
104fce73 | 923 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); |
7bedaa55 RK |
924 | if (!od) |
925 | return -ENOMEM; | |
926 | ||
1b416c4b RK |
927 | od->plat = omap_get_plat_info(); |
928 | if (!od->plat) | |
929 | return -EPROBE_DEFER; | |
930 | ||
7bedaa55 | 931 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
3a774ea9 | 932 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
7bedaa55 RK |
933 | od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources; |
934 | od->ddev.device_free_chan_resources = omap_dma_free_chan_resources; | |
935 | od->ddev.device_tx_status = omap_dma_tx_status; | |
936 | od->ddev.device_issue_pending = omap_dma_issue_pending; | |
937 | od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg; | |
3a774ea9 | 938 | od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic; |
7bedaa55 RK |
939 | od->ddev.device_control = omap_dma_control; |
940 | od->ddev.dev = &pdev->dev; | |
941 | INIT_LIST_HEAD(&od->ddev.channels); | |
942 | INIT_LIST_HEAD(&od->pending); | |
943 | spin_lock_init(&od->lock); | |
944 | ||
945 | tasklet_init(&od->task, omap_dma_sched, (unsigned long)od); | |
946 | ||
947 | for (i = 0; i < 127; i++) { | |
948 | rc = omap_dma_chan_init(od, i); | |
949 | if (rc) { | |
950 | omap_dma_free(od); | |
951 | return rc; | |
952 | } | |
953 | } | |
954 | ||
955 | rc = dma_async_device_register(&od->ddev); | |
956 | if (rc) { | |
957 | pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", | |
958 | rc); | |
959 | omap_dma_free(od); | |
8d30662a JH |
960 | return rc; |
961 | } | |
962 | ||
963 | platform_set_drvdata(pdev, od); | |
964 | ||
965 | if (pdev->dev.of_node) { | |
966 | omap_dma_info.dma_cap = od->ddev.cap_mask; | |
967 | ||
968 | /* Device-tree DMA controller registration */ | |
969 | rc = of_dma_controller_register(pdev->dev.of_node, | |
970 | of_dma_simple_xlate, &omap_dma_info); | |
971 | if (rc) { | |
972 | pr_warn("OMAP-DMA: failed to register DMA controller\n"); | |
973 | dma_async_device_unregister(&od->ddev); | |
974 | omap_dma_free(od); | |
975 | } | |
7bedaa55 RK |
976 | } |
977 | ||
978 | dev_info(&pdev->dev, "OMAP DMA engine driver\n"); | |
979 | ||
980 | return rc; | |
981 | } | |
982 | ||
983 | static int omap_dma_remove(struct platform_device *pdev) | |
984 | { | |
985 | struct omap_dmadev *od = platform_get_drvdata(pdev); | |
986 | ||
8d30662a JH |
987 | if (pdev->dev.of_node) |
988 | of_dma_controller_free(pdev->dev.of_node); | |
989 | ||
7bedaa55 RK |
990 | dma_async_device_unregister(&od->ddev); |
991 | omap_dma_free(od); | |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
8d30662a JH |
996 | static const struct of_device_id omap_dma_match[] = { |
997 | { .compatible = "ti,omap2420-sdma", }, | |
998 | { .compatible = "ti,omap2430-sdma", }, | |
999 | { .compatible = "ti,omap3430-sdma", }, | |
1000 | { .compatible = "ti,omap3630-sdma", }, | |
1001 | { .compatible = "ti,omap4430-sdma", }, | |
1002 | {}, | |
1003 | }; | |
1004 | MODULE_DEVICE_TABLE(of, omap_dma_match); | |
1005 | ||
7bedaa55 RK |
1006 | static struct platform_driver omap_dma_driver = { |
1007 | .probe = omap_dma_probe, | |
1008 | .remove = omap_dma_remove, | |
1009 | .driver = { | |
1010 | .name = "omap-dma-engine", | |
1011 | .owner = THIS_MODULE, | |
8d30662a | 1012 | .of_match_table = of_match_ptr(omap_dma_match), |
7bedaa55 RK |
1013 | }, |
1014 | }; | |
1015 | ||
1016 | bool omap_dma_filter_fn(struct dma_chan *chan, void *param) | |
1017 | { | |
1018 | if (chan->device->dev->driver == &omap_dma_driver.driver) { | |
1019 | struct omap_chan *c = to_omap_dma_chan(chan); | |
1020 | unsigned req = *(unsigned *)param; | |
1021 | ||
1022 | return req == c->dma_sig; | |
1023 | } | |
1024 | return false; | |
1025 | } | |
1026 | EXPORT_SYMBOL_GPL(omap_dma_filter_fn); | |
1027 | ||
7bedaa55 RK |
1028 | static int omap_dma_init(void) |
1029 | { | |
be1f9481 | 1030 | return platform_driver_register(&omap_dma_driver); |
7bedaa55 RK |
1031 | } |
1032 | subsys_initcall(omap_dma_init); | |
1033 | ||
1034 | static void __exit omap_dma_exit(void) | |
1035 | { | |
7bedaa55 RK |
1036 | platform_driver_unregister(&omap_dma_driver); |
1037 | } | |
1038 | module_exit(omap_dma_exit); | |
1039 | ||
1040 | MODULE_AUTHOR("Russell King"); | |
1041 | MODULE_LICENSE("GPL"); |