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7bedaa55 RK |
1 | /* |
2 | * OMAP DMAengine support | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
fa3ad86a | 8 | #include <linux/delay.h> |
7bedaa55 RK |
9 | #include <linux/dmaengine.h> |
10 | #include <linux/dma-mapping.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/omap-dma.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/spinlock.h> | |
8d30662a JH |
20 | #include <linux/of_dma.h> |
21 | #include <linux/of_device.h> | |
7bedaa55 RK |
22 | |
23 | #include "virt-dma.h" | |
7d7e1eba | 24 | |
7bedaa55 RK |
25 | struct omap_dmadev { |
26 | struct dma_device ddev; | |
27 | spinlock_t lock; | |
28 | struct tasklet_struct task; | |
29 | struct list_head pending; | |
1b416c4b | 30 | struct omap_system_dma_plat_info *plat; |
7bedaa55 RK |
31 | }; |
32 | ||
33 | struct omap_chan { | |
34 | struct virt_dma_chan vc; | |
35 | struct list_head node; | |
1b416c4b | 36 | struct omap_system_dma_plat_info *plat; |
7bedaa55 RK |
37 | |
38 | struct dma_slave_config cfg; | |
39 | unsigned dma_sig; | |
3a774ea9 | 40 | bool cyclic; |
2dcdf570 | 41 | bool paused; |
7bedaa55 RK |
42 | |
43 | int dma_ch; | |
44 | struct omap_desc *desc; | |
45 | unsigned sgidx; | |
46 | }; | |
47 | ||
48 | struct omap_sg { | |
49 | dma_addr_t addr; | |
50 | uint32_t en; /* number of elements (24-bit) */ | |
51 | uint32_t fn; /* number of frames (16-bit) */ | |
52 | }; | |
53 | ||
54 | struct omap_desc { | |
55 | struct virt_dma_desc vd; | |
56 | enum dma_transfer_direction dir; | |
57 | dma_addr_t dev_addr; | |
58 | ||
7c836bc7 | 59 | int16_t fi; /* for OMAP_DMA_SYNC_PACKET */ |
9043826d | 60 | uint8_t es; /* CSDP_DATA_TYPE_xxx */ |
3ed4d18f | 61 | uint32_t ccr; /* CCR value */ |
965aeb4d | 62 | uint16_t clnk_ctrl; /* CLNK_CTRL value */ |
fa3ad86a | 63 | uint16_t cicr; /* CICR value */ |
2f0d13bd | 64 | uint32_t csdp; /* CSDP value */ |
7bedaa55 RK |
65 | |
66 | unsigned sglen; | |
67 | struct omap_sg sg[0]; | |
68 | }; | |
69 | ||
9043826d RK |
70 | enum { |
71 | CCR_FS = BIT(5), | |
72 | CCR_READ_PRIORITY = BIT(6), | |
73 | CCR_ENABLE = BIT(7), | |
74 | CCR_AUTO_INIT = BIT(8), /* OMAP1 only */ | |
75 | CCR_REPEAT = BIT(9), /* OMAP1 only */ | |
76 | CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */ | |
77 | CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */ | |
78 | CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */ | |
79 | CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */ | |
80 | CCR_SRC_AMODE_CONSTANT = 0 << 12, | |
81 | CCR_SRC_AMODE_POSTINC = 1 << 12, | |
82 | CCR_SRC_AMODE_SGLIDX = 2 << 12, | |
83 | CCR_SRC_AMODE_DBLIDX = 3 << 12, | |
84 | CCR_DST_AMODE_CONSTANT = 0 << 14, | |
85 | CCR_DST_AMODE_POSTINC = 1 << 14, | |
86 | CCR_DST_AMODE_SGLIDX = 2 << 14, | |
87 | CCR_DST_AMODE_DBLIDX = 3 << 14, | |
88 | CCR_CONSTANT_FILL = BIT(16), | |
89 | CCR_TRANSPARENT_COPY = BIT(17), | |
90 | CCR_BS = BIT(18), | |
91 | CCR_SUPERVISOR = BIT(22), | |
92 | CCR_PREFETCH = BIT(23), | |
93 | CCR_TRIGGER_SRC = BIT(24), | |
94 | CCR_BUFFERING_DISABLE = BIT(25), | |
95 | CCR_WRITE_PRIORITY = BIT(26), | |
96 | CCR_SYNC_ELEMENT = 0, | |
97 | CCR_SYNC_FRAME = CCR_FS, | |
98 | CCR_SYNC_BLOCK = CCR_BS, | |
99 | CCR_SYNC_PACKET = CCR_BS | CCR_FS, | |
100 | ||
101 | CSDP_DATA_TYPE_8 = 0, | |
102 | CSDP_DATA_TYPE_16 = 1, | |
103 | CSDP_DATA_TYPE_32 = 2, | |
104 | CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */ | |
105 | CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */ | |
106 | CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */ | |
107 | CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */ | |
108 | CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */ | |
109 | CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */ | |
110 | CSDP_SRC_PACKED = BIT(6), | |
111 | CSDP_SRC_BURST_1 = 0 << 7, | |
112 | CSDP_SRC_BURST_16 = 1 << 7, | |
113 | CSDP_SRC_BURST_32 = 2 << 7, | |
114 | CSDP_SRC_BURST_64 = 3 << 7, | |
115 | CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */ | |
116 | CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */ | |
117 | CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */ | |
118 | CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */ | |
119 | CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */ | |
120 | CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */ | |
121 | CSDP_DST_PACKED = BIT(13), | |
122 | CSDP_DST_BURST_1 = 0 << 14, | |
123 | CSDP_DST_BURST_16 = 1 << 14, | |
124 | CSDP_DST_BURST_32 = 2 << 14, | |
125 | CSDP_DST_BURST_64 = 3 << 14, | |
126 | ||
127 | CICR_TOUT_IE = BIT(0), /* OMAP1 only */ | |
128 | CICR_DROP_IE = BIT(1), | |
129 | CICR_HALF_IE = BIT(2), | |
130 | CICR_FRAME_IE = BIT(3), | |
131 | CICR_LAST_IE = BIT(4), | |
132 | CICR_BLOCK_IE = BIT(5), | |
133 | CICR_PKT_IE = BIT(7), /* OMAP2+ only */ | |
134 | CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */ | |
135 | CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */ | |
136 | CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */ | |
137 | CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */ | |
138 | CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */ | |
139 | ||
140 | CLNK_CTRL_ENABLE_LNK = BIT(15), | |
141 | }; | |
142 | ||
7bedaa55 | 143 | static const unsigned es_bytes[] = { |
9043826d RK |
144 | [CSDP_DATA_TYPE_8] = 1, |
145 | [CSDP_DATA_TYPE_16] = 2, | |
146 | [CSDP_DATA_TYPE_32] = 4, | |
7bedaa55 RK |
147 | }; |
148 | ||
8d30662a JH |
149 | static struct of_dma_filter_info omap_dma_info = { |
150 | .filter_fn = omap_dma_filter_fn, | |
151 | }; | |
152 | ||
7bedaa55 RK |
153 | static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d) |
154 | { | |
155 | return container_of(d, struct omap_dmadev, ddev); | |
156 | } | |
157 | ||
158 | static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c) | |
159 | { | |
160 | return container_of(c, struct omap_chan, vc.chan); | |
161 | } | |
162 | ||
163 | static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t) | |
164 | { | |
165 | return container_of(t, struct omap_desc, vd.tx); | |
166 | } | |
167 | ||
168 | static void omap_dma_desc_free(struct virt_dma_desc *vd) | |
169 | { | |
170 | kfree(container_of(vd, struct omap_desc, vd)); | |
171 | } | |
172 | ||
470b23f7 RK |
173 | static void omap_dma_clear_csr(struct omap_chan *c) |
174 | { | |
175 | if (dma_omap1()) | |
176 | c->plat->dma_read(CSR, c->dma_ch); | |
177 | else | |
178 | c->plat->dma_write(~0, CSR, c->dma_ch); | |
179 | } | |
180 | ||
fa3ad86a RK |
181 | static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) |
182 | { | |
183 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
184 | uint32_t val; | |
185 | ||
186 | if (__dma_omap15xx(od->plat->dma_attr)) | |
187 | c->plat->dma_write(0, CPC, c->dma_ch); | |
188 | else | |
189 | c->plat->dma_write(0, CDAC, c->dma_ch); | |
190 | ||
470b23f7 | 191 | omap_dma_clear_csr(c); |
fa3ad86a RK |
192 | |
193 | /* Enable interrupts */ | |
194 | c->plat->dma_write(d->cicr, CICR, c->dma_ch); | |
195 | ||
196 | val = c->plat->dma_read(CCR, c->dma_ch); | |
9043826d | 197 | val |= CCR_ENABLE; |
fa3ad86a RK |
198 | c->plat->dma_write(val, CCR, c->dma_ch); |
199 | } | |
200 | ||
201 | static void omap_dma_stop(struct omap_chan *c) | |
202 | { | |
203 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
204 | uint32_t val; | |
205 | ||
206 | /* disable irq */ | |
207 | c->plat->dma_write(0, CICR, c->dma_ch); | |
208 | ||
470b23f7 | 209 | omap_dma_clear_csr(c); |
fa3ad86a RK |
210 | |
211 | val = c->plat->dma_read(CCR, c->dma_ch); | |
9043826d | 212 | if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { |
fa3ad86a RK |
213 | uint32_t sysconfig; |
214 | unsigned i; | |
215 | ||
216 | sysconfig = c->plat->dma_read(OCP_SYSCONFIG, c->dma_ch); | |
217 | val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK; | |
218 | val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
219 | c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch); | |
220 | ||
221 | val = c->plat->dma_read(CCR, c->dma_ch); | |
9043826d | 222 | val &= ~CCR_ENABLE; |
fa3ad86a RK |
223 | c->plat->dma_write(val, CCR, c->dma_ch); |
224 | ||
225 | /* Wait for sDMA FIFO to drain */ | |
226 | for (i = 0; ; i++) { | |
227 | val = c->plat->dma_read(CCR, c->dma_ch); | |
9043826d | 228 | if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))) |
fa3ad86a RK |
229 | break; |
230 | ||
231 | if (i > 100) | |
232 | break; | |
233 | ||
234 | udelay(5); | |
235 | } | |
236 | ||
9043826d | 237 | if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)) |
fa3ad86a RK |
238 | dev_err(c->vc.chan.device->dev, |
239 | "DMA drain did not complete on lch %d\n", | |
240 | c->dma_ch); | |
241 | ||
242 | c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch); | |
243 | } else { | |
9043826d | 244 | val &= ~CCR_ENABLE; |
fa3ad86a RK |
245 | c->plat->dma_write(val, CCR, c->dma_ch); |
246 | } | |
247 | ||
248 | mb(); | |
249 | ||
250 | if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) { | |
251 | val = c->plat->dma_read(CLNK_CTRL, c->dma_ch); | |
252 | ||
253 | if (dma_omap1()) | |
254 | val |= 1 << 14; /* set the STOP_LNK bit */ | |
255 | else | |
9043826d | 256 | val &= ~CLNK_CTRL_ENABLE_LNK; |
fa3ad86a RK |
257 | |
258 | c->plat->dma_write(val, CLNK_CTRL, c->dma_ch); | |
259 | } | |
260 | } | |
261 | ||
7bedaa55 RK |
262 | static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, |
263 | unsigned idx) | |
264 | { | |
265 | struct omap_sg *sg = d->sg + idx; | |
893e63e3 | 266 | unsigned cxsa, cxei, cxfi; |
913a2d0c RK |
267 | |
268 | if (d->dir == DMA_DEV_TO_MEM) { | |
893e63e3 RK |
269 | cxsa = CDSA; |
270 | cxei = CDEI; | |
271 | cxfi = CDFI; | |
913a2d0c | 272 | } else { |
893e63e3 RK |
273 | cxsa = CSSA; |
274 | cxei = CSEI; | |
275 | cxfi = CSFI; | |
913a2d0c RK |
276 | } |
277 | ||
893e63e3 RK |
278 | c->plat->dma_write(sg->addr, cxsa, c->dma_ch); |
279 | c->plat->dma_write(0, cxei, c->dma_ch); | |
280 | c->plat->dma_write(0, cxfi, c->dma_ch); | |
913a2d0c RK |
281 | c->plat->dma_write(sg->en, CEN, c->dma_ch); |
282 | c->plat->dma_write(sg->fn, CFN, c->dma_ch); | |
283 | ||
fa3ad86a | 284 | omap_dma_start(c, d); |
913a2d0c RK |
285 | } |
286 | ||
287 | static void omap_dma_start_desc(struct omap_chan *c) | |
288 | { | |
289 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); | |
290 | struct omap_desc *d; | |
893e63e3 | 291 | unsigned cxsa, cxei, cxfi; |
b9e97822 | 292 | |
913a2d0c RK |
293 | if (!vd) { |
294 | c->desc = NULL; | |
295 | return; | |
296 | } | |
297 | ||
298 | list_del(&vd->node); | |
299 | ||
300 | c->desc = d = to_omap_dma_desc(&vd->tx); | |
301 | c->sgidx = 0; | |
302 | ||
59871902 RK |
303 | /* |
304 | * This provides the necessary barrier to ensure data held in | |
305 | * DMA coherent memory is visible to the DMA engine prior to | |
306 | * the transfer starting. | |
307 | */ | |
308 | mb(); | |
309 | ||
3ed4d18f RK |
310 | c->plat->dma_write(d->ccr, CCR, c->dma_ch); |
311 | if (dma_omap1()) | |
312 | c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch); | |
b9e97822 | 313 | |
3ed4d18f | 314 | if (d->dir == DMA_DEV_TO_MEM) { |
893e63e3 RK |
315 | cxsa = CSSA; |
316 | cxei = CSEI; | |
317 | cxfi = CSFI; | |
b9e97822 | 318 | } else { |
893e63e3 RK |
319 | cxsa = CDSA; |
320 | cxei = CDEI; | |
321 | cxfi = CDFI; | |
b9e97822 RK |
322 | } |
323 | ||
893e63e3 RK |
324 | c->plat->dma_write(d->dev_addr, cxsa, c->dma_ch); |
325 | c->plat->dma_write(0, cxei, c->dma_ch); | |
326 | c->plat->dma_write(d->fi, cxfi, c->dma_ch); | |
2f0d13bd | 327 | c->plat->dma_write(d->csdp, CSDP, c->dma_ch); |
965aeb4d | 328 | c->plat->dma_write(d->clnk_ctrl, CLNK_CTRL, c->dma_ch); |
b9e97822 | 329 | |
7bedaa55 RK |
330 | omap_dma_start_sg(c, d, 0); |
331 | } | |
332 | ||
333 | static void omap_dma_callback(int ch, u16 status, void *data) | |
334 | { | |
335 | struct omap_chan *c = data; | |
336 | struct omap_desc *d; | |
337 | unsigned long flags; | |
338 | ||
339 | spin_lock_irqsave(&c->vc.lock, flags); | |
340 | d = c->desc; | |
341 | if (d) { | |
3a774ea9 RK |
342 | if (!c->cyclic) { |
343 | if (++c->sgidx < d->sglen) { | |
344 | omap_dma_start_sg(c, d, c->sgidx); | |
345 | } else { | |
346 | omap_dma_start_desc(c); | |
347 | vchan_cookie_complete(&d->vd); | |
348 | } | |
7bedaa55 | 349 | } else { |
3a774ea9 | 350 | vchan_cyclic_callback(&d->vd); |
7bedaa55 RK |
351 | } |
352 | } | |
353 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
354 | } | |
355 | ||
356 | /* | |
357 | * This callback schedules all pending channels. We could be more | |
358 | * clever here by postponing allocation of the real DMA channels to | |
359 | * this point, and freeing them when our virtual channel becomes idle. | |
360 | * | |
361 | * We would then need to deal with 'all channels in-use' | |
362 | */ | |
363 | static void omap_dma_sched(unsigned long data) | |
364 | { | |
365 | struct omap_dmadev *d = (struct omap_dmadev *)data; | |
366 | LIST_HEAD(head); | |
367 | ||
368 | spin_lock_irq(&d->lock); | |
369 | list_splice_tail_init(&d->pending, &head); | |
370 | spin_unlock_irq(&d->lock); | |
371 | ||
372 | while (!list_empty(&head)) { | |
373 | struct omap_chan *c = list_first_entry(&head, | |
374 | struct omap_chan, node); | |
375 | ||
376 | spin_lock_irq(&c->vc.lock); | |
377 | list_del_init(&c->node); | |
378 | omap_dma_start_desc(c); | |
379 | spin_unlock_irq(&c->vc.lock); | |
380 | } | |
381 | } | |
382 | ||
383 | static int omap_dma_alloc_chan_resources(struct dma_chan *chan) | |
384 | { | |
385 | struct omap_chan *c = to_omap_dma_chan(chan); | |
386 | ||
9e2f7d82 | 387 | dev_dbg(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig); |
7bedaa55 RK |
388 | |
389 | return omap_request_dma(c->dma_sig, "DMA engine", | |
390 | omap_dma_callback, c, &c->dma_ch); | |
391 | } | |
392 | ||
393 | static void omap_dma_free_chan_resources(struct dma_chan *chan) | |
394 | { | |
395 | struct omap_chan *c = to_omap_dma_chan(chan); | |
396 | ||
397 | vchan_free_chan_resources(&c->vc); | |
398 | omap_free_dma(c->dma_ch); | |
399 | ||
9e2f7d82 | 400 | dev_dbg(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig); |
7bedaa55 RK |
401 | } |
402 | ||
3850e22f RK |
403 | static size_t omap_dma_sg_size(struct omap_sg *sg) |
404 | { | |
405 | return sg->en * sg->fn; | |
406 | } | |
407 | ||
408 | static size_t omap_dma_desc_size(struct omap_desc *d) | |
409 | { | |
410 | unsigned i; | |
411 | size_t size; | |
412 | ||
413 | for (size = i = 0; i < d->sglen; i++) | |
414 | size += omap_dma_sg_size(&d->sg[i]); | |
415 | ||
416 | return size * es_bytes[d->es]; | |
417 | } | |
418 | ||
419 | static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr) | |
420 | { | |
421 | unsigned i; | |
422 | size_t size, es_size = es_bytes[d->es]; | |
423 | ||
424 | for (size = i = 0; i < d->sglen; i++) { | |
425 | size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size; | |
426 | ||
427 | if (size) | |
428 | size += this_size; | |
429 | else if (addr >= d->sg[i].addr && | |
430 | addr < d->sg[i].addr + this_size) | |
431 | size += d->sg[i].addr + this_size - addr; | |
432 | } | |
433 | return size; | |
434 | } | |
435 | ||
3997cab3 RK |
436 | static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c) |
437 | { | |
438 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
439 | dma_addr_t addr; | |
440 | ||
441 | if (__dma_omap15xx(od->plat->dma_attr)) | |
442 | addr = c->plat->dma_read(CPC, c->dma_ch); | |
443 | else | |
444 | addr = c->plat->dma_read(CSAC, c->dma_ch); | |
445 | ||
446 | if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0) | |
447 | addr = c->plat->dma_read(CSAC, c->dma_ch); | |
448 | ||
449 | if (!__dma_omap15xx(od->plat->dma_attr)) { | |
450 | /* | |
451 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
452 | * not been started (no data has been transferred so far). | |
453 | * Return the programmed source start address in this case. | |
454 | */ | |
455 | if (c->plat->dma_read(CDAC, c->dma_ch)) | |
456 | addr = c->plat->dma_read(CSAC, c->dma_ch); | |
457 | else | |
458 | addr = c->plat->dma_read(CSSA, c->dma_ch); | |
459 | } | |
460 | ||
461 | if (dma_omap1()) | |
462 | addr |= c->plat->dma_read(CSSA, c->dma_ch) & 0xffff0000; | |
463 | ||
464 | return addr; | |
465 | } | |
466 | ||
467 | static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c) | |
468 | { | |
469 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
470 | dma_addr_t addr; | |
471 | ||
472 | if (__dma_omap15xx(od->plat->dma_attr)) | |
473 | addr = c->plat->dma_read(CPC, c->dma_ch); | |
474 | else | |
475 | addr = c->plat->dma_read(CDAC, c->dma_ch); | |
476 | ||
477 | /* | |
478 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
479 | * read before the DMA controller finished disabling the channel. | |
480 | */ | |
481 | if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) { | |
482 | addr = c->plat->dma_read(CDAC, c->dma_ch); | |
483 | /* | |
484 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
485 | * not been started (no data has been transferred so far). | |
486 | * Return the programmed destination start address in this case. | |
487 | */ | |
488 | if (addr == 0) | |
489 | addr = c->plat->dma_read(CDSA, c->dma_ch); | |
490 | } | |
491 | ||
492 | if (dma_omap1()) | |
493 | addr |= c->plat->dma_read(CDSA, c->dma_ch) & 0xffff0000; | |
494 | ||
495 | return addr; | |
496 | } | |
497 | ||
7bedaa55 RK |
498 | static enum dma_status omap_dma_tx_status(struct dma_chan *chan, |
499 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
500 | { | |
3850e22f RK |
501 | struct omap_chan *c = to_omap_dma_chan(chan); |
502 | struct virt_dma_desc *vd; | |
503 | enum dma_status ret; | |
504 | unsigned long flags; | |
505 | ||
506 | ret = dma_cookie_status(chan, cookie, txstate); | |
7cce5083 | 507 | if (ret == DMA_COMPLETE || !txstate) |
3850e22f RK |
508 | return ret; |
509 | ||
510 | spin_lock_irqsave(&c->vc.lock, flags); | |
511 | vd = vchan_find_desc(&c->vc, cookie); | |
512 | if (vd) { | |
513 | txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx)); | |
514 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { | |
515 | struct omap_desc *d = c->desc; | |
516 | dma_addr_t pos; | |
517 | ||
518 | if (d->dir == DMA_MEM_TO_DEV) | |
3997cab3 | 519 | pos = omap_dma_get_src_pos(c); |
3850e22f | 520 | else if (d->dir == DMA_DEV_TO_MEM) |
3997cab3 | 521 | pos = omap_dma_get_dst_pos(c); |
3850e22f RK |
522 | else |
523 | pos = 0; | |
524 | ||
525 | txstate->residue = omap_dma_desc_size_pos(d, pos); | |
526 | } else { | |
527 | txstate->residue = 0; | |
528 | } | |
529 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
530 | ||
531 | return ret; | |
7bedaa55 RK |
532 | } |
533 | ||
534 | static void omap_dma_issue_pending(struct dma_chan *chan) | |
535 | { | |
536 | struct omap_chan *c = to_omap_dma_chan(chan); | |
537 | unsigned long flags; | |
538 | ||
539 | spin_lock_irqsave(&c->vc.lock, flags); | |
540 | if (vchan_issue_pending(&c->vc) && !c->desc) { | |
76502469 PU |
541 | /* |
542 | * c->cyclic is used only by audio and in this case the DMA need | |
543 | * to be started without delay. | |
544 | */ | |
545 | if (!c->cyclic) { | |
546 | struct omap_dmadev *d = to_omap_dma_dev(chan->device); | |
547 | spin_lock(&d->lock); | |
548 | if (list_empty(&c->node)) | |
549 | list_add_tail(&c->node, &d->pending); | |
550 | spin_unlock(&d->lock); | |
551 | tasklet_schedule(&d->task); | |
552 | } else { | |
553 | omap_dma_start_desc(c); | |
554 | } | |
7bedaa55 RK |
555 | } |
556 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
557 | } | |
558 | ||
559 | static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg( | |
560 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen, | |
561 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) | |
562 | { | |
49ae0b29 | 563 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
564 | struct omap_chan *c = to_omap_dma_chan(chan); |
565 | enum dma_slave_buswidth dev_width; | |
566 | struct scatterlist *sgent; | |
567 | struct omap_desc *d; | |
568 | dma_addr_t dev_addr; | |
3ed4d18f | 569 | unsigned i, j = 0, es, en, frame_bytes; |
7bedaa55 RK |
570 | u32 burst; |
571 | ||
572 | if (dir == DMA_DEV_TO_MEM) { | |
573 | dev_addr = c->cfg.src_addr; | |
574 | dev_width = c->cfg.src_addr_width; | |
575 | burst = c->cfg.src_maxburst; | |
7bedaa55 RK |
576 | } else if (dir == DMA_MEM_TO_DEV) { |
577 | dev_addr = c->cfg.dst_addr; | |
578 | dev_width = c->cfg.dst_addr_width; | |
579 | burst = c->cfg.dst_maxburst; | |
7bedaa55 RK |
580 | } else { |
581 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
582 | return NULL; | |
583 | } | |
584 | ||
585 | /* Bus width translates to the element size (ES) */ | |
586 | switch (dev_width) { | |
587 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 588 | es = CSDP_DATA_TYPE_8; |
7bedaa55 RK |
589 | break; |
590 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 591 | es = CSDP_DATA_TYPE_16; |
7bedaa55 RK |
592 | break; |
593 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 594 | es = CSDP_DATA_TYPE_32; |
7bedaa55 RK |
595 | break; |
596 | default: /* not reached */ | |
597 | return NULL; | |
598 | } | |
599 | ||
600 | /* Now allocate and setup the descriptor. */ | |
601 | d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC); | |
602 | if (!d) | |
603 | return NULL; | |
604 | ||
605 | d->dir = dir; | |
606 | d->dev_addr = dev_addr; | |
607 | d->es = es; | |
3ed4d18f | 608 | |
9043826d | 609 | d->ccr = CCR_SYNC_FRAME; |
3ed4d18f | 610 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 611 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 612 | else |
9043826d | 613 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 614 | |
9043826d | 615 | d->cicr = CICR_DROP_IE | CICR_BLOCK_IE; |
2f0d13bd | 616 | d->csdp = es; |
fa3ad86a | 617 | |
2f0d13bd | 618 | if (dma_omap1()) { |
3ed4d18f | 619 | if (__dma_omap16xx(od->plat->dma_attr)) { |
9043826d | 620 | d->ccr |= CCR_OMAP31_DISABLE; |
3ed4d18f RK |
621 | /* Duplicate what plat-omap/dma.c does */ |
622 | d->ccr |= c->dma_ch + 1; | |
623 | } else { | |
624 | d->ccr |= c->dma_sig & 0x1f; | |
625 | } | |
626 | ||
9043826d | 627 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
628 | |
629 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 630 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB; |
2f0d13bd | 631 | else |
9043826d | 632 | d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 633 | } else { |
3ed4d18f RK |
634 | d->ccr |= (c->dma_sig & ~0x1f) << 14; |
635 | d->ccr |= c->dma_sig & 0x1f; | |
3ed4d18f RK |
636 | |
637 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 638 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 639 | |
9043826d | 640 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
2f0d13bd | 641 | } |
49ae0b29 RK |
642 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
643 | d->ccr |= CCR_BUFFERING_DISABLE; | |
965aeb4d RK |
644 | if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS) |
645 | d->clnk_ctrl = c->dma_ch; | |
7bedaa55 RK |
646 | |
647 | /* | |
648 | * Build our scatterlist entries: each contains the address, | |
649 | * the number of elements (EN) in each frame, and the number of | |
650 | * frames (FN). Number of bytes for this entry = ES * EN * FN. | |
651 | * | |
652 | * Burst size translates to number of elements with frame sync. | |
653 | * Note: DMA engine defines burst to be the number of dev-width | |
654 | * transfers. | |
655 | */ | |
656 | en = burst; | |
657 | frame_bytes = es_bytes[es] * en; | |
658 | for_each_sg(sgl, sgent, sglen, i) { | |
659 | d->sg[j].addr = sg_dma_address(sgent); | |
660 | d->sg[j].en = en; | |
661 | d->sg[j].fn = sg_dma_len(sgent) / frame_bytes; | |
662 | j++; | |
663 | } | |
664 | ||
665 | d->sglen = j; | |
666 | ||
667 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); | |
668 | } | |
669 | ||
3a774ea9 RK |
670 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( |
671 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
ec8b5e48 PU |
672 | size_t period_len, enum dma_transfer_direction dir, unsigned long flags, |
673 | void *context) | |
3a774ea9 | 674 | { |
fa3ad86a | 675 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
3a774ea9 RK |
676 | struct omap_chan *c = to_omap_dma_chan(chan); |
677 | enum dma_slave_buswidth dev_width; | |
678 | struct omap_desc *d; | |
679 | dma_addr_t dev_addr; | |
3ed4d18f | 680 | unsigned es; |
3a774ea9 RK |
681 | u32 burst; |
682 | ||
683 | if (dir == DMA_DEV_TO_MEM) { | |
684 | dev_addr = c->cfg.src_addr; | |
685 | dev_width = c->cfg.src_addr_width; | |
686 | burst = c->cfg.src_maxburst; | |
3a774ea9 RK |
687 | } else if (dir == DMA_MEM_TO_DEV) { |
688 | dev_addr = c->cfg.dst_addr; | |
689 | dev_width = c->cfg.dst_addr_width; | |
690 | burst = c->cfg.dst_maxburst; | |
3a774ea9 RK |
691 | } else { |
692 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
693 | return NULL; | |
694 | } | |
695 | ||
696 | /* Bus width translates to the element size (ES) */ | |
697 | switch (dev_width) { | |
698 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 699 | es = CSDP_DATA_TYPE_8; |
3a774ea9 RK |
700 | break; |
701 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 702 | es = CSDP_DATA_TYPE_16; |
3a774ea9 RK |
703 | break; |
704 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 705 | es = CSDP_DATA_TYPE_32; |
3a774ea9 RK |
706 | break; |
707 | default: /* not reached */ | |
708 | return NULL; | |
709 | } | |
710 | ||
711 | /* Now allocate and setup the descriptor. */ | |
712 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); | |
713 | if (!d) | |
714 | return NULL; | |
715 | ||
716 | d->dir = dir; | |
717 | d->dev_addr = dev_addr; | |
718 | d->fi = burst; | |
719 | d->es = es; | |
3a774ea9 RK |
720 | d->sg[0].addr = buf_addr; |
721 | d->sg[0].en = period_len / es_bytes[es]; | |
722 | d->sg[0].fn = buf_len / period_len; | |
723 | d->sglen = 1; | |
3ed4d18f RK |
724 | |
725 | d->ccr = 0; | |
3ed4d18f | 726 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 727 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 728 | else |
9043826d | 729 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 730 | |
9043826d | 731 | d->cicr = CICR_DROP_IE; |
fa3ad86a | 732 | if (flags & DMA_PREP_INTERRUPT) |
9043826d | 733 | d->cicr |= CICR_FRAME_IE; |
fa3ad86a | 734 | |
2f0d13bd RK |
735 | d->csdp = es; |
736 | ||
737 | if (dma_omap1()) { | |
3ed4d18f | 738 | if (__dma_omap16xx(od->plat->dma_attr)) { |
9043826d | 739 | d->ccr |= CCR_OMAP31_DISABLE; |
3ed4d18f RK |
740 | /* Duplicate what plat-omap/dma.c does */ |
741 | d->ccr |= c->dma_ch + 1; | |
742 | } else { | |
743 | d->ccr |= c->dma_sig & 0x1f; | |
744 | } | |
745 | ||
9043826d | 746 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
747 | |
748 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 749 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI; |
2f0d13bd | 750 | else |
9043826d | 751 | d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 752 | } else { |
3ed4d18f RK |
753 | d->ccr |= (c->dma_sig & ~0x1f) << 14; |
754 | d->ccr |= c->dma_sig & 0x1f; | |
755 | ||
756 | if (burst) | |
9043826d RK |
757 | d->ccr |= CCR_SYNC_PACKET; |
758 | else | |
759 | d->ccr |= CCR_SYNC_ELEMENT; | |
3ed4d18f RK |
760 | |
761 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 762 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 763 | |
9043826d | 764 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
3a774ea9 | 765 | |
9043826d | 766 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
2f0d13bd | 767 | } |
49ae0b29 RK |
768 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
769 | d->ccr |= CCR_BUFFERING_DISABLE; | |
2f0d13bd | 770 | |
965aeb4d RK |
771 | if (__dma_omap15xx(od->plat->dma_attr)) |
772 | d->ccr |= CCR_AUTO_INIT | CCR_REPEAT; | |
773 | else | |
774 | d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK; | |
775 | ||
3ed4d18f | 776 | c->cyclic = true; |
3a774ea9 | 777 | |
2dde5b90 | 778 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
3a774ea9 RK |
779 | } |
780 | ||
7bedaa55 RK |
781 | static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg) |
782 | { | |
783 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
784 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
785 | return -EINVAL; | |
786 | ||
787 | memcpy(&c->cfg, cfg, sizeof(c->cfg)); | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
792 | static int omap_dma_terminate_all(struct omap_chan *c) | |
793 | { | |
794 | struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device); | |
795 | unsigned long flags; | |
796 | LIST_HEAD(head); | |
797 | ||
798 | spin_lock_irqsave(&c->vc.lock, flags); | |
799 | ||
800 | /* Prevent this channel being scheduled */ | |
801 | spin_lock(&d->lock); | |
802 | list_del_init(&c->node); | |
803 | spin_unlock(&d->lock); | |
804 | ||
805 | /* | |
806 | * Stop DMA activity: we assume the callback will not be called | |
fa3ad86a | 807 | * after omap_dma_stop() returns (even if it does, it will see |
7bedaa55 RK |
808 | * c->desc is NULL and exit.) |
809 | */ | |
810 | if (c->desc) { | |
811 | c->desc = NULL; | |
2dcdf570 PU |
812 | /* Avoid stopping the dma twice */ |
813 | if (!c->paused) | |
fa3ad86a | 814 | omap_dma_stop(c); |
7bedaa55 RK |
815 | } |
816 | ||
3a774ea9 RK |
817 | if (c->cyclic) { |
818 | c->cyclic = false; | |
2dcdf570 | 819 | c->paused = false; |
3a774ea9 RK |
820 | } |
821 | ||
7bedaa55 RK |
822 | vchan_get_all_descriptors(&c->vc, &head); |
823 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
824 | vchan_dma_desc_free_list(&c->vc, &head); | |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
829 | static int omap_dma_pause(struct omap_chan *c) | |
830 | { | |
2dcdf570 PU |
831 | /* Pause/Resume only allowed with cyclic mode */ |
832 | if (!c->cyclic) | |
833 | return -EINVAL; | |
834 | ||
835 | if (!c->paused) { | |
fa3ad86a | 836 | omap_dma_stop(c); |
2dcdf570 PU |
837 | c->paused = true; |
838 | } | |
839 | ||
840 | return 0; | |
7bedaa55 RK |
841 | } |
842 | ||
843 | static int omap_dma_resume(struct omap_chan *c) | |
844 | { | |
2dcdf570 PU |
845 | /* Pause/Resume only allowed with cyclic mode */ |
846 | if (!c->cyclic) | |
847 | return -EINVAL; | |
848 | ||
849 | if (c->paused) { | |
fa3ad86a | 850 | omap_dma_start(c, c->desc); |
2dcdf570 PU |
851 | c->paused = false; |
852 | } | |
853 | ||
854 | return 0; | |
7bedaa55 RK |
855 | } |
856 | ||
857 | static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
858 | unsigned long arg) | |
859 | { | |
860 | struct omap_chan *c = to_omap_dma_chan(chan); | |
861 | int ret; | |
862 | ||
863 | switch (cmd) { | |
864 | case DMA_SLAVE_CONFIG: | |
865 | ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg); | |
866 | break; | |
867 | ||
868 | case DMA_TERMINATE_ALL: | |
869 | ret = omap_dma_terminate_all(c); | |
870 | break; | |
871 | ||
872 | case DMA_PAUSE: | |
873 | ret = omap_dma_pause(c); | |
874 | break; | |
875 | ||
876 | case DMA_RESUME: | |
877 | ret = omap_dma_resume(c); | |
878 | break; | |
879 | ||
880 | default: | |
881 | ret = -ENXIO; | |
882 | break; | |
883 | } | |
884 | ||
885 | return ret; | |
886 | } | |
887 | ||
888 | static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig) | |
889 | { | |
890 | struct omap_chan *c; | |
891 | ||
892 | c = kzalloc(sizeof(*c), GFP_KERNEL); | |
893 | if (!c) | |
894 | return -ENOMEM; | |
895 | ||
1b416c4b | 896 | c->plat = od->plat; |
7bedaa55 RK |
897 | c->dma_sig = dma_sig; |
898 | c->vc.desc_free = omap_dma_desc_free; | |
899 | vchan_init(&c->vc, &od->ddev); | |
900 | INIT_LIST_HEAD(&c->node); | |
901 | ||
902 | od->ddev.chancnt++; | |
903 | ||
904 | return 0; | |
905 | } | |
906 | ||
907 | static void omap_dma_free(struct omap_dmadev *od) | |
908 | { | |
909 | tasklet_kill(&od->task); | |
910 | while (!list_empty(&od->ddev.channels)) { | |
911 | struct omap_chan *c = list_first_entry(&od->ddev.channels, | |
912 | struct omap_chan, vc.chan.device_node); | |
913 | ||
914 | list_del(&c->vc.chan.device_node); | |
915 | tasklet_kill(&c->vc.task); | |
916 | kfree(c); | |
917 | } | |
7bedaa55 RK |
918 | } |
919 | ||
920 | static int omap_dma_probe(struct platform_device *pdev) | |
921 | { | |
922 | struct omap_dmadev *od; | |
923 | int rc, i; | |
924 | ||
104fce73 | 925 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); |
7bedaa55 RK |
926 | if (!od) |
927 | return -ENOMEM; | |
928 | ||
1b416c4b RK |
929 | od->plat = omap_get_plat_info(); |
930 | if (!od->plat) | |
931 | return -EPROBE_DEFER; | |
932 | ||
7bedaa55 | 933 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
3a774ea9 | 934 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
7bedaa55 RK |
935 | od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources; |
936 | od->ddev.device_free_chan_resources = omap_dma_free_chan_resources; | |
937 | od->ddev.device_tx_status = omap_dma_tx_status; | |
938 | od->ddev.device_issue_pending = omap_dma_issue_pending; | |
939 | od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg; | |
3a774ea9 | 940 | od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic; |
7bedaa55 RK |
941 | od->ddev.device_control = omap_dma_control; |
942 | od->ddev.dev = &pdev->dev; | |
943 | INIT_LIST_HEAD(&od->ddev.channels); | |
944 | INIT_LIST_HEAD(&od->pending); | |
945 | spin_lock_init(&od->lock); | |
946 | ||
947 | tasklet_init(&od->task, omap_dma_sched, (unsigned long)od); | |
948 | ||
949 | for (i = 0; i < 127; i++) { | |
950 | rc = omap_dma_chan_init(od, i); | |
951 | if (rc) { | |
952 | omap_dma_free(od); | |
953 | return rc; | |
954 | } | |
955 | } | |
956 | ||
957 | rc = dma_async_device_register(&od->ddev); | |
958 | if (rc) { | |
959 | pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", | |
960 | rc); | |
961 | omap_dma_free(od); | |
8d30662a JH |
962 | return rc; |
963 | } | |
964 | ||
965 | platform_set_drvdata(pdev, od); | |
966 | ||
967 | if (pdev->dev.of_node) { | |
968 | omap_dma_info.dma_cap = od->ddev.cap_mask; | |
969 | ||
970 | /* Device-tree DMA controller registration */ | |
971 | rc = of_dma_controller_register(pdev->dev.of_node, | |
972 | of_dma_simple_xlate, &omap_dma_info); | |
973 | if (rc) { | |
974 | pr_warn("OMAP-DMA: failed to register DMA controller\n"); | |
975 | dma_async_device_unregister(&od->ddev); | |
976 | omap_dma_free(od); | |
977 | } | |
7bedaa55 RK |
978 | } |
979 | ||
980 | dev_info(&pdev->dev, "OMAP DMA engine driver\n"); | |
981 | ||
982 | return rc; | |
983 | } | |
984 | ||
985 | static int omap_dma_remove(struct platform_device *pdev) | |
986 | { | |
987 | struct omap_dmadev *od = platform_get_drvdata(pdev); | |
988 | ||
8d30662a JH |
989 | if (pdev->dev.of_node) |
990 | of_dma_controller_free(pdev->dev.of_node); | |
991 | ||
7bedaa55 RK |
992 | dma_async_device_unregister(&od->ddev); |
993 | omap_dma_free(od); | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
8d30662a JH |
998 | static const struct of_device_id omap_dma_match[] = { |
999 | { .compatible = "ti,omap2420-sdma", }, | |
1000 | { .compatible = "ti,omap2430-sdma", }, | |
1001 | { .compatible = "ti,omap3430-sdma", }, | |
1002 | { .compatible = "ti,omap3630-sdma", }, | |
1003 | { .compatible = "ti,omap4430-sdma", }, | |
1004 | {}, | |
1005 | }; | |
1006 | MODULE_DEVICE_TABLE(of, omap_dma_match); | |
1007 | ||
7bedaa55 RK |
1008 | static struct platform_driver omap_dma_driver = { |
1009 | .probe = omap_dma_probe, | |
1010 | .remove = omap_dma_remove, | |
1011 | .driver = { | |
1012 | .name = "omap-dma-engine", | |
1013 | .owner = THIS_MODULE, | |
8d30662a | 1014 | .of_match_table = of_match_ptr(omap_dma_match), |
7bedaa55 RK |
1015 | }, |
1016 | }; | |
1017 | ||
1018 | bool omap_dma_filter_fn(struct dma_chan *chan, void *param) | |
1019 | { | |
1020 | if (chan->device->dev->driver == &omap_dma_driver.driver) { | |
1021 | struct omap_chan *c = to_omap_dma_chan(chan); | |
1022 | unsigned req = *(unsigned *)param; | |
1023 | ||
1024 | return req == c->dma_sig; | |
1025 | } | |
1026 | return false; | |
1027 | } | |
1028 | EXPORT_SYMBOL_GPL(omap_dma_filter_fn); | |
1029 | ||
7bedaa55 RK |
1030 | static int omap_dma_init(void) |
1031 | { | |
be1f9481 | 1032 | return platform_driver_register(&omap_dma_driver); |
7bedaa55 RK |
1033 | } |
1034 | subsys_initcall(omap_dma_init); | |
1035 | ||
1036 | static void __exit omap_dma_exit(void) | |
1037 | { | |
7bedaa55 RK |
1038 | platform_driver_unregister(&omap_dma_driver); |
1039 | } | |
1040 | module_exit(omap_dma_exit); | |
1041 | ||
1042 | MODULE_AUTHOR("Russell King"); | |
1043 | MODULE_LICENSE("GPL"); |