]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/dma/pl330.c
Merge tag 'tpmdd-next-20151110' of https://github.com/jsakkine/linux-tpmdd into for...
[mirror_ubuntu-zesty-kernel.git] / drivers / dma / pl330.c
CommitLineData
b7d861d9
BK
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
b3040e40
JB
4 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
b7d861d9 14#include <linux/kernel.h>
b3040e40
JB
15#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
b7d861d9
BK
19#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
b3040e40 23#include <linux/dmaengine.h>
b3040e40
JB
24#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
1b9bb715 26#include <linux/scatterlist.h>
93ed5544 27#include <linux/of.h>
a80258f9 28#include <linux/of_dma.h>
bcc7fa95 29#include <linux/err.h>
ae43b328 30#include <linux/pm_runtime.h>
b3040e40 31
d2ebfb33 32#include "dmaengine.h"
b7d861d9
BK
33#define PL330_MAX_CHAN 8
34#define PL330_MAX_IRQS 32
35#define PL330_MAX_PERI 32
36
f0564c7e
LPC
37enum pl330_cachectrl {
38 CCTRL0, /* Noncacheable and nonbufferable */
39 CCTRL1, /* Bufferable only */
40 CCTRL2, /* Cacheable, but do not allocate */
41 CCTRL3, /* Cacheable and bufferable, but do not allocate */
42 INVALID1, /* AWCACHE = 0x1000 */
43 INVALID2,
44 CCTRL6, /* Cacheable write-through, allocate on writes only */
45 CCTRL7, /* Cacheable write-back, allocate on writes only */
b7d861d9
BK
46};
47
48enum pl330_byteswap {
49 SWAP_NO,
50 SWAP_2,
51 SWAP_4,
52 SWAP_8,
53 SWAP_16,
54};
55
b7d861d9
BK
56/* Register and Bit field Definitions */
57#define DS 0x0
58#define DS_ST_STOP 0x0
59#define DS_ST_EXEC 0x1
60#define DS_ST_CMISS 0x2
61#define DS_ST_UPDTPC 0x3
62#define DS_ST_WFE 0x4
63#define DS_ST_ATBRR 0x5
64#define DS_ST_QBUSY 0x6
65#define DS_ST_WFP 0x7
66#define DS_ST_KILL 0x8
67#define DS_ST_CMPLT 0x9
68#define DS_ST_FLTCMP 0xe
69#define DS_ST_FAULT 0xf
70
71#define DPC 0x4
72#define INTEN 0x20
73#define ES 0x24
74#define INTSTATUS 0x28
75#define INTCLR 0x2c
76#define FSM 0x30
77#define FSC 0x34
78#define FTM 0x38
79
80#define _FTC 0x40
81#define FTC(n) (_FTC + (n)*0x4)
82
83#define _CS 0x100
84#define CS(n) (_CS + (n)*0x8)
85#define CS_CNS (1 << 21)
86
87#define _CPC 0x104
88#define CPC(n) (_CPC + (n)*0x8)
89
90#define _SA 0x400
91#define SA(n) (_SA + (n)*0x20)
92
93#define _DA 0x404
94#define DA(n) (_DA + (n)*0x20)
95
96#define _CC 0x408
97#define CC(n) (_CC + (n)*0x20)
98
99#define CC_SRCINC (1 << 0)
100#define CC_DSTINC (1 << 14)
101#define CC_SRCPRI (1 << 8)
102#define CC_DSTPRI (1 << 22)
103#define CC_SRCNS (1 << 9)
104#define CC_DSTNS (1 << 23)
105#define CC_SRCIA (1 << 10)
106#define CC_DSTIA (1 << 24)
107#define CC_SRCBRSTLEN_SHFT 4
108#define CC_DSTBRSTLEN_SHFT 18
109#define CC_SRCBRSTSIZE_SHFT 1
110#define CC_DSTBRSTSIZE_SHFT 15
111#define CC_SRCCCTRL_SHFT 11
112#define CC_SRCCCTRL_MASK 0x7
113#define CC_DSTCCTRL_SHFT 25
114#define CC_DRCCCTRL_MASK 0x7
115#define CC_SWAP_SHFT 28
116
117#define _LC0 0x40c
118#define LC0(n) (_LC0 + (n)*0x20)
119
120#define _LC1 0x410
121#define LC1(n) (_LC1 + (n)*0x20)
122
123#define DBGSTATUS 0xd00
124#define DBG_BUSY (1 << 0)
125
126#define DBGCMD 0xd04
127#define DBGINST0 0xd08
128#define DBGINST1 0xd0c
129
130#define CR0 0xe00
131#define CR1 0xe04
132#define CR2 0xe08
133#define CR3 0xe0c
134#define CR4 0xe10
135#define CRD 0xe14
136
137#define PERIPH_ID 0xfe0
3ecf51a4
BK
138#define PERIPH_REV_SHIFT 20
139#define PERIPH_REV_MASK 0xf
140#define PERIPH_REV_R0P0 0
141#define PERIPH_REV_R1P0 1
142#define PERIPH_REV_R1P1 2
b7d861d9
BK
143
144#define CR0_PERIPH_REQ_SET (1 << 0)
145#define CR0_BOOT_EN_SET (1 << 1)
146#define CR0_BOOT_MAN_NS (1 << 2)
147#define CR0_NUM_CHANS_SHIFT 4
148#define CR0_NUM_CHANS_MASK 0x7
149#define CR0_NUM_PERIPH_SHIFT 12
150#define CR0_NUM_PERIPH_MASK 0x1f
151#define CR0_NUM_EVENTS_SHIFT 17
152#define CR0_NUM_EVENTS_MASK 0x1f
153
154#define CR1_ICACHE_LEN_SHIFT 0
155#define CR1_ICACHE_LEN_MASK 0x7
156#define CR1_NUM_ICACHELINES_SHIFT 4
157#define CR1_NUM_ICACHELINES_MASK 0xf
158
159#define CRD_DATA_WIDTH_SHIFT 0
160#define CRD_DATA_WIDTH_MASK 0x7
161#define CRD_WR_CAP_SHIFT 4
162#define CRD_WR_CAP_MASK 0x7
163#define CRD_WR_Q_DEP_SHIFT 8
164#define CRD_WR_Q_DEP_MASK 0xf
165#define CRD_RD_CAP_SHIFT 12
166#define CRD_RD_CAP_MASK 0x7
167#define CRD_RD_Q_DEP_SHIFT 16
168#define CRD_RD_Q_DEP_MASK 0xf
169#define CRD_DATA_BUFF_SHIFT 20
170#define CRD_DATA_BUFF_MASK 0x3ff
171
172#define PART 0x330
173#define DESIGNER 0x41
174#define REVISION 0x0
175#define INTEG_CFG 0x0
176#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
177
b7d861d9
BK
178#define PL330_STATE_STOPPED (1 << 0)
179#define PL330_STATE_EXECUTING (1 << 1)
180#define PL330_STATE_WFE (1 << 2)
181#define PL330_STATE_FAULTING (1 << 3)
182#define PL330_STATE_COMPLETING (1 << 4)
183#define PL330_STATE_WFP (1 << 5)
184#define PL330_STATE_KILLING (1 << 6)
185#define PL330_STATE_FAULT_COMPLETING (1 << 7)
186#define PL330_STATE_CACHEMISS (1 << 8)
187#define PL330_STATE_UPDTPC (1 << 9)
188#define PL330_STATE_ATBARRIER (1 << 10)
189#define PL330_STATE_QUEUEBUSY (1 << 11)
190#define PL330_STATE_INVALID (1 << 15)
191
192#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
193 | PL330_STATE_WFE | PL330_STATE_FAULTING)
194
195#define CMD_DMAADDH 0x54
196#define CMD_DMAEND 0x00
197#define CMD_DMAFLUSHP 0x35
198#define CMD_DMAGO 0xa0
199#define CMD_DMALD 0x04
200#define CMD_DMALDP 0x25
201#define CMD_DMALP 0x20
202#define CMD_DMALPEND 0x28
203#define CMD_DMAKILL 0x01
204#define CMD_DMAMOV 0xbc
205#define CMD_DMANOP 0x18
206#define CMD_DMARMB 0x12
207#define CMD_DMASEV 0x34
208#define CMD_DMAST 0x08
209#define CMD_DMASTP 0x29
210#define CMD_DMASTZ 0x0c
211#define CMD_DMAWFE 0x36
212#define CMD_DMAWFP 0x30
213#define CMD_DMAWMB 0x13
214
215#define SZ_DMAADDH 3
216#define SZ_DMAEND 1
217#define SZ_DMAFLUSHP 2
218#define SZ_DMALD 1
219#define SZ_DMALDP 2
220#define SZ_DMALP 2
221#define SZ_DMALPEND 2
222#define SZ_DMAKILL 1
223#define SZ_DMAMOV 6
224#define SZ_DMANOP 1
225#define SZ_DMARMB 1
226#define SZ_DMASEV 2
227#define SZ_DMAST 1
228#define SZ_DMASTP 2
229#define SZ_DMASTZ 1
230#define SZ_DMAWFE 2
231#define SZ_DMAWFP 2
232#define SZ_DMAWMB 1
233#define SZ_DMAGO 6
234
235#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
236#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
237
238#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
239#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
240
241/*
242 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
243 * at 1byte/burst for P<->M and M<->M respectively.
244 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
245 * should be enough for P<->M and M<->M respectively.
246 */
247#define MCODE_BUFF_PER_REQ 256
248
b7d861d9
BK
249/* Use this _only_ to wait on transient states */
250#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
251
252#ifdef PL330_DEBUG_MCGEN
253static unsigned cmd_line;
254#define PL330_DBGCMD_DUMP(off, x...) do { \
255 printk("%x:", cmd_line); \
256 printk(x); \
257 cmd_line += off; \
258 } while (0)
259#define PL330_DBGMC_START(addr) (cmd_line = addr)
260#else
261#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
262#define PL330_DBGMC_START(addr) do {} while (0)
263#endif
264
265/* The number of default descriptors */
d2ebfb33 266
b3040e40
JB
267#define NR_DEFAULT_DESC 16
268
ae43b328
KK
269/* Delay for runtime PM autosuspend, ms */
270#define PL330_AUTOSUSPEND_DELAY 20
271
b7d861d9
BK
272/* Populated by the PL330 core driver for DMA API driver's info */
273struct pl330_config {
274 u32 periph_id;
b7d861d9
BK
275#define DMAC_MODE_NS (1 << 0)
276 unsigned int mode;
277 unsigned int data_bus_width:10; /* In number of bits */
1f0a5cbf 278 unsigned int data_buf_dep:11;
b7d861d9
BK
279 unsigned int num_chan:4;
280 unsigned int num_peri:6;
281 u32 peri_ns;
282 unsigned int num_events:6;
283 u32 irq_ns;
284};
285
b7d861d9
BK
286/**
287 * Request Configuration.
288 * The PL330 core does not modify this and uses the last
289 * working configuration if the request doesn't provide any.
290 *
291 * The Client may want to provide this info only for the
292 * first request and a request with new settings.
293 */
294struct pl330_reqcfg {
295 /* Address Incrementing */
296 unsigned dst_inc:1;
297 unsigned src_inc:1;
298
299 /*
300 * For now, the SRC & DST protection levels
301 * and burst size/length are assumed same.
302 */
303 bool nonsecure;
304 bool privileged;
305 bool insnaccess;
306 unsigned brst_len:5;
307 unsigned brst_size:3; /* in power of 2 */
308
f0564c7e
LPC
309 enum pl330_cachectrl dcctl;
310 enum pl330_cachectrl scctl;
b7d861d9 311 enum pl330_byteswap swap;
3ecf51a4 312 struct pl330_config *pcfg;
b7d861d9
BK
313};
314
315/*
316 * One cycle of DMAC operation.
317 * There may be more than one xfer in a request.
318 */
319struct pl330_xfer {
320 u32 src_addr;
321 u32 dst_addr;
322 /* Size to xfer */
323 u32 bytes;
b7d861d9
BK
324};
325
326/* The xfer callbacks are made with one of these arguments. */
327enum pl330_op_err {
328 /* The all xfers in the request were success. */
329 PL330_ERR_NONE,
330 /* If req aborted due to global error. */
331 PL330_ERR_ABORT,
332 /* If req failed due to problem with Channel. */
333 PL330_ERR_FAIL,
334};
335
b7d861d9
BK
336enum dmamov_dst {
337 SAR = 0,
338 CCR,
339 DAR,
340};
341
342enum pl330_dst {
343 SRC = 0,
344 DST,
345};
346
347enum pl330_cond {
348 SINGLE,
349 BURST,
350 ALWAYS,
351};
352
9dc5a315
LPC
353struct dma_pl330_desc;
354
b7d861d9
BK
355struct _pl330_req {
356 u32 mc_bus;
357 void *mc_cpu;
9dc5a315 358 struct dma_pl330_desc *desc;
b7d861d9
BK
359};
360
361/* ToBeDone for tasklet */
362struct _pl330_tbd {
363 bool reset_dmac;
364 bool reset_mngr;
365 u8 reset_chan;
366};
367
368/* A DMAC Thread */
369struct pl330_thread {
370 u8 id;
371 int ev;
372 /* If the channel is not yet acquired by any client */
373 bool free;
374 /* Parent DMAC */
375 struct pl330_dmac *dmac;
376 /* Only two at a time */
377 struct _pl330_req req[2];
378 /* Index of the last enqueued request */
379 unsigned lstenq;
380 /* Index of the last submitted request or -1 if the DMA is stopped */
381 int req_running;
382};
383
384enum pl330_dmac_state {
385 UNINIT,
386 INIT,
387 DYING,
388};
389
b3040e40
JB
390enum desc_status {
391 /* In the DMAC pool */
392 FREE,
393 /*
d73111c6 394 * Allocated to some channel during prep_xxx
b3040e40
JB
395 * Also may be sitting on the work_list.
396 */
397 PREP,
398 /*
399 * Sitting on the work_list and already submitted
400 * to the PL330 core. Not more than two descriptors
401 * of a channel can be BUSY at any time.
402 */
403 BUSY,
404 /*
405 * Sitting on the channel work_list but xfer done
406 * by PL330 core
407 */
408 DONE,
409};
410
411struct dma_pl330_chan {
412 /* Schedule desc completion */
413 struct tasklet_struct task;
414
415 /* DMA-Engine Channel */
416 struct dma_chan chan;
417
04abf5da
LPC
418 /* List of submitted descriptors */
419 struct list_head submitted_list;
420 /* List of issued descriptors */
b3040e40 421 struct list_head work_list;
39ff8613
LPC
422 /* List of completed descriptors */
423 struct list_head completed_list;
b3040e40
JB
424
425 /* Pointer to the DMAC that manages this channel,
426 * NULL if the channel is available to be acquired.
427 * As the parent, this DMAC also provides descriptors
428 * to the channel.
429 */
f6f2421c 430 struct pl330_dmac *dmac;
b3040e40
JB
431
432 /* To protect channel manipulation */
433 spinlock_t lock;
434
65ad6060
LPC
435 /*
436 * Hardware channel thread of PL330 DMAC. NULL if the channel is
437 * available.
b3040e40 438 */
65ad6060 439 struct pl330_thread *thread;
1b9bb715
BK
440
441 /* For D-to-M and M-to-D channels */
442 int burst_sz; /* the peripheral fifo width */
1d0c1d60 443 int burst_len; /* the number of burst */
1b9bb715 444 dma_addr_t fifo_addr;
42bc9cf4
BK
445
446 /* for cyclic capability */
447 bool cyclic;
b3040e40
JB
448};
449
f6f2421c 450struct pl330_dmac {
b3040e40
JB
451 /* DMA-Engine Device */
452 struct dma_device ddma;
453
b714b84e
LPC
454 /* Holds info about sg limitations */
455 struct device_dma_parameters dma_parms;
456
b3040e40
JB
457 /* Pool of descriptors available for the DMAC's channels */
458 struct list_head desc_pool;
459 /* To protect desc_pool manipulation */
460 spinlock_t pool_lock;
461
f6f2421c
LPC
462 /* Size of MicroCode buffers for each channel. */
463 unsigned mcbufsz;
464 /* ioremap'ed address of PL330 registers. */
465 void __iomem *base;
466 /* Populated by the PL330 core driver during pl330_add */
467 struct pl330_config pcfg;
468
469 spinlock_t lock;
470 /* Maximum possible events/irqs */
471 int events[32];
472 /* BUS address of MicroCode buffer */
473 dma_addr_t mcode_bus;
474 /* CPU address of MicroCode buffer */
475 void *mcode_cpu;
476 /* List of all Channel threads */
477 struct pl330_thread *channels;
478 /* Pointer to the MANAGER thread */
479 struct pl330_thread *manager;
480 /* To handle bad news in interrupt */
481 struct tasklet_struct tasks;
482 struct _pl330_tbd dmac_tbd;
483 /* State of DMAC operation */
484 enum pl330_dmac_state state;
485 /* Holds list of reqs with due callbacks */
486 struct list_head req_done;
487
b3040e40 488 /* Peripheral channels connected to this DMAC */
70cbb163 489 unsigned int num_peripherals;
4e0e6109 490 struct dma_pl330_chan *peripherals; /* keep at end */
b3040e40
JB
491};
492
493struct dma_pl330_desc {
494 /* To attach to a queue as child */
495 struct list_head node;
496
497 /* Descriptor for the DMA Engine API */
498 struct dma_async_tx_descriptor txd;
499
500 /* Xfer for PL330 core */
501 struct pl330_xfer px;
502
503 struct pl330_reqcfg rqcfg;
b3040e40
JB
504
505 enum desc_status status;
506
aee4d1fa
RB
507 int bytes_requested;
508 bool last;
509
b3040e40
JB
510 /* The channel which currently holds this desc */
511 struct dma_pl330_chan *pchan;
9dc5a315
LPC
512
513 enum dma_transfer_direction rqtype;
514 /* Index of peripheral for the xfer. */
515 unsigned peri:5;
516 /* Hook to attach to DMAC's list of reqs with due callback */
517 struct list_head rqd;
518};
519
520struct _xfer_spec {
521 u32 ccr;
522 struct dma_pl330_desc *desc;
b3040e40
JB
523};
524
b7d861d9
BK
525static inline bool _queue_empty(struct pl330_thread *thrd)
526{
8ed30a14 527 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
b7d861d9
BK
528}
529
530static inline bool _queue_full(struct pl330_thread *thrd)
531{
8ed30a14 532 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
b7d861d9
BK
533}
534
535static inline bool is_manager(struct pl330_thread *thrd)
536{
fbbcd9be 537 return thrd->dmac->manager == thrd;
b7d861d9
BK
538}
539
540/* If manager of the thread is in Non-Secure mode */
541static inline bool _manager_ns(struct pl330_thread *thrd)
542{
f6f2421c 543 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
b7d861d9
BK
544}
545
3ecf51a4
BK
546static inline u32 get_revision(u32 periph_id)
547{
548 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
549}
550
b7d861d9
BK
551static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
552 enum pl330_dst da, u16 val)
553{
554 if (dry_run)
555 return SZ_DMAADDH;
556
557 buf[0] = CMD_DMAADDH;
558 buf[0] |= (da << 1);
3a2307f7 559 *((__le16 *)&buf[1]) = cpu_to_le16(val);
b7d861d9
BK
560
561 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
562 da == 1 ? "DA" : "SA", val);
563
564 return SZ_DMAADDH;
565}
566
567static inline u32 _emit_END(unsigned dry_run, u8 buf[])
568{
569 if (dry_run)
570 return SZ_DMAEND;
571
572 buf[0] = CMD_DMAEND;
573
574 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
575
576 return SZ_DMAEND;
577}
578
579static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
580{
581 if (dry_run)
582 return SZ_DMAFLUSHP;
583
584 buf[0] = CMD_DMAFLUSHP;
585
586 peri &= 0x1f;
587 peri <<= 3;
588 buf[1] = peri;
589
590 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
591
592 return SZ_DMAFLUSHP;
593}
594
595static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
596{
597 if (dry_run)
598 return SZ_DMALD;
599
600 buf[0] = CMD_DMALD;
601
602 if (cond == SINGLE)
603 buf[0] |= (0 << 1) | (1 << 0);
604 else if (cond == BURST)
605 buf[0] |= (1 << 1) | (1 << 0);
606
607 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
608 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
609
610 return SZ_DMALD;
611}
612
613static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
614 enum pl330_cond cond, u8 peri)
615{
616 if (dry_run)
617 return SZ_DMALDP;
618
619 buf[0] = CMD_DMALDP;
620
621 if (cond == BURST)
622 buf[0] |= (1 << 1);
623
624 peri &= 0x1f;
625 peri <<= 3;
626 buf[1] = peri;
627
628 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
629 cond == SINGLE ? 'S' : 'B', peri >> 3);
630
631 return SZ_DMALDP;
632}
633
634static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
635 unsigned loop, u8 cnt)
636{
637 if (dry_run)
638 return SZ_DMALP;
639
640 buf[0] = CMD_DMALP;
641
642 if (loop)
643 buf[0] |= (1 << 1);
644
645 cnt--; /* DMAC increments by 1 internally */
646 buf[1] = cnt;
647
648 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
649
650 return SZ_DMALP;
651}
652
653struct _arg_LPEND {
654 enum pl330_cond cond;
655 bool forever;
656 unsigned loop;
657 u8 bjump;
658};
659
660static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
661 const struct _arg_LPEND *arg)
662{
663 enum pl330_cond cond = arg->cond;
664 bool forever = arg->forever;
665 unsigned loop = arg->loop;
666 u8 bjump = arg->bjump;
667
668 if (dry_run)
669 return SZ_DMALPEND;
670
671 buf[0] = CMD_DMALPEND;
672
673 if (loop)
674 buf[0] |= (1 << 2);
675
676 if (!forever)
677 buf[0] |= (1 << 4);
678
679 if (cond == SINGLE)
680 buf[0] |= (0 << 1) | (1 << 0);
681 else if (cond == BURST)
682 buf[0] |= (1 << 1) | (1 << 0);
683
684 buf[1] = bjump;
685
686 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
687 forever ? "FE" : "END",
688 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
689 loop ? '1' : '0',
690 bjump);
691
692 return SZ_DMALPEND;
693}
694
695static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
696{
697 if (dry_run)
698 return SZ_DMAKILL;
699
700 buf[0] = CMD_DMAKILL;
701
702 return SZ_DMAKILL;
703}
704
705static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
706 enum dmamov_dst dst, u32 val)
707{
708 if (dry_run)
709 return SZ_DMAMOV;
710
711 buf[0] = CMD_DMAMOV;
712 buf[1] = dst;
3a2307f7 713 *((__le32 *)&buf[2]) = cpu_to_le32(val);
b7d861d9
BK
714
715 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
716 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
717
718 return SZ_DMAMOV;
719}
720
721static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
722{
723 if (dry_run)
724 return SZ_DMANOP;
725
726 buf[0] = CMD_DMANOP;
727
728 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
729
730 return SZ_DMANOP;
731}
732
733static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
734{
735 if (dry_run)
736 return SZ_DMARMB;
737
738 buf[0] = CMD_DMARMB;
739
740 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
741
742 return SZ_DMARMB;
743}
744
745static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
746{
747 if (dry_run)
748 return SZ_DMASEV;
749
750 buf[0] = CMD_DMASEV;
751
752 ev &= 0x1f;
753 ev <<= 3;
754 buf[1] = ev;
755
756 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
757
758 return SZ_DMASEV;
759}
760
761static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
762{
763 if (dry_run)
764 return SZ_DMAST;
765
766 buf[0] = CMD_DMAST;
767
768 if (cond == SINGLE)
769 buf[0] |= (0 << 1) | (1 << 0);
770 else if (cond == BURST)
771 buf[0] |= (1 << 1) | (1 << 0);
772
773 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
774 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
775
776 return SZ_DMAST;
777}
778
779static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
780 enum pl330_cond cond, u8 peri)
781{
782 if (dry_run)
783 return SZ_DMASTP;
784
785 buf[0] = CMD_DMASTP;
786
787 if (cond == BURST)
788 buf[0] |= (1 << 1);
789
790 peri &= 0x1f;
791 peri <<= 3;
792 buf[1] = peri;
793
794 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
795 cond == SINGLE ? 'S' : 'B', peri >> 3);
796
797 return SZ_DMASTP;
798}
799
800static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
801{
802 if (dry_run)
803 return SZ_DMASTZ;
804
805 buf[0] = CMD_DMASTZ;
806
807 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
808
809 return SZ_DMASTZ;
810}
811
812static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
813 unsigned invalidate)
814{
815 if (dry_run)
816 return SZ_DMAWFE;
817
818 buf[0] = CMD_DMAWFE;
819
820 ev &= 0x1f;
821 ev <<= 3;
822 buf[1] = ev;
823
824 if (invalidate)
825 buf[1] |= (1 << 1);
826
827 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
828 ev >> 3, invalidate ? ", I" : "");
829
830 return SZ_DMAWFE;
831}
832
833static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
834 enum pl330_cond cond, u8 peri)
835{
836 if (dry_run)
837 return SZ_DMAWFP;
838
839 buf[0] = CMD_DMAWFP;
840
841 if (cond == SINGLE)
842 buf[0] |= (0 << 1) | (0 << 0);
843 else if (cond == BURST)
844 buf[0] |= (1 << 1) | (0 << 0);
845 else
846 buf[0] |= (0 << 1) | (1 << 0);
847
848 peri &= 0x1f;
849 peri <<= 3;
850 buf[1] = peri;
851
852 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
853 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
854
855 return SZ_DMAWFP;
856}
857
858static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
859{
860 if (dry_run)
861 return SZ_DMAWMB;
862
863 buf[0] = CMD_DMAWMB;
864
865 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
866
867 return SZ_DMAWMB;
868}
869
870struct _arg_GO {
871 u8 chan;
872 u32 addr;
873 unsigned ns;
874};
875
876static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
877 const struct _arg_GO *arg)
878{
879 u8 chan = arg->chan;
880 u32 addr = arg->addr;
881 unsigned ns = arg->ns;
882
883 if (dry_run)
884 return SZ_DMAGO;
885
886 buf[0] = CMD_DMAGO;
887 buf[0] |= (ns << 1);
888
889 buf[1] = chan & 0x7;
890
3a2307f7 891 *((__le32 *)&buf[2]) = cpu_to_le32(addr);
b7d861d9
BK
892
893 return SZ_DMAGO;
894}
895
896#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
897
898/* Returns Time-Out */
899static bool _until_dmac_idle(struct pl330_thread *thrd)
900{
f6f2421c 901 void __iomem *regs = thrd->dmac->base;
b7d861d9
BK
902 unsigned long loops = msecs_to_loops(5);
903
904 do {
905 /* Until Manager is Idle */
906 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
907 break;
908
909 cpu_relax();
910 } while (--loops);
911
912 if (!loops)
913 return true;
914
915 return false;
916}
917
918static inline void _execute_DBGINSN(struct pl330_thread *thrd,
919 u8 insn[], bool as_manager)
920{
f6f2421c 921 void __iomem *regs = thrd->dmac->base;
b7d861d9
BK
922 u32 val;
923
924 val = (insn[0] << 16) | (insn[1] << 24);
925 if (!as_manager) {
926 val |= (1 << 0);
927 val |= (thrd->id << 8); /* Channel Number */
928 }
929 writel(val, regs + DBGINST0);
930
3a2307f7 931 val = le32_to_cpu(*((__le32 *)&insn[2]));
b7d861d9
BK
932 writel(val, regs + DBGINST1);
933
934 /* If timed out due to halted state-machine */
935 if (_until_dmac_idle(thrd)) {
f6f2421c 936 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
b7d861d9
BK
937 return;
938 }
939
940 /* Get going */
941 writel(0, regs + DBGCMD);
942}
943
b7d861d9
BK
944static inline u32 _state(struct pl330_thread *thrd)
945{
f6f2421c 946 void __iomem *regs = thrd->dmac->base;
b7d861d9
BK
947 u32 val;
948
949 if (is_manager(thrd))
950 val = readl(regs + DS) & 0xf;
951 else
952 val = readl(regs + CS(thrd->id)) & 0xf;
953
954 switch (val) {
955 case DS_ST_STOP:
956 return PL330_STATE_STOPPED;
957 case DS_ST_EXEC:
958 return PL330_STATE_EXECUTING;
959 case DS_ST_CMISS:
960 return PL330_STATE_CACHEMISS;
961 case DS_ST_UPDTPC:
962 return PL330_STATE_UPDTPC;
963 case DS_ST_WFE:
964 return PL330_STATE_WFE;
965 case DS_ST_FAULT:
966 return PL330_STATE_FAULTING;
967 case DS_ST_ATBRR:
968 if (is_manager(thrd))
969 return PL330_STATE_INVALID;
970 else
971 return PL330_STATE_ATBARRIER;
972 case DS_ST_QBUSY:
973 if (is_manager(thrd))
974 return PL330_STATE_INVALID;
975 else
976 return PL330_STATE_QUEUEBUSY;
977 case DS_ST_WFP:
978 if (is_manager(thrd))
979 return PL330_STATE_INVALID;
980 else
981 return PL330_STATE_WFP;
982 case DS_ST_KILL:
983 if (is_manager(thrd))
984 return PL330_STATE_INVALID;
985 else
986 return PL330_STATE_KILLING;
987 case DS_ST_CMPLT:
988 if (is_manager(thrd))
989 return PL330_STATE_INVALID;
990 else
991 return PL330_STATE_COMPLETING;
992 case DS_ST_FLTCMP:
993 if (is_manager(thrd))
994 return PL330_STATE_INVALID;
995 else
996 return PL330_STATE_FAULT_COMPLETING;
997 default:
998 return PL330_STATE_INVALID;
999 }
1000}
1001
1002static void _stop(struct pl330_thread *thrd)
1003{
f6f2421c 1004 void __iomem *regs = thrd->dmac->base;
b7d861d9
BK
1005 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1006
1007 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1008 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1009
1010 /* Return if nothing needs to be done */
1011 if (_state(thrd) == PL330_STATE_COMPLETING
1012 || _state(thrd) == PL330_STATE_KILLING
1013 || _state(thrd) == PL330_STATE_STOPPED)
1014 return;
1015
1016 _emit_KILL(0, insn);
1017
1018 /* Stop generating interrupts for SEV */
1019 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1020
1021 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1022}
1023
1024/* Start doing req 'idx' of thread 'thrd' */
1025static bool _trigger(struct pl330_thread *thrd)
1026{
f6f2421c 1027 void __iomem *regs = thrd->dmac->base;
b7d861d9 1028 struct _pl330_req *req;
9dc5a315 1029 struct dma_pl330_desc *desc;
b7d861d9
BK
1030 struct _arg_GO go;
1031 unsigned ns;
1032 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1033 int idx;
1034
1035 /* Return if already ACTIVE */
1036 if (_state(thrd) != PL330_STATE_STOPPED)
1037 return true;
1038
1039 idx = 1 - thrd->lstenq;
8ed30a14 1040 if (thrd->req[idx].desc != NULL) {
b7d861d9 1041 req = &thrd->req[idx];
8ed30a14 1042 } else {
b7d861d9 1043 idx = thrd->lstenq;
8ed30a14 1044 if (thrd->req[idx].desc != NULL)
b7d861d9
BK
1045 req = &thrd->req[idx];
1046 else
1047 req = NULL;
1048 }
1049
1050 /* Return if no request */
8ed30a14 1051 if (!req)
b7d861d9
BK
1052 return true;
1053
0091b9d6
AK
1054 /* Return if req is running */
1055 if (idx == thrd->req_running)
1056 return true;
1057
9dc5a315 1058 desc = req->desc;
b7d861d9 1059
9dc5a315 1060 ns = desc->rqcfg.nonsecure ? 1 : 0;
b7d861d9
BK
1061
1062 /* See 'Abort Sources' point-4 at Page 2-25 */
1063 if (_manager_ns(thrd) && !ns)
f6f2421c 1064 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
b7d861d9
BK
1065 __func__, __LINE__);
1066
1067 go.chan = thrd->id;
1068 go.addr = req->mc_bus;
1069 go.ns = ns;
1070 _emit_GO(0, insn, &go);
1071
1072 /* Set to generate interrupts for SEV */
1073 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1074
1075 /* Only manager can execute GO */
1076 _execute_DBGINSN(thrd, insn, true);
1077
1078 thrd->req_running = idx;
1079
1080 return true;
1081}
1082
1083static bool _start(struct pl330_thread *thrd)
1084{
1085 switch (_state(thrd)) {
1086 case PL330_STATE_FAULT_COMPLETING:
1087 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1088
1089 if (_state(thrd) == PL330_STATE_KILLING)
1090 UNTIL(thrd, PL330_STATE_STOPPED)
1091
1092 case PL330_STATE_FAULTING:
1093 _stop(thrd);
1094
1095 case PL330_STATE_KILLING:
1096 case PL330_STATE_COMPLETING:
1097 UNTIL(thrd, PL330_STATE_STOPPED)
1098
1099 case PL330_STATE_STOPPED:
1100 return _trigger(thrd);
1101
1102 case PL330_STATE_WFP:
1103 case PL330_STATE_QUEUEBUSY:
1104 case PL330_STATE_ATBARRIER:
1105 case PL330_STATE_UPDTPC:
1106 case PL330_STATE_CACHEMISS:
1107 case PL330_STATE_EXECUTING:
1108 return true;
1109
1110 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1111 default:
1112 return false;
1113 }
1114}
1115
1116static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1117 const struct _xfer_spec *pxs, int cyc)
1118{
1119 int off = 0;
9dc5a315 1120 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
b7d861d9 1121
3ecf51a4
BK
1122 /* check lock-up free version */
1123 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1124 while (cyc--) {
1125 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1126 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1127 }
1128 } else {
1129 while (cyc--) {
1130 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1131 off += _emit_RMB(dry_run, &buf[off]);
1132 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1133 off += _emit_WMB(dry_run, &buf[off]);
1134 }
b7d861d9
BK
1135 }
1136
1137 return off;
1138}
1139
1140static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1141 const struct _xfer_spec *pxs, int cyc)
1142{
1143 int off = 0;
1144
1145 while (cyc--) {
9dc5a315
LPC
1146 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1147 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
b7d861d9 1148 off += _emit_ST(dry_run, &buf[off], ALWAYS);
9dc5a315 1149 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
b7d861d9
BK
1150 }
1151
1152 return off;
1153}
1154
1155static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1156 const struct _xfer_spec *pxs, int cyc)
1157{
1158 int off = 0;
1159
1160 while (cyc--) {
9dc5a315 1161 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
b7d861d9 1162 off += _emit_LD(dry_run, &buf[off], ALWAYS);
9dc5a315
LPC
1163 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1164 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
b7d861d9
BK
1165 }
1166
1167 return off;
1168}
1169
1170static int _bursts(unsigned dry_run, u8 buf[],
1171 const struct _xfer_spec *pxs, int cyc)
1172{
1173 int off = 0;
1174
9dc5a315 1175 switch (pxs->desc->rqtype) {
585a9d0b 1176 case DMA_MEM_TO_DEV:
b7d861d9
BK
1177 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1178 break;
585a9d0b 1179 case DMA_DEV_TO_MEM:
b7d861d9
BK
1180 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1181 break;
585a9d0b 1182 case DMA_MEM_TO_MEM:
b7d861d9
BK
1183 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1184 break;
1185 default:
1186 off += 0x40000000; /* Scare off the Client */
1187 break;
1188 }
1189
1190 return off;
1191}
1192
1193/* Returns bytes consumed and updates bursts */
1194static inline int _loop(unsigned dry_run, u8 buf[],
1195 unsigned long *bursts, const struct _xfer_spec *pxs)
1196{
1197 int cyc, cycmax, szlp, szlpend, szbrst, off;
1198 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1199 struct _arg_LPEND lpend;
1200
31495d60
MS
1201 if (*bursts == 1)
1202 return _bursts(dry_run, buf, pxs, 1);
1203
b7d861d9
BK
1204 /* Max iterations possible in DMALP is 256 */
1205 if (*bursts >= 256*256) {
1206 lcnt1 = 256;
1207 lcnt0 = 256;
1208 cyc = *bursts / lcnt1 / lcnt0;
1209 } else if (*bursts > 256) {
1210 lcnt1 = 256;
1211 lcnt0 = *bursts / lcnt1;
1212 cyc = 1;
1213 } else {
1214 lcnt1 = *bursts;
1215 lcnt0 = 0;
1216 cyc = 1;
1217 }
1218
1219 szlp = _emit_LP(1, buf, 0, 0);
1220 szbrst = _bursts(1, buf, pxs, 1);
1221
1222 lpend.cond = ALWAYS;
1223 lpend.forever = false;
1224 lpend.loop = 0;
1225 lpend.bjump = 0;
1226 szlpend = _emit_LPEND(1, buf, &lpend);
1227
1228 if (lcnt0) {
1229 szlp *= 2;
1230 szlpend *= 2;
1231 }
1232
1233 /*
1234 * Max bursts that we can unroll due to limit on the
1235 * size of backward jump that can be encoded in DMALPEND
1236 * which is 8-bits and hence 255
1237 */
1238 cycmax = (255 - (szlp + szlpend)) / szbrst;
1239
1240 cyc = (cycmax < cyc) ? cycmax : cyc;
1241
1242 off = 0;
1243
1244 if (lcnt0) {
1245 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1246 ljmp0 = off;
1247 }
1248
1249 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1250 ljmp1 = off;
1251
1252 off += _bursts(dry_run, &buf[off], pxs, cyc);
1253
1254 lpend.cond = ALWAYS;
1255 lpend.forever = false;
1256 lpend.loop = 1;
1257 lpend.bjump = off - ljmp1;
1258 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1259
1260 if (lcnt0) {
1261 lpend.cond = ALWAYS;
1262 lpend.forever = false;
1263 lpend.loop = 0;
1264 lpend.bjump = off - ljmp0;
1265 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1266 }
1267
1268 *bursts = lcnt1 * cyc;
1269 if (lcnt0)
1270 *bursts *= lcnt0;
1271
1272 return off;
1273}
1274
1275static inline int _setup_loops(unsigned dry_run, u8 buf[],
1276 const struct _xfer_spec *pxs)
1277{
9dc5a315 1278 struct pl330_xfer *x = &pxs->desc->px;
b7d861d9
BK
1279 u32 ccr = pxs->ccr;
1280 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1281 int off = 0;
1282
1283 while (bursts) {
1284 c = bursts;
1285 off += _loop(dry_run, &buf[off], &c, pxs);
1286 bursts -= c;
1287 }
1288
1289 return off;
1290}
1291
1292static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1293 const struct _xfer_spec *pxs)
1294{
9dc5a315 1295 struct pl330_xfer *x = &pxs->desc->px;
b7d861d9
BK
1296 int off = 0;
1297
1298 /* DMAMOV SAR, x->src_addr */
1299 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1300 /* DMAMOV DAR, x->dst_addr */
1301 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1302
1303 /* Setup Loop(s) */
1304 off += _setup_loops(dry_run, &buf[off], pxs);
1305
1306 return off;
1307}
1308
1309/*
1310 * A req is a sequence of one or more xfer units.
1311 * Returns the number of bytes taken to setup the MC for the req.
1312 */
1313static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1314 unsigned index, struct _xfer_spec *pxs)
1315{
1316 struct _pl330_req *req = &thrd->req[index];
1317 struct pl330_xfer *x;
1318 u8 *buf = req->mc_cpu;
1319 int off = 0;
1320
1321 PL330_DBGMC_START(req->mc_bus);
1322
1323 /* DMAMOV CCR, ccr */
1324 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1325
9dc5a315 1326 x = &pxs->desc->px;
d5cef121
LPC
1327 /* Error if xfer length is not aligned at burst size */
1328 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1329 return -EINVAL;
b7d861d9 1330
d5cef121 1331 off += _setup_xfer(dry_run, &buf[off], pxs);
b7d861d9
BK
1332
1333 /* DMASEV peripheral/event */
1334 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1335 /* DMAEND */
1336 off += _emit_END(dry_run, &buf[off]);
1337
1338 return off;
1339}
1340
1341static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1342{
1343 u32 ccr = 0;
1344
1345 if (rqc->src_inc)
1346 ccr |= CC_SRCINC;
1347
1348 if (rqc->dst_inc)
1349 ccr |= CC_DSTINC;
1350
1351 /* We set same protection levels for Src and DST for now */
1352 if (rqc->privileged)
1353 ccr |= CC_SRCPRI | CC_DSTPRI;
1354 if (rqc->nonsecure)
1355 ccr |= CC_SRCNS | CC_DSTNS;
1356 if (rqc->insnaccess)
1357 ccr |= CC_SRCIA | CC_DSTIA;
1358
1359 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1360 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1361
1362 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1363 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1364
1365 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1366 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1367
1368 ccr |= (rqc->swap << CC_SWAP_SHFT);
1369
1370 return ccr;
1371}
1372
b7d861d9
BK
1373/*
1374 * Submit a list of xfers after which the client wants notification.
1375 * Client is not notified after each xfer unit, just once after all
1376 * xfer units are done or some error occurs.
1377 */
9dc5a315
LPC
1378static int pl330_submit_req(struct pl330_thread *thrd,
1379 struct dma_pl330_desc *desc)
b7d861d9 1380{
f6f2421c 1381 struct pl330_dmac *pl330 = thrd->dmac;
b7d861d9
BK
1382 struct _xfer_spec xs;
1383 unsigned long flags;
b7d861d9
BK
1384 unsigned idx;
1385 u32 ccr;
1386 int ret = 0;
1387
b7d861d9
BK
1388 if (pl330->state == DYING
1389 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
f6f2421c 1390 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
b7d861d9
BK
1391 __func__, __LINE__);
1392 return -EAGAIN;
1393 }
1394
1395 /* If request for non-existing peripheral */
9dc5a315
LPC
1396 if (desc->rqtype != DMA_MEM_TO_MEM &&
1397 desc->peri >= pl330->pcfg.num_peri) {
f6f2421c 1398 dev_info(thrd->dmac->ddma.dev,
b7d861d9 1399 "%s:%d Invalid peripheral(%u)!\n",
9dc5a315 1400 __func__, __LINE__, desc->peri);
b7d861d9
BK
1401 return -EINVAL;
1402 }
1403
1404 spin_lock_irqsave(&pl330->lock, flags);
1405
1406 if (_queue_full(thrd)) {
1407 ret = -EAGAIN;
1408 goto xfer_exit;
1409 }
1410
9dc5a315
LPC
1411 /* Prefer Secure Channel */
1412 if (!_manager_ns(thrd))
1413 desc->rqcfg.nonsecure = 0;
1414 else
1415 desc->rqcfg.nonsecure = 1;
b7d861d9 1416
9dc5a315 1417 ccr = _prepare_ccr(&desc->rqcfg);
b7d861d9 1418
8ed30a14 1419 idx = thrd->req[0].desc == NULL ? 0 : 1;
b7d861d9
BK
1420
1421 xs.ccr = ccr;
9dc5a315 1422 xs.desc = desc;
b7d861d9
BK
1423
1424 /* First dry run to check if req is acceptable */
1425 ret = _setup_req(1, thrd, idx, &xs);
1426 if (ret < 0)
1427 goto xfer_exit;
1428
f6f2421c 1429 if (ret > pl330->mcbufsz / 2) {
e5489d5e
MS
1430 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1431 __func__, __LINE__, ret, pl330->mcbufsz / 2);
b7d861d9
BK
1432 ret = -ENOMEM;
1433 goto xfer_exit;
1434 }
1435
1436 /* Hook the request */
1437 thrd->lstenq = idx;
9dc5a315 1438 thrd->req[idx].desc = desc;
be025329 1439 _setup_req(0, thrd, idx, &xs);
b7d861d9
BK
1440
1441 ret = 0;
1442
1443xfer_exit:
1444 spin_unlock_irqrestore(&pl330->lock, flags);
1445
1446 return ret;
1447}
1448
9dc5a315 1449static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
6079d38c 1450{
b1e51d77 1451 struct dma_pl330_chan *pch;
6079d38c
LPC
1452 unsigned long flags;
1453
b1e51d77
JMC
1454 if (!desc)
1455 return;
1456
1457 pch = desc->pchan;
1458
6079d38c
LPC
1459 /* If desc aborted */
1460 if (!pch)
1461 return;
1462
1463 spin_lock_irqsave(&pch->lock, flags);
1464
1465 desc->status = DONE;
1466
1467 spin_unlock_irqrestore(&pch->lock, flags);
1468
1469 tasklet_schedule(&pch->task);
1470}
1471
b7d861d9
BK
1472static void pl330_dotask(unsigned long data)
1473{
1474 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
b7d861d9
BK
1475 unsigned long flags;
1476 int i;
1477
1478 spin_lock_irqsave(&pl330->lock, flags);
1479
1480 /* The DMAC itself gone nuts */
1481 if (pl330->dmac_tbd.reset_dmac) {
1482 pl330->state = DYING;
1483 /* Reset the manager too */
1484 pl330->dmac_tbd.reset_mngr = true;
1485 /* Clear the reset flag */
1486 pl330->dmac_tbd.reset_dmac = false;
1487 }
1488
1489 if (pl330->dmac_tbd.reset_mngr) {
1490 _stop(pl330->manager);
1491 /* Reset all channels */
f6f2421c 1492 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
b7d861d9
BK
1493 /* Clear the reset flag */
1494 pl330->dmac_tbd.reset_mngr = false;
1495 }
1496
f6f2421c 1497 for (i = 0; i < pl330->pcfg.num_chan; i++) {
b7d861d9
BK
1498
1499 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1500 struct pl330_thread *thrd = &pl330->channels[i];
f6f2421c 1501 void __iomem *regs = pl330->base;
b7d861d9
BK
1502 enum pl330_op_err err;
1503
1504 _stop(thrd);
1505
1506 if (readl(regs + FSC) & (1 << thrd->id))
1507 err = PL330_ERR_FAIL;
1508 else
1509 err = PL330_ERR_ABORT;
1510
1511 spin_unlock_irqrestore(&pl330->lock, flags);
9dc5a315
LPC
1512 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1513 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
b7d861d9
BK
1514 spin_lock_irqsave(&pl330->lock, flags);
1515
9dc5a315
LPC
1516 thrd->req[0].desc = NULL;
1517 thrd->req[1].desc = NULL;
8ed30a14 1518 thrd->req_running = -1;
b7d861d9
BK
1519
1520 /* Clear the reset flag */
1521 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1522 }
1523 }
1524
1525 spin_unlock_irqrestore(&pl330->lock, flags);
1526
1527 return;
1528}
1529
1530/* Returns 1 if state was updated, 0 otherwise */
f6f2421c 1531static int pl330_update(struct pl330_dmac *pl330)
b7d861d9 1532{
9dc5a315 1533 struct dma_pl330_desc *descdone, *tmp;
b7d861d9
BK
1534 unsigned long flags;
1535 void __iomem *regs;
1536 u32 val;
1537 int id, ev, ret = 0;
1538
f6f2421c 1539 regs = pl330->base;
b7d861d9
BK
1540
1541 spin_lock_irqsave(&pl330->lock, flags);
1542
1543 val = readl(regs + FSM) & 0x1;
1544 if (val)
1545 pl330->dmac_tbd.reset_mngr = true;
1546 else
1547 pl330->dmac_tbd.reset_mngr = false;
1548
f6f2421c 1549 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
b7d861d9
BK
1550 pl330->dmac_tbd.reset_chan |= val;
1551 if (val) {
1552 int i = 0;
f6f2421c 1553 while (i < pl330->pcfg.num_chan) {
b7d861d9 1554 if (val & (1 << i)) {
f6f2421c 1555 dev_info(pl330->ddma.dev,
b7d861d9
BK
1556 "Reset Channel-%d\t CS-%x FTC-%x\n",
1557 i, readl(regs + CS(i)),
1558 readl(regs + FTC(i)));
1559 _stop(&pl330->channels[i]);
1560 }
1561 i++;
1562 }
1563 }
1564
1565 /* Check which event happened i.e, thread notified */
1566 val = readl(regs + ES);
f6f2421c
LPC
1567 if (pl330->pcfg.num_events < 32
1568 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
b7d861d9 1569 pl330->dmac_tbd.reset_dmac = true;
f6f2421c
LPC
1570 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1571 __LINE__);
b7d861d9
BK
1572 ret = 1;
1573 goto updt_exit;
1574 }
1575
f6f2421c 1576 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
b7d861d9
BK
1577 if (val & (1 << ev)) { /* Event occurred */
1578 struct pl330_thread *thrd;
1579 u32 inten = readl(regs + INTEN);
1580 int active;
1581
1582 /* Clear the event */
1583 if (inten & (1 << ev))
1584 writel(1 << ev, regs + INTCLR);
1585
1586 ret = 1;
1587
1588 id = pl330->events[ev];
1589
1590 thrd = &pl330->channels[id];
1591
1592 active = thrd->req_running;
1593 if (active == -1) /* Aborted */
1594 continue;
1595
fdec53d5 1596 /* Detach the req */
9dc5a315
LPC
1597 descdone = thrd->req[active].desc;
1598 thrd->req[active].desc = NULL;
fdec53d5 1599
0091b9d6
AK
1600 thrd->req_running = -1;
1601
b7d861d9
BK
1602 /* Get going again ASAP */
1603 _start(thrd);
1604
1605 /* For now, just make a list of callbacks to be done */
9dc5a315 1606 list_add_tail(&descdone->rqd, &pl330->req_done);
b7d861d9
BK
1607 }
1608 }
1609
1610 /* Now that we are in no hurry, do the callbacks */
9dc5a315
LPC
1611 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1612 list_del(&descdone->rqd);
b7d861d9 1613 spin_unlock_irqrestore(&pl330->lock, flags);
9dc5a315 1614 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
b7d861d9
BK
1615 spin_lock_irqsave(&pl330->lock, flags);
1616 }
1617
1618updt_exit:
1619 spin_unlock_irqrestore(&pl330->lock, flags);
1620
1621 if (pl330->dmac_tbd.reset_dmac
1622 || pl330->dmac_tbd.reset_mngr
1623 || pl330->dmac_tbd.reset_chan) {
1624 ret = 1;
1625 tasklet_schedule(&pl330->tasks);
1626 }
1627
1628 return ret;
1629}
1630
b7d861d9
BK
1631/* Reserve an event */
1632static inline int _alloc_event(struct pl330_thread *thrd)
1633{
1634 struct pl330_dmac *pl330 = thrd->dmac;
b7d861d9
BK
1635 int ev;
1636
f6f2421c 1637 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
b7d861d9
BK
1638 if (pl330->events[ev] == -1) {
1639 pl330->events[ev] = thrd->id;
1640 return ev;
1641 }
1642
1643 return -1;
1644}
1645
f6f2421c 1646static bool _chan_ns(const struct pl330_dmac *pl330, int i)
b7d861d9 1647{
f6f2421c 1648 return pl330->pcfg.irq_ns & (1 << i);
b7d861d9
BK
1649}
1650
1651/* Upon success, returns IdentityToken for the
1652 * allocated channel, NULL otherwise.
1653 */
f6f2421c 1654static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
b7d861d9
BK
1655{
1656 struct pl330_thread *thrd = NULL;
b7d861d9
BK
1657 unsigned long flags;
1658 int chans, i;
1659
b7d861d9
BK
1660 if (pl330->state == DYING)
1661 return NULL;
1662
f6f2421c 1663 chans = pl330->pcfg.num_chan;
b7d861d9
BK
1664
1665 spin_lock_irqsave(&pl330->lock, flags);
1666
1667 for (i = 0; i < chans; i++) {
1668 thrd = &pl330->channels[i];
1669 if ((thrd->free) && (!_manager_ns(thrd) ||
f6f2421c 1670 _chan_ns(pl330, i))) {
b7d861d9
BK
1671 thrd->ev = _alloc_event(thrd);
1672 if (thrd->ev >= 0) {
1673 thrd->free = false;
1674 thrd->lstenq = 1;
9dc5a315 1675 thrd->req[0].desc = NULL;
9dc5a315 1676 thrd->req[1].desc = NULL;
8ed30a14 1677 thrd->req_running = -1;
b7d861d9
BK
1678 break;
1679 }
1680 }
1681 thrd = NULL;
1682 }
1683
1684 spin_unlock_irqrestore(&pl330->lock, flags);
1685
1686 return thrd;
1687}
1688
1689/* Release an event */
1690static inline void _free_event(struct pl330_thread *thrd, int ev)
1691{
1692 struct pl330_dmac *pl330 = thrd->dmac;
b7d861d9
BK
1693
1694 /* If the event is valid and was held by the thread */
f6f2421c 1695 if (ev >= 0 && ev < pl330->pcfg.num_events
b7d861d9
BK
1696 && pl330->events[ev] == thrd->id)
1697 pl330->events[ev] = -1;
1698}
1699
65ad6060 1700static void pl330_release_channel(struct pl330_thread *thrd)
b7d861d9 1701{
b7d861d9
BK
1702 struct pl330_dmac *pl330;
1703 unsigned long flags;
1704
1705 if (!thrd || thrd->free)
1706 return;
1707
1708 _stop(thrd);
1709
9dc5a315
LPC
1710 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1711 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
b7d861d9
BK
1712
1713 pl330 = thrd->dmac;
1714
1715 spin_lock_irqsave(&pl330->lock, flags);
1716 _free_event(thrd, thrd->ev);
1717 thrd->free = true;
1718 spin_unlock_irqrestore(&pl330->lock, flags);
1719}
1720
1721/* Initialize the structure for PL330 configuration, that can be used
1722 * by the client driver the make best use of the DMAC
1723 */
f6f2421c 1724static void read_dmac_config(struct pl330_dmac *pl330)
b7d861d9 1725{
f6f2421c 1726 void __iomem *regs = pl330->base;
b7d861d9
BK
1727 u32 val;
1728
1729 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1730 val &= CRD_DATA_WIDTH_MASK;
f6f2421c 1731 pl330->pcfg.data_bus_width = 8 * (1 << val);
b7d861d9
BK
1732
1733 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1734 val &= CRD_DATA_BUFF_MASK;
f6f2421c 1735 pl330->pcfg.data_buf_dep = val + 1;
b7d861d9
BK
1736
1737 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1738 val &= CR0_NUM_CHANS_MASK;
1739 val += 1;
f6f2421c 1740 pl330->pcfg.num_chan = val;
b7d861d9
BK
1741
1742 val = readl(regs + CR0);
1743 if (val & CR0_PERIPH_REQ_SET) {
1744 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1745 val += 1;
f6f2421c
LPC
1746 pl330->pcfg.num_peri = val;
1747 pl330->pcfg.peri_ns = readl(regs + CR4);
b7d861d9 1748 } else {
f6f2421c 1749 pl330->pcfg.num_peri = 0;
b7d861d9
BK
1750 }
1751
1752 val = readl(regs + CR0);
1753 if (val & CR0_BOOT_MAN_NS)
f6f2421c 1754 pl330->pcfg.mode |= DMAC_MODE_NS;
b7d861d9 1755 else
f6f2421c 1756 pl330->pcfg.mode &= ~DMAC_MODE_NS;
b7d861d9
BK
1757
1758 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1759 val &= CR0_NUM_EVENTS_MASK;
1760 val += 1;
f6f2421c 1761 pl330->pcfg.num_events = val;
b7d861d9 1762
f6f2421c 1763 pl330->pcfg.irq_ns = readl(regs + CR3);
b7d861d9
BK
1764}
1765
1766static inline void _reset_thread(struct pl330_thread *thrd)
1767{
1768 struct pl330_dmac *pl330 = thrd->dmac;
b7d861d9
BK
1769
1770 thrd->req[0].mc_cpu = pl330->mcode_cpu
f6f2421c 1771 + (thrd->id * pl330->mcbufsz);
b7d861d9 1772 thrd->req[0].mc_bus = pl330->mcode_bus
f6f2421c 1773 + (thrd->id * pl330->mcbufsz);
9dc5a315 1774 thrd->req[0].desc = NULL;
b7d861d9
BK
1775
1776 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
f6f2421c 1777 + pl330->mcbufsz / 2;
b7d861d9 1778 thrd->req[1].mc_bus = thrd->req[0].mc_bus
f6f2421c 1779 + pl330->mcbufsz / 2;
9dc5a315 1780 thrd->req[1].desc = NULL;
8ed30a14
LPC
1781
1782 thrd->req_running = -1;
b7d861d9
BK
1783}
1784
1785static int dmac_alloc_threads(struct pl330_dmac *pl330)
1786{
f6f2421c 1787 int chans = pl330->pcfg.num_chan;
b7d861d9
BK
1788 struct pl330_thread *thrd;
1789 int i;
1790
1791 /* Allocate 1 Manager and 'chans' Channel threads */
1792 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1793 GFP_KERNEL);
1794 if (!pl330->channels)
1795 return -ENOMEM;
1796
1797 /* Init Channel threads */
1798 for (i = 0; i < chans; i++) {
1799 thrd = &pl330->channels[i];
1800 thrd->id = i;
1801 thrd->dmac = pl330;
1802 _reset_thread(thrd);
1803 thrd->free = true;
1804 }
1805
1806 /* MANAGER is indexed at the end */
1807 thrd = &pl330->channels[chans];
1808 thrd->id = chans;
1809 thrd->dmac = pl330;
1810 thrd->free = false;
1811 pl330->manager = thrd;
1812
1813 return 0;
1814}
1815
1816static int dmac_alloc_resources(struct pl330_dmac *pl330)
1817{
f6f2421c 1818 int chans = pl330->pcfg.num_chan;
b7d861d9 1819 int ret;
b3040e40 1820
b3040e40 1821 /*
b7d861d9
BK
1822 * Alloc MicroCode buffer for 'chans' Channel threads.
1823 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
b3040e40 1824 */
f6f2421c
LPC
1825 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1826 chans * pl330->mcbufsz,
b7d861d9
BK
1827 &pl330->mcode_bus, GFP_KERNEL);
1828 if (!pl330->mcode_cpu) {
f6f2421c 1829 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
b7d861d9
BK
1830 __func__, __LINE__);
1831 return -ENOMEM;
1832 }
1833
1834 ret = dmac_alloc_threads(pl330);
1835 if (ret) {
f6f2421c 1836 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
b7d861d9 1837 __func__, __LINE__);
f6f2421c
LPC
1838 dma_free_coherent(pl330->ddma.dev,
1839 chans * pl330->mcbufsz,
b7d861d9
BK
1840 pl330->mcode_cpu, pl330->mcode_bus);
1841 return ret;
1842 }
1843
1844 return 0;
1845}
1846
f6f2421c 1847static int pl330_add(struct pl330_dmac *pl330)
b7d861d9 1848{
b7d861d9
BK
1849 void __iomem *regs;
1850 int i, ret;
1851
f6f2421c 1852 regs = pl330->base;
b3040e40 1853
b7d861d9 1854 /* Check if we can handle this DMAC */
f6f2421c
LPC
1855 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1856 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1857 pl330->pcfg.periph_id);
b7d861d9
BK
1858 return -EINVAL;
1859 }
b3040e40 1860
b7d861d9 1861 /* Read the configuration of the DMAC */
f6f2421c 1862 read_dmac_config(pl330);
b3040e40 1863
f6f2421c
LPC
1864 if (pl330->pcfg.num_events == 0) {
1865 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
b7d861d9
BK
1866 __func__, __LINE__);
1867 return -EINVAL;
1868 }
b3040e40 1869
b7d861d9 1870 spin_lock_init(&pl330->lock);
1b9bb715 1871
b7d861d9 1872 INIT_LIST_HEAD(&pl330->req_done);
42bc9cf4 1873
b7d861d9 1874 /* Use default MC buffer size if not provided */
f6f2421c
LPC
1875 if (!pl330->mcbufsz)
1876 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
b3040e40 1877
b7d861d9 1878 /* Mark all events as free */
f6f2421c 1879 for (i = 0; i < pl330->pcfg.num_events; i++)
b7d861d9 1880 pl330->events[i] = -1;
b3040e40 1881
b7d861d9
BK
1882 /* Allocate resources needed by the DMAC */
1883 ret = dmac_alloc_resources(pl330);
1884 if (ret) {
f6f2421c 1885 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
b7d861d9
BK
1886 return ret;
1887 }
b3040e40 1888
b7d861d9 1889 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
b3040e40 1890
b7d861d9 1891 pl330->state = INIT;
a2f5203f 1892
b7d861d9
BK
1893 return 0;
1894}
b3040e40 1895
b7d861d9
BK
1896static int dmac_free_threads(struct pl330_dmac *pl330)
1897{
b7d861d9
BK
1898 struct pl330_thread *thrd;
1899 int i;
b3040e40 1900
b7d861d9 1901 /* Release Channel threads */
f6f2421c 1902 for (i = 0; i < pl330->pcfg.num_chan; i++) {
b7d861d9 1903 thrd = &pl330->channels[i];
65ad6060 1904 pl330_release_channel(thrd);
b7d861d9 1905 }
b3040e40 1906
b7d861d9
BK
1907 /* Free memory */
1908 kfree(pl330->channels);
b3040e40 1909
b7d861d9
BK
1910 return 0;
1911}
b3040e40 1912
f6f2421c 1913static void pl330_del(struct pl330_dmac *pl330)
b7d861d9 1914{
b7d861d9
BK
1915 pl330->state = UNINIT;
1916
1917 tasklet_kill(&pl330->tasks);
1918
1919 /* Free DMAC resources */
f6f2421c 1920 dmac_free_threads(pl330);
b7d861d9 1921
f6f2421c
LPC
1922 dma_free_coherent(pl330->ddma.dev,
1923 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1924 pl330->mcode_bus);
b7d861d9 1925}
b3040e40 1926
3e2ec13a
TA
1927/* forward declaration */
1928static struct amba_driver pl330_driver;
1929
b3040e40
JB
1930static inline struct dma_pl330_chan *
1931to_pchan(struct dma_chan *ch)
1932{
1933 if (!ch)
1934 return NULL;
1935
1936 return container_of(ch, struct dma_pl330_chan, chan);
1937}
1938
1939static inline struct dma_pl330_desc *
1940to_desc(struct dma_async_tx_descriptor *tx)
1941{
1942 return container_of(tx, struct dma_pl330_desc, txd);
1943}
1944
b3040e40
JB
1945static inline void fill_queue(struct dma_pl330_chan *pch)
1946{
1947 struct dma_pl330_desc *desc;
1948 int ret;
1949
1950 list_for_each_entry(desc, &pch->work_list, node) {
1951
1952 /* If already submitted */
1953 if (desc->status == BUSY)
30fb980b 1954 continue;
b3040e40 1955
9dc5a315 1956 ret = pl330_submit_req(pch->thread, desc);
b3040e40
JB
1957 if (!ret) {
1958 desc->status = BUSY;
b3040e40
JB
1959 } else if (ret == -EAGAIN) {
1960 /* QFull or DMAC Dying */
1961 break;
1962 } else {
1963 /* Unacceptable request */
1964 desc->status = DONE;
f6f2421c 1965 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
b3040e40
JB
1966 __func__, __LINE__, desc->txd.cookie);
1967 tasklet_schedule(&pch->task);
1968 }
1969 }
1970}
1971
1972static void pl330_tasklet(unsigned long data)
1973{
1974 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
1975 struct dma_pl330_desc *desc, *_dt;
1976 unsigned long flags;
ae43b328 1977 bool power_down = false;
b3040e40
JB
1978
1979 spin_lock_irqsave(&pch->lock, flags);
1980
1981 /* Pick up ripe tomatoes */
1982 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
1983 if (desc->status == DONE) {
30c1dc0f 1984 if (!pch->cyclic)
eab21585 1985 dma_cookie_complete(&desc->txd);
39ff8613 1986 list_move_tail(&desc->node, &pch->completed_list);
b3040e40
JB
1987 }
1988
1989 /* Try to submit a req imm. next to the last completed cookie */
1990 fill_queue(pch);
1991
ae43b328
KK
1992 if (list_empty(&pch->work_list)) {
1993 spin_lock(&pch->thread->dmac->lock);
1994 _stop(pch->thread);
1995 spin_unlock(&pch->thread->dmac->lock);
1996 power_down = true;
1997 } else {
1998 /* Make sure the PL330 Channel thread is active */
1999 spin_lock(&pch->thread->dmac->lock);
2000 _start(pch->thread);
2001 spin_unlock(&pch->thread->dmac->lock);
2002 }
b3040e40 2003
39ff8613
LPC
2004 while (!list_empty(&pch->completed_list)) {
2005 dma_async_tx_callback callback;
2006 void *callback_param;
b3040e40 2007
39ff8613
LPC
2008 desc = list_first_entry(&pch->completed_list,
2009 struct dma_pl330_desc, node);
2010
2011 callback = desc->txd.callback;
2012 callback_param = desc->txd.callback_param;
2013
2014 if (pch->cyclic) {
2015 desc->status = PREP;
2016 list_move_tail(&desc->node, &pch->work_list);
ae43b328
KK
2017 if (power_down) {
2018 spin_lock(&pch->thread->dmac->lock);
2019 _start(pch->thread);
2020 spin_unlock(&pch->thread->dmac->lock);
2021 power_down = false;
2022 }
39ff8613
LPC
2023 } else {
2024 desc->status = FREE;
2025 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2026 }
2027
d38a8c62
DW
2028 dma_descriptor_unmap(&desc->txd);
2029
39ff8613
LPC
2030 if (callback) {
2031 spin_unlock_irqrestore(&pch->lock, flags);
2032 callback(callback_param);
2033 spin_lock_irqsave(&pch->lock, flags);
2034 }
2035 }
2036 spin_unlock_irqrestore(&pch->lock, flags);
ae43b328
KK
2037
2038 /* If work list empty, power down */
2039 if (power_down) {
2040 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2041 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2042 }
b3040e40
JB
2043}
2044
3e2ec13a
TA
2045bool pl330_filter(struct dma_chan *chan, void *param)
2046{
cd072515 2047 u8 *peri_id;
3e2ec13a
TA
2048
2049 if (chan->device->dev->driver != &pl330_driver.drv)
2050 return false;
2051
cd072515 2052 peri_id = chan->private;
2f986ec6 2053 return *peri_id == (unsigned long)param;
3e2ec13a
TA
2054}
2055EXPORT_SYMBOL(pl330_filter);
2056
a80258f9
PV
2057static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2058 struct of_dma *ofdma)
2059{
2060 int count = dma_spec->args_count;
f6f2421c 2061 struct pl330_dmac *pl330 = ofdma->of_dma_data;
70cbb163 2062 unsigned int chan_id;
a80258f9 2063
f6f2421c
LPC
2064 if (!pl330)
2065 return NULL;
2066
a80258f9
PV
2067 if (count != 1)
2068 return NULL;
2069
70cbb163 2070 chan_id = dma_spec->args[0];
f6f2421c 2071 if (chan_id >= pl330->num_peripherals)
70cbb163 2072 return NULL;
a80258f9 2073
f6f2421c 2074 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
a80258f9
PV
2075}
2076
b3040e40
JB
2077static int pl330_alloc_chan_resources(struct dma_chan *chan)
2078{
2079 struct dma_pl330_chan *pch = to_pchan(chan);
f6f2421c 2080 struct pl330_dmac *pl330 = pch->dmac;
b3040e40
JB
2081 unsigned long flags;
2082
2083 spin_lock_irqsave(&pch->lock, flags);
2084
d3ee98cd 2085 dma_cookie_init(chan);
42bc9cf4 2086 pch->cyclic = false;
b3040e40 2087
f6f2421c 2088 pch->thread = pl330_request_channel(pl330);
65ad6060 2089 if (!pch->thread) {
b3040e40 2090 spin_unlock_irqrestore(&pch->lock, flags);
02747885 2091 return -ENOMEM;
b3040e40
JB
2092 }
2093
2094 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2095
2096 spin_unlock_irqrestore(&pch->lock, flags);
2097
2098 return 1;
2099}
2100
740aa957
MR
2101static int pl330_config(struct dma_chan *chan,
2102 struct dma_slave_config *slave_config)
2103{
2104 struct dma_pl330_chan *pch = to_pchan(chan);
2105
2106 if (slave_config->direction == DMA_MEM_TO_DEV) {
2107 if (slave_config->dst_addr)
2108 pch->fifo_addr = slave_config->dst_addr;
2109 if (slave_config->dst_addr_width)
2110 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2111 if (slave_config->dst_maxburst)
2112 pch->burst_len = slave_config->dst_maxburst;
2113 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2114 if (slave_config->src_addr)
2115 pch->fifo_addr = slave_config->src_addr;
2116 if (slave_config->src_addr_width)
2117 pch->burst_sz = __ffs(slave_config->src_addr_width);
2118 if (slave_config->src_maxburst)
2119 pch->burst_len = slave_config->src_maxburst;
2120 }
2121
2122 return 0;
2123}
2124
2125static int pl330_terminate_all(struct dma_chan *chan)
b3040e40
JB
2126{
2127 struct dma_pl330_chan *pch = to_pchan(chan);
39ff8613 2128 struct dma_pl330_desc *desc;
b3040e40 2129 unsigned long flags;
f6f2421c 2130 struct pl330_dmac *pl330 = pch->dmac;
ae43b886 2131 LIST_HEAD(list);
b3040e40 2132
81cc6edc 2133 pm_runtime_get_sync(pl330->ddma.dev);
740aa957
MR
2134 spin_lock_irqsave(&pch->lock, flags);
2135 spin_lock(&pl330->lock);
2136 _stop(pch->thread);
2137 spin_unlock(&pl330->lock);
2138
2139 pch->thread->req[0].desc = NULL;
2140 pch->thread->req[1].desc = NULL;
2141 pch->thread->req_running = -1;
2142
2143 /* Mark all desc done */
2144 list_for_each_entry(desc, &pch->submitted_list, node) {
2145 desc->status = FREE;
2146 dma_cookie_complete(&desc->txd);
2147 }
ae43b328 2148
740aa957
MR
2149 list_for_each_entry(desc, &pch->work_list , node) {
2150 desc->status = FREE;
2151 dma_cookie_complete(&desc->txd);
1d0c1d60 2152 }
b3040e40 2153
740aa957
MR
2154 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2155 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2156 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2157 spin_unlock_irqrestore(&pch->lock, flags);
81cc6edc
KK
2158 pm_runtime_mark_last_busy(pl330->ddma.dev);
2159 pm_runtime_put_autosuspend(pl330->ddma.dev);
740aa957 2160
b3040e40
JB
2161 return 0;
2162}
2163
88987d2c
RB
2164/*
2165 * We don't support DMA_RESUME command because of hardware
2166 * limitations, so after pausing the channel we cannot restore
2167 * it to active state. We have to terminate channel and setup
2168 * DMA transfer again. This pause feature was implemented to
2169 * allow safely read residue before channel termination.
2170 */
5503aed8 2171static int pl330_pause(struct dma_chan *chan)
88987d2c
RB
2172{
2173 struct dma_pl330_chan *pch = to_pchan(chan);
2174 struct pl330_dmac *pl330 = pch->dmac;
2175 unsigned long flags;
2176
2177 pm_runtime_get_sync(pl330->ddma.dev);
2178 spin_lock_irqsave(&pch->lock, flags);
2179
2180 spin_lock(&pl330->lock);
2181 _stop(pch->thread);
2182 spin_unlock(&pl330->lock);
2183
2184 spin_unlock_irqrestore(&pch->lock, flags);
2185 pm_runtime_mark_last_busy(pl330->ddma.dev);
2186 pm_runtime_put_autosuspend(pl330->ddma.dev);
2187
2188 return 0;
2189}
2190
b3040e40
JB
2191static void pl330_free_chan_resources(struct dma_chan *chan)
2192{
2193 struct dma_pl330_chan *pch = to_pchan(chan);
2194 unsigned long flags;
2195
b3040e40
JB
2196 tasklet_kill(&pch->task);
2197
ae43b328 2198 pm_runtime_get_sync(pch->dmac->ddma.dev);
da331ba8
BZ
2199 spin_lock_irqsave(&pch->lock, flags);
2200
65ad6060
LPC
2201 pl330_release_channel(pch->thread);
2202 pch->thread = NULL;
b3040e40 2203
42bc9cf4
BK
2204 if (pch->cyclic)
2205 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2206
b3040e40 2207 spin_unlock_irqrestore(&pch->lock, flags);
ae43b328
KK
2208 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2209 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
b3040e40
JB
2210}
2211
5503aed8
BD
2212static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2213 struct dma_pl330_desc *desc)
aee4d1fa
RB
2214{
2215 struct pl330_thread *thrd = pch->thread;
2216 struct pl330_dmac *pl330 = pch->dmac;
2217 void __iomem *regs = thrd->dmac->base;
2218 u32 val, addr;
2219
2220 pm_runtime_get_sync(pl330->ddma.dev);
2221 val = addr = 0;
2222 if (desc->rqcfg.src_inc) {
2223 val = readl(regs + SA(thrd->id));
2224 addr = desc->px.src_addr;
2225 } else {
2226 val = readl(regs + DA(thrd->id));
2227 addr = desc->px.dst_addr;
2228 }
2229 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2230 pm_runtime_put_autosuspend(pl330->ddma.dev);
2231 return val - addr;
2232}
2233
b3040e40
JB
2234static enum dma_status
2235pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2236 struct dma_tx_state *txstate)
2237{
aee4d1fa
RB
2238 enum dma_status ret;
2239 unsigned long flags;
2240 struct dma_pl330_desc *desc, *running = NULL;
2241 struct dma_pl330_chan *pch = to_pchan(chan);
2242 unsigned int transferred, residual = 0;
2243
2244 ret = dma_cookie_status(chan, cookie, txstate);
2245
2246 if (!txstate)
2247 return ret;
2248
2249 if (ret == DMA_COMPLETE)
2250 goto out;
2251
2252 spin_lock_irqsave(&pch->lock, flags);
2253
2254 if (pch->thread->req_running != -1)
2255 running = pch->thread->req[pch->thread->req_running].desc;
2256
2257 /* Check in pending list */
2258 list_for_each_entry(desc, &pch->work_list, node) {
2259 if (desc->status == DONE)
2260 transferred = desc->bytes_requested;
2261 else if (running && desc == running)
2262 transferred =
2263 pl330_get_current_xferred_count(pch, desc);
2264 else
2265 transferred = 0;
2266 residual += desc->bytes_requested - transferred;
2267 if (desc->txd.cookie == cookie) {
75967b78
BD
2268 switch (desc->status) {
2269 case DONE:
2270 ret = DMA_COMPLETE;
2271 break;
2272 case PREP:
2273 case BUSY:
2274 ret = DMA_IN_PROGRESS;
2275 break;
2276 default:
2277 WARN_ON(1);
2278 }
aee4d1fa
RB
2279 break;
2280 }
2281 if (desc->last)
2282 residual = 0;
2283 }
2284 spin_unlock_irqrestore(&pch->lock, flags);
2285
2286out:
2287 dma_set_residue(txstate, residual);
2288
2289 return ret;
b3040e40
JB
2290}
2291
2292static void pl330_issue_pending(struct dma_chan *chan)
2293{
04abf5da
LPC
2294 struct dma_pl330_chan *pch = to_pchan(chan);
2295 unsigned long flags;
2296
2297 spin_lock_irqsave(&pch->lock, flags);
ae43b328
KK
2298 if (list_empty(&pch->work_list)) {
2299 /*
2300 * Warn on nothing pending. Empty submitted_list may
2301 * break our pm_runtime usage counter as it is
2302 * updated on work_list emptiness status.
2303 */
2304 WARN_ON(list_empty(&pch->submitted_list));
2305 pm_runtime_get_sync(pch->dmac->ddma.dev);
2306 }
04abf5da
LPC
2307 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2308 spin_unlock_irqrestore(&pch->lock, flags);
2309
2310 pl330_tasklet((unsigned long)pch);
b3040e40
JB
2311}
2312
2313/*
2314 * We returned the last one of the circular list of descriptor(s)
2315 * from prep_xxx, so the argument to submit corresponds to the last
2316 * descriptor of the list.
2317 */
2318static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2319{
2320 struct dma_pl330_desc *desc, *last = to_desc(tx);
2321 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2322 dma_cookie_t cookie;
2323 unsigned long flags;
2324
2325 spin_lock_irqsave(&pch->lock, flags);
2326
2327 /* Assign cookies to all nodes */
b3040e40
JB
2328 while (!list_empty(&last->node)) {
2329 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
fc514460
LPC
2330 if (pch->cyclic) {
2331 desc->txd.callback = last->txd.callback;
2332 desc->txd.callback_param = last->txd.callback_param;
2333 }
5dd90e5b 2334 desc->last = false;
b3040e40 2335
884485e1 2336 dma_cookie_assign(&desc->txd);
b3040e40 2337
04abf5da 2338 list_move_tail(&desc->node, &pch->submitted_list);
b3040e40
JB
2339 }
2340
aee4d1fa 2341 last->last = true;
884485e1 2342 cookie = dma_cookie_assign(&last->txd);
04abf5da 2343 list_add_tail(&last->node, &pch->submitted_list);
b3040e40
JB
2344 spin_unlock_irqrestore(&pch->lock, flags);
2345
2346 return cookie;
2347}
2348
2349static inline void _init_desc(struct dma_pl330_desc *desc)
2350{
b3040e40 2351 desc->rqcfg.swap = SWAP_NO;
f0564c7e
LPC
2352 desc->rqcfg.scctl = CCTRL0;
2353 desc->rqcfg.dcctl = CCTRL0;
b3040e40
JB
2354 desc->txd.tx_submit = pl330_tx_submit;
2355
2356 INIT_LIST_HEAD(&desc->node);
2357}
2358
2359/* Returns the number of descriptors added to the DMAC pool */
f6f2421c 2360static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
b3040e40
JB
2361{
2362 struct dma_pl330_desc *desc;
2363 unsigned long flags;
2364 int i;
2365
0baf8f6a 2366 desc = kcalloc(count, sizeof(*desc), flg);
b3040e40
JB
2367 if (!desc)
2368 return 0;
2369
f6f2421c 2370 spin_lock_irqsave(&pl330->pool_lock, flags);
b3040e40
JB
2371
2372 for (i = 0; i < count; i++) {
2373 _init_desc(&desc[i]);
f6f2421c 2374 list_add_tail(&desc[i].node, &pl330->desc_pool);
b3040e40
JB
2375 }
2376
f6f2421c 2377 spin_unlock_irqrestore(&pl330->pool_lock, flags);
b3040e40
JB
2378
2379 return count;
2380}
2381
f6f2421c 2382static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
b3040e40
JB
2383{
2384 struct dma_pl330_desc *desc = NULL;
2385 unsigned long flags;
2386
f6f2421c 2387 spin_lock_irqsave(&pl330->pool_lock, flags);
b3040e40 2388
f6f2421c
LPC
2389 if (!list_empty(&pl330->desc_pool)) {
2390 desc = list_entry(pl330->desc_pool.next,
b3040e40
JB
2391 struct dma_pl330_desc, node);
2392
2393 list_del_init(&desc->node);
2394
2395 desc->status = PREP;
2396 desc->txd.callback = NULL;
2397 }
2398
f6f2421c 2399 spin_unlock_irqrestore(&pl330->pool_lock, flags);
b3040e40
JB
2400
2401 return desc;
2402}
2403
2404static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2405{
f6f2421c 2406 struct pl330_dmac *pl330 = pch->dmac;
cd072515 2407 u8 *peri_id = pch->chan.private;
b3040e40
JB
2408 struct dma_pl330_desc *desc;
2409
2410 /* Pluck one desc from the pool of DMAC */
f6f2421c 2411 desc = pluck_desc(pl330);
b3040e40
JB
2412
2413 /* If the DMAC pool is empty, alloc new */
2414 if (!desc) {
f6f2421c 2415 if (!add_desc(pl330, GFP_ATOMIC, 1))
b3040e40
JB
2416 return NULL;
2417
2418 /* Try again */
f6f2421c 2419 desc = pluck_desc(pl330);
b3040e40 2420 if (!desc) {
f6f2421c 2421 dev_err(pch->dmac->ddma.dev,
b3040e40
JB
2422 "%s:%d ALERT!\n", __func__, __LINE__);
2423 return NULL;
2424 }
2425 }
2426
2427 /* Initialize the descriptor */
2428 desc->pchan = pch;
2429 desc->txd.cookie = 0;
2430 async_tx_ack(&desc->txd);
2431
9dc5a315 2432 desc->peri = peri_id ? pch->chan.chan_id : 0;
f6f2421c 2433 desc->rqcfg.pcfg = &pch->dmac->pcfg;
b3040e40
JB
2434
2435 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2436
2437 return desc;
2438}
2439
2440static inline void fill_px(struct pl330_xfer *px,
2441 dma_addr_t dst, dma_addr_t src, size_t len)
2442{
b3040e40
JB
2443 px->bytes = len;
2444 px->dst_addr = dst;
2445 px->src_addr = src;
2446}
2447
2448static struct dma_pl330_desc *
2449__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2450 dma_addr_t src, size_t len)
2451{
2452 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2453
2454 if (!desc) {
f6f2421c 2455 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
b3040e40
JB
2456 __func__, __LINE__);
2457 return NULL;
2458 }
2459
2460 /*
2461 * Ideally we should lookout for reqs bigger than
2462 * those that can be programmed with 256 bytes of
2463 * MC buffer, but considering a req size is seldom
2464 * going to be word-unaligned and more than 200MB,
2465 * we take it easy.
2466 * Also, should the limit is reached we'd rather
2467 * have the platform increase MC buffer size than
2468 * complicating this API driver.
2469 */
2470 fill_px(&desc->px, dst, src, len);
2471
2472 return desc;
2473}
2474
2475/* Call after fixing burst size */
2476static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2477{
2478 struct dma_pl330_chan *pch = desc->pchan;
f6f2421c 2479 struct pl330_dmac *pl330 = pch->dmac;
b3040e40
JB
2480 int burst_len;
2481
f6f2421c 2482 burst_len = pl330->pcfg.data_bus_width / 8;
c27f9556 2483 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
b3040e40
JB
2484 burst_len >>= desc->rqcfg.brst_size;
2485
2486 /* src/dst_burst_len can't be more than 16 */
2487 if (burst_len > 16)
2488 burst_len = 16;
2489
2490 while (burst_len > 1) {
2491 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2492 break;
2493 burst_len--;
2494 }
2495
2496 return burst_len;
2497}
2498
42bc9cf4
BK
2499static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2500 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
185ecb5f 2501 size_t period_len, enum dma_transfer_direction direction,
31c1e5a1 2502 unsigned long flags)
42bc9cf4 2503{
fc514460 2504 struct dma_pl330_desc *desc = NULL, *first = NULL;
42bc9cf4 2505 struct dma_pl330_chan *pch = to_pchan(chan);
f6f2421c 2506 struct pl330_dmac *pl330 = pch->dmac;
fc514460 2507 unsigned int i;
42bc9cf4
BK
2508 dma_addr_t dst;
2509 dma_addr_t src;
2510
fc514460 2511 if (len % period_len != 0)
42bc9cf4 2512 return NULL;
42bc9cf4 2513
fc514460 2514 if (!is_slave_direction(direction)) {
f6f2421c 2515 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
42bc9cf4
BK
2516 __func__, __LINE__);
2517 return NULL;
2518 }
2519
fc514460
LPC
2520 for (i = 0; i < len / period_len; i++) {
2521 desc = pl330_get_desc(pch);
2522 if (!desc) {
f6f2421c 2523 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
fc514460 2524 __func__, __LINE__);
42bc9cf4 2525
fc514460
LPC
2526 if (!first)
2527 return NULL;
2528
f6f2421c 2529 spin_lock_irqsave(&pl330->pool_lock, flags);
fc514460
LPC
2530
2531 while (!list_empty(&first->node)) {
2532 desc = list_entry(first->node.next,
2533 struct dma_pl330_desc, node);
f6f2421c 2534 list_move_tail(&desc->node, &pl330->desc_pool);
fc514460
LPC
2535 }
2536
f6f2421c 2537 list_move_tail(&first->node, &pl330->desc_pool);
fc514460 2538
f6f2421c 2539 spin_unlock_irqrestore(&pl330->pool_lock, flags);
42bc9cf4 2540
fc514460
LPC
2541 return NULL;
2542 }
2543
2544 switch (direction) {
2545 case DMA_MEM_TO_DEV:
2546 desc->rqcfg.src_inc = 1;
2547 desc->rqcfg.dst_inc = 0;
fc514460
LPC
2548 src = dma_addr;
2549 dst = pch->fifo_addr;
2550 break;
2551 case DMA_DEV_TO_MEM:
2552 desc->rqcfg.src_inc = 0;
2553 desc->rqcfg.dst_inc = 1;
fc514460
LPC
2554 src = pch->fifo_addr;
2555 dst = dma_addr;
2556 break;
2557 default:
2558 break;
2559 }
2560
9dc5a315 2561 desc->rqtype = direction;
fc514460
LPC
2562 desc->rqcfg.brst_size = pch->burst_sz;
2563 desc->rqcfg.brst_len = 1;
aee4d1fa 2564 desc->bytes_requested = period_len;
fc514460
LPC
2565 fill_px(&desc->px, dst, src, period_len);
2566
2567 if (!first)
2568 first = desc;
2569 else
2570 list_add_tail(&desc->node, &first->node);
2571
2572 dma_addr += period_len;
2573 }
2574
2575 if (!desc)
2576 return NULL;
2577
2578 pch->cyclic = true;
2579 desc->txd.flags = flags;
42bc9cf4
BK
2580
2581 return &desc->txd;
2582}
2583
b3040e40
JB
2584static struct dma_async_tx_descriptor *
2585pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2586 dma_addr_t src, size_t len, unsigned long flags)
2587{
2588 struct dma_pl330_desc *desc;
2589 struct dma_pl330_chan *pch = to_pchan(chan);
f5636854 2590 struct pl330_dmac *pl330;
b3040e40
JB
2591 int burst;
2592
4e0e6109 2593 if (unlikely(!pch || !len))
b3040e40
JB
2594 return NULL;
2595
f5636854
MS
2596 pl330 = pch->dmac;
2597
b3040e40
JB
2598 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2599 if (!desc)
2600 return NULL;
2601
2602 desc->rqcfg.src_inc = 1;
2603 desc->rqcfg.dst_inc = 1;
9dc5a315 2604 desc->rqtype = DMA_MEM_TO_MEM;
b3040e40
JB
2605
2606 /* Select max possible burst size */
f6f2421c 2607 burst = pl330->pcfg.data_bus_width / 8;
b3040e40 2608
137bd110
JM
2609 /*
2610 * Make sure we use a burst size that aligns with all the memcpy
2611 * parameters because our DMA programming algorithm doesn't cope with
2612 * transfers which straddle an entry in the DMA device's MFIFO.
2613 */
2614 while ((src | dst | len) & (burst - 1))
b3040e40 2615 burst /= 2;
b3040e40
JB
2616
2617 desc->rqcfg.brst_size = 0;
2618 while (burst != (1 << desc->rqcfg.brst_size))
2619 desc->rqcfg.brst_size++;
2620
137bd110
JM
2621 /*
2622 * If burst size is smaller than bus width then make sure we only
2623 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2624 */
2625 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2626 desc->rqcfg.brst_len = 1;
2627
b3040e40 2628 desc->rqcfg.brst_len = get_burst_len(desc, len);
ae128293 2629 desc->bytes_requested = len;
b3040e40
JB
2630
2631 desc->txd.flags = flags;
2632
2633 return &desc->txd;
2634}
2635
f6f2421c 2636static void __pl330_giveback_desc(struct pl330_dmac *pl330,
52a9d179
CP
2637 struct dma_pl330_desc *first)
2638{
2639 unsigned long flags;
2640 struct dma_pl330_desc *desc;
2641
2642 if (!first)
2643 return;
2644
f6f2421c 2645 spin_lock_irqsave(&pl330->pool_lock, flags);
52a9d179
CP
2646
2647 while (!list_empty(&first->node)) {
2648 desc = list_entry(first->node.next,
2649 struct dma_pl330_desc, node);
f6f2421c 2650 list_move_tail(&desc->node, &pl330->desc_pool);
52a9d179
CP
2651 }
2652
f6f2421c 2653 list_move_tail(&first->node, &pl330->desc_pool);
52a9d179 2654
f6f2421c 2655 spin_unlock_irqrestore(&pl330->pool_lock, flags);
52a9d179
CP
2656}
2657
b3040e40
JB
2658static struct dma_async_tx_descriptor *
2659pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
db8196df 2660 unsigned int sg_len, enum dma_transfer_direction direction,
185ecb5f 2661 unsigned long flg, void *context)
b3040e40
JB
2662{
2663 struct dma_pl330_desc *first, *desc = NULL;
2664 struct dma_pl330_chan *pch = to_pchan(chan);
b3040e40 2665 struct scatterlist *sg;
1b9bb715 2666 int i;
b3040e40
JB
2667 dma_addr_t addr;
2668
cd072515 2669 if (unlikely(!pch || !sgl || !sg_len))
b3040e40
JB
2670 return NULL;
2671
1b9bb715 2672 addr = pch->fifo_addr;
b3040e40
JB
2673
2674 first = NULL;
2675
2676 for_each_sg(sgl, sg, sg_len, i) {
2677
2678 desc = pl330_get_desc(pch);
2679 if (!desc) {
f6f2421c 2680 struct pl330_dmac *pl330 = pch->dmac;
b3040e40 2681
f6f2421c 2682 dev_err(pch->dmac->ddma.dev,
b3040e40
JB
2683 "%s:%d Unable to fetch desc\n",
2684 __func__, __LINE__);
f6f2421c 2685 __pl330_giveback_desc(pl330, first);
b3040e40
JB
2686
2687 return NULL;
2688 }
2689
2690 if (!first)
2691 first = desc;
2692 else
2693 list_add_tail(&desc->node, &first->node);
2694
db8196df 2695 if (direction == DMA_MEM_TO_DEV) {
b3040e40
JB
2696 desc->rqcfg.src_inc = 1;
2697 desc->rqcfg.dst_inc = 0;
2698 fill_px(&desc->px,
2699 addr, sg_dma_address(sg), sg_dma_len(sg));
2700 } else {
2701 desc->rqcfg.src_inc = 0;
2702 desc->rqcfg.dst_inc = 1;
2703 fill_px(&desc->px,
2704 sg_dma_address(sg), addr, sg_dma_len(sg));
2705 }
2706
1b9bb715 2707 desc->rqcfg.brst_size = pch->burst_sz;
b3040e40 2708 desc->rqcfg.brst_len = 1;
9dc5a315 2709 desc->rqtype = direction;
aee4d1fa 2710 desc->bytes_requested = sg_dma_len(sg);
b3040e40
JB
2711 }
2712
2713 /* Return the last desc in the chain */
2714 desc->txd.flags = flg;
2715 return &desc->txd;
2716}
2717
2718static irqreturn_t pl330_irq_handler(int irq, void *data)
2719{
2720 if (pl330_update(data))
2721 return IRQ_HANDLED;
2722 else
2723 return IRQ_NONE;
2724}
2725
ca38ff13
LPC
2726#define PL330_DMA_BUSWIDTHS \
2727 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2728 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2729 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2730 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2731 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2732
b816ccc5
KK
2733/*
2734 * Runtime PM callbacks are provided by amba/bus.c driver.
2735 *
2736 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2737 * bus driver will only disable/enable the clock in runtime PM callbacks.
2738 */
2739static int __maybe_unused pl330_suspend(struct device *dev)
2740{
2741 struct amba_device *pcdev = to_amba_device(dev);
2742
2743 pm_runtime_disable(dev);
2744
2745 if (!pm_runtime_status_suspended(dev)) {
2746 /* amba did not disable the clock */
2747 amba_pclk_disable(pcdev);
2748 }
2749 amba_pclk_unprepare(pcdev);
2750
2751 return 0;
2752}
2753
2754static int __maybe_unused pl330_resume(struct device *dev)
2755{
2756 struct amba_device *pcdev = to_amba_device(dev);
2757 int ret;
2758
2759 ret = amba_pclk_prepare(pcdev);
2760 if (ret)
2761 return ret;
2762
2763 if (!pm_runtime_status_suspended(dev))
2764 ret = amba_pclk_enable(pcdev);
2765
2766 pm_runtime_enable(dev);
2767
2768 return ret;
2769}
2770
2771static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2772
463a1f8b 2773static int
aa25afad 2774pl330_probe(struct amba_device *adev, const struct amba_id *id)
b3040e40
JB
2775{
2776 struct dma_pl330_platdata *pdat;
f6f2421c
LPC
2777 struct pl330_config *pcfg;
2778 struct pl330_dmac *pl330;
0b94c577 2779 struct dma_pl330_chan *pch, *_p;
b3040e40
JB
2780 struct dma_device *pd;
2781 struct resource *res;
2782 int i, ret, irq;
4e0e6109 2783 int num_chan;
b3040e40 2784
d4adcc01 2785 pdat = dev_get_platdata(&adev->dev);
b3040e40 2786
64113016
RK
2787 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2788 if (ret)
2789 return ret;
2790
b3040e40 2791 /* Allocate a new DMAC and its Channels */
f6f2421c
LPC
2792 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2793 if (!pl330) {
b3040e40
JB
2794 dev_err(&adev->dev, "unable to allocate mem\n");
2795 return -ENOMEM;
2796 }
2797
cee42392
AJ
2798 pd = &pl330->ddma;
2799 pd->dev = &adev->dev;
2800
f6f2421c 2801 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
b3040e40
JB
2802
2803 res = &adev->res;
f6f2421c
LPC
2804 pl330->base = devm_ioremap_resource(&adev->dev, res);
2805 if (IS_ERR(pl330->base))
2806 return PTR_ERR(pl330->base);
b3040e40 2807
f6f2421c 2808 amba_set_drvdata(adev, pl330);
a2f5203f 2809
02808b42 2810 for (i = 0; i < AMBA_NR_IRQS; i++) {
e98b3caf
MS
2811 irq = adev->irq[i];
2812 if (irq) {
2813 ret = devm_request_irq(&adev->dev, irq,
2814 pl330_irq_handler, 0,
f6f2421c 2815 dev_name(&adev->dev), pl330);
e98b3caf
MS
2816 if (ret)
2817 return ret;
2818 } else {
2819 break;
2820 }
2821 }
b3040e40 2822
f6f2421c
LPC
2823 pcfg = &pl330->pcfg;
2824
2825 pcfg->periph_id = adev->periphid;
2826 ret = pl330_add(pl330);
b3040e40 2827 if (ret)
173e838c 2828 return ret;
b3040e40 2829
f6f2421c
LPC
2830 INIT_LIST_HEAD(&pl330->desc_pool);
2831 spin_lock_init(&pl330->pool_lock);
b3040e40
JB
2832
2833 /* Create a descriptor pool of default size */
f6f2421c 2834 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
b3040e40
JB
2835 dev_warn(&adev->dev, "unable to allocate desc\n");
2836
b3040e40
JB
2837 INIT_LIST_HEAD(&pd->channels);
2838
2839 /* Initialize channel parameters */
c8473828 2840 if (pdat)
f6f2421c 2841 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
c8473828 2842 else
f6f2421c 2843 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
c8473828 2844
f6f2421c 2845 pl330->num_peripherals = num_chan;
70cbb163 2846
f6f2421c
LPC
2847 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2848 if (!pl330->peripherals) {
61c6e753 2849 ret = -ENOMEM;
f6f2421c 2850 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
e4d43c17 2851 goto probe_err2;
61c6e753 2852 }
b3040e40 2853
4e0e6109 2854 for (i = 0; i < num_chan; i++) {
f6f2421c 2855 pch = &pl330->peripherals[i];
93ed5544
TA
2856 if (!adev->dev.of_node)
2857 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2858 else
2859 pch->chan.private = adev->dev.of_node;
b3040e40 2860
04abf5da 2861 INIT_LIST_HEAD(&pch->submitted_list);
b3040e40 2862 INIT_LIST_HEAD(&pch->work_list);
39ff8613 2863 INIT_LIST_HEAD(&pch->completed_list);
b3040e40 2864 spin_lock_init(&pch->lock);
65ad6060 2865 pch->thread = NULL;
b3040e40 2866 pch->chan.device = pd;
f6f2421c 2867 pch->dmac = pl330;
b3040e40
JB
2868
2869 /* Add the channel to the DMAC list */
b3040e40
JB
2870 list_add_tail(&pch->chan.device_node, &pd->channels);
2871 }
2872
93ed5544 2873 if (pdat) {
cd072515 2874 pd->cap_mask = pdat->cap_mask;
93ed5544 2875 } else {
cd072515 2876 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
f6f2421c 2877 if (pcfg->num_peri) {
93ed5544
TA
2878 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2879 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
5557a419 2880 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
93ed5544
TA
2881 }
2882 }
b3040e40
JB
2883
2884 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2885 pd->device_free_chan_resources = pl330_free_chan_resources;
2886 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
42bc9cf4 2887 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
b3040e40
JB
2888 pd->device_tx_status = pl330_tx_status;
2889 pd->device_prep_slave_sg = pl330_prep_slave_sg;
740aa957 2890 pd->device_config = pl330_config;
88987d2c 2891 pd->device_pause = pl330_pause;
740aa957 2892 pd->device_terminate_all = pl330_terminate_all;
b3040e40 2893 pd->device_issue_pending = pl330_issue_pending;
dcabe456
MR
2894 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2895 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2896 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
aee4d1fa 2897 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
b3040e40
JB
2898
2899 ret = dma_async_device_register(pd);
2900 if (ret) {
2901 dev_err(&adev->dev, "unable to register DMAC\n");
0b94c577
PV
2902 goto probe_err3;
2903 }
2904
2905 if (adev->dev.of_node) {
2906 ret = of_dma_controller_register(adev->dev.of_node,
f6f2421c 2907 of_dma_pl330_xlate, pl330);
0b94c577
PV
2908 if (ret) {
2909 dev_err(&adev->dev,
2910 "unable to register DMA to the generic DT DMA helpers\n");
2911 }
b3040e40 2912 }
b714b84e 2913
f6f2421c 2914 adev->dev.dma_parms = &pl330->dma_parms;
b714b84e 2915
dbaf6d85
VK
2916 /*
2917 * This is the limit for transfers with a buswidth of 1, larger
2918 * buswidths will have larger limits.
2919 */
2920 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2921 if (ret)
2922 dev_err(&adev->dev, "unable to set the seg size\n");
2923
b3040e40 2924
b3040e40 2925 dev_info(&adev->dev,
1f0a5cbf 2926 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
b3040e40
JB
2927 dev_info(&adev->dev,
2928 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
f6f2421c
LPC
2929 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2930 pcfg->num_peri, pcfg->num_events);
b3040e40 2931
ae43b328
KK
2932 pm_runtime_irq_safe(&adev->dev);
2933 pm_runtime_use_autosuspend(&adev->dev);
2934 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2935 pm_runtime_mark_last_busy(&adev->dev);
2936 pm_runtime_put_autosuspend(&adev->dev);
2937
b3040e40 2938 return 0;
0b94c577 2939probe_err3:
0b94c577 2940 /* Idle the DMAC */
f6f2421c 2941 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
0b94c577
PV
2942 chan.device_node) {
2943
2944 /* Remove the channel */
2945 list_del(&pch->chan.device_node);
2946
2947 /* Flush the channel */
0f5ebabd 2948 if (pch->thread) {
740aa957 2949 pl330_terminate_all(&pch->chan);
0f5ebabd
KK
2950 pl330_free_chan_resources(&pch->chan);
2951 }
0b94c577 2952 }
b3040e40 2953probe_err2:
f6f2421c 2954 pl330_del(pl330);
b3040e40
JB
2955
2956 return ret;
2957}
2958
4bf27b8b 2959static int pl330_remove(struct amba_device *adev)
b3040e40 2960{
f6f2421c 2961 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
b3040e40 2962 struct dma_pl330_chan *pch, *_p;
b3040e40 2963
ae43b328
KK
2964 pm_runtime_get_noresume(pl330->ddma.dev);
2965
0b94c577
PV
2966 if (adev->dev.of_node)
2967 of_dma_controller_free(adev->dev.of_node);
421da89a 2968
f6f2421c 2969 dma_async_device_unregister(&pl330->ddma);
b3040e40
JB
2970
2971 /* Idle the DMAC */
f6f2421c 2972 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
b3040e40
JB
2973 chan.device_node) {
2974
2975 /* Remove the channel */
2976 list_del(&pch->chan.device_node);
2977
2978 /* Flush the channel */
6e4a2a83 2979 if (pch->thread) {
740aa957 2980 pl330_terminate_all(&pch->chan);
6e4a2a83
KK
2981 pl330_free_chan_resources(&pch->chan);
2982 }
b3040e40
JB
2983 }
2984
f6f2421c 2985 pl330_del(pl330);
b3040e40 2986
b3040e40
JB
2987 return 0;
2988}
2989
2990static struct amba_id pl330_ids[] = {
2991 {
2992 .id = 0x00041330,
2993 .mask = 0x000fffff,
2994 },
2995 { 0, 0 },
2996};
2997
e8fa516a
DM
2998MODULE_DEVICE_TABLE(amba, pl330_ids);
2999
b3040e40
JB
3000static struct amba_driver pl330_driver = {
3001 .drv = {
3002 .owner = THIS_MODULE,
3003 .name = "dma-pl330",
b816ccc5 3004 .pm = &pl330_pm,
b3040e40
JB
3005 },
3006 .id_table = pl330_ids,
3007 .probe = pl330_probe,
3008 .remove = pl330_remove,
3009};
3010
9e5ed094 3011module_amba_driver(pl330_driver);
b3040e40 3012
046209f6 3013MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
b3040e40
JB
3014MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3015MODULE_LICENSE("GPL");