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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
b7d861d9 BK |
2 | /* |
3 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
b3040e40 JB |
5 | * |
6 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
7 | * Jaswinder Singh <jassi.brar@samsung.com> | |
b3040e40 JB |
8 | */ |
9 | ||
b45aef3a | 10 | #include <linux/debugfs.h> |
b7d861d9 | 11 | #include <linux/kernel.h> |
b3040e40 JB |
12 | #include <linux/io.h> |
13 | #include <linux/init.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/module.h> | |
b7d861d9 BK |
16 | #include <linux/string.h> |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/dma-mapping.h> | |
b3040e40 | 20 | #include <linux/dmaengine.h> |
b3040e40 | 21 | #include <linux/amba/bus.h> |
1b9bb715 | 22 | #include <linux/scatterlist.h> |
93ed5544 | 23 | #include <linux/of.h> |
a80258f9 | 24 | #include <linux/of_dma.h> |
bcc7fa95 | 25 | #include <linux/err.h> |
ae43b328 | 26 | #include <linux/pm_runtime.h> |
1d48745b | 27 | #include <linux/bug.h> |
b3040e40 | 28 | |
d2ebfb33 | 29 | #include "dmaengine.h" |
b7d861d9 BK |
30 | #define PL330_MAX_CHAN 8 |
31 | #define PL330_MAX_IRQS 32 | |
32 | #define PL330_MAX_PERI 32 | |
86a8ce7d | 33 | #define PL330_MAX_BURST 16 |
b7d861d9 | 34 | |
271e1b86 AK |
35 | #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0) |
36 | ||
f0564c7e LPC |
37 | enum pl330_cachectrl { |
38 | CCTRL0, /* Noncacheable and nonbufferable */ | |
39 | CCTRL1, /* Bufferable only */ | |
40 | CCTRL2, /* Cacheable, but do not allocate */ | |
41 | CCTRL3, /* Cacheable and bufferable, but do not allocate */ | |
42 | INVALID1, /* AWCACHE = 0x1000 */ | |
43 | INVALID2, | |
44 | CCTRL6, /* Cacheable write-through, allocate on writes only */ | |
45 | CCTRL7, /* Cacheable write-back, allocate on writes only */ | |
b7d861d9 BK |
46 | }; |
47 | ||
48 | enum pl330_byteswap { | |
49 | SWAP_NO, | |
50 | SWAP_2, | |
51 | SWAP_4, | |
52 | SWAP_8, | |
53 | SWAP_16, | |
54 | }; | |
55 | ||
b7d861d9 BK |
56 | /* Register and Bit field Definitions */ |
57 | #define DS 0x0 | |
58 | #define DS_ST_STOP 0x0 | |
59 | #define DS_ST_EXEC 0x1 | |
60 | #define DS_ST_CMISS 0x2 | |
61 | #define DS_ST_UPDTPC 0x3 | |
62 | #define DS_ST_WFE 0x4 | |
63 | #define DS_ST_ATBRR 0x5 | |
64 | #define DS_ST_QBUSY 0x6 | |
65 | #define DS_ST_WFP 0x7 | |
66 | #define DS_ST_KILL 0x8 | |
67 | #define DS_ST_CMPLT 0x9 | |
68 | #define DS_ST_FLTCMP 0xe | |
69 | #define DS_ST_FAULT 0xf | |
70 | ||
71 | #define DPC 0x4 | |
72 | #define INTEN 0x20 | |
73 | #define ES 0x24 | |
74 | #define INTSTATUS 0x28 | |
75 | #define INTCLR 0x2c | |
76 | #define FSM 0x30 | |
77 | #define FSC 0x34 | |
78 | #define FTM 0x38 | |
79 | ||
80 | #define _FTC 0x40 | |
81 | #define FTC(n) (_FTC + (n)*0x4) | |
82 | ||
83 | #define _CS 0x100 | |
84 | #define CS(n) (_CS + (n)*0x8) | |
85 | #define CS_CNS (1 << 21) | |
86 | ||
87 | #define _CPC 0x104 | |
88 | #define CPC(n) (_CPC + (n)*0x8) | |
89 | ||
90 | #define _SA 0x400 | |
91 | #define SA(n) (_SA + (n)*0x20) | |
92 | ||
93 | #define _DA 0x404 | |
94 | #define DA(n) (_DA + (n)*0x20) | |
95 | ||
96 | #define _CC 0x408 | |
97 | #define CC(n) (_CC + (n)*0x20) | |
98 | ||
99 | #define CC_SRCINC (1 << 0) | |
100 | #define CC_DSTINC (1 << 14) | |
101 | #define CC_SRCPRI (1 << 8) | |
102 | #define CC_DSTPRI (1 << 22) | |
103 | #define CC_SRCNS (1 << 9) | |
104 | #define CC_DSTNS (1 << 23) | |
105 | #define CC_SRCIA (1 << 10) | |
106 | #define CC_DSTIA (1 << 24) | |
107 | #define CC_SRCBRSTLEN_SHFT 4 | |
108 | #define CC_DSTBRSTLEN_SHFT 18 | |
109 | #define CC_SRCBRSTSIZE_SHFT 1 | |
110 | #define CC_DSTBRSTSIZE_SHFT 15 | |
111 | #define CC_SRCCCTRL_SHFT 11 | |
112 | #define CC_SRCCCTRL_MASK 0x7 | |
113 | #define CC_DSTCCTRL_SHFT 25 | |
114 | #define CC_DRCCCTRL_MASK 0x7 | |
115 | #define CC_SWAP_SHFT 28 | |
116 | ||
117 | #define _LC0 0x40c | |
118 | #define LC0(n) (_LC0 + (n)*0x20) | |
119 | ||
120 | #define _LC1 0x410 | |
121 | #define LC1(n) (_LC1 + (n)*0x20) | |
122 | ||
123 | #define DBGSTATUS 0xd00 | |
124 | #define DBG_BUSY (1 << 0) | |
125 | ||
126 | #define DBGCMD 0xd04 | |
127 | #define DBGINST0 0xd08 | |
128 | #define DBGINST1 0xd0c | |
129 | ||
130 | #define CR0 0xe00 | |
131 | #define CR1 0xe04 | |
132 | #define CR2 0xe08 | |
133 | #define CR3 0xe0c | |
134 | #define CR4 0xe10 | |
135 | #define CRD 0xe14 | |
136 | ||
137 | #define PERIPH_ID 0xfe0 | |
3ecf51a4 BK |
138 | #define PERIPH_REV_SHIFT 20 |
139 | #define PERIPH_REV_MASK 0xf | |
140 | #define PERIPH_REV_R0P0 0 | |
141 | #define PERIPH_REV_R1P0 1 | |
142 | #define PERIPH_REV_R1P1 2 | |
b7d861d9 BK |
143 | |
144 | #define CR0_PERIPH_REQ_SET (1 << 0) | |
145 | #define CR0_BOOT_EN_SET (1 << 1) | |
146 | #define CR0_BOOT_MAN_NS (1 << 2) | |
147 | #define CR0_NUM_CHANS_SHIFT 4 | |
148 | #define CR0_NUM_CHANS_MASK 0x7 | |
149 | #define CR0_NUM_PERIPH_SHIFT 12 | |
150 | #define CR0_NUM_PERIPH_MASK 0x1f | |
151 | #define CR0_NUM_EVENTS_SHIFT 17 | |
152 | #define CR0_NUM_EVENTS_MASK 0x1f | |
153 | ||
154 | #define CR1_ICACHE_LEN_SHIFT 0 | |
155 | #define CR1_ICACHE_LEN_MASK 0x7 | |
156 | #define CR1_NUM_ICACHELINES_SHIFT 4 | |
157 | #define CR1_NUM_ICACHELINES_MASK 0xf | |
158 | ||
159 | #define CRD_DATA_WIDTH_SHIFT 0 | |
160 | #define CRD_DATA_WIDTH_MASK 0x7 | |
161 | #define CRD_WR_CAP_SHIFT 4 | |
162 | #define CRD_WR_CAP_MASK 0x7 | |
163 | #define CRD_WR_Q_DEP_SHIFT 8 | |
164 | #define CRD_WR_Q_DEP_MASK 0xf | |
165 | #define CRD_RD_CAP_SHIFT 12 | |
166 | #define CRD_RD_CAP_MASK 0x7 | |
167 | #define CRD_RD_Q_DEP_SHIFT 16 | |
168 | #define CRD_RD_Q_DEP_MASK 0xf | |
169 | #define CRD_DATA_BUFF_SHIFT 20 | |
170 | #define CRD_DATA_BUFF_MASK 0x3ff | |
171 | ||
172 | #define PART 0x330 | |
173 | #define DESIGNER 0x41 | |
174 | #define REVISION 0x0 | |
175 | #define INTEG_CFG 0x0 | |
176 | #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) | |
177 | ||
b7d861d9 BK |
178 | #define PL330_STATE_STOPPED (1 << 0) |
179 | #define PL330_STATE_EXECUTING (1 << 1) | |
180 | #define PL330_STATE_WFE (1 << 2) | |
181 | #define PL330_STATE_FAULTING (1 << 3) | |
182 | #define PL330_STATE_COMPLETING (1 << 4) | |
183 | #define PL330_STATE_WFP (1 << 5) | |
184 | #define PL330_STATE_KILLING (1 << 6) | |
185 | #define PL330_STATE_FAULT_COMPLETING (1 << 7) | |
186 | #define PL330_STATE_CACHEMISS (1 << 8) | |
187 | #define PL330_STATE_UPDTPC (1 << 9) | |
188 | #define PL330_STATE_ATBARRIER (1 << 10) | |
189 | #define PL330_STATE_QUEUEBUSY (1 << 11) | |
190 | #define PL330_STATE_INVALID (1 << 15) | |
191 | ||
192 | #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | |
193 | | PL330_STATE_WFE | PL330_STATE_FAULTING) | |
194 | ||
195 | #define CMD_DMAADDH 0x54 | |
196 | #define CMD_DMAEND 0x00 | |
197 | #define CMD_DMAFLUSHP 0x35 | |
198 | #define CMD_DMAGO 0xa0 | |
199 | #define CMD_DMALD 0x04 | |
200 | #define CMD_DMALDP 0x25 | |
201 | #define CMD_DMALP 0x20 | |
202 | #define CMD_DMALPEND 0x28 | |
203 | #define CMD_DMAKILL 0x01 | |
204 | #define CMD_DMAMOV 0xbc | |
205 | #define CMD_DMANOP 0x18 | |
206 | #define CMD_DMARMB 0x12 | |
207 | #define CMD_DMASEV 0x34 | |
208 | #define CMD_DMAST 0x08 | |
209 | #define CMD_DMASTP 0x29 | |
210 | #define CMD_DMASTZ 0x0c | |
211 | #define CMD_DMAWFE 0x36 | |
212 | #define CMD_DMAWFP 0x30 | |
213 | #define CMD_DMAWMB 0x13 | |
214 | ||
215 | #define SZ_DMAADDH 3 | |
216 | #define SZ_DMAEND 1 | |
217 | #define SZ_DMAFLUSHP 2 | |
218 | #define SZ_DMALD 1 | |
219 | #define SZ_DMALDP 2 | |
220 | #define SZ_DMALP 2 | |
221 | #define SZ_DMALPEND 2 | |
222 | #define SZ_DMAKILL 1 | |
223 | #define SZ_DMAMOV 6 | |
224 | #define SZ_DMANOP 1 | |
225 | #define SZ_DMARMB 1 | |
226 | #define SZ_DMASEV 2 | |
227 | #define SZ_DMAST 1 | |
228 | #define SZ_DMASTP 2 | |
229 | #define SZ_DMASTZ 1 | |
230 | #define SZ_DMAWFE 2 | |
231 | #define SZ_DMAWFP 2 | |
232 | #define SZ_DMAWMB 1 | |
233 | #define SZ_DMAGO 6 | |
234 | ||
235 | #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) | |
236 | #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) | |
237 | ||
238 | #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) | |
239 | #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) | |
240 | ||
241 | /* | |
242 | * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req | |
243 | * at 1byte/burst for P<->M and M<->M respectively. | |
244 | * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req | |
245 | * should be enough for P<->M and M<->M respectively. | |
246 | */ | |
247 | #define MCODE_BUFF_PER_REQ 256 | |
248 | ||
b7d861d9 BK |
249 | /* Use this _only_ to wait on transient states */ |
250 | #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); | |
251 | ||
252 | #ifdef PL330_DEBUG_MCGEN | |
253 | static unsigned cmd_line; | |
254 | #define PL330_DBGCMD_DUMP(off, x...) do { \ | |
255 | printk("%x:", cmd_line); \ | |
256 | printk(x); \ | |
257 | cmd_line += off; \ | |
258 | } while (0) | |
259 | #define PL330_DBGMC_START(addr) (cmd_line = addr) | |
260 | #else | |
261 | #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) | |
262 | #define PL330_DBGMC_START(addr) do {} while (0) | |
263 | #endif | |
264 | ||
265 | /* The number of default descriptors */ | |
d2ebfb33 | 266 | |
b3040e40 JB |
267 | #define NR_DEFAULT_DESC 16 |
268 | ||
ae43b328 KK |
269 | /* Delay for runtime PM autosuspend, ms */ |
270 | #define PL330_AUTOSUSPEND_DELAY 20 | |
271 | ||
b7d861d9 BK |
272 | /* Populated by the PL330 core driver for DMA API driver's info */ |
273 | struct pl330_config { | |
274 | u32 periph_id; | |
b7d861d9 BK |
275 | #define DMAC_MODE_NS (1 << 0) |
276 | unsigned int mode; | |
277 | unsigned int data_bus_width:10; /* In number of bits */ | |
1f0a5cbf | 278 | unsigned int data_buf_dep:11; |
b7d861d9 BK |
279 | unsigned int num_chan:4; |
280 | unsigned int num_peri:6; | |
281 | u32 peri_ns; | |
282 | unsigned int num_events:6; | |
283 | u32 irq_ns; | |
284 | }; | |
285 | ||
b7d861d9 BK |
286 | /** |
287 | * Request Configuration. | |
288 | * The PL330 core does not modify this and uses the last | |
289 | * working configuration if the request doesn't provide any. | |
290 | * | |
291 | * The Client may want to provide this info only for the | |
292 | * first request and a request with new settings. | |
293 | */ | |
294 | struct pl330_reqcfg { | |
295 | /* Address Incrementing */ | |
296 | unsigned dst_inc:1; | |
297 | unsigned src_inc:1; | |
298 | ||
299 | /* | |
300 | * For now, the SRC & DST protection levels | |
301 | * and burst size/length are assumed same. | |
302 | */ | |
303 | bool nonsecure; | |
304 | bool privileged; | |
305 | bool insnaccess; | |
306 | unsigned brst_len:5; | |
307 | unsigned brst_size:3; /* in power of 2 */ | |
308 | ||
f0564c7e LPC |
309 | enum pl330_cachectrl dcctl; |
310 | enum pl330_cachectrl scctl; | |
b7d861d9 | 311 | enum pl330_byteswap swap; |
3ecf51a4 | 312 | struct pl330_config *pcfg; |
b7d861d9 BK |
313 | }; |
314 | ||
315 | /* | |
316 | * One cycle of DMAC operation. | |
317 | * There may be more than one xfer in a request. | |
318 | */ | |
319 | struct pl330_xfer { | |
320 | u32 src_addr; | |
321 | u32 dst_addr; | |
322 | /* Size to xfer */ | |
323 | u32 bytes; | |
b7d861d9 BK |
324 | }; |
325 | ||
326 | /* The xfer callbacks are made with one of these arguments. */ | |
327 | enum pl330_op_err { | |
328 | /* The all xfers in the request were success. */ | |
329 | PL330_ERR_NONE, | |
330 | /* If req aborted due to global error. */ | |
331 | PL330_ERR_ABORT, | |
332 | /* If req failed due to problem with Channel. */ | |
333 | PL330_ERR_FAIL, | |
334 | }; | |
335 | ||
b7d861d9 BK |
336 | enum dmamov_dst { |
337 | SAR = 0, | |
338 | CCR, | |
339 | DAR, | |
340 | }; | |
341 | ||
342 | enum pl330_dst { | |
343 | SRC = 0, | |
344 | DST, | |
345 | }; | |
346 | ||
347 | enum pl330_cond { | |
348 | SINGLE, | |
349 | BURST, | |
350 | ALWAYS, | |
351 | }; | |
352 | ||
9dc5a315 LPC |
353 | struct dma_pl330_desc; |
354 | ||
b7d861d9 BK |
355 | struct _pl330_req { |
356 | u32 mc_bus; | |
357 | void *mc_cpu; | |
9dc5a315 | 358 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
359 | }; |
360 | ||
361 | /* ToBeDone for tasklet */ | |
362 | struct _pl330_tbd { | |
363 | bool reset_dmac; | |
364 | bool reset_mngr; | |
365 | u8 reset_chan; | |
366 | }; | |
367 | ||
368 | /* A DMAC Thread */ | |
369 | struct pl330_thread { | |
370 | u8 id; | |
371 | int ev; | |
372 | /* If the channel is not yet acquired by any client */ | |
373 | bool free; | |
374 | /* Parent DMAC */ | |
375 | struct pl330_dmac *dmac; | |
376 | /* Only two at a time */ | |
377 | struct _pl330_req req[2]; | |
378 | /* Index of the last enqueued request */ | |
379 | unsigned lstenq; | |
380 | /* Index of the last submitted request or -1 if the DMA is stopped */ | |
381 | int req_running; | |
382 | }; | |
383 | ||
384 | enum pl330_dmac_state { | |
385 | UNINIT, | |
386 | INIT, | |
387 | DYING, | |
388 | }; | |
389 | ||
b3040e40 JB |
390 | enum desc_status { |
391 | /* In the DMAC pool */ | |
392 | FREE, | |
393 | /* | |
d73111c6 | 394 | * Allocated to some channel during prep_xxx |
b3040e40 JB |
395 | * Also may be sitting on the work_list. |
396 | */ | |
397 | PREP, | |
398 | /* | |
399 | * Sitting on the work_list and already submitted | |
400 | * to the PL330 core. Not more than two descriptors | |
401 | * of a channel can be BUSY at any time. | |
402 | */ | |
403 | BUSY, | |
404 | /* | |
405 | * Sitting on the channel work_list but xfer done | |
406 | * by PL330 core | |
407 | */ | |
408 | DONE, | |
409 | }; | |
410 | ||
411 | struct dma_pl330_chan { | |
412 | /* Schedule desc completion */ | |
413 | struct tasklet_struct task; | |
414 | ||
415 | /* DMA-Engine Channel */ | |
416 | struct dma_chan chan; | |
417 | ||
04abf5da LPC |
418 | /* List of submitted descriptors */ |
419 | struct list_head submitted_list; | |
420 | /* List of issued descriptors */ | |
b3040e40 | 421 | struct list_head work_list; |
39ff8613 LPC |
422 | /* List of completed descriptors */ |
423 | struct list_head completed_list; | |
b3040e40 JB |
424 | |
425 | /* Pointer to the DMAC that manages this channel, | |
426 | * NULL if the channel is available to be acquired. | |
427 | * As the parent, this DMAC also provides descriptors | |
428 | * to the channel. | |
429 | */ | |
f6f2421c | 430 | struct pl330_dmac *dmac; |
b3040e40 JB |
431 | |
432 | /* To protect channel manipulation */ | |
433 | spinlock_t lock; | |
434 | ||
65ad6060 LPC |
435 | /* |
436 | * Hardware channel thread of PL330 DMAC. NULL if the channel is | |
437 | * available. | |
b3040e40 | 438 | */ |
65ad6060 | 439 | struct pl330_thread *thread; |
1b9bb715 BK |
440 | |
441 | /* For D-to-M and M-to-D channels */ | |
442 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 443 | int burst_len; /* the number of burst */ |
4d6d74e2 RM |
444 | phys_addr_t fifo_addr; |
445 | /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */ | |
446 | dma_addr_t fifo_dma; | |
447 | enum dma_data_direction dir; | |
445897cb | 448 | struct dma_slave_config slave_config; |
42bc9cf4 BK |
449 | |
450 | /* for cyclic capability */ | |
451 | bool cyclic; | |
5c9e6c2b MS |
452 | |
453 | /* for runtime pm tracking */ | |
454 | bool active; | |
b3040e40 JB |
455 | }; |
456 | ||
f6f2421c | 457 | struct pl330_dmac { |
b3040e40 JB |
458 | /* DMA-Engine Device */ |
459 | struct dma_device ddma; | |
460 | ||
b714b84e LPC |
461 | /* Holds info about sg limitations */ |
462 | struct device_dma_parameters dma_parms; | |
463 | ||
b3040e40 JB |
464 | /* Pool of descriptors available for the DMAC's channels */ |
465 | struct list_head desc_pool; | |
466 | /* To protect desc_pool manipulation */ | |
467 | spinlock_t pool_lock; | |
468 | ||
f6f2421c LPC |
469 | /* Size of MicroCode buffers for each channel. */ |
470 | unsigned mcbufsz; | |
471 | /* ioremap'ed address of PL330 registers. */ | |
472 | void __iomem *base; | |
473 | /* Populated by the PL330 core driver during pl330_add */ | |
474 | struct pl330_config pcfg; | |
475 | ||
476 | spinlock_t lock; | |
477 | /* Maximum possible events/irqs */ | |
478 | int events[32]; | |
479 | /* BUS address of MicroCode buffer */ | |
480 | dma_addr_t mcode_bus; | |
481 | /* CPU address of MicroCode buffer */ | |
482 | void *mcode_cpu; | |
483 | /* List of all Channel threads */ | |
484 | struct pl330_thread *channels; | |
485 | /* Pointer to the MANAGER thread */ | |
486 | struct pl330_thread *manager; | |
487 | /* To handle bad news in interrupt */ | |
488 | struct tasklet_struct tasks; | |
489 | struct _pl330_tbd dmac_tbd; | |
490 | /* State of DMAC operation */ | |
491 | enum pl330_dmac_state state; | |
492 | /* Holds list of reqs with due callbacks */ | |
493 | struct list_head req_done; | |
494 | ||
b3040e40 | 495 | /* Peripheral channels connected to this DMAC */ |
70cbb163 | 496 | unsigned int num_peripherals; |
4e0e6109 | 497 | struct dma_pl330_chan *peripherals; /* keep at end */ |
271e1b86 AK |
498 | int quirks; |
499 | }; | |
500 | ||
501 | static struct pl330_of_quirks { | |
502 | char *quirk; | |
503 | int id; | |
504 | } of_quirks[] = { | |
505 | { | |
506 | .quirk = "arm,pl330-broken-no-flushp", | |
507 | .id = PL330_QUIRK_BROKEN_NO_FLUSHP, | |
508 | } | |
b3040e40 JB |
509 | }; |
510 | ||
511 | struct dma_pl330_desc { | |
512 | /* To attach to a queue as child */ | |
513 | struct list_head node; | |
514 | ||
515 | /* Descriptor for the DMA Engine API */ | |
516 | struct dma_async_tx_descriptor txd; | |
517 | ||
518 | /* Xfer for PL330 core */ | |
519 | struct pl330_xfer px; | |
520 | ||
521 | struct pl330_reqcfg rqcfg; | |
b3040e40 JB |
522 | |
523 | enum desc_status status; | |
524 | ||
aee4d1fa RB |
525 | int bytes_requested; |
526 | bool last; | |
527 | ||
b3040e40 JB |
528 | /* The channel which currently holds this desc */ |
529 | struct dma_pl330_chan *pchan; | |
9dc5a315 LPC |
530 | |
531 | enum dma_transfer_direction rqtype; | |
532 | /* Index of peripheral for the xfer. */ | |
533 | unsigned peri:5; | |
534 | /* Hook to attach to DMAC's list of reqs with due callback */ | |
535 | struct list_head rqd; | |
536 | }; | |
537 | ||
538 | struct _xfer_spec { | |
539 | u32 ccr; | |
540 | struct dma_pl330_desc *desc; | |
b3040e40 JB |
541 | }; |
542 | ||
445897cb VK |
543 | static int pl330_config_write(struct dma_chan *chan, |
544 | struct dma_slave_config *slave_config, | |
545 | enum dma_transfer_direction direction); | |
546 | ||
b7d861d9 BK |
547 | static inline bool _queue_full(struct pl330_thread *thrd) |
548 | { | |
8ed30a14 | 549 | return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; |
b7d861d9 BK |
550 | } |
551 | ||
552 | static inline bool is_manager(struct pl330_thread *thrd) | |
553 | { | |
fbbcd9be | 554 | return thrd->dmac->manager == thrd; |
b7d861d9 BK |
555 | } |
556 | ||
557 | /* If manager of the thread is in Non-Secure mode */ | |
558 | static inline bool _manager_ns(struct pl330_thread *thrd) | |
559 | { | |
f6f2421c | 560 | return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; |
b7d861d9 BK |
561 | } |
562 | ||
3ecf51a4 BK |
563 | static inline u32 get_revision(u32 periph_id) |
564 | { | |
565 | return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; | |
566 | } | |
567 | ||
b7d861d9 BK |
568 | static inline u32 _emit_END(unsigned dry_run, u8 buf[]) |
569 | { | |
570 | if (dry_run) | |
571 | return SZ_DMAEND; | |
572 | ||
573 | buf[0] = CMD_DMAEND; | |
574 | ||
575 | PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); | |
576 | ||
577 | return SZ_DMAEND; | |
578 | } | |
579 | ||
580 | static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) | |
581 | { | |
582 | if (dry_run) | |
583 | return SZ_DMAFLUSHP; | |
584 | ||
585 | buf[0] = CMD_DMAFLUSHP; | |
586 | ||
587 | peri &= 0x1f; | |
588 | peri <<= 3; | |
589 | buf[1] = peri; | |
590 | ||
591 | PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); | |
592 | ||
593 | return SZ_DMAFLUSHP; | |
594 | } | |
595 | ||
596 | static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
597 | { | |
598 | if (dry_run) | |
599 | return SZ_DMALD; | |
600 | ||
601 | buf[0] = CMD_DMALD; | |
602 | ||
603 | if (cond == SINGLE) | |
604 | buf[0] |= (0 << 1) | (1 << 0); | |
605 | else if (cond == BURST) | |
606 | buf[0] |= (1 << 1) | (1 << 0); | |
607 | ||
608 | PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", | |
609 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
610 | ||
611 | return SZ_DMALD; | |
612 | } | |
613 | ||
614 | static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], | |
615 | enum pl330_cond cond, u8 peri) | |
616 | { | |
617 | if (dry_run) | |
618 | return SZ_DMALDP; | |
619 | ||
620 | buf[0] = CMD_DMALDP; | |
621 | ||
622 | if (cond == BURST) | |
623 | buf[0] |= (1 << 1); | |
624 | ||
625 | peri &= 0x1f; | |
626 | peri <<= 3; | |
627 | buf[1] = peri; | |
628 | ||
629 | PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", | |
630 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
631 | ||
632 | return SZ_DMALDP; | |
633 | } | |
634 | ||
635 | static inline u32 _emit_LP(unsigned dry_run, u8 buf[], | |
636 | unsigned loop, u8 cnt) | |
637 | { | |
638 | if (dry_run) | |
639 | return SZ_DMALP; | |
640 | ||
641 | buf[0] = CMD_DMALP; | |
642 | ||
643 | if (loop) | |
644 | buf[0] |= (1 << 1); | |
645 | ||
646 | cnt--; /* DMAC increments by 1 internally */ | |
647 | buf[1] = cnt; | |
648 | ||
649 | PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); | |
650 | ||
651 | return SZ_DMALP; | |
652 | } | |
653 | ||
654 | struct _arg_LPEND { | |
655 | enum pl330_cond cond; | |
656 | bool forever; | |
657 | unsigned loop; | |
658 | u8 bjump; | |
659 | }; | |
660 | ||
661 | static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], | |
662 | const struct _arg_LPEND *arg) | |
663 | { | |
664 | enum pl330_cond cond = arg->cond; | |
665 | bool forever = arg->forever; | |
666 | unsigned loop = arg->loop; | |
667 | u8 bjump = arg->bjump; | |
668 | ||
669 | if (dry_run) | |
670 | return SZ_DMALPEND; | |
671 | ||
672 | buf[0] = CMD_DMALPEND; | |
673 | ||
674 | if (loop) | |
675 | buf[0] |= (1 << 2); | |
676 | ||
677 | if (!forever) | |
678 | buf[0] |= (1 << 4); | |
679 | ||
680 | if (cond == SINGLE) | |
681 | buf[0] |= (0 << 1) | (1 << 0); | |
682 | else if (cond == BURST) | |
683 | buf[0] |= (1 << 1) | (1 << 0); | |
684 | ||
685 | buf[1] = bjump; | |
686 | ||
687 | PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", | |
688 | forever ? "FE" : "END", | |
689 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), | |
690 | loop ? '1' : '0', | |
691 | bjump); | |
692 | ||
693 | return SZ_DMALPEND; | |
694 | } | |
695 | ||
696 | static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) | |
697 | { | |
698 | if (dry_run) | |
699 | return SZ_DMAKILL; | |
700 | ||
701 | buf[0] = CMD_DMAKILL; | |
702 | ||
703 | return SZ_DMAKILL; | |
704 | } | |
705 | ||
706 | static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], | |
707 | enum dmamov_dst dst, u32 val) | |
708 | { | |
709 | if (dry_run) | |
710 | return SZ_DMAMOV; | |
711 | ||
712 | buf[0] = CMD_DMAMOV; | |
713 | buf[1] = dst; | |
d07c9e1e VM |
714 | buf[2] = val; |
715 | buf[3] = val >> 8; | |
716 | buf[4] = val >> 16; | |
717 | buf[5] = val >> 24; | |
b7d861d9 BK |
718 | |
719 | PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", | |
720 | dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); | |
721 | ||
722 | return SZ_DMAMOV; | |
723 | } | |
724 | ||
b7d861d9 BK |
725 | static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) |
726 | { | |
727 | if (dry_run) | |
728 | return SZ_DMARMB; | |
729 | ||
730 | buf[0] = CMD_DMARMB; | |
731 | ||
732 | PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); | |
733 | ||
734 | return SZ_DMARMB; | |
735 | } | |
736 | ||
737 | static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) | |
738 | { | |
739 | if (dry_run) | |
740 | return SZ_DMASEV; | |
741 | ||
742 | buf[0] = CMD_DMASEV; | |
743 | ||
744 | ev &= 0x1f; | |
745 | ev <<= 3; | |
746 | buf[1] = ev; | |
747 | ||
748 | PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); | |
749 | ||
750 | return SZ_DMASEV; | |
751 | } | |
752 | ||
753 | static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
754 | { | |
755 | if (dry_run) | |
756 | return SZ_DMAST; | |
757 | ||
758 | buf[0] = CMD_DMAST; | |
759 | ||
760 | if (cond == SINGLE) | |
761 | buf[0] |= (0 << 1) | (1 << 0); | |
762 | else if (cond == BURST) | |
763 | buf[0] |= (1 << 1) | (1 << 0); | |
764 | ||
765 | PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", | |
766 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
767 | ||
768 | return SZ_DMAST; | |
769 | } | |
770 | ||
771 | static inline u32 _emit_STP(unsigned dry_run, u8 buf[], | |
772 | enum pl330_cond cond, u8 peri) | |
773 | { | |
774 | if (dry_run) | |
775 | return SZ_DMASTP; | |
776 | ||
777 | buf[0] = CMD_DMASTP; | |
778 | ||
779 | if (cond == BURST) | |
780 | buf[0] |= (1 << 1); | |
781 | ||
782 | peri &= 0x1f; | |
783 | peri <<= 3; | |
784 | buf[1] = peri; | |
785 | ||
786 | PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", | |
787 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
788 | ||
789 | return SZ_DMASTP; | |
790 | } | |
791 | ||
b7d861d9 BK |
792 | static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], |
793 | enum pl330_cond cond, u8 peri) | |
794 | { | |
795 | if (dry_run) | |
796 | return SZ_DMAWFP; | |
797 | ||
798 | buf[0] = CMD_DMAWFP; | |
799 | ||
800 | if (cond == SINGLE) | |
801 | buf[0] |= (0 << 1) | (0 << 0); | |
802 | else if (cond == BURST) | |
803 | buf[0] |= (1 << 1) | (0 << 0); | |
804 | else | |
805 | buf[0] |= (0 << 1) | (1 << 0); | |
806 | ||
807 | peri &= 0x1f; | |
808 | peri <<= 3; | |
809 | buf[1] = peri; | |
810 | ||
811 | PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", | |
812 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); | |
813 | ||
814 | return SZ_DMAWFP; | |
815 | } | |
816 | ||
817 | static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) | |
818 | { | |
819 | if (dry_run) | |
820 | return SZ_DMAWMB; | |
821 | ||
822 | buf[0] = CMD_DMAWMB; | |
823 | ||
824 | PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); | |
825 | ||
826 | return SZ_DMAWMB; | |
827 | } | |
828 | ||
829 | struct _arg_GO { | |
830 | u8 chan; | |
831 | u32 addr; | |
832 | unsigned ns; | |
833 | }; | |
834 | ||
835 | static inline u32 _emit_GO(unsigned dry_run, u8 buf[], | |
836 | const struct _arg_GO *arg) | |
837 | { | |
838 | u8 chan = arg->chan; | |
839 | u32 addr = arg->addr; | |
840 | unsigned ns = arg->ns; | |
841 | ||
842 | if (dry_run) | |
843 | return SZ_DMAGO; | |
844 | ||
845 | buf[0] = CMD_DMAGO; | |
846 | buf[0] |= (ns << 1); | |
b7d861d9 | 847 | buf[1] = chan & 0x7; |
d07c9e1e VM |
848 | buf[2] = addr; |
849 | buf[3] = addr >> 8; | |
850 | buf[4] = addr >> 16; | |
851 | buf[5] = addr >> 24; | |
b7d861d9 BK |
852 | |
853 | return SZ_DMAGO; | |
854 | } | |
855 | ||
856 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
857 | ||
858 | /* Returns Time-Out */ | |
859 | static bool _until_dmac_idle(struct pl330_thread *thrd) | |
860 | { | |
f6f2421c | 861 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
862 | unsigned long loops = msecs_to_loops(5); |
863 | ||
864 | do { | |
865 | /* Until Manager is Idle */ | |
866 | if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) | |
867 | break; | |
868 | ||
869 | cpu_relax(); | |
870 | } while (--loops); | |
871 | ||
872 | if (!loops) | |
873 | return true; | |
874 | ||
875 | return false; | |
876 | } | |
877 | ||
878 | static inline void _execute_DBGINSN(struct pl330_thread *thrd, | |
879 | u8 insn[], bool as_manager) | |
880 | { | |
f6f2421c | 881 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
882 | u32 val; |
883 | ||
884 | val = (insn[0] << 16) | (insn[1] << 24); | |
885 | if (!as_manager) { | |
886 | val |= (1 << 0); | |
887 | val |= (thrd->id << 8); /* Channel Number */ | |
888 | } | |
889 | writel(val, regs + DBGINST0); | |
890 | ||
3a2307f7 | 891 | val = le32_to_cpu(*((__le32 *)&insn[2])); |
b7d861d9 BK |
892 | writel(val, regs + DBGINST1); |
893 | ||
894 | /* If timed out due to halted state-machine */ | |
895 | if (_until_dmac_idle(thrd)) { | |
f6f2421c | 896 | dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); |
b7d861d9 BK |
897 | return; |
898 | } | |
899 | ||
900 | /* Get going */ | |
901 | writel(0, regs + DBGCMD); | |
902 | } | |
903 | ||
b7d861d9 BK |
904 | static inline u32 _state(struct pl330_thread *thrd) |
905 | { | |
f6f2421c | 906 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
907 | u32 val; |
908 | ||
909 | if (is_manager(thrd)) | |
910 | val = readl(regs + DS) & 0xf; | |
911 | else | |
912 | val = readl(regs + CS(thrd->id)) & 0xf; | |
913 | ||
914 | switch (val) { | |
915 | case DS_ST_STOP: | |
916 | return PL330_STATE_STOPPED; | |
917 | case DS_ST_EXEC: | |
918 | return PL330_STATE_EXECUTING; | |
919 | case DS_ST_CMISS: | |
920 | return PL330_STATE_CACHEMISS; | |
921 | case DS_ST_UPDTPC: | |
922 | return PL330_STATE_UPDTPC; | |
923 | case DS_ST_WFE: | |
924 | return PL330_STATE_WFE; | |
925 | case DS_ST_FAULT: | |
926 | return PL330_STATE_FAULTING; | |
927 | case DS_ST_ATBRR: | |
928 | if (is_manager(thrd)) | |
929 | return PL330_STATE_INVALID; | |
930 | else | |
931 | return PL330_STATE_ATBARRIER; | |
932 | case DS_ST_QBUSY: | |
933 | if (is_manager(thrd)) | |
934 | return PL330_STATE_INVALID; | |
935 | else | |
936 | return PL330_STATE_QUEUEBUSY; | |
937 | case DS_ST_WFP: | |
938 | if (is_manager(thrd)) | |
939 | return PL330_STATE_INVALID; | |
940 | else | |
941 | return PL330_STATE_WFP; | |
942 | case DS_ST_KILL: | |
943 | if (is_manager(thrd)) | |
944 | return PL330_STATE_INVALID; | |
945 | else | |
946 | return PL330_STATE_KILLING; | |
947 | case DS_ST_CMPLT: | |
948 | if (is_manager(thrd)) | |
949 | return PL330_STATE_INVALID; | |
950 | else | |
951 | return PL330_STATE_COMPLETING; | |
952 | case DS_ST_FLTCMP: | |
953 | if (is_manager(thrd)) | |
954 | return PL330_STATE_INVALID; | |
955 | else | |
956 | return PL330_STATE_FAULT_COMPLETING; | |
957 | default: | |
958 | return PL330_STATE_INVALID; | |
959 | } | |
960 | } | |
961 | ||
962 | static void _stop(struct pl330_thread *thrd) | |
963 | { | |
f6f2421c | 964 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 | 965 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; |
2da254cc | 966 | u32 inten = readl(regs + INTEN); |
b7d861d9 BK |
967 | |
968 | if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) | |
969 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
970 | ||
971 | /* Return if nothing needs to be done */ | |
972 | if (_state(thrd) == PL330_STATE_COMPLETING | |
973 | || _state(thrd) == PL330_STATE_KILLING | |
974 | || _state(thrd) == PL330_STATE_STOPPED) | |
975 | return; | |
976 | ||
977 | _emit_KILL(0, insn); | |
978 | ||
b7d861d9 | 979 | _execute_DBGINSN(thrd, insn, is_manager(thrd)); |
2da254cc SZ |
980 | |
981 | /* clear the event */ | |
982 | if (inten & (1 << thrd->ev)) | |
983 | writel(1 << thrd->ev, regs + INTCLR); | |
984 | /* Stop generating interrupts for SEV */ | |
985 | writel(inten & ~(1 << thrd->ev), regs + INTEN); | |
b7d861d9 BK |
986 | } |
987 | ||
988 | /* Start doing req 'idx' of thread 'thrd' */ | |
989 | static bool _trigger(struct pl330_thread *thrd) | |
990 | { | |
f6f2421c | 991 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 | 992 | struct _pl330_req *req; |
9dc5a315 | 993 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
994 | struct _arg_GO go; |
995 | unsigned ns; | |
996 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; | |
997 | int idx; | |
998 | ||
999 | /* Return if already ACTIVE */ | |
1000 | if (_state(thrd) != PL330_STATE_STOPPED) | |
1001 | return true; | |
1002 | ||
1003 | idx = 1 - thrd->lstenq; | |
8ed30a14 | 1004 | if (thrd->req[idx].desc != NULL) { |
b7d861d9 | 1005 | req = &thrd->req[idx]; |
8ed30a14 | 1006 | } else { |
b7d861d9 | 1007 | idx = thrd->lstenq; |
8ed30a14 | 1008 | if (thrd->req[idx].desc != NULL) |
b7d861d9 BK |
1009 | req = &thrd->req[idx]; |
1010 | else | |
1011 | req = NULL; | |
1012 | } | |
1013 | ||
1014 | /* Return if no request */ | |
8ed30a14 | 1015 | if (!req) |
b7d861d9 BK |
1016 | return true; |
1017 | ||
0091b9d6 AK |
1018 | /* Return if req is running */ |
1019 | if (idx == thrd->req_running) | |
1020 | return true; | |
1021 | ||
9dc5a315 | 1022 | desc = req->desc; |
b7d861d9 | 1023 | |
9dc5a315 | 1024 | ns = desc->rqcfg.nonsecure ? 1 : 0; |
b7d861d9 BK |
1025 | |
1026 | /* See 'Abort Sources' point-4 at Page 2-25 */ | |
1027 | if (_manager_ns(thrd) && !ns) | |
f6f2421c | 1028 | dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", |
b7d861d9 BK |
1029 | __func__, __LINE__); |
1030 | ||
1031 | go.chan = thrd->id; | |
1032 | go.addr = req->mc_bus; | |
1033 | go.ns = ns; | |
1034 | _emit_GO(0, insn, &go); | |
1035 | ||
1036 | /* Set to generate interrupts for SEV */ | |
1037 | writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); | |
1038 | ||
1039 | /* Only manager can execute GO */ | |
1040 | _execute_DBGINSN(thrd, insn, true); | |
1041 | ||
1042 | thrd->req_running = idx; | |
1043 | ||
1044 | return true; | |
1045 | } | |
1046 | ||
1047 | static bool _start(struct pl330_thread *thrd) | |
1048 | { | |
1049 | switch (_state(thrd)) { | |
1050 | case PL330_STATE_FAULT_COMPLETING: | |
1051 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1052 | ||
1053 | if (_state(thrd) == PL330_STATE_KILLING) | |
1054 | UNTIL(thrd, PL330_STATE_STOPPED) | |
bbcb8755 | 1055 | /* fall through */ |
b7d861d9 BK |
1056 | |
1057 | case PL330_STATE_FAULTING: | |
1058 | _stop(thrd); | |
bbcb8755 | 1059 | /* fall through */ |
b7d861d9 BK |
1060 | |
1061 | case PL330_STATE_KILLING: | |
1062 | case PL330_STATE_COMPLETING: | |
1063 | UNTIL(thrd, PL330_STATE_STOPPED) | |
bbcb8755 | 1064 | /* fall through */ |
b7d861d9 BK |
1065 | |
1066 | case PL330_STATE_STOPPED: | |
1067 | return _trigger(thrd); | |
1068 | ||
1069 | case PL330_STATE_WFP: | |
1070 | case PL330_STATE_QUEUEBUSY: | |
1071 | case PL330_STATE_ATBARRIER: | |
1072 | case PL330_STATE_UPDTPC: | |
1073 | case PL330_STATE_CACHEMISS: | |
1074 | case PL330_STATE_EXECUTING: | |
1075 | return true; | |
1076 | ||
1077 | case PL330_STATE_WFE: /* For RESUME, nothing yet */ | |
1078 | default: | |
1079 | return false; | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], | |
1084 | const struct _xfer_spec *pxs, int cyc) | |
1085 | { | |
1086 | int off = 0; | |
9dc5a315 | 1087 | struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; |
b7d861d9 | 1088 | |
3ecf51a4 BK |
1089 | /* check lock-up free version */ |
1090 | if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { | |
1091 | while (cyc--) { | |
1092 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1093 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1094 | } | |
1095 | } else { | |
1096 | while (cyc--) { | |
1097 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1098 | off += _emit_RMB(dry_run, &buf[off]); | |
1099 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1100 | off += _emit_WMB(dry_run, &buf[off]); | |
1101 | } | |
b7d861d9 BK |
1102 | } |
1103 | ||
1104 | return off; | |
1105 | } | |
1106 | ||
1d48745b FMH |
1107 | static u32 _emit_load(unsigned int dry_run, u8 buf[], |
1108 | enum pl330_cond cond, enum dma_transfer_direction direction, | |
1109 | u8 peri) | |
b7d861d9 BK |
1110 | { |
1111 | int off = 0; | |
848e9776 | 1112 | |
1d48745b FMH |
1113 | switch (direction) { |
1114 | case DMA_MEM_TO_MEM: | |
1115 | /* fall through */ | |
1116 | case DMA_MEM_TO_DEV: | |
1117 | off += _emit_LD(dry_run, &buf[off], cond); | |
1118 | break; | |
b7d861d9 | 1119 | |
1d48745b FMH |
1120 | case DMA_DEV_TO_MEM: |
1121 | if (cond == ALWAYS) { | |
1122 | off += _emit_LDP(dry_run, &buf[off], SINGLE, | |
1123 | peri); | |
1124 | off += _emit_LDP(dry_run, &buf[off], BURST, | |
1125 | peri); | |
1126 | } else { | |
1127 | off += _emit_LDP(dry_run, &buf[off], cond, | |
1128 | peri); | |
1129 | } | |
1130 | break; | |
271e1b86 | 1131 | |
1d48745b FMH |
1132 | default: |
1133 | /* this code should be unreachable */ | |
1134 | WARN_ON(1); | |
1135 | break; | |
b7d861d9 BK |
1136 | } |
1137 | ||
1138 | return off; | |
1139 | } | |
1140 | ||
1d48745b FMH |
1141 | static inline u32 _emit_store(unsigned int dry_run, u8 buf[], |
1142 | enum pl330_cond cond, enum dma_transfer_direction direction, | |
1143 | u8 peri) | |
1144 | { | |
1145 | int off = 0; | |
1146 | ||
1147 | switch (direction) { | |
1148 | case DMA_MEM_TO_MEM: | |
1149 | /* fall through */ | |
1150 | case DMA_DEV_TO_MEM: | |
1151 | off += _emit_ST(dry_run, &buf[off], cond); | |
1152 | break; | |
1153 | ||
1154 | case DMA_MEM_TO_DEV: | |
1155 | if (cond == ALWAYS) { | |
1156 | off += _emit_STP(dry_run, &buf[off], SINGLE, | |
1157 | peri); | |
1158 | off += _emit_STP(dry_run, &buf[off], BURST, | |
1159 | peri); | |
1160 | } else { | |
1161 | off += _emit_STP(dry_run, &buf[off], cond, | |
1162 | peri); | |
1163 | } | |
1164 | break; | |
1165 | ||
1166 | default: | |
1167 | /* this code should be unreachable */ | |
1168 | WARN_ON(1); | |
1169 | break; | |
1170 | } | |
1171 | ||
1172 | return off; | |
1173 | } | |
1174 | ||
1175 | static inline int _ldst_peripheral(struct pl330_dmac *pl330, | |
271e1b86 | 1176 | unsigned dry_run, u8 buf[], |
1d48745b FMH |
1177 | const struct _xfer_spec *pxs, int cyc, |
1178 | enum pl330_cond cond) | |
b7d861d9 BK |
1179 | { |
1180 | int off = 0; | |
848e9776 | 1181 | |
271e1b86 AK |
1182 | if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) |
1183 | cond = BURST; | |
b7d861d9 | 1184 | |
1d48745b FMH |
1185 | /* |
1186 | * do FLUSHP at beginning to clear any stale dma requests before the | |
1187 | * first WFP. | |
1188 | */ | |
1189 | if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) | |
1190 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); | |
b7d861d9 | 1191 | while (cyc--) { |
848e9776 | 1192 | off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); |
1d48745b FMH |
1193 | off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype, |
1194 | pxs->desc->peri); | |
1195 | off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype, | |
1196 | pxs->desc->peri); | |
b7d861d9 BK |
1197 | } |
1198 | ||
1199 | return off; | |
1200 | } | |
1201 | ||
271e1b86 | 1202 | static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], |
b7d861d9 BK |
1203 | const struct _xfer_spec *pxs, int cyc) |
1204 | { | |
1205 | int off = 0; | |
1d48745b | 1206 | enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE; |
b7d861d9 | 1207 | |
9dc5a315 | 1208 | switch (pxs->desc->rqtype) { |
585a9d0b | 1209 | case DMA_MEM_TO_DEV: |
1d48745b | 1210 | /* fall through */ |
585a9d0b | 1211 | case DMA_DEV_TO_MEM: |
1d48745b FMH |
1212 | off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc, |
1213 | cond); | |
b7d861d9 | 1214 | break; |
1d48745b | 1215 | |
585a9d0b | 1216 | case DMA_MEM_TO_MEM: |
b7d861d9 BK |
1217 | off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); |
1218 | break; | |
1d48745b FMH |
1219 | |
1220 | default: | |
1221 | /* this code should be unreachable */ | |
1222 | WARN_ON(1); | |
1223 | break; | |
1224 | } | |
1225 | ||
1226 | return off; | |
1227 | } | |
1228 | ||
1229 | /* | |
1230 | * transfer dregs with single transfers to peripheral, or a reduced size burst | |
1231 | * for mem-to-mem. | |
1232 | */ | |
1233 | static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[], | |
1234 | const struct _xfer_spec *pxs, int transfer_length) | |
1235 | { | |
1236 | int off = 0; | |
1237 | int dregs_ccr; | |
1238 | ||
1239 | if (transfer_length == 0) | |
1240 | return off; | |
1241 | ||
1242 | switch (pxs->desc->rqtype) { | |
1243 | case DMA_MEM_TO_DEV: | |
1244 | /* fall through */ | |
1245 | case DMA_DEV_TO_MEM: | |
1246 | off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, | |
1247 | transfer_length, SINGLE); | |
1248 | break; | |
1249 | ||
1250 | case DMA_MEM_TO_MEM: | |
1251 | dregs_ccr = pxs->ccr; | |
1252 | dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) | | |
1253 | (0xf << CC_DSTBRSTLEN_SHFT)); | |
1254 | dregs_ccr |= (((transfer_length - 1) & 0xf) << | |
1255 | CC_SRCBRSTLEN_SHFT); | |
1256 | dregs_ccr |= (((transfer_length - 1) & 0xf) << | |
1257 | CC_DSTBRSTLEN_SHFT); | |
1258 | off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); | |
1259 | off += _ldst_memtomem(dry_run, &buf[off], pxs, 1); | |
1260 | break; | |
1261 | ||
b7d861d9 | 1262 | default: |
1d48745b FMH |
1263 | /* this code should be unreachable */ |
1264 | WARN_ON(1); | |
b7d861d9 BK |
1265 | break; |
1266 | } | |
1267 | ||
1268 | return off; | |
1269 | } | |
1270 | ||
1271 | /* Returns bytes consumed and updates bursts */ | |
271e1b86 | 1272 | static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], |
b7d861d9 BK |
1273 | unsigned long *bursts, const struct _xfer_spec *pxs) |
1274 | { | |
1275 | int cyc, cycmax, szlp, szlpend, szbrst, off; | |
1276 | unsigned lcnt0, lcnt1, ljmp0, ljmp1; | |
1277 | struct _arg_LPEND lpend; | |
1278 | ||
31495d60 | 1279 | if (*bursts == 1) |
848e9776 | 1280 | return _bursts(pl330, dry_run, buf, pxs, 1); |
31495d60 | 1281 | |
b7d861d9 BK |
1282 | /* Max iterations possible in DMALP is 256 */ |
1283 | if (*bursts >= 256*256) { | |
1284 | lcnt1 = 256; | |
1285 | lcnt0 = 256; | |
1286 | cyc = *bursts / lcnt1 / lcnt0; | |
1287 | } else if (*bursts > 256) { | |
1288 | lcnt1 = 256; | |
1289 | lcnt0 = *bursts / lcnt1; | |
1290 | cyc = 1; | |
1291 | } else { | |
1292 | lcnt1 = *bursts; | |
1293 | lcnt0 = 0; | |
1294 | cyc = 1; | |
1295 | } | |
1296 | ||
1297 | szlp = _emit_LP(1, buf, 0, 0); | |
271e1b86 | 1298 | szbrst = _bursts(pl330, 1, buf, pxs, 1); |
b7d861d9 BK |
1299 | |
1300 | lpend.cond = ALWAYS; | |
1301 | lpend.forever = false; | |
1302 | lpend.loop = 0; | |
1303 | lpend.bjump = 0; | |
1304 | szlpend = _emit_LPEND(1, buf, &lpend); | |
1305 | ||
1306 | if (lcnt0) { | |
1307 | szlp *= 2; | |
1308 | szlpend *= 2; | |
1309 | } | |
1310 | ||
1311 | /* | |
1312 | * Max bursts that we can unroll due to limit on the | |
1313 | * size of backward jump that can be encoded in DMALPEND | |
1314 | * which is 8-bits and hence 255 | |
1315 | */ | |
1316 | cycmax = (255 - (szlp + szlpend)) / szbrst; | |
1317 | ||
1318 | cyc = (cycmax < cyc) ? cycmax : cyc; | |
1319 | ||
1320 | off = 0; | |
1321 | ||
1322 | if (lcnt0) { | |
1323 | off += _emit_LP(dry_run, &buf[off], 0, lcnt0); | |
1324 | ljmp0 = off; | |
1325 | } | |
1326 | ||
1327 | off += _emit_LP(dry_run, &buf[off], 1, lcnt1); | |
1328 | ljmp1 = off; | |
1329 | ||
271e1b86 | 1330 | off += _bursts(pl330, dry_run, &buf[off], pxs, cyc); |
b7d861d9 BK |
1331 | |
1332 | lpend.cond = ALWAYS; | |
1333 | lpend.forever = false; | |
1334 | lpend.loop = 1; | |
1335 | lpend.bjump = off - ljmp1; | |
1336 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1337 | ||
1338 | if (lcnt0) { | |
1339 | lpend.cond = ALWAYS; | |
1340 | lpend.forever = false; | |
1341 | lpend.loop = 0; | |
1342 | lpend.bjump = off - ljmp0; | |
1343 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1344 | } | |
1345 | ||
1346 | *bursts = lcnt1 * cyc; | |
1347 | if (lcnt0) | |
1348 | *bursts *= lcnt0; | |
1349 | ||
1350 | return off; | |
1351 | } | |
1352 | ||
271e1b86 AK |
1353 | static inline int _setup_loops(struct pl330_dmac *pl330, |
1354 | unsigned dry_run, u8 buf[], | |
1355 | const struct _xfer_spec *pxs) | |
b7d861d9 | 1356 | { |
9dc5a315 | 1357 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1358 | u32 ccr = pxs->ccr; |
1359 | unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); | |
1d48745b FMH |
1360 | int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) / |
1361 | BRST_SIZE(ccr); | |
b7d861d9 BK |
1362 | int off = 0; |
1363 | ||
1364 | while (bursts) { | |
1365 | c = bursts; | |
271e1b86 | 1366 | off += _loop(pl330, dry_run, &buf[off], &c, pxs); |
b7d861d9 BK |
1367 | bursts -= c; |
1368 | } | |
1d48745b | 1369 | off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs); |
b7d861d9 BK |
1370 | |
1371 | return off; | |
1372 | } | |
1373 | ||
271e1b86 AK |
1374 | static inline int _setup_xfer(struct pl330_dmac *pl330, |
1375 | unsigned dry_run, u8 buf[], | |
1376 | const struct _xfer_spec *pxs) | |
b7d861d9 | 1377 | { |
9dc5a315 | 1378 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1379 | int off = 0; |
1380 | ||
1381 | /* DMAMOV SAR, x->src_addr */ | |
1382 | off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); | |
1383 | /* DMAMOV DAR, x->dst_addr */ | |
1384 | off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); | |
1385 | ||
1386 | /* Setup Loop(s) */ | |
271e1b86 | 1387 | off += _setup_loops(pl330, dry_run, &buf[off], pxs); |
b7d861d9 BK |
1388 | |
1389 | return off; | |
1390 | } | |
1391 | ||
1392 | /* | |
1393 | * A req is a sequence of one or more xfer units. | |
1394 | * Returns the number of bytes taken to setup the MC for the req. | |
1395 | */ | |
271e1b86 AK |
1396 | static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run, |
1397 | struct pl330_thread *thrd, unsigned index, | |
1398 | struct _xfer_spec *pxs) | |
b7d861d9 BK |
1399 | { |
1400 | struct _pl330_req *req = &thrd->req[index]; | |
b7d861d9 BK |
1401 | u8 *buf = req->mc_cpu; |
1402 | int off = 0; | |
1403 | ||
1404 | PL330_DBGMC_START(req->mc_bus); | |
1405 | ||
1406 | /* DMAMOV CCR, ccr */ | |
1407 | off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); | |
1408 | ||
271e1b86 | 1409 | off += _setup_xfer(pl330, dry_run, &buf[off], pxs); |
b7d861d9 BK |
1410 | |
1411 | /* DMASEV peripheral/event */ | |
1412 | off += _emit_SEV(dry_run, &buf[off], thrd->ev); | |
1413 | /* DMAEND */ | |
1414 | off += _emit_END(dry_run, &buf[off]); | |
1415 | ||
1416 | return off; | |
1417 | } | |
1418 | ||
1419 | static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) | |
1420 | { | |
1421 | u32 ccr = 0; | |
1422 | ||
1423 | if (rqc->src_inc) | |
1424 | ccr |= CC_SRCINC; | |
1425 | ||
1426 | if (rqc->dst_inc) | |
1427 | ccr |= CC_DSTINC; | |
1428 | ||
1429 | /* We set same protection levels for Src and DST for now */ | |
1430 | if (rqc->privileged) | |
1431 | ccr |= CC_SRCPRI | CC_DSTPRI; | |
1432 | if (rqc->nonsecure) | |
1433 | ccr |= CC_SRCNS | CC_DSTNS; | |
1434 | if (rqc->insnaccess) | |
1435 | ccr |= CC_SRCIA | CC_DSTIA; | |
1436 | ||
1437 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); | |
1438 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); | |
1439 | ||
1440 | ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); | |
1441 | ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); | |
1442 | ||
1443 | ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); | |
1444 | ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); | |
1445 | ||
1446 | ccr |= (rqc->swap << CC_SWAP_SHFT); | |
1447 | ||
1448 | return ccr; | |
1449 | } | |
1450 | ||
b7d861d9 BK |
1451 | /* |
1452 | * Submit a list of xfers after which the client wants notification. | |
1453 | * Client is not notified after each xfer unit, just once after all | |
1454 | * xfer units are done or some error occurs. | |
1455 | */ | |
9dc5a315 LPC |
1456 | static int pl330_submit_req(struct pl330_thread *thrd, |
1457 | struct dma_pl330_desc *desc) | |
b7d861d9 | 1458 | { |
f6f2421c | 1459 | struct pl330_dmac *pl330 = thrd->dmac; |
b7d861d9 BK |
1460 | struct _xfer_spec xs; |
1461 | unsigned long flags; | |
b7d861d9 BK |
1462 | unsigned idx; |
1463 | u32 ccr; | |
1464 | int ret = 0; | |
1465 | ||
1d48745b FMH |
1466 | switch (desc->rqtype) { |
1467 | case DMA_MEM_TO_DEV: | |
1468 | break; | |
1469 | ||
1470 | case DMA_DEV_TO_MEM: | |
1471 | break; | |
1472 | ||
1473 | case DMA_MEM_TO_MEM: | |
1474 | break; | |
1475 | ||
1476 | default: | |
1477 | return -ENOTSUPP; | |
1478 | } | |
1479 | ||
b7d861d9 BK |
1480 | if (pl330->state == DYING |
1481 | || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { | |
f6f2421c | 1482 | dev_info(thrd->dmac->ddma.dev, "%s:%d\n", |
b7d861d9 BK |
1483 | __func__, __LINE__); |
1484 | return -EAGAIN; | |
1485 | } | |
1486 | ||
1487 | /* If request for non-existing peripheral */ | |
9dc5a315 LPC |
1488 | if (desc->rqtype != DMA_MEM_TO_MEM && |
1489 | desc->peri >= pl330->pcfg.num_peri) { | |
f6f2421c | 1490 | dev_info(thrd->dmac->ddma.dev, |
b7d861d9 | 1491 | "%s:%d Invalid peripheral(%u)!\n", |
9dc5a315 | 1492 | __func__, __LINE__, desc->peri); |
b7d861d9 BK |
1493 | return -EINVAL; |
1494 | } | |
1495 | ||
1496 | spin_lock_irqsave(&pl330->lock, flags); | |
1497 | ||
1498 | if (_queue_full(thrd)) { | |
1499 | ret = -EAGAIN; | |
1500 | goto xfer_exit; | |
1501 | } | |
1502 | ||
9dc5a315 LPC |
1503 | /* Prefer Secure Channel */ |
1504 | if (!_manager_ns(thrd)) | |
1505 | desc->rqcfg.nonsecure = 0; | |
1506 | else | |
1507 | desc->rqcfg.nonsecure = 1; | |
b7d861d9 | 1508 | |
9dc5a315 | 1509 | ccr = _prepare_ccr(&desc->rqcfg); |
b7d861d9 | 1510 | |
8ed30a14 | 1511 | idx = thrd->req[0].desc == NULL ? 0 : 1; |
b7d861d9 BK |
1512 | |
1513 | xs.ccr = ccr; | |
9dc5a315 | 1514 | xs.desc = desc; |
b7d861d9 BK |
1515 | |
1516 | /* First dry run to check if req is acceptable */ | |
271e1b86 | 1517 | ret = _setup_req(pl330, 1, thrd, idx, &xs); |
b7d861d9 BK |
1518 | if (ret < 0) |
1519 | goto xfer_exit; | |
1520 | ||
f6f2421c | 1521 | if (ret > pl330->mcbufsz / 2) { |
e5489d5e MS |
1522 | dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n", |
1523 | __func__, __LINE__, ret, pl330->mcbufsz / 2); | |
b7d861d9 BK |
1524 | ret = -ENOMEM; |
1525 | goto xfer_exit; | |
1526 | } | |
1527 | ||
1528 | /* Hook the request */ | |
1529 | thrd->lstenq = idx; | |
9dc5a315 | 1530 | thrd->req[idx].desc = desc; |
271e1b86 | 1531 | _setup_req(pl330, 0, thrd, idx, &xs); |
b7d861d9 BK |
1532 | |
1533 | ret = 0; | |
1534 | ||
1535 | xfer_exit: | |
1536 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1537 | ||
1538 | return ret; | |
1539 | } | |
1540 | ||
9dc5a315 | 1541 | static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) |
6079d38c | 1542 | { |
b1e51d77 | 1543 | struct dma_pl330_chan *pch; |
6079d38c LPC |
1544 | unsigned long flags; |
1545 | ||
b1e51d77 JMC |
1546 | if (!desc) |
1547 | return; | |
1548 | ||
1549 | pch = desc->pchan; | |
1550 | ||
6079d38c LPC |
1551 | /* If desc aborted */ |
1552 | if (!pch) | |
1553 | return; | |
1554 | ||
1555 | spin_lock_irqsave(&pch->lock, flags); | |
1556 | ||
1557 | desc->status = DONE; | |
1558 | ||
1559 | spin_unlock_irqrestore(&pch->lock, flags); | |
1560 | ||
1561 | tasklet_schedule(&pch->task); | |
1562 | } | |
1563 | ||
b7d861d9 BK |
1564 | static void pl330_dotask(unsigned long data) |
1565 | { | |
1566 | struct pl330_dmac *pl330 = (struct pl330_dmac *) data; | |
b7d861d9 BK |
1567 | unsigned long flags; |
1568 | int i; | |
1569 | ||
1570 | spin_lock_irqsave(&pl330->lock, flags); | |
1571 | ||
1572 | /* The DMAC itself gone nuts */ | |
1573 | if (pl330->dmac_tbd.reset_dmac) { | |
1574 | pl330->state = DYING; | |
1575 | /* Reset the manager too */ | |
1576 | pl330->dmac_tbd.reset_mngr = true; | |
1577 | /* Clear the reset flag */ | |
1578 | pl330->dmac_tbd.reset_dmac = false; | |
1579 | } | |
1580 | ||
1581 | if (pl330->dmac_tbd.reset_mngr) { | |
1582 | _stop(pl330->manager); | |
1583 | /* Reset all channels */ | |
f6f2421c | 1584 | pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; |
b7d861d9 BK |
1585 | /* Clear the reset flag */ |
1586 | pl330->dmac_tbd.reset_mngr = false; | |
1587 | } | |
1588 | ||
f6f2421c | 1589 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 BK |
1590 | |
1591 | if (pl330->dmac_tbd.reset_chan & (1 << i)) { | |
1592 | struct pl330_thread *thrd = &pl330->channels[i]; | |
f6f2421c | 1593 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1594 | enum pl330_op_err err; |
1595 | ||
1596 | _stop(thrd); | |
1597 | ||
1598 | if (readl(regs + FSC) & (1 << thrd->id)) | |
1599 | err = PL330_ERR_FAIL; | |
1600 | else | |
1601 | err = PL330_ERR_ABORT; | |
1602 | ||
1603 | spin_unlock_irqrestore(&pl330->lock, flags); | |
9dc5a315 LPC |
1604 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); |
1605 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); | |
b7d861d9 BK |
1606 | spin_lock_irqsave(&pl330->lock, flags); |
1607 | ||
9dc5a315 LPC |
1608 | thrd->req[0].desc = NULL; |
1609 | thrd->req[1].desc = NULL; | |
8ed30a14 | 1610 | thrd->req_running = -1; |
b7d861d9 BK |
1611 | |
1612 | /* Clear the reset flag */ | |
1613 | pl330->dmac_tbd.reset_chan &= ~(1 << i); | |
1614 | } | |
1615 | } | |
1616 | ||
1617 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1618 | ||
1619 | return; | |
1620 | } | |
1621 | ||
1622 | /* Returns 1 if state was updated, 0 otherwise */ | |
f6f2421c | 1623 | static int pl330_update(struct pl330_dmac *pl330) |
b7d861d9 | 1624 | { |
a3ca8312 | 1625 | struct dma_pl330_desc *descdone; |
b7d861d9 BK |
1626 | unsigned long flags; |
1627 | void __iomem *regs; | |
1628 | u32 val; | |
1629 | int id, ev, ret = 0; | |
1630 | ||
f6f2421c | 1631 | regs = pl330->base; |
b7d861d9 BK |
1632 | |
1633 | spin_lock_irqsave(&pl330->lock, flags); | |
1634 | ||
1635 | val = readl(regs + FSM) & 0x1; | |
1636 | if (val) | |
1637 | pl330->dmac_tbd.reset_mngr = true; | |
1638 | else | |
1639 | pl330->dmac_tbd.reset_mngr = false; | |
1640 | ||
f6f2421c | 1641 | val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); |
b7d861d9 BK |
1642 | pl330->dmac_tbd.reset_chan |= val; |
1643 | if (val) { | |
1644 | int i = 0; | |
f6f2421c | 1645 | while (i < pl330->pcfg.num_chan) { |
b7d861d9 | 1646 | if (val & (1 << i)) { |
f6f2421c | 1647 | dev_info(pl330->ddma.dev, |
b7d861d9 BK |
1648 | "Reset Channel-%d\t CS-%x FTC-%x\n", |
1649 | i, readl(regs + CS(i)), | |
1650 | readl(regs + FTC(i))); | |
1651 | _stop(&pl330->channels[i]); | |
1652 | } | |
1653 | i++; | |
1654 | } | |
1655 | } | |
1656 | ||
1657 | /* Check which event happened i.e, thread notified */ | |
1658 | val = readl(regs + ES); | |
f6f2421c LPC |
1659 | if (pl330->pcfg.num_events < 32 |
1660 | && val & ~((1 << pl330->pcfg.num_events) - 1)) { | |
b7d861d9 | 1661 | pl330->dmac_tbd.reset_dmac = true; |
f6f2421c LPC |
1662 | dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, |
1663 | __LINE__); | |
b7d861d9 BK |
1664 | ret = 1; |
1665 | goto updt_exit; | |
1666 | } | |
1667 | ||
f6f2421c | 1668 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) { |
b7d861d9 BK |
1669 | if (val & (1 << ev)) { /* Event occurred */ |
1670 | struct pl330_thread *thrd; | |
1671 | u32 inten = readl(regs + INTEN); | |
1672 | int active; | |
1673 | ||
1674 | /* Clear the event */ | |
1675 | if (inten & (1 << ev)) | |
1676 | writel(1 << ev, regs + INTCLR); | |
1677 | ||
1678 | ret = 1; | |
1679 | ||
1680 | id = pl330->events[ev]; | |
1681 | ||
1682 | thrd = &pl330->channels[id]; | |
1683 | ||
1684 | active = thrd->req_running; | |
1685 | if (active == -1) /* Aborted */ | |
1686 | continue; | |
1687 | ||
fdec53d5 | 1688 | /* Detach the req */ |
9dc5a315 LPC |
1689 | descdone = thrd->req[active].desc; |
1690 | thrd->req[active].desc = NULL; | |
fdec53d5 | 1691 | |
0091b9d6 AK |
1692 | thrd->req_running = -1; |
1693 | ||
b7d861d9 BK |
1694 | /* Get going again ASAP */ |
1695 | _start(thrd); | |
1696 | ||
1697 | /* For now, just make a list of callbacks to be done */ | |
9dc5a315 | 1698 | list_add_tail(&descdone->rqd, &pl330->req_done); |
b7d861d9 BK |
1699 | } |
1700 | } | |
1701 | ||
1702 | /* Now that we are in no hurry, do the callbacks */ | |
a3ca8312 QH |
1703 | while (!list_empty(&pl330->req_done)) { |
1704 | descdone = list_first_entry(&pl330->req_done, | |
1705 | struct dma_pl330_desc, rqd); | |
9dc5a315 | 1706 | list_del(&descdone->rqd); |
b7d861d9 | 1707 | spin_unlock_irqrestore(&pl330->lock, flags); |
9dc5a315 | 1708 | dma_pl330_rqcb(descdone, PL330_ERR_NONE); |
b7d861d9 BK |
1709 | spin_lock_irqsave(&pl330->lock, flags); |
1710 | } | |
1711 | ||
1712 | updt_exit: | |
1713 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1714 | ||
1715 | if (pl330->dmac_tbd.reset_dmac | |
1716 | || pl330->dmac_tbd.reset_mngr | |
1717 | || pl330->dmac_tbd.reset_chan) { | |
1718 | ret = 1; | |
1719 | tasklet_schedule(&pl330->tasks); | |
1720 | } | |
1721 | ||
1722 | return ret; | |
1723 | } | |
1724 | ||
b7d861d9 BK |
1725 | /* Reserve an event */ |
1726 | static inline int _alloc_event(struct pl330_thread *thrd) | |
1727 | { | |
1728 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1729 | int ev; |
1730 | ||
f6f2421c | 1731 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) |
b7d861d9 BK |
1732 | if (pl330->events[ev] == -1) { |
1733 | pl330->events[ev] = thrd->id; | |
1734 | return ev; | |
1735 | } | |
1736 | ||
1737 | return -1; | |
1738 | } | |
1739 | ||
f6f2421c | 1740 | static bool _chan_ns(const struct pl330_dmac *pl330, int i) |
b7d861d9 | 1741 | { |
f6f2421c | 1742 | return pl330->pcfg.irq_ns & (1 << i); |
b7d861d9 BK |
1743 | } |
1744 | ||
1745 | /* Upon success, returns IdentityToken for the | |
1746 | * allocated channel, NULL otherwise. | |
1747 | */ | |
f6f2421c | 1748 | static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) |
b7d861d9 BK |
1749 | { |
1750 | struct pl330_thread *thrd = NULL; | |
b7d861d9 BK |
1751 | int chans, i; |
1752 | ||
b7d861d9 BK |
1753 | if (pl330->state == DYING) |
1754 | return NULL; | |
1755 | ||
f6f2421c | 1756 | chans = pl330->pcfg.num_chan; |
b7d861d9 | 1757 | |
b7d861d9 BK |
1758 | for (i = 0; i < chans; i++) { |
1759 | thrd = &pl330->channels[i]; | |
1760 | if ((thrd->free) && (!_manager_ns(thrd) || | |
f6f2421c | 1761 | _chan_ns(pl330, i))) { |
b7d861d9 BK |
1762 | thrd->ev = _alloc_event(thrd); |
1763 | if (thrd->ev >= 0) { | |
1764 | thrd->free = false; | |
1765 | thrd->lstenq = 1; | |
9dc5a315 | 1766 | thrd->req[0].desc = NULL; |
9dc5a315 | 1767 | thrd->req[1].desc = NULL; |
8ed30a14 | 1768 | thrd->req_running = -1; |
b7d861d9 BK |
1769 | break; |
1770 | } | |
1771 | } | |
1772 | thrd = NULL; | |
1773 | } | |
1774 | ||
b7d861d9 BK |
1775 | return thrd; |
1776 | } | |
1777 | ||
1778 | /* Release an event */ | |
1779 | static inline void _free_event(struct pl330_thread *thrd, int ev) | |
1780 | { | |
1781 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1782 | |
1783 | /* If the event is valid and was held by the thread */ | |
f6f2421c | 1784 | if (ev >= 0 && ev < pl330->pcfg.num_events |
b7d861d9 BK |
1785 | && pl330->events[ev] == thrd->id) |
1786 | pl330->events[ev] = -1; | |
1787 | } | |
1788 | ||
65ad6060 | 1789 | static void pl330_release_channel(struct pl330_thread *thrd) |
b7d861d9 | 1790 | { |
b7d861d9 BK |
1791 | if (!thrd || thrd->free) |
1792 | return; | |
1793 | ||
1794 | _stop(thrd); | |
1795 | ||
9dc5a315 LPC |
1796 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); |
1797 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); | |
b7d861d9 | 1798 | |
b7d861d9 BK |
1799 | _free_event(thrd, thrd->ev); |
1800 | thrd->free = true; | |
b7d861d9 BK |
1801 | } |
1802 | ||
1803 | /* Initialize the structure for PL330 configuration, that can be used | |
1804 | * by the client driver the make best use of the DMAC | |
1805 | */ | |
f6f2421c | 1806 | static void read_dmac_config(struct pl330_dmac *pl330) |
b7d861d9 | 1807 | { |
f6f2421c | 1808 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1809 | u32 val; |
1810 | ||
1811 | val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; | |
1812 | val &= CRD_DATA_WIDTH_MASK; | |
f6f2421c | 1813 | pl330->pcfg.data_bus_width = 8 * (1 << val); |
b7d861d9 BK |
1814 | |
1815 | val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; | |
1816 | val &= CRD_DATA_BUFF_MASK; | |
f6f2421c | 1817 | pl330->pcfg.data_buf_dep = val + 1; |
b7d861d9 BK |
1818 | |
1819 | val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; | |
1820 | val &= CR0_NUM_CHANS_MASK; | |
1821 | val += 1; | |
f6f2421c | 1822 | pl330->pcfg.num_chan = val; |
b7d861d9 BK |
1823 | |
1824 | val = readl(regs + CR0); | |
1825 | if (val & CR0_PERIPH_REQ_SET) { | |
1826 | val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; | |
1827 | val += 1; | |
f6f2421c LPC |
1828 | pl330->pcfg.num_peri = val; |
1829 | pl330->pcfg.peri_ns = readl(regs + CR4); | |
b7d861d9 | 1830 | } else { |
f6f2421c | 1831 | pl330->pcfg.num_peri = 0; |
b7d861d9 BK |
1832 | } |
1833 | ||
1834 | val = readl(regs + CR0); | |
1835 | if (val & CR0_BOOT_MAN_NS) | |
f6f2421c | 1836 | pl330->pcfg.mode |= DMAC_MODE_NS; |
b7d861d9 | 1837 | else |
f6f2421c | 1838 | pl330->pcfg.mode &= ~DMAC_MODE_NS; |
b7d861d9 BK |
1839 | |
1840 | val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; | |
1841 | val &= CR0_NUM_EVENTS_MASK; | |
1842 | val += 1; | |
f6f2421c | 1843 | pl330->pcfg.num_events = val; |
b7d861d9 | 1844 | |
f6f2421c | 1845 | pl330->pcfg.irq_ns = readl(regs + CR3); |
b7d861d9 BK |
1846 | } |
1847 | ||
1848 | static inline void _reset_thread(struct pl330_thread *thrd) | |
1849 | { | |
1850 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1851 | |
1852 | thrd->req[0].mc_cpu = pl330->mcode_cpu | |
f6f2421c | 1853 | + (thrd->id * pl330->mcbufsz); |
b7d861d9 | 1854 | thrd->req[0].mc_bus = pl330->mcode_bus |
f6f2421c | 1855 | + (thrd->id * pl330->mcbufsz); |
9dc5a315 | 1856 | thrd->req[0].desc = NULL; |
b7d861d9 BK |
1857 | |
1858 | thrd->req[1].mc_cpu = thrd->req[0].mc_cpu | |
f6f2421c | 1859 | + pl330->mcbufsz / 2; |
b7d861d9 | 1860 | thrd->req[1].mc_bus = thrd->req[0].mc_bus |
f6f2421c | 1861 | + pl330->mcbufsz / 2; |
9dc5a315 | 1862 | thrd->req[1].desc = NULL; |
8ed30a14 LPC |
1863 | |
1864 | thrd->req_running = -1; | |
b7d861d9 BK |
1865 | } |
1866 | ||
1867 | static int dmac_alloc_threads(struct pl330_dmac *pl330) | |
1868 | { | |
f6f2421c | 1869 | int chans = pl330->pcfg.num_chan; |
b7d861d9 BK |
1870 | struct pl330_thread *thrd; |
1871 | int i; | |
1872 | ||
1873 | /* Allocate 1 Manager and 'chans' Channel threads */ | |
6396bb22 | 1874 | pl330->channels = kcalloc(1 + chans, sizeof(*thrd), |
b7d861d9 BK |
1875 | GFP_KERNEL); |
1876 | if (!pl330->channels) | |
1877 | return -ENOMEM; | |
1878 | ||
1879 | /* Init Channel threads */ | |
1880 | for (i = 0; i < chans; i++) { | |
1881 | thrd = &pl330->channels[i]; | |
1882 | thrd->id = i; | |
1883 | thrd->dmac = pl330; | |
1884 | _reset_thread(thrd); | |
1885 | thrd->free = true; | |
1886 | } | |
1887 | ||
1888 | /* MANAGER is indexed at the end */ | |
1889 | thrd = &pl330->channels[chans]; | |
1890 | thrd->id = chans; | |
1891 | thrd->dmac = pl330; | |
1892 | thrd->free = false; | |
1893 | pl330->manager = thrd; | |
1894 | ||
1895 | return 0; | |
1896 | } | |
1897 | ||
1898 | static int dmac_alloc_resources(struct pl330_dmac *pl330) | |
1899 | { | |
f6f2421c | 1900 | int chans = pl330->pcfg.num_chan; |
b7d861d9 | 1901 | int ret; |
b3040e40 | 1902 | |
b3040e40 | 1903 | /* |
b7d861d9 BK |
1904 | * Alloc MicroCode buffer for 'chans' Channel threads. |
1905 | * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) | |
b3040e40 | 1906 | */ |
1b2354db | 1907 | pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev, |
f6f2421c | 1908 | chans * pl330->mcbufsz, |
1b2354db MH |
1909 | &pl330->mcode_bus, GFP_KERNEL, |
1910 | DMA_ATTR_PRIVILEGED); | |
b7d861d9 | 1911 | if (!pl330->mcode_cpu) { |
f6f2421c | 1912 | dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", |
b7d861d9 BK |
1913 | __func__, __LINE__); |
1914 | return -ENOMEM; | |
1915 | } | |
1916 | ||
1917 | ret = dmac_alloc_threads(pl330); | |
1918 | if (ret) { | |
f6f2421c | 1919 | dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", |
b7d861d9 | 1920 | __func__, __LINE__); |
f6f2421c LPC |
1921 | dma_free_coherent(pl330->ddma.dev, |
1922 | chans * pl330->mcbufsz, | |
b7d861d9 BK |
1923 | pl330->mcode_cpu, pl330->mcode_bus); |
1924 | return ret; | |
1925 | } | |
1926 | ||
1927 | return 0; | |
1928 | } | |
1929 | ||
f6f2421c | 1930 | static int pl330_add(struct pl330_dmac *pl330) |
b7d861d9 | 1931 | { |
b7d861d9 BK |
1932 | int i, ret; |
1933 | ||
b7d861d9 | 1934 | /* Check if we can handle this DMAC */ |
f6f2421c LPC |
1935 | if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { |
1936 | dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", | |
1937 | pl330->pcfg.periph_id); | |
b7d861d9 BK |
1938 | return -EINVAL; |
1939 | } | |
b3040e40 | 1940 | |
b7d861d9 | 1941 | /* Read the configuration of the DMAC */ |
f6f2421c | 1942 | read_dmac_config(pl330); |
b3040e40 | 1943 | |
f6f2421c LPC |
1944 | if (pl330->pcfg.num_events == 0) { |
1945 | dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", | |
b7d861d9 BK |
1946 | __func__, __LINE__); |
1947 | return -EINVAL; | |
1948 | } | |
b3040e40 | 1949 | |
b7d861d9 | 1950 | spin_lock_init(&pl330->lock); |
1b9bb715 | 1951 | |
b7d861d9 | 1952 | INIT_LIST_HEAD(&pl330->req_done); |
42bc9cf4 | 1953 | |
b7d861d9 | 1954 | /* Use default MC buffer size if not provided */ |
f6f2421c LPC |
1955 | if (!pl330->mcbufsz) |
1956 | pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; | |
b3040e40 | 1957 | |
b7d861d9 | 1958 | /* Mark all events as free */ |
f6f2421c | 1959 | for (i = 0; i < pl330->pcfg.num_events; i++) |
b7d861d9 | 1960 | pl330->events[i] = -1; |
b3040e40 | 1961 | |
b7d861d9 BK |
1962 | /* Allocate resources needed by the DMAC */ |
1963 | ret = dmac_alloc_resources(pl330); | |
1964 | if (ret) { | |
f6f2421c | 1965 | dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); |
b7d861d9 BK |
1966 | return ret; |
1967 | } | |
b3040e40 | 1968 | |
b7d861d9 | 1969 | tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); |
b3040e40 | 1970 | |
b7d861d9 | 1971 | pl330->state = INIT; |
a2f5203f | 1972 | |
b7d861d9 BK |
1973 | return 0; |
1974 | } | |
b3040e40 | 1975 | |
b7d861d9 BK |
1976 | static int dmac_free_threads(struct pl330_dmac *pl330) |
1977 | { | |
b7d861d9 BK |
1978 | struct pl330_thread *thrd; |
1979 | int i; | |
b3040e40 | 1980 | |
b7d861d9 | 1981 | /* Release Channel threads */ |
f6f2421c | 1982 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 | 1983 | thrd = &pl330->channels[i]; |
65ad6060 | 1984 | pl330_release_channel(thrd); |
b7d861d9 | 1985 | } |
b3040e40 | 1986 | |
b7d861d9 BK |
1987 | /* Free memory */ |
1988 | kfree(pl330->channels); | |
b3040e40 | 1989 | |
b7d861d9 BK |
1990 | return 0; |
1991 | } | |
b3040e40 | 1992 | |
f6f2421c | 1993 | static void pl330_del(struct pl330_dmac *pl330) |
b7d861d9 | 1994 | { |
b7d861d9 BK |
1995 | pl330->state = UNINIT; |
1996 | ||
1997 | tasklet_kill(&pl330->tasks); | |
1998 | ||
1999 | /* Free DMAC resources */ | |
f6f2421c | 2000 | dmac_free_threads(pl330); |
b7d861d9 | 2001 | |
f6f2421c LPC |
2002 | dma_free_coherent(pl330->ddma.dev, |
2003 | pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, | |
2004 | pl330->mcode_bus); | |
b7d861d9 | 2005 | } |
b3040e40 | 2006 | |
3e2ec13a TA |
2007 | /* forward declaration */ |
2008 | static struct amba_driver pl330_driver; | |
2009 | ||
b3040e40 JB |
2010 | static inline struct dma_pl330_chan * |
2011 | to_pchan(struct dma_chan *ch) | |
2012 | { | |
2013 | if (!ch) | |
2014 | return NULL; | |
2015 | ||
2016 | return container_of(ch, struct dma_pl330_chan, chan); | |
2017 | } | |
2018 | ||
2019 | static inline struct dma_pl330_desc * | |
2020 | to_desc(struct dma_async_tx_descriptor *tx) | |
2021 | { | |
2022 | return container_of(tx, struct dma_pl330_desc, txd); | |
2023 | } | |
2024 | ||
b3040e40 JB |
2025 | static inline void fill_queue(struct dma_pl330_chan *pch) |
2026 | { | |
2027 | struct dma_pl330_desc *desc; | |
2028 | int ret; | |
2029 | ||
2030 | list_for_each_entry(desc, &pch->work_list, node) { | |
2031 | ||
2032 | /* If already submitted */ | |
2033 | if (desc->status == BUSY) | |
30fb980b | 2034 | continue; |
b3040e40 | 2035 | |
9dc5a315 | 2036 | ret = pl330_submit_req(pch->thread, desc); |
b3040e40 JB |
2037 | if (!ret) { |
2038 | desc->status = BUSY; | |
b3040e40 JB |
2039 | } else if (ret == -EAGAIN) { |
2040 | /* QFull or DMAC Dying */ | |
2041 | break; | |
2042 | } else { | |
2043 | /* Unacceptable request */ | |
2044 | desc->status = DONE; | |
f6f2421c | 2045 | dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", |
b3040e40 JB |
2046 | __func__, __LINE__, desc->txd.cookie); |
2047 | tasklet_schedule(&pch->task); | |
2048 | } | |
2049 | } | |
2050 | } | |
2051 | ||
2052 | static void pl330_tasklet(unsigned long data) | |
2053 | { | |
2054 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
2055 | struct dma_pl330_desc *desc, *_dt; | |
2056 | unsigned long flags; | |
ae43b328 | 2057 | bool power_down = false; |
b3040e40 JB |
2058 | |
2059 | spin_lock_irqsave(&pch->lock, flags); | |
2060 | ||
2061 | /* Pick up ripe tomatoes */ | |
2062 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
2063 | if (desc->status == DONE) { | |
30c1dc0f | 2064 | if (!pch->cyclic) |
eab21585 | 2065 | dma_cookie_complete(&desc->txd); |
39ff8613 | 2066 | list_move_tail(&desc->node, &pch->completed_list); |
b3040e40 JB |
2067 | } |
2068 | ||
2069 | /* Try to submit a req imm. next to the last completed cookie */ | |
2070 | fill_queue(pch); | |
2071 | ||
ae43b328 KK |
2072 | if (list_empty(&pch->work_list)) { |
2073 | spin_lock(&pch->thread->dmac->lock); | |
2074 | _stop(pch->thread); | |
2075 | spin_unlock(&pch->thread->dmac->lock); | |
2076 | power_down = true; | |
5c9e6c2b | 2077 | pch->active = false; |
ae43b328 KK |
2078 | } else { |
2079 | /* Make sure the PL330 Channel thread is active */ | |
2080 | spin_lock(&pch->thread->dmac->lock); | |
2081 | _start(pch->thread); | |
2082 | spin_unlock(&pch->thread->dmac->lock); | |
2083 | } | |
b3040e40 | 2084 | |
39ff8613 | 2085 | while (!list_empty(&pch->completed_list)) { |
f08462c6 | 2086 | struct dmaengine_desc_callback cb; |
b3040e40 | 2087 | |
39ff8613 LPC |
2088 | desc = list_first_entry(&pch->completed_list, |
2089 | struct dma_pl330_desc, node); | |
2090 | ||
f08462c6 | 2091 | dmaengine_desc_get_callback(&desc->txd, &cb); |
39ff8613 LPC |
2092 | |
2093 | if (pch->cyclic) { | |
2094 | desc->status = PREP; | |
2095 | list_move_tail(&desc->node, &pch->work_list); | |
ae43b328 | 2096 | if (power_down) { |
5c9e6c2b | 2097 | pch->active = true; |
ae43b328 KK |
2098 | spin_lock(&pch->thread->dmac->lock); |
2099 | _start(pch->thread); | |
2100 | spin_unlock(&pch->thread->dmac->lock); | |
2101 | power_down = false; | |
2102 | } | |
39ff8613 LPC |
2103 | } else { |
2104 | desc->status = FREE; | |
2105 | list_move_tail(&desc->node, &pch->dmac->desc_pool); | |
2106 | } | |
2107 | ||
d38a8c62 DW |
2108 | dma_descriptor_unmap(&desc->txd); |
2109 | ||
f08462c6 | 2110 | if (dmaengine_desc_callback_valid(&cb)) { |
39ff8613 | 2111 | spin_unlock_irqrestore(&pch->lock, flags); |
f08462c6 | 2112 | dmaengine_desc_callback_invoke(&cb, NULL); |
39ff8613 LPC |
2113 | spin_lock_irqsave(&pch->lock, flags); |
2114 | } | |
2115 | } | |
2116 | spin_unlock_irqrestore(&pch->lock, flags); | |
ae43b328 KK |
2117 | |
2118 | /* If work list empty, power down */ | |
2119 | if (power_down) { | |
2120 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); | |
2121 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); | |
2122 | } | |
b3040e40 JB |
2123 | } |
2124 | ||
a80258f9 PV |
2125 | static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, |
2126 | struct of_dma *ofdma) | |
2127 | { | |
2128 | int count = dma_spec->args_count; | |
f6f2421c | 2129 | struct pl330_dmac *pl330 = ofdma->of_dma_data; |
70cbb163 | 2130 | unsigned int chan_id; |
a80258f9 | 2131 | |
f6f2421c LPC |
2132 | if (!pl330) |
2133 | return NULL; | |
2134 | ||
a80258f9 PV |
2135 | if (count != 1) |
2136 | return NULL; | |
2137 | ||
70cbb163 | 2138 | chan_id = dma_spec->args[0]; |
f6f2421c | 2139 | if (chan_id >= pl330->num_peripherals) |
70cbb163 | 2140 | return NULL; |
a80258f9 | 2141 | |
f6f2421c | 2142 | return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); |
a80258f9 PV |
2143 | } |
2144 | ||
b3040e40 JB |
2145 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
2146 | { | |
2147 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f6f2421c | 2148 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2149 | unsigned long flags; |
2150 | ||
91539eb1 | 2151 | spin_lock_irqsave(&pl330->lock, flags); |
b3040e40 | 2152 | |
d3ee98cd | 2153 | dma_cookie_init(chan); |
42bc9cf4 | 2154 | pch->cyclic = false; |
b3040e40 | 2155 | |
f6f2421c | 2156 | pch->thread = pl330_request_channel(pl330); |
65ad6060 | 2157 | if (!pch->thread) { |
91539eb1 | 2158 | spin_unlock_irqrestore(&pl330->lock, flags); |
02747885 | 2159 | return -ENOMEM; |
b3040e40 JB |
2160 | } |
2161 | ||
2162 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
2163 | ||
91539eb1 | 2164 | spin_unlock_irqrestore(&pl330->lock, flags); |
b3040e40 JB |
2165 | |
2166 | return 1; | |
2167 | } | |
2168 | ||
4d6d74e2 RM |
2169 | /* |
2170 | * We need the data direction between the DMAC (the dma-mapping "device") and | |
2171 | * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing! | |
2172 | */ | |
2173 | static enum dma_data_direction | |
2174 | pl330_dma_slave_map_dir(enum dma_transfer_direction dir) | |
2175 | { | |
2176 | switch (dir) { | |
2177 | case DMA_MEM_TO_DEV: | |
2178 | return DMA_FROM_DEVICE; | |
2179 | case DMA_DEV_TO_MEM: | |
2180 | return DMA_TO_DEVICE; | |
2181 | case DMA_DEV_TO_DEV: | |
2182 | return DMA_BIDIRECTIONAL; | |
2183 | default: | |
2184 | return DMA_NONE; | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch) | |
2189 | { | |
2190 | if (pch->dir != DMA_NONE) | |
2191 | dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma, | |
2192 | 1 << pch->burst_sz, pch->dir, 0); | |
2193 | pch->dir = DMA_NONE; | |
2194 | } | |
2195 | ||
2196 | ||
2197 | static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch, | |
2198 | enum dma_transfer_direction dir) | |
2199 | { | |
2200 | struct device *dev = pch->chan.device->dev; | |
2201 | enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir); | |
2202 | ||
2203 | /* Already mapped for this config? */ | |
2204 | if (pch->dir == dma_dir) | |
2205 | return true; | |
2206 | ||
2207 | pl330_unprep_slave_fifo(pch); | |
2208 | pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr, | |
2209 | 1 << pch->burst_sz, dma_dir, 0); | |
2210 | if (dma_mapping_error(dev, pch->fifo_dma)) | |
2211 | return false; | |
2212 | ||
2213 | pch->dir = dma_dir; | |
2214 | return true; | |
2215 | } | |
2216 | ||
1d48745b FMH |
2217 | static int fixup_burst_len(int max_burst_len, int quirks) |
2218 | { | |
2219 | if (quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) | |
2220 | return 1; | |
2221 | else if (max_burst_len > PL330_MAX_BURST) | |
2222 | return PL330_MAX_BURST; | |
2223 | else if (max_burst_len < 1) | |
2224 | return 1; | |
2225 | else | |
2226 | return max_burst_len; | |
2227 | } | |
2228 | ||
445897cb VK |
2229 | static int pl330_config_write(struct dma_chan *chan, |
2230 | struct dma_slave_config *slave_config, | |
2231 | enum dma_transfer_direction direction) | |
740aa957 MR |
2232 | { |
2233 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2234 | ||
4d6d74e2 | 2235 | pl330_unprep_slave_fifo(pch); |
445897cb | 2236 | if (direction == DMA_MEM_TO_DEV) { |
740aa957 MR |
2237 | if (slave_config->dst_addr) |
2238 | pch->fifo_addr = slave_config->dst_addr; | |
2239 | if (slave_config->dst_addr_width) | |
2240 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
1d48745b FMH |
2241 | pch->burst_len = fixup_burst_len(slave_config->dst_maxburst, |
2242 | pch->dmac->quirks); | |
445897cb | 2243 | } else if (direction == DMA_DEV_TO_MEM) { |
740aa957 MR |
2244 | if (slave_config->src_addr) |
2245 | pch->fifo_addr = slave_config->src_addr; | |
2246 | if (slave_config->src_addr_width) | |
2247 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
1d48745b FMH |
2248 | pch->burst_len = fixup_burst_len(slave_config->src_maxburst, |
2249 | pch->dmac->quirks); | |
740aa957 MR |
2250 | } |
2251 | ||
2252 | return 0; | |
2253 | } | |
2254 | ||
445897cb VK |
2255 | static int pl330_config(struct dma_chan *chan, |
2256 | struct dma_slave_config *slave_config) | |
2257 | { | |
2258 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2259 | ||
2260 | memcpy(&pch->slave_config, slave_config, sizeof(*slave_config)); | |
2261 | ||
2262 | return 0; | |
2263 | } | |
2264 | ||
740aa957 | 2265 | static int pl330_terminate_all(struct dma_chan *chan) |
b3040e40 JB |
2266 | { |
2267 | struct dma_pl330_chan *pch = to_pchan(chan); | |
39ff8613 | 2268 | struct dma_pl330_desc *desc; |
b3040e40 | 2269 | unsigned long flags; |
f6f2421c | 2270 | struct pl330_dmac *pl330 = pch->dmac; |
5c9e6c2b | 2271 | bool power_down = false; |
b3040e40 | 2272 | |
81cc6edc | 2273 | pm_runtime_get_sync(pl330->ddma.dev); |
740aa957 | 2274 | spin_lock_irqsave(&pch->lock, flags); |
e4975654 | 2275 | |
740aa957 MR |
2276 | spin_lock(&pl330->lock); |
2277 | _stop(pch->thread); | |
740aa957 MR |
2278 | pch->thread->req[0].desc = NULL; |
2279 | pch->thread->req[1].desc = NULL; | |
2280 | pch->thread->req_running = -1; | |
e4975654 JK |
2281 | spin_unlock(&pl330->lock); |
2282 | ||
5c9e6c2b MS |
2283 | power_down = pch->active; |
2284 | pch->active = false; | |
740aa957 MR |
2285 | |
2286 | /* Mark all desc done */ | |
2287 | list_for_each_entry(desc, &pch->submitted_list, node) { | |
2288 | desc->status = FREE; | |
2289 | dma_cookie_complete(&desc->txd); | |
2290 | } | |
ae43b328 | 2291 | |
740aa957 MR |
2292 | list_for_each_entry(desc, &pch->work_list , node) { |
2293 | desc->status = FREE; | |
2294 | dma_cookie_complete(&desc->txd); | |
1d0c1d60 | 2295 | } |
b3040e40 | 2296 | |
740aa957 MR |
2297 | list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); |
2298 | list_splice_tail_init(&pch->work_list, &pl330->desc_pool); | |
2299 | list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); | |
2300 | spin_unlock_irqrestore(&pch->lock, flags); | |
81cc6edc | 2301 | pm_runtime_mark_last_busy(pl330->ddma.dev); |
5c9e6c2b MS |
2302 | if (power_down) |
2303 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
81cc6edc | 2304 | pm_runtime_put_autosuspend(pl330->ddma.dev); |
740aa957 | 2305 | |
b3040e40 JB |
2306 | return 0; |
2307 | } | |
2308 | ||
88987d2c RB |
2309 | /* |
2310 | * We don't support DMA_RESUME command because of hardware | |
2311 | * limitations, so after pausing the channel we cannot restore | |
2312 | * it to active state. We have to terminate channel and setup | |
2313 | * DMA transfer again. This pause feature was implemented to | |
2314 | * allow safely read residue before channel termination. | |
2315 | */ | |
5503aed8 | 2316 | static int pl330_pause(struct dma_chan *chan) |
88987d2c RB |
2317 | { |
2318 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2319 | struct pl330_dmac *pl330 = pch->dmac; | |
2320 | unsigned long flags; | |
2321 | ||
2322 | pm_runtime_get_sync(pl330->ddma.dev); | |
2323 | spin_lock_irqsave(&pch->lock, flags); | |
2324 | ||
2325 | spin_lock(&pl330->lock); | |
2326 | _stop(pch->thread); | |
2327 | spin_unlock(&pl330->lock); | |
2328 | ||
2329 | spin_unlock_irqrestore(&pch->lock, flags); | |
2330 | pm_runtime_mark_last_busy(pl330->ddma.dev); | |
2331 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
2332 | ||
2333 | return 0; | |
2334 | } | |
2335 | ||
b3040e40 JB |
2336 | static void pl330_free_chan_resources(struct dma_chan *chan) |
2337 | { | |
2338 | struct dma_pl330_chan *pch = to_pchan(chan); | |
91539eb1 | 2339 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2340 | unsigned long flags; |
2341 | ||
b3040e40 JB |
2342 | tasklet_kill(&pch->task); |
2343 | ||
ae43b328 | 2344 | pm_runtime_get_sync(pch->dmac->ddma.dev); |
91539eb1 | 2345 | spin_lock_irqsave(&pl330->lock, flags); |
da331ba8 | 2346 | |
65ad6060 LPC |
2347 | pl330_release_channel(pch->thread); |
2348 | pch->thread = NULL; | |
b3040e40 | 2349 | |
42bc9cf4 BK |
2350 | if (pch->cyclic) |
2351 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
2352 | ||
91539eb1 | 2353 | spin_unlock_irqrestore(&pl330->lock, flags); |
ae43b328 KK |
2354 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); |
2355 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); | |
4d6d74e2 | 2356 | pl330_unprep_slave_fifo(pch); |
b3040e40 JB |
2357 | } |
2358 | ||
5503aed8 BD |
2359 | static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch, |
2360 | struct dma_pl330_desc *desc) | |
aee4d1fa RB |
2361 | { |
2362 | struct pl330_thread *thrd = pch->thread; | |
2363 | struct pl330_dmac *pl330 = pch->dmac; | |
2364 | void __iomem *regs = thrd->dmac->base; | |
2365 | u32 val, addr; | |
2366 | ||
2367 | pm_runtime_get_sync(pl330->ddma.dev); | |
2368 | val = addr = 0; | |
2369 | if (desc->rqcfg.src_inc) { | |
2370 | val = readl(regs + SA(thrd->id)); | |
2371 | addr = desc->px.src_addr; | |
2372 | } else { | |
2373 | val = readl(regs + DA(thrd->id)); | |
2374 | addr = desc->px.dst_addr; | |
2375 | } | |
2376 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); | |
2377 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
c44da03d SB |
2378 | |
2379 | /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */ | |
2380 | if (!val) | |
2381 | return 0; | |
2382 | ||
aee4d1fa RB |
2383 | return val - addr; |
2384 | } | |
2385 | ||
b3040e40 JB |
2386 | static enum dma_status |
2387 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
2388 | struct dma_tx_state *txstate) | |
2389 | { | |
aee4d1fa RB |
2390 | enum dma_status ret; |
2391 | unsigned long flags; | |
d64e9a2c | 2392 | struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL; |
aee4d1fa RB |
2393 | struct dma_pl330_chan *pch = to_pchan(chan); |
2394 | unsigned int transferred, residual = 0; | |
2395 | ||
2396 | ret = dma_cookie_status(chan, cookie, txstate); | |
2397 | ||
2398 | if (!txstate) | |
2399 | return ret; | |
2400 | ||
2401 | if (ret == DMA_COMPLETE) | |
2402 | goto out; | |
2403 | ||
2404 | spin_lock_irqsave(&pch->lock, flags); | |
a40235a2 | 2405 | spin_lock(&pch->thread->dmac->lock); |
aee4d1fa RB |
2406 | |
2407 | if (pch->thread->req_running != -1) | |
2408 | running = pch->thread->req[pch->thread->req_running].desc; | |
2409 | ||
d64e9a2c SB |
2410 | last_enq = pch->thread->req[pch->thread->lstenq].desc; |
2411 | ||
aee4d1fa RB |
2412 | /* Check in pending list */ |
2413 | list_for_each_entry(desc, &pch->work_list, node) { | |
2414 | if (desc->status == DONE) | |
2415 | transferred = desc->bytes_requested; | |
2416 | else if (running && desc == running) | |
2417 | transferred = | |
2418 | pl330_get_current_xferred_count(pch, desc); | |
d64e9a2c SB |
2419 | else if (desc->status == BUSY) |
2420 | /* | |
2421 | * Busy but not running means either just enqueued, | |
2422 | * or finished and not yet marked done | |
2423 | */ | |
2424 | if (desc == last_enq) | |
2425 | transferred = 0; | |
2426 | else | |
2427 | transferred = desc->bytes_requested; | |
aee4d1fa RB |
2428 | else |
2429 | transferred = 0; | |
2430 | residual += desc->bytes_requested - transferred; | |
2431 | if (desc->txd.cookie == cookie) { | |
75967b78 BD |
2432 | switch (desc->status) { |
2433 | case DONE: | |
2434 | ret = DMA_COMPLETE; | |
2435 | break; | |
2436 | case PREP: | |
2437 | case BUSY: | |
2438 | ret = DMA_IN_PROGRESS; | |
2439 | break; | |
2440 | default: | |
2441 | WARN_ON(1); | |
2442 | } | |
aee4d1fa RB |
2443 | break; |
2444 | } | |
2445 | if (desc->last) | |
2446 | residual = 0; | |
2447 | } | |
a40235a2 | 2448 | spin_unlock(&pch->thread->dmac->lock); |
aee4d1fa RB |
2449 | spin_unlock_irqrestore(&pch->lock, flags); |
2450 | ||
2451 | out: | |
2452 | dma_set_residue(txstate, residual); | |
2453 | ||
2454 | return ret; | |
b3040e40 JB |
2455 | } |
2456 | ||
2457 | static void pl330_issue_pending(struct dma_chan *chan) | |
2458 | { | |
04abf5da LPC |
2459 | struct dma_pl330_chan *pch = to_pchan(chan); |
2460 | unsigned long flags; | |
2461 | ||
2462 | spin_lock_irqsave(&pch->lock, flags); | |
ae43b328 KK |
2463 | if (list_empty(&pch->work_list)) { |
2464 | /* | |
2465 | * Warn on nothing pending. Empty submitted_list may | |
2466 | * break our pm_runtime usage counter as it is | |
2467 | * updated on work_list emptiness status. | |
2468 | */ | |
2469 | WARN_ON(list_empty(&pch->submitted_list)); | |
5c9e6c2b | 2470 | pch->active = true; |
ae43b328 KK |
2471 | pm_runtime_get_sync(pch->dmac->ddma.dev); |
2472 | } | |
04abf5da LPC |
2473 | list_splice_tail_init(&pch->submitted_list, &pch->work_list); |
2474 | spin_unlock_irqrestore(&pch->lock, flags); | |
2475 | ||
2476 | pl330_tasklet((unsigned long)pch); | |
b3040e40 JB |
2477 | } |
2478 | ||
2479 | /* | |
2480 | * We returned the last one of the circular list of descriptor(s) | |
2481 | * from prep_xxx, so the argument to submit corresponds to the last | |
2482 | * descriptor of the list. | |
2483 | */ | |
2484 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
2485 | { | |
2486 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
2487 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
2488 | dma_cookie_t cookie; | |
2489 | unsigned long flags; | |
2490 | ||
2491 | spin_lock_irqsave(&pch->lock, flags); | |
2492 | ||
2493 | /* Assign cookies to all nodes */ | |
b3040e40 JB |
2494 | while (!list_empty(&last->node)) { |
2495 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
fc514460 LPC |
2496 | if (pch->cyclic) { |
2497 | desc->txd.callback = last->txd.callback; | |
2498 | desc->txd.callback_param = last->txd.callback_param; | |
2499 | } | |
5dd90e5b | 2500 | desc->last = false; |
b3040e40 | 2501 | |
884485e1 | 2502 | dma_cookie_assign(&desc->txd); |
b3040e40 | 2503 | |
04abf5da | 2504 | list_move_tail(&desc->node, &pch->submitted_list); |
b3040e40 JB |
2505 | } |
2506 | ||
aee4d1fa | 2507 | last->last = true; |
884485e1 | 2508 | cookie = dma_cookie_assign(&last->txd); |
04abf5da | 2509 | list_add_tail(&last->node, &pch->submitted_list); |
b3040e40 JB |
2510 | spin_unlock_irqrestore(&pch->lock, flags); |
2511 | ||
2512 | return cookie; | |
2513 | } | |
2514 | ||
2515 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
2516 | { | |
b3040e40 | 2517 | desc->rqcfg.swap = SWAP_NO; |
f0564c7e LPC |
2518 | desc->rqcfg.scctl = CCTRL0; |
2519 | desc->rqcfg.dcctl = CCTRL0; | |
b3040e40 JB |
2520 | desc->txd.tx_submit = pl330_tx_submit; |
2521 | ||
2522 | INIT_LIST_HEAD(&desc->node); | |
2523 | } | |
2524 | ||
2525 | /* Returns the number of descriptors added to the DMAC pool */ | |
e5887103 AK |
2526 | static int add_desc(struct list_head *pool, spinlock_t *lock, |
2527 | gfp_t flg, int count) | |
b3040e40 JB |
2528 | { |
2529 | struct dma_pl330_desc *desc; | |
2530 | unsigned long flags; | |
2531 | int i; | |
2532 | ||
0baf8f6a | 2533 | desc = kcalloc(count, sizeof(*desc), flg); |
b3040e40 JB |
2534 | if (!desc) |
2535 | return 0; | |
2536 | ||
e5887103 | 2537 | spin_lock_irqsave(lock, flags); |
b3040e40 JB |
2538 | |
2539 | for (i = 0; i < count; i++) { | |
2540 | _init_desc(&desc[i]); | |
e5887103 | 2541 | list_add_tail(&desc[i].node, pool); |
b3040e40 JB |
2542 | } |
2543 | ||
e5887103 | 2544 | spin_unlock_irqrestore(lock, flags); |
b3040e40 JB |
2545 | |
2546 | return count; | |
2547 | } | |
2548 | ||
e5887103 AK |
2549 | static struct dma_pl330_desc *pluck_desc(struct list_head *pool, |
2550 | spinlock_t *lock) | |
b3040e40 JB |
2551 | { |
2552 | struct dma_pl330_desc *desc = NULL; | |
2553 | unsigned long flags; | |
2554 | ||
e5887103 | 2555 | spin_lock_irqsave(lock, flags); |
b3040e40 | 2556 | |
e5887103 AK |
2557 | if (!list_empty(pool)) { |
2558 | desc = list_entry(pool->next, | |
b3040e40 JB |
2559 | struct dma_pl330_desc, node); |
2560 | ||
2561 | list_del_init(&desc->node); | |
2562 | ||
2563 | desc->status = PREP; | |
2564 | desc->txd.callback = NULL; | |
2565 | } | |
2566 | ||
e5887103 | 2567 | spin_unlock_irqrestore(lock, flags); |
b3040e40 JB |
2568 | |
2569 | return desc; | |
2570 | } | |
2571 | ||
2572 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
2573 | { | |
f6f2421c | 2574 | struct pl330_dmac *pl330 = pch->dmac; |
cd072515 | 2575 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
2576 | struct dma_pl330_desc *desc; |
2577 | ||
2578 | /* Pluck one desc from the pool of DMAC */ | |
e5887103 | 2579 | desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock); |
b3040e40 JB |
2580 | |
2581 | /* If the DMAC pool is empty, alloc new */ | |
2582 | if (!desc) { | |
e5887103 AK |
2583 | DEFINE_SPINLOCK(lock); |
2584 | LIST_HEAD(pool); | |
b3040e40 | 2585 | |
e5887103 | 2586 | if (!add_desc(&pool, &lock, GFP_ATOMIC, 1)) |
b3040e40 | 2587 | return NULL; |
e5887103 AK |
2588 | |
2589 | desc = pluck_desc(&pool, &lock); | |
2590 | WARN_ON(!desc || !list_empty(&pool)); | |
b3040e40 JB |
2591 | } |
2592 | ||
2593 | /* Initialize the descriptor */ | |
2594 | desc->pchan = pch; | |
2595 | desc->txd.cookie = 0; | |
2596 | async_tx_ack(&desc->txd); | |
2597 | ||
9dc5a315 | 2598 | desc->peri = peri_id ? pch->chan.chan_id : 0; |
f6f2421c | 2599 | desc->rqcfg.pcfg = &pch->dmac->pcfg; |
b3040e40 JB |
2600 | |
2601 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
2602 | ||
2603 | return desc; | |
2604 | } | |
2605 | ||
2606 | static inline void fill_px(struct pl330_xfer *px, | |
2607 | dma_addr_t dst, dma_addr_t src, size_t len) | |
2608 | { | |
b3040e40 JB |
2609 | px->bytes = len; |
2610 | px->dst_addr = dst; | |
2611 | px->src_addr = src; | |
2612 | } | |
2613 | ||
2614 | static struct dma_pl330_desc * | |
2615 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
2616 | dma_addr_t src, size_t len) | |
2617 | { | |
2618 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
2619 | ||
2620 | if (!desc) { | |
f6f2421c | 2621 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
b3040e40 JB |
2622 | __func__, __LINE__); |
2623 | return NULL; | |
2624 | } | |
2625 | ||
2626 | /* | |
2627 | * Ideally we should lookout for reqs bigger than | |
2628 | * those that can be programmed with 256 bytes of | |
2629 | * MC buffer, but considering a req size is seldom | |
2630 | * going to be word-unaligned and more than 200MB, | |
2631 | * we take it easy. | |
2632 | * Also, should the limit is reached we'd rather | |
2633 | * have the platform increase MC buffer size than | |
2634 | * complicating this API driver. | |
2635 | */ | |
2636 | fill_px(&desc->px, dst, src, len); | |
2637 | ||
2638 | return desc; | |
2639 | } | |
2640 | ||
2641 | /* Call after fixing burst size */ | |
2642 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
2643 | { | |
2644 | struct dma_pl330_chan *pch = desc->pchan; | |
f6f2421c | 2645 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2646 | int burst_len; |
2647 | ||
f6f2421c | 2648 | burst_len = pl330->pcfg.data_bus_width / 8; |
c27f9556 | 2649 | burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; |
b3040e40 JB |
2650 | burst_len >>= desc->rqcfg.brst_size; |
2651 | ||
2652 | /* src/dst_burst_len can't be more than 16 */ | |
1d48745b FMH |
2653 | if (burst_len > PL330_MAX_BURST) |
2654 | burst_len = PL330_MAX_BURST; | |
b3040e40 JB |
2655 | |
2656 | return burst_len; | |
2657 | } | |
2658 | ||
42bc9cf4 BK |
2659 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
2660 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
185ecb5f | 2661 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 2662 | unsigned long flags) |
42bc9cf4 | 2663 | { |
fc514460 | 2664 | struct dma_pl330_desc *desc = NULL, *first = NULL; |
42bc9cf4 | 2665 | struct dma_pl330_chan *pch = to_pchan(chan); |
f6f2421c | 2666 | struct pl330_dmac *pl330 = pch->dmac; |
fc514460 | 2667 | unsigned int i; |
42bc9cf4 BK |
2668 | dma_addr_t dst; |
2669 | dma_addr_t src; | |
2670 | ||
fc514460 | 2671 | if (len % period_len != 0) |
42bc9cf4 | 2672 | return NULL; |
42bc9cf4 | 2673 | |
fc514460 | 2674 | if (!is_slave_direction(direction)) { |
f6f2421c | 2675 | dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", |
42bc9cf4 BK |
2676 | __func__, __LINE__); |
2677 | return NULL; | |
2678 | } | |
2679 | ||
445897cb VK |
2680 | pl330_config_write(chan, &pch->slave_config, direction); |
2681 | ||
4d6d74e2 RM |
2682 | if (!pl330_prep_slave_fifo(pch, direction)) |
2683 | return NULL; | |
2684 | ||
fc514460 LPC |
2685 | for (i = 0; i < len / period_len; i++) { |
2686 | desc = pl330_get_desc(pch); | |
2687 | if (!desc) { | |
f6f2421c | 2688 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
fc514460 | 2689 | __func__, __LINE__); |
42bc9cf4 | 2690 | |
fc514460 LPC |
2691 | if (!first) |
2692 | return NULL; | |
2693 | ||
f6f2421c | 2694 | spin_lock_irqsave(&pl330->pool_lock, flags); |
fc514460 LPC |
2695 | |
2696 | while (!list_empty(&first->node)) { | |
2697 | desc = list_entry(first->node.next, | |
2698 | struct dma_pl330_desc, node); | |
f6f2421c | 2699 | list_move_tail(&desc->node, &pl330->desc_pool); |
fc514460 LPC |
2700 | } |
2701 | ||
f6f2421c | 2702 | list_move_tail(&first->node, &pl330->desc_pool); |
fc514460 | 2703 | |
f6f2421c | 2704 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
42bc9cf4 | 2705 | |
fc514460 LPC |
2706 | return NULL; |
2707 | } | |
2708 | ||
2709 | switch (direction) { | |
2710 | case DMA_MEM_TO_DEV: | |
2711 | desc->rqcfg.src_inc = 1; | |
2712 | desc->rqcfg.dst_inc = 0; | |
fc514460 | 2713 | src = dma_addr; |
4d6d74e2 | 2714 | dst = pch->fifo_dma; |
fc514460 LPC |
2715 | break; |
2716 | case DMA_DEV_TO_MEM: | |
2717 | desc->rqcfg.src_inc = 0; | |
2718 | desc->rqcfg.dst_inc = 1; | |
4d6d74e2 | 2719 | src = pch->fifo_dma; |
fc514460 LPC |
2720 | dst = dma_addr; |
2721 | break; | |
2722 | default: | |
2723 | break; | |
2724 | } | |
2725 | ||
9dc5a315 | 2726 | desc->rqtype = direction; |
fc514460 | 2727 | desc->rqcfg.brst_size = pch->burst_sz; |
1d48745b | 2728 | desc->rqcfg.brst_len = pch->burst_len; |
aee4d1fa | 2729 | desc->bytes_requested = period_len; |
fc514460 LPC |
2730 | fill_px(&desc->px, dst, src, period_len); |
2731 | ||
2732 | if (!first) | |
2733 | first = desc; | |
2734 | else | |
2735 | list_add_tail(&desc->node, &first->node); | |
2736 | ||
2737 | dma_addr += period_len; | |
2738 | } | |
2739 | ||
2740 | if (!desc) | |
2741 | return NULL; | |
2742 | ||
2743 | pch->cyclic = true; | |
2744 | desc->txd.flags = flags; | |
42bc9cf4 BK |
2745 | |
2746 | return &desc->txd; | |
2747 | } | |
2748 | ||
b3040e40 JB |
2749 | static struct dma_async_tx_descriptor * |
2750 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
2751 | dma_addr_t src, size_t len, unsigned long flags) | |
2752 | { | |
2753 | struct dma_pl330_desc *desc; | |
2754 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f5636854 | 2755 | struct pl330_dmac *pl330; |
b3040e40 JB |
2756 | int burst; |
2757 | ||
4e0e6109 | 2758 | if (unlikely(!pch || !len)) |
b3040e40 JB |
2759 | return NULL; |
2760 | ||
f5636854 MS |
2761 | pl330 = pch->dmac; |
2762 | ||
b3040e40 JB |
2763 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); |
2764 | if (!desc) | |
2765 | return NULL; | |
2766 | ||
2767 | desc->rqcfg.src_inc = 1; | |
2768 | desc->rqcfg.dst_inc = 1; | |
9dc5a315 | 2769 | desc->rqtype = DMA_MEM_TO_MEM; |
b3040e40 JB |
2770 | |
2771 | /* Select max possible burst size */ | |
f6f2421c | 2772 | burst = pl330->pcfg.data_bus_width / 8; |
b3040e40 | 2773 | |
137bd110 JM |
2774 | /* |
2775 | * Make sure we use a burst size that aligns with all the memcpy | |
2776 | * parameters because our DMA programming algorithm doesn't cope with | |
2777 | * transfers which straddle an entry in the DMA device's MFIFO. | |
2778 | */ | |
2779 | while ((src | dst | len) & (burst - 1)) | |
b3040e40 | 2780 | burst /= 2; |
b3040e40 JB |
2781 | |
2782 | desc->rqcfg.brst_size = 0; | |
2783 | while (burst != (1 << desc->rqcfg.brst_size)) | |
2784 | desc->rqcfg.brst_size++; | |
2785 | ||
137bd110 JM |
2786 | /* |
2787 | * If burst size is smaller than bus width then make sure we only | |
2788 | * transfer one at a time to avoid a burst stradling an MFIFO entry. | |
2789 | */ | |
2790 | if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) | |
2791 | desc->rqcfg.brst_len = 1; | |
2792 | ||
b3040e40 | 2793 | desc->rqcfg.brst_len = get_burst_len(desc, len); |
ae128293 | 2794 | desc->bytes_requested = len; |
b3040e40 JB |
2795 | |
2796 | desc->txd.flags = flags; | |
2797 | ||
2798 | return &desc->txd; | |
2799 | } | |
2800 | ||
f6f2421c | 2801 | static void __pl330_giveback_desc(struct pl330_dmac *pl330, |
52a9d179 CP |
2802 | struct dma_pl330_desc *first) |
2803 | { | |
2804 | unsigned long flags; | |
2805 | struct dma_pl330_desc *desc; | |
2806 | ||
2807 | if (!first) | |
2808 | return; | |
2809 | ||
f6f2421c | 2810 | spin_lock_irqsave(&pl330->pool_lock, flags); |
52a9d179 CP |
2811 | |
2812 | while (!list_empty(&first->node)) { | |
2813 | desc = list_entry(first->node.next, | |
2814 | struct dma_pl330_desc, node); | |
f6f2421c | 2815 | list_move_tail(&desc->node, &pl330->desc_pool); |
52a9d179 CP |
2816 | } |
2817 | ||
f6f2421c | 2818 | list_move_tail(&first->node, &pl330->desc_pool); |
52a9d179 | 2819 | |
f6f2421c | 2820 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
52a9d179 CP |
2821 | } |
2822 | ||
b3040e40 JB |
2823 | static struct dma_async_tx_descriptor * |
2824 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 2825 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 2826 | unsigned long flg, void *context) |
b3040e40 JB |
2827 | { |
2828 | struct dma_pl330_desc *first, *desc = NULL; | |
2829 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 | 2830 | struct scatterlist *sg; |
1b9bb715 | 2831 | int i; |
b3040e40 | 2832 | |
cd072515 | 2833 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 JB |
2834 | return NULL; |
2835 | ||
445897cb VK |
2836 | pl330_config_write(chan, &pch->slave_config, direction); |
2837 | ||
4d6d74e2 RM |
2838 | if (!pl330_prep_slave_fifo(pch, direction)) |
2839 | return NULL; | |
b3040e40 JB |
2840 | |
2841 | first = NULL; | |
2842 | ||
2843 | for_each_sg(sgl, sg, sg_len, i) { | |
2844 | ||
2845 | desc = pl330_get_desc(pch); | |
2846 | if (!desc) { | |
f6f2421c | 2847 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 | 2848 | |
f6f2421c | 2849 | dev_err(pch->dmac->ddma.dev, |
b3040e40 JB |
2850 | "%s:%d Unable to fetch desc\n", |
2851 | __func__, __LINE__); | |
f6f2421c | 2852 | __pl330_giveback_desc(pl330, first); |
b3040e40 JB |
2853 | |
2854 | return NULL; | |
2855 | } | |
2856 | ||
2857 | if (!first) | |
2858 | first = desc; | |
2859 | else | |
2860 | list_add_tail(&desc->node, &first->node); | |
2861 | ||
db8196df | 2862 | if (direction == DMA_MEM_TO_DEV) { |
b3040e40 JB |
2863 | desc->rqcfg.src_inc = 1; |
2864 | desc->rqcfg.dst_inc = 0; | |
4d6d74e2 RM |
2865 | fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg), |
2866 | sg_dma_len(sg)); | |
b3040e40 JB |
2867 | } else { |
2868 | desc->rqcfg.src_inc = 0; | |
2869 | desc->rqcfg.dst_inc = 1; | |
4d6d74e2 RM |
2870 | fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma, |
2871 | sg_dma_len(sg)); | |
b3040e40 JB |
2872 | } |
2873 | ||
1b9bb715 | 2874 | desc->rqcfg.brst_size = pch->burst_sz; |
1d48745b | 2875 | desc->rqcfg.brst_len = pch->burst_len; |
9dc5a315 | 2876 | desc->rqtype = direction; |
aee4d1fa | 2877 | desc->bytes_requested = sg_dma_len(sg); |
b3040e40 JB |
2878 | } |
2879 | ||
2880 | /* Return the last desc in the chain */ | |
2881 | desc->txd.flags = flg; | |
2882 | return &desc->txd; | |
2883 | } | |
2884 | ||
2885 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
2886 | { | |
2887 | if (pl330_update(data)) | |
2888 | return IRQ_HANDLED; | |
2889 | else | |
2890 | return IRQ_NONE; | |
2891 | } | |
2892 | ||
ca38ff13 LPC |
2893 | #define PL330_DMA_BUSWIDTHS \ |
2894 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
2895 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
2896 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
2897 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ | |
2898 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | |
2899 | ||
b45aef3a KS |
2900 | #ifdef CONFIG_DEBUG_FS |
2901 | static int pl330_debugfs_show(struct seq_file *s, void *data) | |
2902 | { | |
2903 | struct pl330_dmac *pl330 = s->private; | |
2904 | int chans, pchs, ch, pr; | |
2905 | ||
2906 | chans = pl330->pcfg.num_chan; | |
2907 | pchs = pl330->num_peripherals; | |
2908 | ||
2909 | seq_puts(s, "PL330 physical channels:\n"); | |
2910 | seq_puts(s, "THREAD:\t\tCHANNEL:\n"); | |
2911 | seq_puts(s, "--------\t-----\n"); | |
2912 | for (ch = 0; ch < chans; ch++) { | |
2913 | struct pl330_thread *thrd = &pl330->channels[ch]; | |
2914 | int found = -1; | |
2915 | ||
2916 | for (pr = 0; pr < pchs; pr++) { | |
2917 | struct dma_pl330_chan *pch = &pl330->peripherals[pr]; | |
2918 | ||
2919 | if (!pch->thread || thrd->id != pch->thread->id) | |
2920 | continue; | |
2921 | ||
2922 | found = pr; | |
2923 | } | |
2924 | ||
2925 | seq_printf(s, "%d\t\t", thrd->id); | |
2926 | if (found == -1) | |
2927 | seq_puts(s, "--\n"); | |
2928 | else | |
2929 | seq_printf(s, "%d\n", found); | |
2930 | } | |
2931 | ||
2932 | return 0; | |
2933 | } | |
2934 | ||
2935 | DEFINE_SHOW_ATTRIBUTE(pl330_debugfs); | |
2936 | ||
2937 | static inline void init_pl330_debugfs(struct pl330_dmac *pl330) | |
2938 | { | |
2939 | debugfs_create_file(dev_name(pl330->ddma.dev), | |
2940 | S_IFREG | 0444, NULL, pl330, | |
2941 | &pl330_debugfs_fops); | |
2942 | } | |
2943 | #else | |
2944 | static inline void init_pl330_debugfs(struct pl330_dmac *pl330) | |
2945 | { | |
2946 | } | |
2947 | #endif | |
2948 | ||
b816ccc5 KK |
2949 | /* |
2950 | * Runtime PM callbacks are provided by amba/bus.c driver. | |
2951 | * | |
2952 | * It is assumed here that IRQ safe runtime PM is chosen in probe and amba | |
2953 | * bus driver will only disable/enable the clock in runtime PM callbacks. | |
2954 | */ | |
2955 | static int __maybe_unused pl330_suspend(struct device *dev) | |
2956 | { | |
2957 | struct amba_device *pcdev = to_amba_device(dev); | |
2958 | ||
2959 | pm_runtime_disable(dev); | |
2960 | ||
2961 | if (!pm_runtime_status_suspended(dev)) { | |
2962 | /* amba did not disable the clock */ | |
2963 | amba_pclk_disable(pcdev); | |
2964 | } | |
2965 | amba_pclk_unprepare(pcdev); | |
2966 | ||
2967 | return 0; | |
2968 | } | |
2969 | ||
2970 | static int __maybe_unused pl330_resume(struct device *dev) | |
2971 | { | |
2972 | struct amba_device *pcdev = to_amba_device(dev); | |
2973 | int ret; | |
2974 | ||
2975 | ret = amba_pclk_prepare(pcdev); | |
2976 | if (ret) | |
2977 | return ret; | |
2978 | ||
2979 | if (!pm_runtime_status_suspended(dev)) | |
2980 | ret = amba_pclk_enable(pcdev); | |
2981 | ||
2982 | pm_runtime_enable(dev); | |
2983 | ||
2984 | return ret; | |
2985 | } | |
2986 | ||
2987 | static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume); | |
2988 | ||
463a1f8b | 2989 | static int |
aa25afad | 2990 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 | 2991 | { |
f6f2421c LPC |
2992 | struct pl330_config *pcfg; |
2993 | struct pl330_dmac *pl330; | |
0b94c577 | 2994 | struct dma_pl330_chan *pch, *_p; |
b3040e40 JB |
2995 | struct dma_device *pd; |
2996 | struct resource *res; | |
2997 | int i, ret, irq; | |
4e0e6109 | 2998 | int num_chan; |
271e1b86 | 2999 | struct device_node *np = adev->dev.of_node; |
b3040e40 | 3000 | |
64113016 RK |
3001 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); |
3002 | if (ret) | |
3003 | return ret; | |
3004 | ||
b3040e40 | 3005 | /* Allocate a new DMAC and its Channels */ |
f6f2421c | 3006 | pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); |
aef94fea | 3007 | if (!pl330) |
b3040e40 | 3008 | return -ENOMEM; |
b3040e40 | 3009 | |
cee42392 AJ |
3010 | pd = &pl330->ddma; |
3011 | pd->dev = &adev->dev; | |
3012 | ||
e8bb4673 | 3013 | pl330->mcbufsz = 0; |
b3040e40 | 3014 | |
271e1b86 AK |
3015 | /* get quirk */ |
3016 | for (i = 0; i < ARRAY_SIZE(of_quirks); i++) | |
3017 | if (of_property_read_bool(np, of_quirks[i].quirk)) | |
3018 | pl330->quirks |= of_quirks[i].id; | |
3019 | ||
b3040e40 | 3020 | res = &adev->res; |
f6f2421c LPC |
3021 | pl330->base = devm_ioremap_resource(&adev->dev, res); |
3022 | if (IS_ERR(pl330->base)) | |
3023 | return PTR_ERR(pl330->base); | |
b3040e40 | 3024 | |
f6f2421c | 3025 | amba_set_drvdata(adev, pl330); |
a2f5203f | 3026 | |
02808b42 | 3027 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
e98b3caf MS |
3028 | irq = adev->irq[i]; |
3029 | if (irq) { | |
3030 | ret = devm_request_irq(&adev->dev, irq, | |
3031 | pl330_irq_handler, 0, | |
f6f2421c | 3032 | dev_name(&adev->dev), pl330); |
e98b3caf MS |
3033 | if (ret) |
3034 | return ret; | |
3035 | } else { | |
3036 | break; | |
3037 | } | |
3038 | } | |
b3040e40 | 3039 | |
f6f2421c LPC |
3040 | pcfg = &pl330->pcfg; |
3041 | ||
3042 | pcfg->periph_id = adev->periphid; | |
3043 | ret = pl330_add(pl330); | |
b3040e40 | 3044 | if (ret) |
173e838c | 3045 | return ret; |
b3040e40 | 3046 | |
f6f2421c LPC |
3047 | INIT_LIST_HEAD(&pl330->desc_pool); |
3048 | spin_lock_init(&pl330->pool_lock); | |
b3040e40 JB |
3049 | |
3050 | /* Create a descriptor pool of default size */ | |
e5887103 AK |
3051 | if (!add_desc(&pl330->desc_pool, &pl330->pool_lock, |
3052 | GFP_KERNEL, NR_DEFAULT_DESC)) | |
b3040e40 JB |
3053 | dev_warn(&adev->dev, "unable to allocate desc\n"); |
3054 | ||
b3040e40 JB |
3055 | INIT_LIST_HEAD(&pd->channels); |
3056 | ||
3057 | /* Initialize channel parameters */ | |
e8bb4673 | 3058 | num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); |
c8473828 | 3059 | |
f6f2421c | 3060 | pl330->num_peripherals = num_chan; |
70cbb163 | 3061 | |
6396bb22 | 3062 | pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL); |
f6f2421c | 3063 | if (!pl330->peripherals) { |
61c6e753 | 3064 | ret = -ENOMEM; |
e4d43c17 | 3065 | goto probe_err2; |
61c6e753 | 3066 | } |
b3040e40 | 3067 | |
4e0e6109 | 3068 | for (i = 0; i < num_chan; i++) { |
f6f2421c | 3069 | pch = &pl330->peripherals[i]; |
b3040e40 | 3070 | |
e8bb4673 | 3071 | pch->chan.private = adev->dev.of_node; |
04abf5da | 3072 | INIT_LIST_HEAD(&pch->submitted_list); |
b3040e40 | 3073 | INIT_LIST_HEAD(&pch->work_list); |
39ff8613 | 3074 | INIT_LIST_HEAD(&pch->completed_list); |
b3040e40 | 3075 | spin_lock_init(&pch->lock); |
65ad6060 | 3076 | pch->thread = NULL; |
b3040e40 | 3077 | pch->chan.device = pd; |
f6f2421c | 3078 | pch->dmac = pl330; |
4d6d74e2 | 3079 | pch->dir = DMA_NONE; |
b3040e40 JB |
3080 | |
3081 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
3082 | list_add_tail(&pch->chan.device_node, &pd->channels); |
3083 | } | |
3084 | ||
e8bb4673 MS |
3085 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
3086 | if (pcfg->num_peri) { | |
3087 | dma_cap_set(DMA_SLAVE, pd->cap_mask); | |
3088 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); | |
3089 | dma_cap_set(DMA_PRIVATE, pd->cap_mask); | |
93ed5544 | 3090 | } |
b3040e40 JB |
3091 | |
3092 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
3093 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
3094 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 3095 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
3096 | pd->device_tx_status = pl330_tx_status; |
3097 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
740aa957 | 3098 | pd->device_config = pl330_config; |
88987d2c | 3099 | pd->device_pause = pl330_pause; |
740aa957 | 3100 | pd->device_terminate_all = pl330_terminate_all; |
b3040e40 | 3101 | pd->device_issue_pending = pl330_issue_pending; |
dcabe456 MR |
3102 | pd->src_addr_widths = PL330_DMA_BUSWIDTHS; |
3103 | pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; | |
3104 | pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
e3f329c6 | 3105 | pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
86a8ce7d SL |
3106 | pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ? |
3107 | 1 : PL330_MAX_BURST); | |
b3040e40 JB |
3108 | |
3109 | ret = dma_async_device_register(pd); | |
3110 | if (ret) { | |
3111 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
0b94c577 PV |
3112 | goto probe_err3; |
3113 | } | |
3114 | ||
3115 | if (adev->dev.of_node) { | |
3116 | ret = of_dma_controller_register(adev->dev.of_node, | |
f6f2421c | 3117 | of_dma_pl330_xlate, pl330); |
0b94c577 PV |
3118 | if (ret) { |
3119 | dev_err(&adev->dev, | |
3120 | "unable to register DMA to the generic DT DMA helpers\n"); | |
3121 | } | |
b3040e40 | 3122 | } |
b714b84e | 3123 | |
f6f2421c | 3124 | adev->dev.dma_parms = &pl330->dma_parms; |
b714b84e | 3125 | |
dbaf6d85 VK |
3126 | /* |
3127 | * This is the limit for transfers with a buswidth of 1, larger | |
3128 | * buswidths will have larger limits. | |
3129 | */ | |
3130 | ret = dma_set_max_seg_size(&adev->dev, 1900800); | |
3131 | if (ret) | |
3132 | dev_err(&adev->dev, "unable to set the seg size\n"); | |
3133 | ||
b3040e40 | 3134 | |
b45aef3a | 3135 | init_pl330_debugfs(pl330); |
b3040e40 | 3136 | dev_info(&adev->dev, |
1f0a5cbf | 3137 | "Loaded driver for PL330 DMAC-%x\n", adev->periphid); |
b3040e40 JB |
3138 | dev_info(&adev->dev, |
3139 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
f6f2421c LPC |
3140 | pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, |
3141 | pcfg->num_peri, pcfg->num_events); | |
b3040e40 | 3142 | |
ae43b328 KK |
3143 | pm_runtime_irq_safe(&adev->dev); |
3144 | pm_runtime_use_autosuspend(&adev->dev); | |
3145 | pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); | |
3146 | pm_runtime_mark_last_busy(&adev->dev); | |
3147 | pm_runtime_put_autosuspend(&adev->dev); | |
3148 | ||
b3040e40 | 3149 | return 0; |
0b94c577 | 3150 | probe_err3: |
0b94c577 | 3151 | /* Idle the DMAC */ |
f6f2421c | 3152 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
0b94c577 PV |
3153 | chan.device_node) { |
3154 | ||
3155 | /* Remove the channel */ | |
3156 | list_del(&pch->chan.device_node); | |
3157 | ||
3158 | /* Flush the channel */ | |
0f5ebabd | 3159 | if (pch->thread) { |
740aa957 | 3160 | pl330_terminate_all(&pch->chan); |
0f5ebabd KK |
3161 | pl330_free_chan_resources(&pch->chan); |
3162 | } | |
0b94c577 | 3163 | } |
b3040e40 | 3164 | probe_err2: |
f6f2421c | 3165 | pl330_del(pl330); |
b3040e40 JB |
3166 | |
3167 | return ret; | |
3168 | } | |
3169 | ||
4bf27b8b | 3170 | static int pl330_remove(struct amba_device *adev) |
b3040e40 | 3171 | { |
f6f2421c | 3172 | struct pl330_dmac *pl330 = amba_get_drvdata(adev); |
b3040e40 | 3173 | struct dma_pl330_chan *pch, *_p; |
46cf94d6 | 3174 | int i, irq; |
b3040e40 | 3175 | |
ae43b328 KK |
3176 | pm_runtime_get_noresume(pl330->ddma.dev); |
3177 | ||
0b94c577 PV |
3178 | if (adev->dev.of_node) |
3179 | of_dma_controller_free(adev->dev.of_node); | |
421da89a | 3180 | |
46cf94d6 VK |
3181 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
3182 | irq = adev->irq[i]; | |
ebcdaee4 JPB |
3183 | if (irq) |
3184 | devm_free_irq(&adev->dev, irq, pl330); | |
46cf94d6 VK |
3185 | } |
3186 | ||
f6f2421c | 3187 | dma_async_device_unregister(&pl330->ddma); |
b3040e40 JB |
3188 | |
3189 | /* Idle the DMAC */ | |
f6f2421c | 3190 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
b3040e40 JB |
3191 | chan.device_node) { |
3192 | ||
3193 | /* Remove the channel */ | |
3194 | list_del(&pch->chan.device_node); | |
3195 | ||
3196 | /* Flush the channel */ | |
6e4a2a83 | 3197 | if (pch->thread) { |
740aa957 | 3198 | pl330_terminate_all(&pch->chan); |
6e4a2a83 KK |
3199 | pl330_free_chan_resources(&pch->chan); |
3200 | } | |
b3040e40 JB |
3201 | } |
3202 | ||
f6f2421c | 3203 | pl330_del(pl330); |
b3040e40 | 3204 | |
b3040e40 JB |
3205 | return 0; |
3206 | } | |
3207 | ||
b753351e | 3208 | static const struct amba_id pl330_ids[] = { |
b3040e40 JB |
3209 | { |
3210 | .id = 0x00041330, | |
3211 | .mask = 0x000fffff, | |
3212 | }, | |
3213 | { 0, 0 }, | |
3214 | }; | |
3215 | ||
e8fa516a DM |
3216 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
3217 | ||
b3040e40 JB |
3218 | static struct amba_driver pl330_driver = { |
3219 | .drv = { | |
3220 | .owner = THIS_MODULE, | |
3221 | .name = "dma-pl330", | |
b816ccc5 | 3222 | .pm = &pl330_pm, |
b3040e40 JB |
3223 | }, |
3224 | .id_table = pl330_ids, | |
3225 | .probe = pl330_probe, | |
3226 | .remove = pl330_remove, | |
3227 | }; | |
3228 | ||
9e5ed094 | 3229 | module_amba_driver(pl330_driver); |
b3040e40 | 3230 | |
046209f6 | 3231 | MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); |
b3040e40 JB |
3232 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); |
3233 | MODULE_LICENSE("GPL"); |