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b7d861d9 BK |
1 | /* |
2 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
b3040e40 JB |
4 | * |
5 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
6 | * Jaswinder Singh <jassi.brar@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
b7d861d9 | 14 | #include <linux/kernel.h> |
b3040e40 JB |
15 | #include <linux/io.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/module.h> | |
b7d861d9 BK |
19 | #include <linux/string.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/dma-mapping.h> | |
b3040e40 | 23 | #include <linux/dmaengine.h> |
b3040e40 JB |
24 | #include <linux/amba/bus.h> |
25 | #include <linux/amba/pl330.h> | |
1b9bb715 | 26 | #include <linux/scatterlist.h> |
93ed5544 | 27 | #include <linux/of.h> |
a80258f9 | 28 | #include <linux/of_dma.h> |
bcc7fa95 | 29 | #include <linux/err.h> |
b3040e40 | 30 | |
d2ebfb33 | 31 | #include "dmaengine.h" |
b7d861d9 BK |
32 | #define PL330_MAX_CHAN 8 |
33 | #define PL330_MAX_IRQS 32 | |
34 | #define PL330_MAX_PERI 32 | |
35 | ||
f0564c7e LPC |
36 | enum pl330_cachectrl { |
37 | CCTRL0, /* Noncacheable and nonbufferable */ | |
38 | CCTRL1, /* Bufferable only */ | |
39 | CCTRL2, /* Cacheable, but do not allocate */ | |
40 | CCTRL3, /* Cacheable and bufferable, but do not allocate */ | |
41 | INVALID1, /* AWCACHE = 0x1000 */ | |
42 | INVALID2, | |
43 | CCTRL6, /* Cacheable write-through, allocate on writes only */ | |
44 | CCTRL7, /* Cacheable write-back, allocate on writes only */ | |
b7d861d9 BK |
45 | }; |
46 | ||
47 | enum pl330_byteswap { | |
48 | SWAP_NO, | |
49 | SWAP_2, | |
50 | SWAP_4, | |
51 | SWAP_8, | |
52 | SWAP_16, | |
53 | }; | |
54 | ||
b7d861d9 BK |
55 | /* Register and Bit field Definitions */ |
56 | #define DS 0x0 | |
57 | #define DS_ST_STOP 0x0 | |
58 | #define DS_ST_EXEC 0x1 | |
59 | #define DS_ST_CMISS 0x2 | |
60 | #define DS_ST_UPDTPC 0x3 | |
61 | #define DS_ST_WFE 0x4 | |
62 | #define DS_ST_ATBRR 0x5 | |
63 | #define DS_ST_QBUSY 0x6 | |
64 | #define DS_ST_WFP 0x7 | |
65 | #define DS_ST_KILL 0x8 | |
66 | #define DS_ST_CMPLT 0x9 | |
67 | #define DS_ST_FLTCMP 0xe | |
68 | #define DS_ST_FAULT 0xf | |
69 | ||
70 | #define DPC 0x4 | |
71 | #define INTEN 0x20 | |
72 | #define ES 0x24 | |
73 | #define INTSTATUS 0x28 | |
74 | #define INTCLR 0x2c | |
75 | #define FSM 0x30 | |
76 | #define FSC 0x34 | |
77 | #define FTM 0x38 | |
78 | ||
79 | #define _FTC 0x40 | |
80 | #define FTC(n) (_FTC + (n)*0x4) | |
81 | ||
82 | #define _CS 0x100 | |
83 | #define CS(n) (_CS + (n)*0x8) | |
84 | #define CS_CNS (1 << 21) | |
85 | ||
86 | #define _CPC 0x104 | |
87 | #define CPC(n) (_CPC + (n)*0x8) | |
88 | ||
89 | #define _SA 0x400 | |
90 | #define SA(n) (_SA + (n)*0x20) | |
91 | ||
92 | #define _DA 0x404 | |
93 | #define DA(n) (_DA + (n)*0x20) | |
94 | ||
95 | #define _CC 0x408 | |
96 | #define CC(n) (_CC + (n)*0x20) | |
97 | ||
98 | #define CC_SRCINC (1 << 0) | |
99 | #define CC_DSTINC (1 << 14) | |
100 | #define CC_SRCPRI (1 << 8) | |
101 | #define CC_DSTPRI (1 << 22) | |
102 | #define CC_SRCNS (1 << 9) | |
103 | #define CC_DSTNS (1 << 23) | |
104 | #define CC_SRCIA (1 << 10) | |
105 | #define CC_DSTIA (1 << 24) | |
106 | #define CC_SRCBRSTLEN_SHFT 4 | |
107 | #define CC_DSTBRSTLEN_SHFT 18 | |
108 | #define CC_SRCBRSTSIZE_SHFT 1 | |
109 | #define CC_DSTBRSTSIZE_SHFT 15 | |
110 | #define CC_SRCCCTRL_SHFT 11 | |
111 | #define CC_SRCCCTRL_MASK 0x7 | |
112 | #define CC_DSTCCTRL_SHFT 25 | |
113 | #define CC_DRCCCTRL_MASK 0x7 | |
114 | #define CC_SWAP_SHFT 28 | |
115 | ||
116 | #define _LC0 0x40c | |
117 | #define LC0(n) (_LC0 + (n)*0x20) | |
118 | ||
119 | #define _LC1 0x410 | |
120 | #define LC1(n) (_LC1 + (n)*0x20) | |
121 | ||
122 | #define DBGSTATUS 0xd00 | |
123 | #define DBG_BUSY (1 << 0) | |
124 | ||
125 | #define DBGCMD 0xd04 | |
126 | #define DBGINST0 0xd08 | |
127 | #define DBGINST1 0xd0c | |
128 | ||
129 | #define CR0 0xe00 | |
130 | #define CR1 0xe04 | |
131 | #define CR2 0xe08 | |
132 | #define CR3 0xe0c | |
133 | #define CR4 0xe10 | |
134 | #define CRD 0xe14 | |
135 | ||
136 | #define PERIPH_ID 0xfe0 | |
3ecf51a4 BK |
137 | #define PERIPH_REV_SHIFT 20 |
138 | #define PERIPH_REV_MASK 0xf | |
139 | #define PERIPH_REV_R0P0 0 | |
140 | #define PERIPH_REV_R1P0 1 | |
141 | #define PERIPH_REV_R1P1 2 | |
b7d861d9 BK |
142 | |
143 | #define CR0_PERIPH_REQ_SET (1 << 0) | |
144 | #define CR0_BOOT_EN_SET (1 << 1) | |
145 | #define CR0_BOOT_MAN_NS (1 << 2) | |
146 | #define CR0_NUM_CHANS_SHIFT 4 | |
147 | #define CR0_NUM_CHANS_MASK 0x7 | |
148 | #define CR0_NUM_PERIPH_SHIFT 12 | |
149 | #define CR0_NUM_PERIPH_MASK 0x1f | |
150 | #define CR0_NUM_EVENTS_SHIFT 17 | |
151 | #define CR0_NUM_EVENTS_MASK 0x1f | |
152 | ||
153 | #define CR1_ICACHE_LEN_SHIFT 0 | |
154 | #define CR1_ICACHE_LEN_MASK 0x7 | |
155 | #define CR1_NUM_ICACHELINES_SHIFT 4 | |
156 | #define CR1_NUM_ICACHELINES_MASK 0xf | |
157 | ||
158 | #define CRD_DATA_WIDTH_SHIFT 0 | |
159 | #define CRD_DATA_WIDTH_MASK 0x7 | |
160 | #define CRD_WR_CAP_SHIFT 4 | |
161 | #define CRD_WR_CAP_MASK 0x7 | |
162 | #define CRD_WR_Q_DEP_SHIFT 8 | |
163 | #define CRD_WR_Q_DEP_MASK 0xf | |
164 | #define CRD_RD_CAP_SHIFT 12 | |
165 | #define CRD_RD_CAP_MASK 0x7 | |
166 | #define CRD_RD_Q_DEP_SHIFT 16 | |
167 | #define CRD_RD_Q_DEP_MASK 0xf | |
168 | #define CRD_DATA_BUFF_SHIFT 20 | |
169 | #define CRD_DATA_BUFF_MASK 0x3ff | |
170 | ||
171 | #define PART 0x330 | |
172 | #define DESIGNER 0x41 | |
173 | #define REVISION 0x0 | |
174 | #define INTEG_CFG 0x0 | |
175 | #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) | |
176 | ||
b7d861d9 BK |
177 | #define PL330_STATE_STOPPED (1 << 0) |
178 | #define PL330_STATE_EXECUTING (1 << 1) | |
179 | #define PL330_STATE_WFE (1 << 2) | |
180 | #define PL330_STATE_FAULTING (1 << 3) | |
181 | #define PL330_STATE_COMPLETING (1 << 4) | |
182 | #define PL330_STATE_WFP (1 << 5) | |
183 | #define PL330_STATE_KILLING (1 << 6) | |
184 | #define PL330_STATE_FAULT_COMPLETING (1 << 7) | |
185 | #define PL330_STATE_CACHEMISS (1 << 8) | |
186 | #define PL330_STATE_UPDTPC (1 << 9) | |
187 | #define PL330_STATE_ATBARRIER (1 << 10) | |
188 | #define PL330_STATE_QUEUEBUSY (1 << 11) | |
189 | #define PL330_STATE_INVALID (1 << 15) | |
190 | ||
191 | #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | |
192 | | PL330_STATE_WFE | PL330_STATE_FAULTING) | |
193 | ||
194 | #define CMD_DMAADDH 0x54 | |
195 | #define CMD_DMAEND 0x00 | |
196 | #define CMD_DMAFLUSHP 0x35 | |
197 | #define CMD_DMAGO 0xa0 | |
198 | #define CMD_DMALD 0x04 | |
199 | #define CMD_DMALDP 0x25 | |
200 | #define CMD_DMALP 0x20 | |
201 | #define CMD_DMALPEND 0x28 | |
202 | #define CMD_DMAKILL 0x01 | |
203 | #define CMD_DMAMOV 0xbc | |
204 | #define CMD_DMANOP 0x18 | |
205 | #define CMD_DMARMB 0x12 | |
206 | #define CMD_DMASEV 0x34 | |
207 | #define CMD_DMAST 0x08 | |
208 | #define CMD_DMASTP 0x29 | |
209 | #define CMD_DMASTZ 0x0c | |
210 | #define CMD_DMAWFE 0x36 | |
211 | #define CMD_DMAWFP 0x30 | |
212 | #define CMD_DMAWMB 0x13 | |
213 | ||
214 | #define SZ_DMAADDH 3 | |
215 | #define SZ_DMAEND 1 | |
216 | #define SZ_DMAFLUSHP 2 | |
217 | #define SZ_DMALD 1 | |
218 | #define SZ_DMALDP 2 | |
219 | #define SZ_DMALP 2 | |
220 | #define SZ_DMALPEND 2 | |
221 | #define SZ_DMAKILL 1 | |
222 | #define SZ_DMAMOV 6 | |
223 | #define SZ_DMANOP 1 | |
224 | #define SZ_DMARMB 1 | |
225 | #define SZ_DMASEV 2 | |
226 | #define SZ_DMAST 1 | |
227 | #define SZ_DMASTP 2 | |
228 | #define SZ_DMASTZ 1 | |
229 | #define SZ_DMAWFE 2 | |
230 | #define SZ_DMAWFP 2 | |
231 | #define SZ_DMAWMB 1 | |
232 | #define SZ_DMAGO 6 | |
233 | ||
234 | #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) | |
235 | #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) | |
236 | ||
237 | #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) | |
238 | #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) | |
239 | ||
240 | /* | |
241 | * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req | |
242 | * at 1byte/burst for P<->M and M<->M respectively. | |
243 | * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req | |
244 | * should be enough for P<->M and M<->M respectively. | |
245 | */ | |
246 | #define MCODE_BUFF_PER_REQ 256 | |
247 | ||
248 | /* If the _pl330_req is available to the client */ | |
249 | #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND) | |
250 | ||
251 | /* Use this _only_ to wait on transient states */ | |
252 | #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); | |
253 | ||
254 | #ifdef PL330_DEBUG_MCGEN | |
255 | static unsigned cmd_line; | |
256 | #define PL330_DBGCMD_DUMP(off, x...) do { \ | |
257 | printk("%x:", cmd_line); \ | |
258 | printk(x); \ | |
259 | cmd_line += off; \ | |
260 | } while (0) | |
261 | #define PL330_DBGMC_START(addr) (cmd_line = addr) | |
262 | #else | |
263 | #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) | |
264 | #define PL330_DBGMC_START(addr) do {} while (0) | |
265 | #endif | |
266 | ||
267 | /* The number of default descriptors */ | |
d2ebfb33 | 268 | |
b3040e40 JB |
269 | #define NR_DEFAULT_DESC 16 |
270 | ||
b7d861d9 BK |
271 | /* Populated by the PL330 core driver for DMA API driver's info */ |
272 | struct pl330_config { | |
273 | u32 periph_id; | |
b7d861d9 BK |
274 | #define DMAC_MODE_NS (1 << 0) |
275 | unsigned int mode; | |
276 | unsigned int data_bus_width:10; /* In number of bits */ | |
277 | unsigned int data_buf_dep:10; | |
278 | unsigned int num_chan:4; | |
279 | unsigned int num_peri:6; | |
280 | u32 peri_ns; | |
281 | unsigned int num_events:6; | |
282 | u32 irq_ns; | |
283 | }; | |
284 | ||
285 | /* Handle to the DMAC provided to the PL330 core */ | |
286 | struct pl330_info { | |
287 | /* Owning device */ | |
288 | struct device *dev; | |
289 | /* Size of MicroCode buffers for each channel. */ | |
290 | unsigned mcbufsz; | |
291 | /* ioremap'ed address of PL330 registers. */ | |
292 | void __iomem *base; | |
b7d861d9 BK |
293 | /* PL330 core data, Client must not touch it. */ |
294 | void *pl330_data; | |
295 | /* Populated by the PL330 core driver during pl330_add */ | |
296 | struct pl330_config pcfg; | |
b7d861d9 BK |
297 | }; |
298 | ||
299 | /** | |
300 | * Request Configuration. | |
301 | * The PL330 core does not modify this and uses the last | |
302 | * working configuration if the request doesn't provide any. | |
303 | * | |
304 | * The Client may want to provide this info only for the | |
305 | * first request and a request with new settings. | |
306 | */ | |
307 | struct pl330_reqcfg { | |
308 | /* Address Incrementing */ | |
309 | unsigned dst_inc:1; | |
310 | unsigned src_inc:1; | |
311 | ||
312 | /* | |
313 | * For now, the SRC & DST protection levels | |
314 | * and burst size/length are assumed same. | |
315 | */ | |
316 | bool nonsecure; | |
317 | bool privileged; | |
318 | bool insnaccess; | |
319 | unsigned brst_len:5; | |
320 | unsigned brst_size:3; /* in power of 2 */ | |
321 | ||
f0564c7e LPC |
322 | enum pl330_cachectrl dcctl; |
323 | enum pl330_cachectrl scctl; | |
b7d861d9 | 324 | enum pl330_byteswap swap; |
3ecf51a4 | 325 | struct pl330_config *pcfg; |
b7d861d9 BK |
326 | }; |
327 | ||
328 | /* | |
329 | * One cycle of DMAC operation. | |
330 | * There may be more than one xfer in a request. | |
331 | */ | |
332 | struct pl330_xfer { | |
333 | u32 src_addr; | |
334 | u32 dst_addr; | |
335 | /* Size to xfer */ | |
336 | u32 bytes; | |
b7d861d9 BK |
337 | }; |
338 | ||
339 | /* The xfer callbacks are made with one of these arguments. */ | |
340 | enum pl330_op_err { | |
341 | /* The all xfers in the request were success. */ | |
342 | PL330_ERR_NONE, | |
343 | /* If req aborted due to global error. */ | |
344 | PL330_ERR_ABORT, | |
345 | /* If req failed due to problem with Channel. */ | |
346 | PL330_ERR_FAIL, | |
347 | }; | |
348 | ||
349 | /* A request defining Scatter-Gather List ending with NULL xfer. */ | |
350 | struct pl330_req { | |
585a9d0b | 351 | enum dma_transfer_direction rqtype; |
b7d861d9 BK |
352 | /* Index of peripheral for the xfer. */ |
353 | unsigned peri:5; | |
b7d861d9 BK |
354 | /* If NULL, req will be done at last set parameters. */ |
355 | struct pl330_reqcfg *cfg; | |
356 | /* Pointer to first xfer in the request. */ | |
357 | struct pl330_xfer *x; | |
fdec53d5 JM |
358 | /* Hook to attach to DMAC's list of reqs with due callback */ |
359 | struct list_head rqd; | |
b7d861d9 BK |
360 | }; |
361 | ||
b7d861d9 BK |
362 | enum pl330_chan_op { |
363 | /* Start the channel */ | |
364 | PL330_OP_START, | |
365 | /* Abort the active xfer */ | |
366 | PL330_OP_ABORT, | |
367 | /* Stop xfer and flush queue */ | |
368 | PL330_OP_FLUSH, | |
369 | }; | |
370 | ||
371 | struct _xfer_spec { | |
372 | u32 ccr; | |
373 | struct pl330_req *r; | |
374 | struct pl330_xfer *x; | |
375 | }; | |
376 | ||
377 | enum dmamov_dst { | |
378 | SAR = 0, | |
379 | CCR, | |
380 | DAR, | |
381 | }; | |
382 | ||
383 | enum pl330_dst { | |
384 | SRC = 0, | |
385 | DST, | |
386 | }; | |
387 | ||
388 | enum pl330_cond { | |
389 | SINGLE, | |
390 | BURST, | |
391 | ALWAYS, | |
392 | }; | |
393 | ||
394 | struct _pl330_req { | |
395 | u32 mc_bus; | |
396 | void *mc_cpu; | |
b7d861d9 | 397 | struct pl330_req *r; |
b7d861d9 BK |
398 | }; |
399 | ||
400 | /* ToBeDone for tasklet */ | |
401 | struct _pl330_tbd { | |
402 | bool reset_dmac; | |
403 | bool reset_mngr; | |
404 | u8 reset_chan; | |
405 | }; | |
406 | ||
407 | /* A DMAC Thread */ | |
408 | struct pl330_thread { | |
409 | u8 id; | |
410 | int ev; | |
411 | /* If the channel is not yet acquired by any client */ | |
412 | bool free; | |
413 | /* Parent DMAC */ | |
414 | struct pl330_dmac *dmac; | |
415 | /* Only two at a time */ | |
416 | struct _pl330_req req[2]; | |
417 | /* Index of the last enqueued request */ | |
418 | unsigned lstenq; | |
419 | /* Index of the last submitted request or -1 if the DMA is stopped */ | |
420 | int req_running; | |
421 | }; | |
422 | ||
423 | enum pl330_dmac_state { | |
424 | UNINIT, | |
425 | INIT, | |
426 | DYING, | |
427 | }; | |
428 | ||
429 | /* A DMAC */ | |
430 | struct pl330_dmac { | |
431 | spinlock_t lock; | |
432 | /* Holds list of reqs with due callbacks */ | |
433 | struct list_head req_done; | |
434 | /* Pointer to platform specific stuff */ | |
435 | struct pl330_info *pinfo; | |
436 | /* Maximum possible events/irqs */ | |
437 | int events[32]; | |
438 | /* BUS address of MicroCode buffer */ | |
fed8c457 | 439 | dma_addr_t mcode_bus; |
b7d861d9 BK |
440 | /* CPU address of MicroCode buffer */ |
441 | void *mcode_cpu; | |
442 | /* List of all Channel threads */ | |
443 | struct pl330_thread *channels; | |
444 | /* Pointer to the MANAGER thread */ | |
445 | struct pl330_thread *manager; | |
446 | /* To handle bad news in interrupt */ | |
447 | struct tasklet_struct tasks; | |
448 | struct _pl330_tbd dmac_tbd; | |
449 | /* State of DMAC operation */ | |
450 | enum pl330_dmac_state state; | |
451 | }; | |
452 | ||
b3040e40 JB |
453 | enum desc_status { |
454 | /* In the DMAC pool */ | |
455 | FREE, | |
456 | /* | |
d73111c6 | 457 | * Allocated to some channel during prep_xxx |
b3040e40 JB |
458 | * Also may be sitting on the work_list. |
459 | */ | |
460 | PREP, | |
461 | /* | |
462 | * Sitting on the work_list and already submitted | |
463 | * to the PL330 core. Not more than two descriptors | |
464 | * of a channel can be BUSY at any time. | |
465 | */ | |
466 | BUSY, | |
467 | /* | |
468 | * Sitting on the channel work_list but xfer done | |
469 | * by PL330 core | |
470 | */ | |
471 | DONE, | |
472 | }; | |
473 | ||
474 | struct dma_pl330_chan { | |
475 | /* Schedule desc completion */ | |
476 | struct tasklet_struct task; | |
477 | ||
478 | /* DMA-Engine Channel */ | |
479 | struct dma_chan chan; | |
480 | ||
04abf5da LPC |
481 | /* List of submitted descriptors */ |
482 | struct list_head submitted_list; | |
483 | /* List of issued descriptors */ | |
b3040e40 | 484 | struct list_head work_list; |
39ff8613 LPC |
485 | /* List of completed descriptors */ |
486 | struct list_head completed_list; | |
b3040e40 JB |
487 | |
488 | /* Pointer to the DMAC that manages this channel, | |
489 | * NULL if the channel is available to be acquired. | |
490 | * As the parent, this DMAC also provides descriptors | |
491 | * to the channel. | |
492 | */ | |
493 | struct dma_pl330_dmac *dmac; | |
494 | ||
495 | /* To protect channel manipulation */ | |
496 | spinlock_t lock; | |
497 | ||
498 | /* Token of a hardware channel thread of PL330 DMAC | |
499 | * NULL if the channel is available to be acquired. | |
500 | */ | |
501 | void *pl330_chid; | |
1b9bb715 BK |
502 | |
503 | /* For D-to-M and M-to-D channels */ | |
504 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 505 | int burst_len; /* the number of burst */ |
1b9bb715 | 506 | dma_addr_t fifo_addr; |
42bc9cf4 BK |
507 | |
508 | /* for cyclic capability */ | |
509 | bool cyclic; | |
b3040e40 JB |
510 | }; |
511 | ||
512 | struct dma_pl330_dmac { | |
513 | struct pl330_info pif; | |
514 | ||
515 | /* DMA-Engine Device */ | |
516 | struct dma_device ddma; | |
517 | ||
b714b84e LPC |
518 | /* Holds info about sg limitations */ |
519 | struct device_dma_parameters dma_parms; | |
520 | ||
b3040e40 JB |
521 | /* Pool of descriptors available for the DMAC's channels */ |
522 | struct list_head desc_pool; | |
523 | /* To protect desc_pool manipulation */ | |
524 | spinlock_t pool_lock; | |
525 | ||
526 | /* Peripheral channels connected to this DMAC */ | |
70cbb163 | 527 | unsigned int num_peripherals; |
4e0e6109 | 528 | struct dma_pl330_chan *peripherals; /* keep at end */ |
b3040e40 JB |
529 | }; |
530 | ||
531 | struct dma_pl330_desc { | |
532 | /* To attach to a queue as child */ | |
533 | struct list_head node; | |
534 | ||
535 | /* Descriptor for the DMA Engine API */ | |
536 | struct dma_async_tx_descriptor txd; | |
537 | ||
538 | /* Xfer for PL330 core */ | |
539 | struct pl330_xfer px; | |
540 | ||
541 | struct pl330_reqcfg rqcfg; | |
542 | struct pl330_req req; | |
543 | ||
544 | enum desc_status status; | |
545 | ||
546 | /* The channel which currently holds this desc */ | |
547 | struct dma_pl330_chan *pchan; | |
548 | }; | |
549 | ||
b7d861d9 BK |
550 | static inline bool _queue_empty(struct pl330_thread *thrd) |
551 | { | |
552 | return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1])) | |
553 | ? true : false; | |
554 | } | |
555 | ||
556 | static inline bool _queue_full(struct pl330_thread *thrd) | |
557 | { | |
558 | return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1])) | |
559 | ? false : true; | |
560 | } | |
561 | ||
562 | static inline bool is_manager(struct pl330_thread *thrd) | |
563 | { | |
564 | struct pl330_dmac *pl330 = thrd->dmac; | |
565 | ||
566 | /* MANAGER is indexed at the end */ | |
567 | if (thrd->id == pl330->pinfo->pcfg.num_chan) | |
568 | return true; | |
569 | else | |
570 | return false; | |
571 | } | |
572 | ||
573 | /* If manager of the thread is in Non-Secure mode */ | |
574 | static inline bool _manager_ns(struct pl330_thread *thrd) | |
575 | { | |
576 | struct pl330_dmac *pl330 = thrd->dmac; | |
577 | ||
578 | return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false; | |
579 | } | |
580 | ||
3ecf51a4 BK |
581 | static inline u32 get_revision(u32 periph_id) |
582 | { | |
583 | return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; | |
584 | } | |
585 | ||
b7d861d9 BK |
586 | static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], |
587 | enum pl330_dst da, u16 val) | |
588 | { | |
589 | if (dry_run) | |
590 | return SZ_DMAADDH; | |
591 | ||
592 | buf[0] = CMD_DMAADDH; | |
593 | buf[0] |= (da << 1); | |
594 | *((u16 *)&buf[1]) = val; | |
595 | ||
596 | PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", | |
597 | da == 1 ? "DA" : "SA", val); | |
598 | ||
599 | return SZ_DMAADDH; | |
600 | } | |
601 | ||
602 | static inline u32 _emit_END(unsigned dry_run, u8 buf[]) | |
603 | { | |
604 | if (dry_run) | |
605 | return SZ_DMAEND; | |
606 | ||
607 | buf[0] = CMD_DMAEND; | |
608 | ||
609 | PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); | |
610 | ||
611 | return SZ_DMAEND; | |
612 | } | |
613 | ||
614 | static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) | |
615 | { | |
616 | if (dry_run) | |
617 | return SZ_DMAFLUSHP; | |
618 | ||
619 | buf[0] = CMD_DMAFLUSHP; | |
620 | ||
621 | peri &= 0x1f; | |
622 | peri <<= 3; | |
623 | buf[1] = peri; | |
624 | ||
625 | PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); | |
626 | ||
627 | return SZ_DMAFLUSHP; | |
628 | } | |
629 | ||
630 | static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
631 | { | |
632 | if (dry_run) | |
633 | return SZ_DMALD; | |
634 | ||
635 | buf[0] = CMD_DMALD; | |
636 | ||
637 | if (cond == SINGLE) | |
638 | buf[0] |= (0 << 1) | (1 << 0); | |
639 | else if (cond == BURST) | |
640 | buf[0] |= (1 << 1) | (1 << 0); | |
641 | ||
642 | PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", | |
643 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
644 | ||
645 | return SZ_DMALD; | |
646 | } | |
647 | ||
648 | static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], | |
649 | enum pl330_cond cond, u8 peri) | |
650 | { | |
651 | if (dry_run) | |
652 | return SZ_DMALDP; | |
653 | ||
654 | buf[0] = CMD_DMALDP; | |
655 | ||
656 | if (cond == BURST) | |
657 | buf[0] |= (1 << 1); | |
658 | ||
659 | peri &= 0x1f; | |
660 | peri <<= 3; | |
661 | buf[1] = peri; | |
662 | ||
663 | PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", | |
664 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
665 | ||
666 | return SZ_DMALDP; | |
667 | } | |
668 | ||
669 | static inline u32 _emit_LP(unsigned dry_run, u8 buf[], | |
670 | unsigned loop, u8 cnt) | |
671 | { | |
672 | if (dry_run) | |
673 | return SZ_DMALP; | |
674 | ||
675 | buf[0] = CMD_DMALP; | |
676 | ||
677 | if (loop) | |
678 | buf[0] |= (1 << 1); | |
679 | ||
680 | cnt--; /* DMAC increments by 1 internally */ | |
681 | buf[1] = cnt; | |
682 | ||
683 | PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); | |
684 | ||
685 | return SZ_DMALP; | |
686 | } | |
687 | ||
688 | struct _arg_LPEND { | |
689 | enum pl330_cond cond; | |
690 | bool forever; | |
691 | unsigned loop; | |
692 | u8 bjump; | |
693 | }; | |
694 | ||
695 | static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], | |
696 | const struct _arg_LPEND *arg) | |
697 | { | |
698 | enum pl330_cond cond = arg->cond; | |
699 | bool forever = arg->forever; | |
700 | unsigned loop = arg->loop; | |
701 | u8 bjump = arg->bjump; | |
702 | ||
703 | if (dry_run) | |
704 | return SZ_DMALPEND; | |
705 | ||
706 | buf[0] = CMD_DMALPEND; | |
707 | ||
708 | if (loop) | |
709 | buf[0] |= (1 << 2); | |
710 | ||
711 | if (!forever) | |
712 | buf[0] |= (1 << 4); | |
713 | ||
714 | if (cond == SINGLE) | |
715 | buf[0] |= (0 << 1) | (1 << 0); | |
716 | else if (cond == BURST) | |
717 | buf[0] |= (1 << 1) | (1 << 0); | |
718 | ||
719 | buf[1] = bjump; | |
720 | ||
721 | PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", | |
722 | forever ? "FE" : "END", | |
723 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), | |
724 | loop ? '1' : '0', | |
725 | bjump); | |
726 | ||
727 | return SZ_DMALPEND; | |
728 | } | |
729 | ||
730 | static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) | |
731 | { | |
732 | if (dry_run) | |
733 | return SZ_DMAKILL; | |
734 | ||
735 | buf[0] = CMD_DMAKILL; | |
736 | ||
737 | return SZ_DMAKILL; | |
738 | } | |
739 | ||
740 | static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], | |
741 | enum dmamov_dst dst, u32 val) | |
742 | { | |
743 | if (dry_run) | |
744 | return SZ_DMAMOV; | |
745 | ||
746 | buf[0] = CMD_DMAMOV; | |
747 | buf[1] = dst; | |
748 | *((u32 *)&buf[2]) = val; | |
749 | ||
750 | PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", | |
751 | dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); | |
752 | ||
753 | return SZ_DMAMOV; | |
754 | } | |
755 | ||
756 | static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) | |
757 | { | |
758 | if (dry_run) | |
759 | return SZ_DMANOP; | |
760 | ||
761 | buf[0] = CMD_DMANOP; | |
762 | ||
763 | PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); | |
764 | ||
765 | return SZ_DMANOP; | |
766 | } | |
767 | ||
768 | static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) | |
769 | { | |
770 | if (dry_run) | |
771 | return SZ_DMARMB; | |
772 | ||
773 | buf[0] = CMD_DMARMB; | |
774 | ||
775 | PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); | |
776 | ||
777 | return SZ_DMARMB; | |
778 | } | |
779 | ||
780 | static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) | |
781 | { | |
782 | if (dry_run) | |
783 | return SZ_DMASEV; | |
784 | ||
785 | buf[0] = CMD_DMASEV; | |
786 | ||
787 | ev &= 0x1f; | |
788 | ev <<= 3; | |
789 | buf[1] = ev; | |
790 | ||
791 | PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); | |
792 | ||
793 | return SZ_DMASEV; | |
794 | } | |
795 | ||
796 | static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
797 | { | |
798 | if (dry_run) | |
799 | return SZ_DMAST; | |
800 | ||
801 | buf[0] = CMD_DMAST; | |
802 | ||
803 | if (cond == SINGLE) | |
804 | buf[0] |= (0 << 1) | (1 << 0); | |
805 | else if (cond == BURST) | |
806 | buf[0] |= (1 << 1) | (1 << 0); | |
807 | ||
808 | PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", | |
809 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
810 | ||
811 | return SZ_DMAST; | |
812 | } | |
813 | ||
814 | static inline u32 _emit_STP(unsigned dry_run, u8 buf[], | |
815 | enum pl330_cond cond, u8 peri) | |
816 | { | |
817 | if (dry_run) | |
818 | return SZ_DMASTP; | |
819 | ||
820 | buf[0] = CMD_DMASTP; | |
821 | ||
822 | if (cond == BURST) | |
823 | buf[0] |= (1 << 1); | |
824 | ||
825 | peri &= 0x1f; | |
826 | peri <<= 3; | |
827 | buf[1] = peri; | |
828 | ||
829 | PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", | |
830 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
831 | ||
832 | return SZ_DMASTP; | |
833 | } | |
834 | ||
835 | static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) | |
836 | { | |
837 | if (dry_run) | |
838 | return SZ_DMASTZ; | |
839 | ||
840 | buf[0] = CMD_DMASTZ; | |
841 | ||
842 | PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); | |
843 | ||
844 | return SZ_DMASTZ; | |
845 | } | |
846 | ||
847 | static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, | |
848 | unsigned invalidate) | |
849 | { | |
850 | if (dry_run) | |
851 | return SZ_DMAWFE; | |
852 | ||
853 | buf[0] = CMD_DMAWFE; | |
854 | ||
855 | ev &= 0x1f; | |
856 | ev <<= 3; | |
857 | buf[1] = ev; | |
858 | ||
859 | if (invalidate) | |
860 | buf[1] |= (1 << 1); | |
861 | ||
862 | PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", | |
863 | ev >> 3, invalidate ? ", I" : ""); | |
864 | ||
865 | return SZ_DMAWFE; | |
866 | } | |
867 | ||
868 | static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], | |
869 | enum pl330_cond cond, u8 peri) | |
870 | { | |
871 | if (dry_run) | |
872 | return SZ_DMAWFP; | |
873 | ||
874 | buf[0] = CMD_DMAWFP; | |
875 | ||
876 | if (cond == SINGLE) | |
877 | buf[0] |= (0 << 1) | (0 << 0); | |
878 | else if (cond == BURST) | |
879 | buf[0] |= (1 << 1) | (0 << 0); | |
880 | else | |
881 | buf[0] |= (0 << 1) | (1 << 0); | |
882 | ||
883 | peri &= 0x1f; | |
884 | peri <<= 3; | |
885 | buf[1] = peri; | |
886 | ||
887 | PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", | |
888 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); | |
889 | ||
890 | return SZ_DMAWFP; | |
891 | } | |
892 | ||
893 | static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) | |
894 | { | |
895 | if (dry_run) | |
896 | return SZ_DMAWMB; | |
897 | ||
898 | buf[0] = CMD_DMAWMB; | |
899 | ||
900 | PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); | |
901 | ||
902 | return SZ_DMAWMB; | |
903 | } | |
904 | ||
905 | struct _arg_GO { | |
906 | u8 chan; | |
907 | u32 addr; | |
908 | unsigned ns; | |
909 | }; | |
910 | ||
911 | static inline u32 _emit_GO(unsigned dry_run, u8 buf[], | |
912 | const struct _arg_GO *arg) | |
913 | { | |
914 | u8 chan = arg->chan; | |
915 | u32 addr = arg->addr; | |
916 | unsigned ns = arg->ns; | |
917 | ||
918 | if (dry_run) | |
919 | return SZ_DMAGO; | |
920 | ||
921 | buf[0] = CMD_DMAGO; | |
922 | buf[0] |= (ns << 1); | |
923 | ||
924 | buf[1] = chan & 0x7; | |
925 | ||
926 | *((u32 *)&buf[2]) = addr; | |
927 | ||
928 | return SZ_DMAGO; | |
929 | } | |
930 | ||
931 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
932 | ||
933 | /* Returns Time-Out */ | |
934 | static bool _until_dmac_idle(struct pl330_thread *thrd) | |
935 | { | |
936 | void __iomem *regs = thrd->dmac->pinfo->base; | |
937 | unsigned long loops = msecs_to_loops(5); | |
938 | ||
939 | do { | |
940 | /* Until Manager is Idle */ | |
941 | if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) | |
942 | break; | |
943 | ||
944 | cpu_relax(); | |
945 | } while (--loops); | |
946 | ||
947 | if (!loops) | |
948 | return true; | |
949 | ||
950 | return false; | |
951 | } | |
952 | ||
953 | static inline void _execute_DBGINSN(struct pl330_thread *thrd, | |
954 | u8 insn[], bool as_manager) | |
955 | { | |
956 | void __iomem *regs = thrd->dmac->pinfo->base; | |
957 | u32 val; | |
958 | ||
959 | val = (insn[0] << 16) | (insn[1] << 24); | |
960 | if (!as_manager) { | |
961 | val |= (1 << 0); | |
962 | val |= (thrd->id << 8); /* Channel Number */ | |
963 | } | |
964 | writel(val, regs + DBGINST0); | |
965 | ||
966 | val = *((u32 *)&insn[2]); | |
967 | writel(val, regs + DBGINST1); | |
968 | ||
969 | /* If timed out due to halted state-machine */ | |
970 | if (_until_dmac_idle(thrd)) { | |
971 | dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n"); | |
972 | return; | |
973 | } | |
974 | ||
975 | /* Get going */ | |
976 | writel(0, regs + DBGCMD); | |
977 | } | |
978 | ||
979 | /* | |
980 | * Mark a _pl330_req as free. | |
981 | * We do it by writing DMAEND as the first instruction | |
982 | * because no valid request is going to have DMAEND as | |
983 | * its first instruction to execute. | |
984 | */ | |
985 | static void mark_free(struct pl330_thread *thrd, int idx) | |
986 | { | |
987 | struct _pl330_req *req = &thrd->req[idx]; | |
988 | ||
989 | _emit_END(0, req->mc_cpu); | |
b7d861d9 BK |
990 | |
991 | thrd->req_running = -1; | |
992 | } | |
993 | ||
994 | static inline u32 _state(struct pl330_thread *thrd) | |
995 | { | |
996 | void __iomem *regs = thrd->dmac->pinfo->base; | |
997 | u32 val; | |
998 | ||
999 | if (is_manager(thrd)) | |
1000 | val = readl(regs + DS) & 0xf; | |
1001 | else | |
1002 | val = readl(regs + CS(thrd->id)) & 0xf; | |
1003 | ||
1004 | switch (val) { | |
1005 | case DS_ST_STOP: | |
1006 | return PL330_STATE_STOPPED; | |
1007 | case DS_ST_EXEC: | |
1008 | return PL330_STATE_EXECUTING; | |
1009 | case DS_ST_CMISS: | |
1010 | return PL330_STATE_CACHEMISS; | |
1011 | case DS_ST_UPDTPC: | |
1012 | return PL330_STATE_UPDTPC; | |
1013 | case DS_ST_WFE: | |
1014 | return PL330_STATE_WFE; | |
1015 | case DS_ST_FAULT: | |
1016 | return PL330_STATE_FAULTING; | |
1017 | case DS_ST_ATBRR: | |
1018 | if (is_manager(thrd)) | |
1019 | return PL330_STATE_INVALID; | |
1020 | else | |
1021 | return PL330_STATE_ATBARRIER; | |
1022 | case DS_ST_QBUSY: | |
1023 | if (is_manager(thrd)) | |
1024 | return PL330_STATE_INVALID; | |
1025 | else | |
1026 | return PL330_STATE_QUEUEBUSY; | |
1027 | case DS_ST_WFP: | |
1028 | if (is_manager(thrd)) | |
1029 | return PL330_STATE_INVALID; | |
1030 | else | |
1031 | return PL330_STATE_WFP; | |
1032 | case DS_ST_KILL: | |
1033 | if (is_manager(thrd)) | |
1034 | return PL330_STATE_INVALID; | |
1035 | else | |
1036 | return PL330_STATE_KILLING; | |
1037 | case DS_ST_CMPLT: | |
1038 | if (is_manager(thrd)) | |
1039 | return PL330_STATE_INVALID; | |
1040 | else | |
1041 | return PL330_STATE_COMPLETING; | |
1042 | case DS_ST_FLTCMP: | |
1043 | if (is_manager(thrd)) | |
1044 | return PL330_STATE_INVALID; | |
1045 | else | |
1046 | return PL330_STATE_FAULT_COMPLETING; | |
1047 | default: | |
1048 | return PL330_STATE_INVALID; | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | static void _stop(struct pl330_thread *thrd) | |
1053 | { | |
1054 | void __iomem *regs = thrd->dmac->pinfo->base; | |
1055 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; | |
1056 | ||
1057 | if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) | |
1058 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1059 | ||
1060 | /* Return if nothing needs to be done */ | |
1061 | if (_state(thrd) == PL330_STATE_COMPLETING | |
1062 | || _state(thrd) == PL330_STATE_KILLING | |
1063 | || _state(thrd) == PL330_STATE_STOPPED) | |
1064 | return; | |
1065 | ||
1066 | _emit_KILL(0, insn); | |
1067 | ||
1068 | /* Stop generating interrupts for SEV */ | |
1069 | writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); | |
1070 | ||
1071 | _execute_DBGINSN(thrd, insn, is_manager(thrd)); | |
1072 | } | |
1073 | ||
1074 | /* Start doing req 'idx' of thread 'thrd' */ | |
1075 | static bool _trigger(struct pl330_thread *thrd) | |
1076 | { | |
1077 | void __iomem *regs = thrd->dmac->pinfo->base; | |
1078 | struct _pl330_req *req; | |
1079 | struct pl330_req *r; | |
1080 | struct _arg_GO go; | |
1081 | unsigned ns; | |
1082 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; | |
1083 | int idx; | |
1084 | ||
1085 | /* Return if already ACTIVE */ | |
1086 | if (_state(thrd) != PL330_STATE_STOPPED) | |
1087 | return true; | |
1088 | ||
1089 | idx = 1 - thrd->lstenq; | |
1090 | if (!IS_FREE(&thrd->req[idx])) | |
1091 | req = &thrd->req[idx]; | |
1092 | else { | |
1093 | idx = thrd->lstenq; | |
1094 | if (!IS_FREE(&thrd->req[idx])) | |
1095 | req = &thrd->req[idx]; | |
1096 | else | |
1097 | req = NULL; | |
1098 | } | |
1099 | ||
1100 | /* Return if no request */ | |
1101 | if (!req || !req->r) | |
1102 | return true; | |
1103 | ||
1104 | r = req->r; | |
1105 | ||
1106 | if (r->cfg) | |
1107 | ns = r->cfg->nonsecure ? 1 : 0; | |
1108 | else if (readl(regs + CS(thrd->id)) & CS_CNS) | |
1109 | ns = 1; | |
1110 | else | |
1111 | ns = 0; | |
1112 | ||
1113 | /* See 'Abort Sources' point-4 at Page 2-25 */ | |
1114 | if (_manager_ns(thrd) && !ns) | |
1115 | dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n", | |
1116 | __func__, __LINE__); | |
1117 | ||
1118 | go.chan = thrd->id; | |
1119 | go.addr = req->mc_bus; | |
1120 | go.ns = ns; | |
1121 | _emit_GO(0, insn, &go); | |
1122 | ||
1123 | /* Set to generate interrupts for SEV */ | |
1124 | writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); | |
1125 | ||
1126 | /* Only manager can execute GO */ | |
1127 | _execute_DBGINSN(thrd, insn, true); | |
1128 | ||
1129 | thrd->req_running = idx; | |
1130 | ||
1131 | return true; | |
1132 | } | |
1133 | ||
1134 | static bool _start(struct pl330_thread *thrd) | |
1135 | { | |
1136 | switch (_state(thrd)) { | |
1137 | case PL330_STATE_FAULT_COMPLETING: | |
1138 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1139 | ||
1140 | if (_state(thrd) == PL330_STATE_KILLING) | |
1141 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1142 | ||
1143 | case PL330_STATE_FAULTING: | |
1144 | _stop(thrd); | |
1145 | ||
1146 | case PL330_STATE_KILLING: | |
1147 | case PL330_STATE_COMPLETING: | |
1148 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1149 | ||
1150 | case PL330_STATE_STOPPED: | |
1151 | return _trigger(thrd); | |
1152 | ||
1153 | case PL330_STATE_WFP: | |
1154 | case PL330_STATE_QUEUEBUSY: | |
1155 | case PL330_STATE_ATBARRIER: | |
1156 | case PL330_STATE_UPDTPC: | |
1157 | case PL330_STATE_CACHEMISS: | |
1158 | case PL330_STATE_EXECUTING: | |
1159 | return true; | |
1160 | ||
1161 | case PL330_STATE_WFE: /* For RESUME, nothing yet */ | |
1162 | default: | |
1163 | return false; | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], | |
1168 | const struct _xfer_spec *pxs, int cyc) | |
1169 | { | |
1170 | int off = 0; | |
3ecf51a4 | 1171 | struct pl330_config *pcfg = pxs->r->cfg->pcfg; |
b7d861d9 | 1172 | |
3ecf51a4 BK |
1173 | /* check lock-up free version */ |
1174 | if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { | |
1175 | while (cyc--) { | |
1176 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1177 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1178 | } | |
1179 | } else { | |
1180 | while (cyc--) { | |
1181 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1182 | off += _emit_RMB(dry_run, &buf[off]); | |
1183 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1184 | off += _emit_WMB(dry_run, &buf[off]); | |
1185 | } | |
b7d861d9 BK |
1186 | } |
1187 | ||
1188 | return off; | |
1189 | } | |
1190 | ||
1191 | static inline int _ldst_devtomem(unsigned dry_run, u8 buf[], | |
1192 | const struct _xfer_spec *pxs, int cyc) | |
1193 | { | |
1194 | int off = 0; | |
1195 | ||
1196 | while (cyc--) { | |
1197 | off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); | |
1198 | off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri); | |
1199 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1200 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); | |
1201 | } | |
1202 | ||
1203 | return off; | |
1204 | } | |
1205 | ||
1206 | static inline int _ldst_memtodev(unsigned dry_run, u8 buf[], | |
1207 | const struct _xfer_spec *pxs, int cyc) | |
1208 | { | |
1209 | int off = 0; | |
1210 | ||
1211 | while (cyc--) { | |
1212 | off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); | |
1213 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1214 | off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri); | |
1215 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); | |
1216 | } | |
1217 | ||
1218 | return off; | |
1219 | } | |
1220 | ||
1221 | static int _bursts(unsigned dry_run, u8 buf[], | |
1222 | const struct _xfer_spec *pxs, int cyc) | |
1223 | { | |
1224 | int off = 0; | |
1225 | ||
1226 | switch (pxs->r->rqtype) { | |
585a9d0b | 1227 | case DMA_MEM_TO_DEV: |
b7d861d9 BK |
1228 | off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); |
1229 | break; | |
585a9d0b | 1230 | case DMA_DEV_TO_MEM: |
b7d861d9 BK |
1231 | off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); |
1232 | break; | |
585a9d0b | 1233 | case DMA_MEM_TO_MEM: |
b7d861d9 BK |
1234 | off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); |
1235 | break; | |
1236 | default: | |
1237 | off += 0x40000000; /* Scare off the Client */ | |
1238 | break; | |
1239 | } | |
1240 | ||
1241 | return off; | |
1242 | } | |
1243 | ||
1244 | /* Returns bytes consumed and updates bursts */ | |
1245 | static inline int _loop(unsigned dry_run, u8 buf[], | |
1246 | unsigned long *bursts, const struct _xfer_spec *pxs) | |
1247 | { | |
1248 | int cyc, cycmax, szlp, szlpend, szbrst, off; | |
1249 | unsigned lcnt0, lcnt1, ljmp0, ljmp1; | |
1250 | struct _arg_LPEND lpend; | |
1251 | ||
1252 | /* Max iterations possible in DMALP is 256 */ | |
1253 | if (*bursts >= 256*256) { | |
1254 | lcnt1 = 256; | |
1255 | lcnt0 = 256; | |
1256 | cyc = *bursts / lcnt1 / lcnt0; | |
1257 | } else if (*bursts > 256) { | |
1258 | lcnt1 = 256; | |
1259 | lcnt0 = *bursts / lcnt1; | |
1260 | cyc = 1; | |
1261 | } else { | |
1262 | lcnt1 = *bursts; | |
1263 | lcnt0 = 0; | |
1264 | cyc = 1; | |
1265 | } | |
1266 | ||
1267 | szlp = _emit_LP(1, buf, 0, 0); | |
1268 | szbrst = _bursts(1, buf, pxs, 1); | |
1269 | ||
1270 | lpend.cond = ALWAYS; | |
1271 | lpend.forever = false; | |
1272 | lpend.loop = 0; | |
1273 | lpend.bjump = 0; | |
1274 | szlpend = _emit_LPEND(1, buf, &lpend); | |
1275 | ||
1276 | if (lcnt0) { | |
1277 | szlp *= 2; | |
1278 | szlpend *= 2; | |
1279 | } | |
1280 | ||
1281 | /* | |
1282 | * Max bursts that we can unroll due to limit on the | |
1283 | * size of backward jump that can be encoded in DMALPEND | |
1284 | * which is 8-bits and hence 255 | |
1285 | */ | |
1286 | cycmax = (255 - (szlp + szlpend)) / szbrst; | |
1287 | ||
1288 | cyc = (cycmax < cyc) ? cycmax : cyc; | |
1289 | ||
1290 | off = 0; | |
1291 | ||
1292 | if (lcnt0) { | |
1293 | off += _emit_LP(dry_run, &buf[off], 0, lcnt0); | |
1294 | ljmp0 = off; | |
1295 | } | |
1296 | ||
1297 | off += _emit_LP(dry_run, &buf[off], 1, lcnt1); | |
1298 | ljmp1 = off; | |
1299 | ||
1300 | off += _bursts(dry_run, &buf[off], pxs, cyc); | |
1301 | ||
1302 | lpend.cond = ALWAYS; | |
1303 | lpend.forever = false; | |
1304 | lpend.loop = 1; | |
1305 | lpend.bjump = off - ljmp1; | |
1306 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1307 | ||
1308 | if (lcnt0) { | |
1309 | lpend.cond = ALWAYS; | |
1310 | lpend.forever = false; | |
1311 | lpend.loop = 0; | |
1312 | lpend.bjump = off - ljmp0; | |
1313 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1314 | } | |
1315 | ||
1316 | *bursts = lcnt1 * cyc; | |
1317 | if (lcnt0) | |
1318 | *bursts *= lcnt0; | |
1319 | ||
1320 | return off; | |
1321 | } | |
1322 | ||
1323 | static inline int _setup_loops(unsigned dry_run, u8 buf[], | |
1324 | const struct _xfer_spec *pxs) | |
1325 | { | |
1326 | struct pl330_xfer *x = pxs->x; | |
1327 | u32 ccr = pxs->ccr; | |
1328 | unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); | |
1329 | int off = 0; | |
1330 | ||
1331 | while (bursts) { | |
1332 | c = bursts; | |
1333 | off += _loop(dry_run, &buf[off], &c, pxs); | |
1334 | bursts -= c; | |
1335 | } | |
1336 | ||
1337 | return off; | |
1338 | } | |
1339 | ||
1340 | static inline int _setup_xfer(unsigned dry_run, u8 buf[], | |
1341 | const struct _xfer_spec *pxs) | |
1342 | { | |
1343 | struct pl330_xfer *x = pxs->x; | |
1344 | int off = 0; | |
1345 | ||
1346 | /* DMAMOV SAR, x->src_addr */ | |
1347 | off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); | |
1348 | /* DMAMOV DAR, x->dst_addr */ | |
1349 | off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); | |
1350 | ||
1351 | /* Setup Loop(s) */ | |
1352 | off += _setup_loops(dry_run, &buf[off], pxs); | |
1353 | ||
1354 | return off; | |
1355 | } | |
1356 | ||
1357 | /* | |
1358 | * A req is a sequence of one or more xfer units. | |
1359 | * Returns the number of bytes taken to setup the MC for the req. | |
1360 | */ | |
1361 | static int _setup_req(unsigned dry_run, struct pl330_thread *thrd, | |
1362 | unsigned index, struct _xfer_spec *pxs) | |
1363 | { | |
1364 | struct _pl330_req *req = &thrd->req[index]; | |
1365 | struct pl330_xfer *x; | |
1366 | u8 *buf = req->mc_cpu; | |
1367 | int off = 0; | |
1368 | ||
1369 | PL330_DBGMC_START(req->mc_bus); | |
1370 | ||
1371 | /* DMAMOV CCR, ccr */ | |
1372 | off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); | |
1373 | ||
1374 | x = pxs->r->x; | |
d5cef121 LPC |
1375 | /* Error if xfer length is not aligned at burst size */ |
1376 | if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) | |
1377 | return -EINVAL; | |
b7d861d9 | 1378 | |
d5cef121 LPC |
1379 | pxs->x = x; |
1380 | off += _setup_xfer(dry_run, &buf[off], pxs); | |
b7d861d9 BK |
1381 | |
1382 | /* DMASEV peripheral/event */ | |
1383 | off += _emit_SEV(dry_run, &buf[off], thrd->ev); | |
1384 | /* DMAEND */ | |
1385 | off += _emit_END(dry_run, &buf[off]); | |
1386 | ||
1387 | return off; | |
1388 | } | |
1389 | ||
1390 | static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) | |
1391 | { | |
1392 | u32 ccr = 0; | |
1393 | ||
1394 | if (rqc->src_inc) | |
1395 | ccr |= CC_SRCINC; | |
1396 | ||
1397 | if (rqc->dst_inc) | |
1398 | ccr |= CC_DSTINC; | |
1399 | ||
1400 | /* We set same protection levels for Src and DST for now */ | |
1401 | if (rqc->privileged) | |
1402 | ccr |= CC_SRCPRI | CC_DSTPRI; | |
1403 | if (rqc->nonsecure) | |
1404 | ccr |= CC_SRCNS | CC_DSTNS; | |
1405 | if (rqc->insnaccess) | |
1406 | ccr |= CC_SRCIA | CC_DSTIA; | |
1407 | ||
1408 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); | |
1409 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); | |
1410 | ||
1411 | ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); | |
1412 | ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); | |
1413 | ||
1414 | ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); | |
1415 | ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); | |
1416 | ||
1417 | ccr |= (rqc->swap << CC_SWAP_SHFT); | |
1418 | ||
1419 | return ccr; | |
1420 | } | |
1421 | ||
1422 | static inline bool _is_valid(u32 ccr) | |
1423 | { | |
f0564c7e LPC |
1424 | enum pl330_cachectrl dcctl; |
1425 | enum pl330_cachectrl scctl; | |
b7d861d9 BK |
1426 | |
1427 | dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK; | |
1428 | scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK; | |
1429 | ||
f0564c7e LPC |
1430 | if (dcctl == INVALID1 || dcctl == INVALID2 |
1431 | || scctl == INVALID1 || scctl == INVALID2) | |
b7d861d9 BK |
1432 | return false; |
1433 | else | |
1434 | return true; | |
1435 | } | |
1436 | ||
1437 | /* | |
1438 | * Submit a list of xfers after which the client wants notification. | |
1439 | * Client is not notified after each xfer unit, just once after all | |
1440 | * xfer units are done or some error occurs. | |
1441 | */ | |
1442 | static int pl330_submit_req(void *ch_id, struct pl330_req *r) | |
1443 | { | |
1444 | struct pl330_thread *thrd = ch_id; | |
1445 | struct pl330_dmac *pl330; | |
1446 | struct pl330_info *pi; | |
1447 | struct _xfer_spec xs; | |
1448 | unsigned long flags; | |
1449 | void __iomem *regs; | |
1450 | unsigned idx; | |
1451 | u32 ccr; | |
1452 | int ret = 0; | |
1453 | ||
1454 | /* No Req or Unacquired Channel or DMAC */ | |
1455 | if (!r || !thrd || thrd->free) | |
1456 | return -EINVAL; | |
1457 | ||
1458 | pl330 = thrd->dmac; | |
1459 | pi = pl330->pinfo; | |
1460 | regs = pi->base; | |
1461 | ||
1462 | if (pl330->state == DYING | |
1463 | || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { | |
1464 | dev_info(thrd->dmac->pinfo->dev, "%s:%d\n", | |
1465 | __func__, __LINE__); | |
1466 | return -EAGAIN; | |
1467 | } | |
1468 | ||
1469 | /* If request for non-existing peripheral */ | |
585a9d0b | 1470 | if (r->rqtype != DMA_MEM_TO_MEM && r->peri >= pi->pcfg.num_peri) { |
b7d861d9 BK |
1471 | dev_info(thrd->dmac->pinfo->dev, |
1472 | "%s:%d Invalid peripheral(%u)!\n", | |
1473 | __func__, __LINE__, r->peri); | |
1474 | return -EINVAL; | |
1475 | } | |
1476 | ||
1477 | spin_lock_irqsave(&pl330->lock, flags); | |
1478 | ||
1479 | if (_queue_full(thrd)) { | |
1480 | ret = -EAGAIN; | |
1481 | goto xfer_exit; | |
1482 | } | |
1483 | ||
b7d861d9 BK |
1484 | |
1485 | /* Use last settings, if not provided */ | |
2e2c682b SK |
1486 | if (r->cfg) { |
1487 | /* Prefer Secure Channel */ | |
1488 | if (!_manager_ns(thrd)) | |
1489 | r->cfg->nonsecure = 0; | |
1490 | else | |
1491 | r->cfg->nonsecure = 1; | |
1492 | ||
b7d861d9 | 1493 | ccr = _prepare_ccr(r->cfg); |
2e2c682b | 1494 | } else { |
b7d861d9 | 1495 | ccr = readl(regs + CC(thrd->id)); |
2e2c682b | 1496 | } |
b7d861d9 BK |
1497 | |
1498 | /* If this req doesn't have valid xfer settings */ | |
1499 | if (!_is_valid(ccr)) { | |
1500 | ret = -EINVAL; | |
1501 | dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n", | |
1502 | __func__, __LINE__, ccr); | |
1503 | goto xfer_exit; | |
1504 | } | |
1505 | ||
1506 | idx = IS_FREE(&thrd->req[0]) ? 0 : 1; | |
1507 | ||
1508 | xs.ccr = ccr; | |
1509 | xs.r = r; | |
1510 | ||
1511 | /* First dry run to check if req is acceptable */ | |
1512 | ret = _setup_req(1, thrd, idx, &xs); | |
1513 | if (ret < 0) | |
1514 | goto xfer_exit; | |
1515 | ||
1516 | if (ret > pi->mcbufsz / 2) { | |
1517 | dev_info(thrd->dmac->pinfo->dev, | |
1518 | "%s:%d Trying increasing mcbufsz\n", | |
1519 | __func__, __LINE__); | |
1520 | ret = -ENOMEM; | |
1521 | goto xfer_exit; | |
1522 | } | |
1523 | ||
1524 | /* Hook the request */ | |
1525 | thrd->lstenq = idx; | |
b7d861d9 | 1526 | thrd->req[idx].r = r; |
be025329 | 1527 | _setup_req(0, thrd, idx, &xs); |
b7d861d9 BK |
1528 | |
1529 | ret = 0; | |
1530 | ||
1531 | xfer_exit: | |
1532 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1533 | ||
1534 | return ret; | |
1535 | } | |
1536 | ||
6079d38c LPC |
1537 | static void dma_pl330_rqcb(struct pl330_req *req, enum pl330_op_err err) |
1538 | { | |
1539 | struct dma_pl330_desc *desc = container_of(req, struct dma_pl330_desc, req); | |
1540 | struct dma_pl330_chan *pch = desc->pchan; | |
1541 | unsigned long flags; | |
1542 | ||
1543 | /* If desc aborted */ | |
1544 | if (!pch) | |
1545 | return; | |
1546 | ||
1547 | spin_lock_irqsave(&pch->lock, flags); | |
1548 | ||
1549 | desc->status = DONE; | |
1550 | ||
1551 | spin_unlock_irqrestore(&pch->lock, flags); | |
1552 | ||
1553 | tasklet_schedule(&pch->task); | |
1554 | } | |
1555 | ||
b7d861d9 BK |
1556 | static void pl330_dotask(unsigned long data) |
1557 | { | |
1558 | struct pl330_dmac *pl330 = (struct pl330_dmac *) data; | |
1559 | struct pl330_info *pi = pl330->pinfo; | |
1560 | unsigned long flags; | |
1561 | int i; | |
1562 | ||
1563 | spin_lock_irqsave(&pl330->lock, flags); | |
1564 | ||
1565 | /* The DMAC itself gone nuts */ | |
1566 | if (pl330->dmac_tbd.reset_dmac) { | |
1567 | pl330->state = DYING; | |
1568 | /* Reset the manager too */ | |
1569 | pl330->dmac_tbd.reset_mngr = true; | |
1570 | /* Clear the reset flag */ | |
1571 | pl330->dmac_tbd.reset_dmac = false; | |
1572 | } | |
1573 | ||
1574 | if (pl330->dmac_tbd.reset_mngr) { | |
1575 | _stop(pl330->manager); | |
1576 | /* Reset all channels */ | |
1577 | pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1; | |
1578 | /* Clear the reset flag */ | |
1579 | pl330->dmac_tbd.reset_mngr = false; | |
1580 | } | |
1581 | ||
1582 | for (i = 0; i < pi->pcfg.num_chan; i++) { | |
1583 | ||
1584 | if (pl330->dmac_tbd.reset_chan & (1 << i)) { | |
1585 | struct pl330_thread *thrd = &pl330->channels[i]; | |
1586 | void __iomem *regs = pi->base; | |
1587 | enum pl330_op_err err; | |
1588 | ||
1589 | _stop(thrd); | |
1590 | ||
1591 | if (readl(regs + FSC) & (1 << thrd->id)) | |
1592 | err = PL330_ERR_FAIL; | |
1593 | else | |
1594 | err = PL330_ERR_ABORT; | |
1595 | ||
1596 | spin_unlock_irqrestore(&pl330->lock, flags); | |
6079d38c LPC |
1597 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].r, err); |
1598 | dma_pl330_rqcb(thrd->req[thrd->lstenq].r, err); | |
b7d861d9 BK |
1599 | spin_lock_irqsave(&pl330->lock, flags); |
1600 | ||
1601 | thrd->req[0].r = NULL; | |
1602 | thrd->req[1].r = NULL; | |
1603 | mark_free(thrd, 0); | |
1604 | mark_free(thrd, 1); | |
1605 | ||
1606 | /* Clear the reset flag */ | |
1607 | pl330->dmac_tbd.reset_chan &= ~(1 << i); | |
1608 | } | |
1609 | } | |
1610 | ||
1611 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1612 | ||
1613 | return; | |
1614 | } | |
1615 | ||
1616 | /* Returns 1 if state was updated, 0 otherwise */ | |
1617 | static int pl330_update(const struct pl330_info *pi) | |
1618 | { | |
fdec53d5 | 1619 | struct pl330_req *rqdone, *tmp; |
b7d861d9 BK |
1620 | struct pl330_dmac *pl330; |
1621 | unsigned long flags; | |
1622 | void __iomem *regs; | |
1623 | u32 val; | |
1624 | int id, ev, ret = 0; | |
1625 | ||
1626 | if (!pi || !pi->pl330_data) | |
1627 | return 0; | |
1628 | ||
1629 | regs = pi->base; | |
1630 | pl330 = pi->pl330_data; | |
1631 | ||
1632 | spin_lock_irqsave(&pl330->lock, flags); | |
1633 | ||
1634 | val = readl(regs + FSM) & 0x1; | |
1635 | if (val) | |
1636 | pl330->dmac_tbd.reset_mngr = true; | |
1637 | else | |
1638 | pl330->dmac_tbd.reset_mngr = false; | |
1639 | ||
1640 | val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1); | |
1641 | pl330->dmac_tbd.reset_chan |= val; | |
1642 | if (val) { | |
1643 | int i = 0; | |
1644 | while (i < pi->pcfg.num_chan) { | |
1645 | if (val & (1 << i)) { | |
1646 | dev_info(pi->dev, | |
1647 | "Reset Channel-%d\t CS-%x FTC-%x\n", | |
1648 | i, readl(regs + CS(i)), | |
1649 | readl(regs + FTC(i))); | |
1650 | _stop(&pl330->channels[i]); | |
1651 | } | |
1652 | i++; | |
1653 | } | |
1654 | } | |
1655 | ||
1656 | /* Check which event happened i.e, thread notified */ | |
1657 | val = readl(regs + ES); | |
1658 | if (pi->pcfg.num_events < 32 | |
1659 | && val & ~((1 << pi->pcfg.num_events) - 1)) { | |
1660 | pl330->dmac_tbd.reset_dmac = true; | |
1661 | dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__); | |
1662 | ret = 1; | |
1663 | goto updt_exit; | |
1664 | } | |
1665 | ||
1666 | for (ev = 0; ev < pi->pcfg.num_events; ev++) { | |
1667 | if (val & (1 << ev)) { /* Event occurred */ | |
1668 | struct pl330_thread *thrd; | |
1669 | u32 inten = readl(regs + INTEN); | |
1670 | int active; | |
1671 | ||
1672 | /* Clear the event */ | |
1673 | if (inten & (1 << ev)) | |
1674 | writel(1 << ev, regs + INTCLR); | |
1675 | ||
1676 | ret = 1; | |
1677 | ||
1678 | id = pl330->events[ev]; | |
1679 | ||
1680 | thrd = &pl330->channels[id]; | |
1681 | ||
1682 | active = thrd->req_running; | |
1683 | if (active == -1) /* Aborted */ | |
1684 | continue; | |
1685 | ||
fdec53d5 JM |
1686 | /* Detach the req */ |
1687 | rqdone = thrd->req[active].r; | |
1688 | thrd->req[active].r = NULL; | |
1689 | ||
b7d861d9 BK |
1690 | mark_free(thrd, active); |
1691 | ||
1692 | /* Get going again ASAP */ | |
1693 | _start(thrd); | |
1694 | ||
1695 | /* For now, just make a list of callbacks to be done */ | |
1696 | list_add_tail(&rqdone->rqd, &pl330->req_done); | |
1697 | } | |
1698 | } | |
1699 | ||
1700 | /* Now that we are in no hurry, do the callbacks */ | |
fdec53d5 JM |
1701 | list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) { |
1702 | list_del(&rqdone->rqd); | |
b7d861d9 BK |
1703 | |
1704 | spin_unlock_irqrestore(&pl330->lock, flags); | |
6079d38c | 1705 | dma_pl330_rqcb(rqdone, PL330_ERR_NONE); |
b7d861d9 BK |
1706 | spin_lock_irqsave(&pl330->lock, flags); |
1707 | } | |
1708 | ||
1709 | updt_exit: | |
1710 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1711 | ||
1712 | if (pl330->dmac_tbd.reset_dmac | |
1713 | || pl330->dmac_tbd.reset_mngr | |
1714 | || pl330->dmac_tbd.reset_chan) { | |
1715 | ret = 1; | |
1716 | tasklet_schedule(&pl330->tasks); | |
1717 | } | |
1718 | ||
1719 | return ret; | |
1720 | } | |
1721 | ||
1722 | static int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op) | |
1723 | { | |
1724 | struct pl330_thread *thrd = ch_id; | |
1725 | struct pl330_dmac *pl330; | |
1726 | unsigned long flags; | |
ef08e782 | 1727 | int ret = 0, active; |
b7d861d9 BK |
1728 | |
1729 | if (!thrd || thrd->free || thrd->dmac->state == DYING) | |
1730 | return -EINVAL; | |
1731 | ||
1732 | pl330 = thrd->dmac; | |
ef08e782 | 1733 | active = thrd->req_running; |
b7d861d9 BK |
1734 | |
1735 | spin_lock_irqsave(&pl330->lock, flags); | |
1736 | ||
1737 | switch (op) { | |
1738 | case PL330_OP_FLUSH: | |
1739 | /* Make sure the channel is stopped */ | |
1740 | _stop(thrd); | |
1741 | ||
1742 | thrd->req[0].r = NULL; | |
1743 | thrd->req[1].r = NULL; | |
1744 | mark_free(thrd, 0); | |
1745 | mark_free(thrd, 1); | |
1746 | break; | |
1747 | ||
1748 | case PL330_OP_ABORT: | |
1749 | /* Make sure the channel is stopped */ | |
1750 | _stop(thrd); | |
1751 | ||
1752 | /* ABORT is only for the active req */ | |
1753 | if (active == -1) | |
1754 | break; | |
1755 | ||
1756 | thrd->req[active].r = NULL; | |
1757 | mark_free(thrd, active); | |
1758 | ||
1759 | /* Start the next */ | |
1760 | case PL330_OP_START: | |
1761 | if ((active == -1) && !_start(thrd)) | |
1762 | ret = -EIO; | |
1763 | break; | |
1764 | ||
1765 | default: | |
1766 | ret = -EINVAL; | |
1767 | } | |
1768 | ||
1769 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1770 | return ret; | |
1771 | } | |
1772 | ||
b7d861d9 BK |
1773 | /* Reserve an event */ |
1774 | static inline int _alloc_event(struct pl330_thread *thrd) | |
1775 | { | |
1776 | struct pl330_dmac *pl330 = thrd->dmac; | |
1777 | struct pl330_info *pi = pl330->pinfo; | |
1778 | int ev; | |
1779 | ||
1780 | for (ev = 0; ev < pi->pcfg.num_events; ev++) | |
1781 | if (pl330->events[ev] == -1) { | |
1782 | pl330->events[ev] = thrd->id; | |
1783 | return ev; | |
1784 | } | |
1785 | ||
1786 | return -1; | |
1787 | } | |
1788 | ||
1789 | static bool _chan_ns(const struct pl330_info *pi, int i) | |
1790 | { | |
1791 | return pi->pcfg.irq_ns & (1 << i); | |
1792 | } | |
1793 | ||
1794 | /* Upon success, returns IdentityToken for the | |
1795 | * allocated channel, NULL otherwise. | |
1796 | */ | |
1797 | static void *pl330_request_channel(const struct pl330_info *pi) | |
1798 | { | |
1799 | struct pl330_thread *thrd = NULL; | |
1800 | struct pl330_dmac *pl330; | |
1801 | unsigned long flags; | |
1802 | int chans, i; | |
1803 | ||
1804 | if (!pi || !pi->pl330_data) | |
1805 | return NULL; | |
b3040e40 | 1806 | |
b7d861d9 BK |
1807 | pl330 = pi->pl330_data; |
1808 | ||
1809 | if (pl330->state == DYING) | |
1810 | return NULL; | |
1811 | ||
1812 | chans = pi->pcfg.num_chan; | |
1813 | ||
1814 | spin_lock_irqsave(&pl330->lock, flags); | |
1815 | ||
1816 | for (i = 0; i < chans; i++) { | |
1817 | thrd = &pl330->channels[i]; | |
1818 | if ((thrd->free) && (!_manager_ns(thrd) || | |
1819 | _chan_ns(pi, i))) { | |
1820 | thrd->ev = _alloc_event(thrd); | |
1821 | if (thrd->ev >= 0) { | |
1822 | thrd->free = false; | |
1823 | thrd->lstenq = 1; | |
1824 | thrd->req[0].r = NULL; | |
1825 | mark_free(thrd, 0); | |
1826 | thrd->req[1].r = NULL; | |
1827 | mark_free(thrd, 1); | |
1828 | break; | |
1829 | } | |
1830 | } | |
1831 | thrd = NULL; | |
1832 | } | |
1833 | ||
1834 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1835 | ||
1836 | return thrd; | |
1837 | } | |
1838 | ||
1839 | /* Release an event */ | |
1840 | static inline void _free_event(struct pl330_thread *thrd, int ev) | |
1841 | { | |
1842 | struct pl330_dmac *pl330 = thrd->dmac; | |
1843 | struct pl330_info *pi = pl330->pinfo; | |
1844 | ||
1845 | /* If the event is valid and was held by the thread */ | |
1846 | if (ev >= 0 && ev < pi->pcfg.num_events | |
1847 | && pl330->events[ev] == thrd->id) | |
1848 | pl330->events[ev] = -1; | |
1849 | } | |
1850 | ||
1851 | static void pl330_release_channel(void *ch_id) | |
1852 | { | |
1853 | struct pl330_thread *thrd = ch_id; | |
1854 | struct pl330_dmac *pl330; | |
1855 | unsigned long flags; | |
1856 | ||
1857 | if (!thrd || thrd->free) | |
1858 | return; | |
1859 | ||
1860 | _stop(thrd); | |
1861 | ||
6079d38c LPC |
1862 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT); |
1863 | dma_pl330_rqcb(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT); | |
b7d861d9 BK |
1864 | |
1865 | pl330 = thrd->dmac; | |
1866 | ||
1867 | spin_lock_irqsave(&pl330->lock, flags); | |
1868 | _free_event(thrd, thrd->ev); | |
1869 | thrd->free = true; | |
1870 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1871 | } | |
1872 | ||
1873 | /* Initialize the structure for PL330 configuration, that can be used | |
1874 | * by the client driver the make best use of the DMAC | |
1875 | */ | |
1876 | static void read_dmac_config(struct pl330_info *pi) | |
1877 | { | |
1878 | void __iomem *regs = pi->base; | |
1879 | u32 val; | |
1880 | ||
1881 | val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; | |
1882 | val &= CRD_DATA_WIDTH_MASK; | |
1883 | pi->pcfg.data_bus_width = 8 * (1 << val); | |
1884 | ||
1885 | val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; | |
1886 | val &= CRD_DATA_BUFF_MASK; | |
1887 | pi->pcfg.data_buf_dep = val + 1; | |
1888 | ||
1889 | val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; | |
1890 | val &= CR0_NUM_CHANS_MASK; | |
1891 | val += 1; | |
1892 | pi->pcfg.num_chan = val; | |
1893 | ||
1894 | val = readl(regs + CR0); | |
1895 | if (val & CR0_PERIPH_REQ_SET) { | |
1896 | val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; | |
1897 | val += 1; | |
1898 | pi->pcfg.num_peri = val; | |
1899 | pi->pcfg.peri_ns = readl(regs + CR4); | |
1900 | } else { | |
1901 | pi->pcfg.num_peri = 0; | |
1902 | } | |
1903 | ||
1904 | val = readl(regs + CR0); | |
1905 | if (val & CR0_BOOT_MAN_NS) | |
1906 | pi->pcfg.mode |= DMAC_MODE_NS; | |
1907 | else | |
1908 | pi->pcfg.mode &= ~DMAC_MODE_NS; | |
1909 | ||
1910 | val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; | |
1911 | val &= CR0_NUM_EVENTS_MASK; | |
1912 | val += 1; | |
1913 | pi->pcfg.num_events = val; | |
1914 | ||
1915 | pi->pcfg.irq_ns = readl(regs + CR3); | |
b7d861d9 BK |
1916 | } |
1917 | ||
1918 | static inline void _reset_thread(struct pl330_thread *thrd) | |
1919 | { | |
1920 | struct pl330_dmac *pl330 = thrd->dmac; | |
1921 | struct pl330_info *pi = pl330->pinfo; | |
1922 | ||
1923 | thrd->req[0].mc_cpu = pl330->mcode_cpu | |
1924 | + (thrd->id * pi->mcbufsz); | |
1925 | thrd->req[0].mc_bus = pl330->mcode_bus | |
1926 | + (thrd->id * pi->mcbufsz); | |
1927 | thrd->req[0].r = NULL; | |
1928 | mark_free(thrd, 0); | |
1929 | ||
1930 | thrd->req[1].mc_cpu = thrd->req[0].mc_cpu | |
1931 | + pi->mcbufsz / 2; | |
1932 | thrd->req[1].mc_bus = thrd->req[0].mc_bus | |
1933 | + pi->mcbufsz / 2; | |
1934 | thrd->req[1].r = NULL; | |
1935 | mark_free(thrd, 1); | |
1936 | } | |
1937 | ||
1938 | static int dmac_alloc_threads(struct pl330_dmac *pl330) | |
1939 | { | |
1940 | struct pl330_info *pi = pl330->pinfo; | |
1941 | int chans = pi->pcfg.num_chan; | |
1942 | struct pl330_thread *thrd; | |
1943 | int i; | |
1944 | ||
1945 | /* Allocate 1 Manager and 'chans' Channel threads */ | |
1946 | pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), | |
1947 | GFP_KERNEL); | |
1948 | if (!pl330->channels) | |
1949 | return -ENOMEM; | |
1950 | ||
1951 | /* Init Channel threads */ | |
1952 | for (i = 0; i < chans; i++) { | |
1953 | thrd = &pl330->channels[i]; | |
1954 | thrd->id = i; | |
1955 | thrd->dmac = pl330; | |
1956 | _reset_thread(thrd); | |
1957 | thrd->free = true; | |
1958 | } | |
1959 | ||
1960 | /* MANAGER is indexed at the end */ | |
1961 | thrd = &pl330->channels[chans]; | |
1962 | thrd->id = chans; | |
1963 | thrd->dmac = pl330; | |
1964 | thrd->free = false; | |
1965 | pl330->manager = thrd; | |
1966 | ||
1967 | return 0; | |
1968 | } | |
1969 | ||
1970 | static int dmac_alloc_resources(struct pl330_dmac *pl330) | |
1971 | { | |
1972 | struct pl330_info *pi = pl330->pinfo; | |
1973 | int chans = pi->pcfg.num_chan; | |
1974 | int ret; | |
b3040e40 | 1975 | |
b3040e40 | 1976 | /* |
b7d861d9 BK |
1977 | * Alloc MicroCode buffer for 'chans' Channel threads. |
1978 | * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) | |
b3040e40 | 1979 | */ |
b7d861d9 BK |
1980 | pl330->mcode_cpu = dma_alloc_coherent(pi->dev, |
1981 | chans * pi->mcbufsz, | |
1982 | &pl330->mcode_bus, GFP_KERNEL); | |
1983 | if (!pl330->mcode_cpu) { | |
1984 | dev_err(pi->dev, "%s:%d Can't allocate memory!\n", | |
1985 | __func__, __LINE__); | |
1986 | return -ENOMEM; | |
1987 | } | |
1988 | ||
1989 | ret = dmac_alloc_threads(pl330); | |
1990 | if (ret) { | |
1991 | dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n", | |
1992 | __func__, __LINE__); | |
1993 | dma_free_coherent(pi->dev, | |
1994 | chans * pi->mcbufsz, | |
1995 | pl330->mcode_cpu, pl330->mcode_bus); | |
1996 | return ret; | |
1997 | } | |
1998 | ||
1999 | return 0; | |
2000 | } | |
2001 | ||
2002 | static int pl330_add(struct pl330_info *pi) | |
2003 | { | |
2004 | struct pl330_dmac *pl330; | |
2005 | void __iomem *regs; | |
2006 | int i, ret; | |
2007 | ||
2008 | if (!pi || !pi->dev) | |
2009 | return -EINVAL; | |
2010 | ||
2011 | /* If already added */ | |
2012 | if (pi->pl330_data) | |
2013 | return -EINVAL; | |
2014 | ||
b7d861d9 | 2015 | regs = pi->base; |
b3040e40 | 2016 | |
b7d861d9 | 2017 | /* Check if we can handle this DMAC */ |
09677176 WD |
2018 | if ((pi->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { |
2019 | dev_err(pi->dev, "PERIPH_ID 0x%x !\n", pi->pcfg.periph_id); | |
b7d861d9 BK |
2020 | return -EINVAL; |
2021 | } | |
b3040e40 | 2022 | |
b7d861d9 BK |
2023 | /* Read the configuration of the DMAC */ |
2024 | read_dmac_config(pi); | |
b3040e40 | 2025 | |
b7d861d9 BK |
2026 | if (pi->pcfg.num_events == 0) { |
2027 | dev_err(pi->dev, "%s:%d Can't work without events!\n", | |
2028 | __func__, __LINE__); | |
2029 | return -EINVAL; | |
2030 | } | |
b3040e40 | 2031 | |
b7d861d9 BK |
2032 | pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL); |
2033 | if (!pl330) { | |
2034 | dev_err(pi->dev, "%s:%d Can't allocate memory!\n", | |
2035 | __func__, __LINE__); | |
2036 | return -ENOMEM; | |
2037 | } | |
b3040e40 | 2038 | |
b7d861d9 BK |
2039 | /* Assign the info structure and private data */ |
2040 | pl330->pinfo = pi; | |
2041 | pi->pl330_data = pl330; | |
b3040e40 | 2042 | |
b7d861d9 | 2043 | spin_lock_init(&pl330->lock); |
1b9bb715 | 2044 | |
b7d861d9 | 2045 | INIT_LIST_HEAD(&pl330->req_done); |
42bc9cf4 | 2046 | |
b7d861d9 BK |
2047 | /* Use default MC buffer size if not provided */ |
2048 | if (!pi->mcbufsz) | |
2049 | pi->mcbufsz = MCODE_BUFF_PER_REQ * 2; | |
b3040e40 | 2050 | |
b7d861d9 BK |
2051 | /* Mark all events as free */ |
2052 | for (i = 0; i < pi->pcfg.num_events; i++) | |
2053 | pl330->events[i] = -1; | |
b3040e40 | 2054 | |
b7d861d9 BK |
2055 | /* Allocate resources needed by the DMAC */ |
2056 | ret = dmac_alloc_resources(pl330); | |
2057 | if (ret) { | |
2058 | dev_err(pi->dev, "Unable to create channels for DMAC\n"); | |
2059 | kfree(pl330); | |
2060 | return ret; | |
2061 | } | |
b3040e40 | 2062 | |
b7d861d9 | 2063 | tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); |
b3040e40 | 2064 | |
b7d861d9 | 2065 | pl330->state = INIT; |
a2f5203f | 2066 | |
b7d861d9 BK |
2067 | return 0; |
2068 | } | |
b3040e40 | 2069 | |
b7d861d9 BK |
2070 | static int dmac_free_threads(struct pl330_dmac *pl330) |
2071 | { | |
2072 | struct pl330_info *pi = pl330->pinfo; | |
2073 | int chans = pi->pcfg.num_chan; | |
2074 | struct pl330_thread *thrd; | |
2075 | int i; | |
b3040e40 | 2076 | |
b7d861d9 BK |
2077 | /* Release Channel threads */ |
2078 | for (i = 0; i < chans; i++) { | |
2079 | thrd = &pl330->channels[i]; | |
2080 | pl330_release_channel((void *)thrd); | |
2081 | } | |
b3040e40 | 2082 | |
b7d861d9 BK |
2083 | /* Free memory */ |
2084 | kfree(pl330->channels); | |
b3040e40 | 2085 | |
b7d861d9 BK |
2086 | return 0; |
2087 | } | |
b3040e40 | 2088 | |
b7d861d9 BK |
2089 | static void dmac_free_resources(struct pl330_dmac *pl330) |
2090 | { | |
2091 | struct pl330_info *pi = pl330->pinfo; | |
2092 | int chans = pi->pcfg.num_chan; | |
b3040e40 | 2093 | |
b7d861d9 BK |
2094 | dmac_free_threads(pl330); |
2095 | ||
2096 | dma_free_coherent(pi->dev, chans * pi->mcbufsz, | |
2097 | pl330->mcode_cpu, pl330->mcode_bus); | |
2098 | } | |
2099 | ||
2100 | static void pl330_del(struct pl330_info *pi) | |
2101 | { | |
2102 | struct pl330_dmac *pl330; | |
2103 | ||
2104 | if (!pi || !pi->pl330_data) | |
2105 | return; | |
2106 | ||
2107 | pl330 = pi->pl330_data; | |
2108 | ||
2109 | pl330->state = UNINIT; | |
2110 | ||
2111 | tasklet_kill(&pl330->tasks); | |
2112 | ||
2113 | /* Free DMAC resources */ | |
2114 | dmac_free_resources(pl330); | |
2115 | ||
2116 | kfree(pl330); | |
2117 | pi->pl330_data = NULL; | |
2118 | } | |
b3040e40 | 2119 | |
3e2ec13a TA |
2120 | /* forward declaration */ |
2121 | static struct amba_driver pl330_driver; | |
2122 | ||
b3040e40 JB |
2123 | static inline struct dma_pl330_chan * |
2124 | to_pchan(struct dma_chan *ch) | |
2125 | { | |
2126 | if (!ch) | |
2127 | return NULL; | |
2128 | ||
2129 | return container_of(ch, struct dma_pl330_chan, chan); | |
2130 | } | |
2131 | ||
2132 | static inline struct dma_pl330_desc * | |
2133 | to_desc(struct dma_async_tx_descriptor *tx) | |
2134 | { | |
2135 | return container_of(tx, struct dma_pl330_desc, txd); | |
2136 | } | |
2137 | ||
b3040e40 JB |
2138 | static inline void fill_queue(struct dma_pl330_chan *pch) |
2139 | { | |
2140 | struct dma_pl330_desc *desc; | |
2141 | int ret; | |
2142 | ||
2143 | list_for_each_entry(desc, &pch->work_list, node) { | |
2144 | ||
2145 | /* If already submitted */ | |
2146 | if (desc->status == BUSY) | |
30fb980b | 2147 | continue; |
b3040e40 JB |
2148 | |
2149 | ret = pl330_submit_req(pch->pl330_chid, | |
2150 | &desc->req); | |
2151 | if (!ret) { | |
2152 | desc->status = BUSY; | |
b3040e40 JB |
2153 | } else if (ret == -EAGAIN) { |
2154 | /* QFull or DMAC Dying */ | |
2155 | break; | |
2156 | } else { | |
2157 | /* Unacceptable request */ | |
2158 | desc->status = DONE; | |
2159 | dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n", | |
2160 | __func__, __LINE__, desc->txd.cookie); | |
2161 | tasklet_schedule(&pch->task); | |
2162 | } | |
2163 | } | |
2164 | } | |
2165 | ||
2166 | static void pl330_tasklet(unsigned long data) | |
2167 | { | |
2168 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
2169 | struct dma_pl330_desc *desc, *_dt; | |
2170 | unsigned long flags; | |
b3040e40 JB |
2171 | |
2172 | spin_lock_irqsave(&pch->lock, flags); | |
2173 | ||
2174 | /* Pick up ripe tomatoes */ | |
2175 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
2176 | if (desc->status == DONE) { | |
30c1dc0f | 2177 | if (!pch->cyclic) |
eab21585 | 2178 | dma_cookie_complete(&desc->txd); |
39ff8613 | 2179 | list_move_tail(&desc->node, &pch->completed_list); |
b3040e40 JB |
2180 | } |
2181 | ||
2182 | /* Try to submit a req imm. next to the last completed cookie */ | |
2183 | fill_queue(pch); | |
2184 | ||
2185 | /* Make sure the PL330 Channel thread is active */ | |
2186 | pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START); | |
2187 | ||
39ff8613 LPC |
2188 | while (!list_empty(&pch->completed_list)) { |
2189 | dma_async_tx_callback callback; | |
2190 | void *callback_param; | |
b3040e40 | 2191 | |
39ff8613 LPC |
2192 | desc = list_first_entry(&pch->completed_list, |
2193 | struct dma_pl330_desc, node); | |
2194 | ||
2195 | callback = desc->txd.callback; | |
2196 | callback_param = desc->txd.callback_param; | |
2197 | ||
2198 | if (pch->cyclic) { | |
2199 | desc->status = PREP; | |
2200 | list_move_tail(&desc->node, &pch->work_list); | |
2201 | } else { | |
2202 | desc->status = FREE; | |
2203 | list_move_tail(&desc->node, &pch->dmac->desc_pool); | |
2204 | } | |
2205 | ||
d38a8c62 DW |
2206 | dma_descriptor_unmap(&desc->txd); |
2207 | ||
39ff8613 LPC |
2208 | if (callback) { |
2209 | spin_unlock_irqrestore(&pch->lock, flags); | |
2210 | callback(callback_param); | |
2211 | spin_lock_irqsave(&pch->lock, flags); | |
2212 | } | |
2213 | } | |
2214 | spin_unlock_irqrestore(&pch->lock, flags); | |
b3040e40 JB |
2215 | } |
2216 | ||
3e2ec13a TA |
2217 | bool pl330_filter(struct dma_chan *chan, void *param) |
2218 | { | |
cd072515 | 2219 | u8 *peri_id; |
3e2ec13a TA |
2220 | |
2221 | if (chan->device->dev->driver != &pl330_driver.drv) | |
2222 | return false; | |
2223 | ||
cd072515 | 2224 | peri_id = chan->private; |
2f986ec6 | 2225 | return *peri_id == (unsigned long)param; |
3e2ec13a TA |
2226 | } |
2227 | EXPORT_SYMBOL(pl330_filter); | |
2228 | ||
a80258f9 PV |
2229 | static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, |
2230 | struct of_dma *ofdma) | |
2231 | { | |
2232 | int count = dma_spec->args_count; | |
2233 | struct dma_pl330_dmac *pdmac = ofdma->of_dma_data; | |
70cbb163 | 2234 | unsigned int chan_id; |
a80258f9 PV |
2235 | |
2236 | if (count != 1) | |
2237 | return NULL; | |
2238 | ||
70cbb163 LPC |
2239 | chan_id = dma_spec->args[0]; |
2240 | if (chan_id >= pdmac->num_peripherals) | |
2241 | return NULL; | |
a80258f9 | 2242 | |
70cbb163 | 2243 | return dma_get_slave_channel(&pdmac->peripherals[chan_id].chan); |
a80258f9 PV |
2244 | } |
2245 | ||
b3040e40 JB |
2246 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
2247 | { | |
2248 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2249 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
2250 | unsigned long flags; | |
2251 | ||
2252 | spin_lock_irqsave(&pch->lock, flags); | |
2253 | ||
d3ee98cd | 2254 | dma_cookie_init(chan); |
42bc9cf4 | 2255 | pch->cyclic = false; |
b3040e40 JB |
2256 | |
2257 | pch->pl330_chid = pl330_request_channel(&pdmac->pif); | |
2258 | if (!pch->pl330_chid) { | |
2259 | spin_unlock_irqrestore(&pch->lock, flags); | |
02747885 | 2260 | return -ENOMEM; |
b3040e40 JB |
2261 | } |
2262 | ||
2263 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
2264 | ||
2265 | spin_unlock_irqrestore(&pch->lock, flags); | |
2266 | ||
2267 | return 1; | |
2268 | } | |
2269 | ||
2270 | static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) | |
2271 | { | |
2272 | struct dma_pl330_chan *pch = to_pchan(chan); | |
39ff8613 | 2273 | struct dma_pl330_desc *desc; |
b3040e40 | 2274 | unsigned long flags; |
1d0c1d60 BK |
2275 | struct dma_pl330_dmac *pdmac = pch->dmac; |
2276 | struct dma_slave_config *slave_config; | |
ae43b886 | 2277 | LIST_HEAD(list); |
b3040e40 | 2278 | |
1d0c1d60 BK |
2279 | switch (cmd) { |
2280 | case DMA_TERMINATE_ALL: | |
2281 | spin_lock_irqsave(&pch->lock, flags); | |
b3040e40 | 2282 | |
1d0c1d60 BK |
2283 | /* FLUSH the PL330 Channel thread */ |
2284 | pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH); | |
b3040e40 | 2285 | |
1d0c1d60 | 2286 | /* Mark all desc done */ |
04abf5da LPC |
2287 | list_for_each_entry(desc, &pch->submitted_list, node) { |
2288 | desc->status = FREE; | |
2289 | dma_cookie_complete(&desc->txd); | |
2290 | } | |
2291 | ||
39ff8613 LPC |
2292 | list_for_each_entry(desc, &pch->work_list , node) { |
2293 | desc->status = FREE; | |
2294 | dma_cookie_complete(&desc->txd); | |
2295 | } | |
2296 | ||
2297 | list_for_each_entry(desc, &pch->completed_list , node) { | |
2298 | desc->status = FREE; | |
2299 | dma_cookie_complete(&desc->txd); | |
ae43b886 | 2300 | } |
b3040e40 | 2301 | |
04abf5da | 2302 | list_splice_tail_init(&pch->submitted_list, &pdmac->desc_pool); |
39ff8613 LPC |
2303 | list_splice_tail_init(&pch->work_list, &pdmac->desc_pool); |
2304 | list_splice_tail_init(&pch->completed_list, &pdmac->desc_pool); | |
1d0c1d60 | 2305 | spin_unlock_irqrestore(&pch->lock, flags); |
1d0c1d60 BK |
2306 | break; |
2307 | case DMA_SLAVE_CONFIG: | |
2308 | slave_config = (struct dma_slave_config *)arg; | |
2309 | ||
db8196df | 2310 | if (slave_config->direction == DMA_MEM_TO_DEV) { |
1d0c1d60 BK |
2311 | if (slave_config->dst_addr) |
2312 | pch->fifo_addr = slave_config->dst_addr; | |
2313 | if (slave_config->dst_addr_width) | |
2314 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
2315 | if (slave_config->dst_maxburst) | |
2316 | pch->burst_len = slave_config->dst_maxburst; | |
db8196df | 2317 | } else if (slave_config->direction == DMA_DEV_TO_MEM) { |
1d0c1d60 BK |
2318 | if (slave_config->src_addr) |
2319 | pch->fifo_addr = slave_config->src_addr; | |
2320 | if (slave_config->src_addr_width) | |
2321 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
2322 | if (slave_config->src_maxburst) | |
2323 | pch->burst_len = slave_config->src_maxburst; | |
2324 | } | |
2325 | break; | |
2326 | default: | |
2327 | dev_err(pch->dmac->pif.dev, "Not supported command.\n"); | |
2328 | return -ENXIO; | |
2329 | } | |
b3040e40 JB |
2330 | |
2331 | return 0; | |
2332 | } | |
2333 | ||
2334 | static void pl330_free_chan_resources(struct dma_chan *chan) | |
2335 | { | |
2336 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2337 | unsigned long flags; | |
2338 | ||
b3040e40 JB |
2339 | tasklet_kill(&pch->task); |
2340 | ||
da331ba8 BZ |
2341 | spin_lock_irqsave(&pch->lock, flags); |
2342 | ||
b3040e40 JB |
2343 | pl330_release_channel(pch->pl330_chid); |
2344 | pch->pl330_chid = NULL; | |
2345 | ||
42bc9cf4 BK |
2346 | if (pch->cyclic) |
2347 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
2348 | ||
b3040e40 JB |
2349 | spin_unlock_irqrestore(&pch->lock, flags); |
2350 | } | |
2351 | ||
2352 | static enum dma_status | |
2353 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
2354 | struct dma_tx_state *txstate) | |
2355 | { | |
96a2af41 | 2356 | return dma_cookie_status(chan, cookie, txstate); |
b3040e40 JB |
2357 | } |
2358 | ||
2359 | static void pl330_issue_pending(struct dma_chan *chan) | |
2360 | { | |
04abf5da LPC |
2361 | struct dma_pl330_chan *pch = to_pchan(chan); |
2362 | unsigned long flags; | |
2363 | ||
2364 | spin_lock_irqsave(&pch->lock, flags); | |
2365 | list_splice_tail_init(&pch->submitted_list, &pch->work_list); | |
2366 | spin_unlock_irqrestore(&pch->lock, flags); | |
2367 | ||
2368 | pl330_tasklet((unsigned long)pch); | |
b3040e40 JB |
2369 | } |
2370 | ||
2371 | /* | |
2372 | * We returned the last one of the circular list of descriptor(s) | |
2373 | * from prep_xxx, so the argument to submit corresponds to the last | |
2374 | * descriptor of the list. | |
2375 | */ | |
2376 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
2377 | { | |
2378 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
2379 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
2380 | dma_cookie_t cookie; | |
2381 | unsigned long flags; | |
2382 | ||
2383 | spin_lock_irqsave(&pch->lock, flags); | |
2384 | ||
2385 | /* Assign cookies to all nodes */ | |
b3040e40 JB |
2386 | while (!list_empty(&last->node)) { |
2387 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
fc514460 LPC |
2388 | if (pch->cyclic) { |
2389 | desc->txd.callback = last->txd.callback; | |
2390 | desc->txd.callback_param = last->txd.callback_param; | |
2391 | } | |
b3040e40 | 2392 | |
884485e1 | 2393 | dma_cookie_assign(&desc->txd); |
b3040e40 | 2394 | |
04abf5da | 2395 | list_move_tail(&desc->node, &pch->submitted_list); |
b3040e40 JB |
2396 | } |
2397 | ||
884485e1 | 2398 | cookie = dma_cookie_assign(&last->txd); |
04abf5da | 2399 | list_add_tail(&last->node, &pch->submitted_list); |
b3040e40 JB |
2400 | spin_unlock_irqrestore(&pch->lock, flags); |
2401 | ||
2402 | return cookie; | |
2403 | } | |
2404 | ||
2405 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
2406 | { | |
b3040e40 | 2407 | desc->req.x = &desc->px; |
b3040e40 | 2408 | desc->rqcfg.swap = SWAP_NO; |
f0564c7e LPC |
2409 | desc->rqcfg.scctl = CCTRL0; |
2410 | desc->rqcfg.dcctl = CCTRL0; | |
b3040e40 | 2411 | desc->req.cfg = &desc->rqcfg; |
b3040e40 JB |
2412 | desc->txd.tx_submit = pl330_tx_submit; |
2413 | ||
2414 | INIT_LIST_HEAD(&desc->node); | |
2415 | } | |
2416 | ||
2417 | /* Returns the number of descriptors added to the DMAC pool */ | |
5a67ac57 | 2418 | static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count) |
b3040e40 JB |
2419 | { |
2420 | struct dma_pl330_desc *desc; | |
2421 | unsigned long flags; | |
2422 | int i; | |
2423 | ||
2424 | if (!pdmac) | |
2425 | return 0; | |
2426 | ||
0baf8f6a | 2427 | desc = kcalloc(count, sizeof(*desc), flg); |
b3040e40 JB |
2428 | if (!desc) |
2429 | return 0; | |
2430 | ||
2431 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
2432 | ||
2433 | for (i = 0; i < count; i++) { | |
2434 | _init_desc(&desc[i]); | |
2435 | list_add_tail(&desc[i].node, &pdmac->desc_pool); | |
2436 | } | |
2437 | ||
2438 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
2439 | ||
2440 | return count; | |
2441 | } | |
2442 | ||
2443 | static struct dma_pl330_desc * | |
2444 | pluck_desc(struct dma_pl330_dmac *pdmac) | |
2445 | { | |
2446 | struct dma_pl330_desc *desc = NULL; | |
2447 | unsigned long flags; | |
2448 | ||
2449 | if (!pdmac) | |
2450 | return NULL; | |
2451 | ||
2452 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
2453 | ||
2454 | if (!list_empty(&pdmac->desc_pool)) { | |
2455 | desc = list_entry(pdmac->desc_pool.next, | |
2456 | struct dma_pl330_desc, node); | |
2457 | ||
2458 | list_del_init(&desc->node); | |
2459 | ||
2460 | desc->status = PREP; | |
2461 | desc->txd.callback = NULL; | |
2462 | } | |
2463 | ||
2464 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
2465 | ||
2466 | return desc; | |
2467 | } | |
2468 | ||
2469 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
2470 | { | |
2471 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
cd072515 | 2472 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
2473 | struct dma_pl330_desc *desc; |
2474 | ||
2475 | /* Pluck one desc from the pool of DMAC */ | |
2476 | desc = pluck_desc(pdmac); | |
2477 | ||
2478 | /* If the DMAC pool is empty, alloc new */ | |
2479 | if (!desc) { | |
2480 | if (!add_desc(pdmac, GFP_ATOMIC, 1)) | |
2481 | return NULL; | |
2482 | ||
2483 | /* Try again */ | |
2484 | desc = pluck_desc(pdmac); | |
2485 | if (!desc) { | |
2486 | dev_err(pch->dmac->pif.dev, | |
2487 | "%s:%d ALERT!\n", __func__, __LINE__); | |
2488 | return NULL; | |
2489 | } | |
2490 | } | |
2491 | ||
2492 | /* Initialize the descriptor */ | |
2493 | desc->pchan = pch; | |
2494 | desc->txd.cookie = 0; | |
2495 | async_tx_ack(&desc->txd); | |
2496 | ||
cd072515 | 2497 | desc->req.peri = peri_id ? pch->chan.chan_id : 0; |
3ecf51a4 | 2498 | desc->rqcfg.pcfg = &pch->dmac->pif.pcfg; |
b3040e40 JB |
2499 | |
2500 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
2501 | ||
2502 | return desc; | |
2503 | } | |
2504 | ||
2505 | static inline void fill_px(struct pl330_xfer *px, | |
2506 | dma_addr_t dst, dma_addr_t src, size_t len) | |
2507 | { | |
b3040e40 JB |
2508 | px->bytes = len; |
2509 | px->dst_addr = dst; | |
2510 | px->src_addr = src; | |
2511 | } | |
2512 | ||
2513 | static struct dma_pl330_desc * | |
2514 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
2515 | dma_addr_t src, size_t len) | |
2516 | { | |
2517 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
2518 | ||
2519 | if (!desc) { | |
2520 | dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", | |
2521 | __func__, __LINE__); | |
2522 | return NULL; | |
2523 | } | |
2524 | ||
2525 | /* | |
2526 | * Ideally we should lookout for reqs bigger than | |
2527 | * those that can be programmed with 256 bytes of | |
2528 | * MC buffer, but considering a req size is seldom | |
2529 | * going to be word-unaligned and more than 200MB, | |
2530 | * we take it easy. | |
2531 | * Also, should the limit is reached we'd rather | |
2532 | * have the platform increase MC buffer size than | |
2533 | * complicating this API driver. | |
2534 | */ | |
2535 | fill_px(&desc->px, dst, src, len); | |
2536 | ||
2537 | return desc; | |
2538 | } | |
2539 | ||
2540 | /* Call after fixing burst size */ | |
2541 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
2542 | { | |
2543 | struct dma_pl330_chan *pch = desc->pchan; | |
2544 | struct pl330_info *pi = &pch->dmac->pif; | |
2545 | int burst_len; | |
2546 | ||
2547 | burst_len = pi->pcfg.data_bus_width / 8; | |
2548 | burst_len *= pi->pcfg.data_buf_dep; | |
2549 | burst_len >>= desc->rqcfg.brst_size; | |
2550 | ||
2551 | /* src/dst_burst_len can't be more than 16 */ | |
2552 | if (burst_len > 16) | |
2553 | burst_len = 16; | |
2554 | ||
2555 | while (burst_len > 1) { | |
2556 | if (!(len % (burst_len << desc->rqcfg.brst_size))) | |
2557 | break; | |
2558 | burst_len--; | |
2559 | } | |
2560 | ||
2561 | return burst_len; | |
2562 | } | |
2563 | ||
42bc9cf4 BK |
2564 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
2565 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
185ecb5f | 2566 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 2567 | unsigned long flags, void *context) |
42bc9cf4 | 2568 | { |
fc514460 | 2569 | struct dma_pl330_desc *desc = NULL, *first = NULL; |
42bc9cf4 | 2570 | struct dma_pl330_chan *pch = to_pchan(chan); |
fc514460 LPC |
2571 | struct dma_pl330_dmac *pdmac = pch->dmac; |
2572 | unsigned int i; | |
42bc9cf4 BK |
2573 | dma_addr_t dst; |
2574 | dma_addr_t src; | |
2575 | ||
fc514460 | 2576 | if (len % period_len != 0) |
42bc9cf4 | 2577 | return NULL; |
42bc9cf4 | 2578 | |
fc514460 | 2579 | if (!is_slave_direction(direction)) { |
42bc9cf4 BK |
2580 | dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n", |
2581 | __func__, __LINE__); | |
2582 | return NULL; | |
2583 | } | |
2584 | ||
fc514460 LPC |
2585 | for (i = 0; i < len / period_len; i++) { |
2586 | desc = pl330_get_desc(pch); | |
2587 | if (!desc) { | |
2588 | dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", | |
2589 | __func__, __LINE__); | |
42bc9cf4 | 2590 | |
fc514460 LPC |
2591 | if (!first) |
2592 | return NULL; | |
2593 | ||
2594 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
2595 | ||
2596 | while (!list_empty(&first->node)) { | |
2597 | desc = list_entry(first->node.next, | |
2598 | struct dma_pl330_desc, node); | |
2599 | list_move_tail(&desc->node, &pdmac->desc_pool); | |
2600 | } | |
2601 | ||
2602 | list_move_tail(&first->node, &pdmac->desc_pool); | |
2603 | ||
2604 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
42bc9cf4 | 2605 | |
fc514460 LPC |
2606 | return NULL; |
2607 | } | |
2608 | ||
2609 | switch (direction) { | |
2610 | case DMA_MEM_TO_DEV: | |
2611 | desc->rqcfg.src_inc = 1; | |
2612 | desc->rqcfg.dst_inc = 0; | |
fc514460 LPC |
2613 | src = dma_addr; |
2614 | dst = pch->fifo_addr; | |
2615 | break; | |
2616 | case DMA_DEV_TO_MEM: | |
2617 | desc->rqcfg.src_inc = 0; | |
2618 | desc->rqcfg.dst_inc = 1; | |
fc514460 LPC |
2619 | src = pch->fifo_addr; |
2620 | dst = dma_addr; | |
2621 | break; | |
2622 | default: | |
2623 | break; | |
2624 | } | |
2625 | ||
585a9d0b | 2626 | desc->req.rqtype = direction; |
fc514460 LPC |
2627 | desc->rqcfg.brst_size = pch->burst_sz; |
2628 | desc->rqcfg.brst_len = 1; | |
2629 | fill_px(&desc->px, dst, src, period_len); | |
2630 | ||
2631 | if (!first) | |
2632 | first = desc; | |
2633 | else | |
2634 | list_add_tail(&desc->node, &first->node); | |
2635 | ||
2636 | dma_addr += period_len; | |
2637 | } | |
2638 | ||
2639 | if (!desc) | |
2640 | return NULL; | |
2641 | ||
2642 | pch->cyclic = true; | |
2643 | desc->txd.flags = flags; | |
42bc9cf4 BK |
2644 | |
2645 | return &desc->txd; | |
2646 | } | |
2647 | ||
b3040e40 JB |
2648 | static struct dma_async_tx_descriptor * |
2649 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
2650 | dma_addr_t src, size_t len, unsigned long flags) | |
2651 | { | |
2652 | struct dma_pl330_desc *desc; | |
2653 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 JB |
2654 | struct pl330_info *pi; |
2655 | int burst; | |
2656 | ||
4e0e6109 | 2657 | if (unlikely(!pch || !len)) |
b3040e40 JB |
2658 | return NULL; |
2659 | ||
b3040e40 JB |
2660 | pi = &pch->dmac->pif; |
2661 | ||
2662 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); | |
2663 | if (!desc) | |
2664 | return NULL; | |
2665 | ||
2666 | desc->rqcfg.src_inc = 1; | |
2667 | desc->rqcfg.dst_inc = 1; | |
585a9d0b | 2668 | desc->req.rqtype = DMA_MEM_TO_MEM; |
b3040e40 JB |
2669 | |
2670 | /* Select max possible burst size */ | |
2671 | burst = pi->pcfg.data_bus_width / 8; | |
2672 | ||
2673 | while (burst > 1) { | |
2674 | if (!(len % burst)) | |
2675 | break; | |
2676 | burst /= 2; | |
2677 | } | |
2678 | ||
2679 | desc->rqcfg.brst_size = 0; | |
2680 | while (burst != (1 << desc->rqcfg.brst_size)) | |
2681 | desc->rqcfg.brst_size++; | |
2682 | ||
2683 | desc->rqcfg.brst_len = get_burst_len(desc, len); | |
2684 | ||
2685 | desc->txd.flags = flags; | |
2686 | ||
2687 | return &desc->txd; | |
2688 | } | |
2689 | ||
52a9d179 CP |
2690 | static void __pl330_giveback_desc(struct dma_pl330_dmac *pdmac, |
2691 | struct dma_pl330_desc *first) | |
2692 | { | |
2693 | unsigned long flags; | |
2694 | struct dma_pl330_desc *desc; | |
2695 | ||
2696 | if (!first) | |
2697 | return; | |
2698 | ||
2699 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
2700 | ||
2701 | while (!list_empty(&first->node)) { | |
2702 | desc = list_entry(first->node.next, | |
2703 | struct dma_pl330_desc, node); | |
2704 | list_move_tail(&desc->node, &pdmac->desc_pool); | |
2705 | } | |
2706 | ||
2707 | list_move_tail(&first->node, &pdmac->desc_pool); | |
2708 | ||
2709 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
2710 | } | |
2711 | ||
b3040e40 JB |
2712 | static struct dma_async_tx_descriptor * |
2713 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 2714 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 2715 | unsigned long flg, void *context) |
b3040e40 JB |
2716 | { |
2717 | struct dma_pl330_desc *first, *desc = NULL; | |
2718 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 | 2719 | struct scatterlist *sg; |
1b9bb715 | 2720 | int i; |
b3040e40 JB |
2721 | dma_addr_t addr; |
2722 | ||
cd072515 | 2723 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 JB |
2724 | return NULL; |
2725 | ||
1b9bb715 | 2726 | addr = pch->fifo_addr; |
b3040e40 JB |
2727 | |
2728 | first = NULL; | |
2729 | ||
2730 | for_each_sg(sgl, sg, sg_len, i) { | |
2731 | ||
2732 | desc = pl330_get_desc(pch); | |
2733 | if (!desc) { | |
2734 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
2735 | ||
2736 | dev_err(pch->dmac->pif.dev, | |
2737 | "%s:%d Unable to fetch desc\n", | |
2738 | __func__, __LINE__); | |
52a9d179 | 2739 | __pl330_giveback_desc(pdmac, first); |
b3040e40 JB |
2740 | |
2741 | return NULL; | |
2742 | } | |
2743 | ||
2744 | if (!first) | |
2745 | first = desc; | |
2746 | else | |
2747 | list_add_tail(&desc->node, &first->node); | |
2748 | ||
db8196df | 2749 | if (direction == DMA_MEM_TO_DEV) { |
b3040e40 JB |
2750 | desc->rqcfg.src_inc = 1; |
2751 | desc->rqcfg.dst_inc = 0; | |
2752 | fill_px(&desc->px, | |
2753 | addr, sg_dma_address(sg), sg_dma_len(sg)); | |
2754 | } else { | |
2755 | desc->rqcfg.src_inc = 0; | |
2756 | desc->rqcfg.dst_inc = 1; | |
2757 | fill_px(&desc->px, | |
2758 | sg_dma_address(sg), addr, sg_dma_len(sg)); | |
2759 | } | |
2760 | ||
1b9bb715 | 2761 | desc->rqcfg.brst_size = pch->burst_sz; |
b3040e40 | 2762 | desc->rqcfg.brst_len = 1; |
585a9d0b | 2763 | desc->req.rqtype = direction; |
b3040e40 JB |
2764 | } |
2765 | ||
2766 | /* Return the last desc in the chain */ | |
2767 | desc->txd.flags = flg; | |
2768 | return &desc->txd; | |
2769 | } | |
2770 | ||
2771 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
2772 | { | |
2773 | if (pl330_update(data)) | |
2774 | return IRQ_HANDLED; | |
2775 | else | |
2776 | return IRQ_NONE; | |
2777 | } | |
2778 | ||
ca38ff13 LPC |
2779 | #define PL330_DMA_BUSWIDTHS \ |
2780 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
2781 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
2782 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
2783 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ | |
2784 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | |
2785 | ||
2786 | static int pl330_dma_device_slave_caps(struct dma_chan *dchan, | |
2787 | struct dma_slave_caps *caps) | |
2788 | { | |
2789 | caps->src_addr_widths = PL330_DMA_BUSWIDTHS; | |
2790 | caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS; | |
2791 | caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
2792 | caps->cmd_pause = false; | |
2793 | caps->cmd_terminate = true; | |
bfb9bb42 | 2794 | caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; |
ca38ff13 | 2795 | |
ca38ff13 LPC |
2796 | return 0; |
2797 | } | |
2798 | ||
463a1f8b | 2799 | static int |
aa25afad | 2800 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 JB |
2801 | { |
2802 | struct dma_pl330_platdata *pdat; | |
2803 | struct dma_pl330_dmac *pdmac; | |
0b94c577 | 2804 | struct dma_pl330_chan *pch, *_p; |
b3040e40 JB |
2805 | struct pl330_info *pi; |
2806 | struct dma_device *pd; | |
2807 | struct resource *res; | |
2808 | int i, ret, irq; | |
4e0e6109 | 2809 | int num_chan; |
b3040e40 | 2810 | |
d4adcc01 | 2811 | pdat = dev_get_platdata(&adev->dev); |
b3040e40 | 2812 | |
64113016 RK |
2813 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); |
2814 | if (ret) | |
2815 | return ret; | |
2816 | ||
b3040e40 | 2817 | /* Allocate a new DMAC and its Channels */ |
e4d43c17 | 2818 | pdmac = devm_kzalloc(&adev->dev, sizeof(*pdmac), GFP_KERNEL); |
b3040e40 JB |
2819 | if (!pdmac) { |
2820 | dev_err(&adev->dev, "unable to allocate mem\n"); | |
2821 | return -ENOMEM; | |
2822 | } | |
2823 | ||
2824 | pi = &pdmac->pif; | |
2825 | pi->dev = &adev->dev; | |
2826 | pi->pl330_data = NULL; | |
4e0e6109 | 2827 | pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0; |
b3040e40 JB |
2828 | |
2829 | res = &adev->res; | |
bcc7fa95 SK |
2830 | pi->base = devm_ioremap_resource(&adev->dev, res); |
2831 | if (IS_ERR(pi->base)) | |
2832 | return PTR_ERR(pi->base); | |
b3040e40 | 2833 | |
a2f5203f BK |
2834 | amba_set_drvdata(adev, pdmac); |
2835 | ||
02808b42 | 2836 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
e98b3caf MS |
2837 | irq = adev->irq[i]; |
2838 | if (irq) { | |
2839 | ret = devm_request_irq(&adev->dev, irq, | |
2840 | pl330_irq_handler, 0, | |
2841 | dev_name(&adev->dev), pi); | |
2842 | if (ret) | |
2843 | return ret; | |
2844 | } else { | |
2845 | break; | |
2846 | } | |
2847 | } | |
b3040e40 | 2848 | |
09677176 | 2849 | pi->pcfg.periph_id = adev->periphid; |
b3040e40 JB |
2850 | ret = pl330_add(pi); |
2851 | if (ret) | |
173e838c | 2852 | return ret; |
b3040e40 JB |
2853 | |
2854 | INIT_LIST_HEAD(&pdmac->desc_pool); | |
2855 | spin_lock_init(&pdmac->pool_lock); | |
2856 | ||
2857 | /* Create a descriptor pool of default size */ | |
2858 | if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC)) | |
2859 | dev_warn(&adev->dev, "unable to allocate desc\n"); | |
2860 | ||
2861 | pd = &pdmac->ddma; | |
2862 | INIT_LIST_HEAD(&pd->channels); | |
2863 | ||
2864 | /* Initialize channel parameters */ | |
c8473828 OJ |
2865 | if (pdat) |
2866 | num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan); | |
2867 | else | |
2868 | num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan); | |
2869 | ||
70cbb163 LPC |
2870 | pdmac->num_peripherals = num_chan; |
2871 | ||
4e0e6109 | 2872 | pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); |
61c6e753 SK |
2873 | if (!pdmac->peripherals) { |
2874 | ret = -ENOMEM; | |
2875 | dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n"); | |
e4d43c17 | 2876 | goto probe_err2; |
61c6e753 | 2877 | } |
b3040e40 | 2878 | |
4e0e6109 RH |
2879 | for (i = 0; i < num_chan; i++) { |
2880 | pch = &pdmac->peripherals[i]; | |
93ed5544 TA |
2881 | if (!adev->dev.of_node) |
2882 | pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; | |
2883 | else | |
2884 | pch->chan.private = adev->dev.of_node; | |
b3040e40 | 2885 | |
04abf5da | 2886 | INIT_LIST_HEAD(&pch->submitted_list); |
b3040e40 | 2887 | INIT_LIST_HEAD(&pch->work_list); |
39ff8613 | 2888 | INIT_LIST_HEAD(&pch->completed_list); |
b3040e40 JB |
2889 | spin_lock_init(&pch->lock); |
2890 | pch->pl330_chid = NULL; | |
b3040e40 | 2891 | pch->chan.device = pd; |
b3040e40 JB |
2892 | pch->dmac = pdmac; |
2893 | ||
2894 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
2895 | list_add_tail(&pch->chan.device_node, &pd->channels); |
2896 | } | |
2897 | ||
2898 | pd->dev = &adev->dev; | |
93ed5544 | 2899 | if (pdat) { |
cd072515 | 2900 | pd->cap_mask = pdat->cap_mask; |
93ed5544 | 2901 | } else { |
cd072515 | 2902 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
93ed5544 TA |
2903 | if (pi->pcfg.num_peri) { |
2904 | dma_cap_set(DMA_SLAVE, pd->cap_mask); | |
2905 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); | |
5557a419 | 2906 | dma_cap_set(DMA_PRIVATE, pd->cap_mask); |
93ed5544 TA |
2907 | } |
2908 | } | |
b3040e40 JB |
2909 | |
2910 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
2911 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
2912 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 2913 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
2914 | pd->device_tx_status = pl330_tx_status; |
2915 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
2916 | pd->device_control = pl330_control; | |
2917 | pd->device_issue_pending = pl330_issue_pending; | |
ca38ff13 | 2918 | pd->device_slave_caps = pl330_dma_device_slave_caps; |
b3040e40 JB |
2919 | |
2920 | ret = dma_async_device_register(pd); | |
2921 | if (ret) { | |
2922 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
0b94c577 PV |
2923 | goto probe_err3; |
2924 | } | |
2925 | ||
2926 | if (adev->dev.of_node) { | |
2927 | ret = of_dma_controller_register(adev->dev.of_node, | |
2928 | of_dma_pl330_xlate, pdmac); | |
2929 | if (ret) { | |
2930 | dev_err(&adev->dev, | |
2931 | "unable to register DMA to the generic DT DMA helpers\n"); | |
2932 | } | |
b3040e40 | 2933 | } |
b714b84e LPC |
2934 | |
2935 | adev->dev.dma_parms = &pdmac->dma_parms; | |
2936 | ||
dbaf6d85 VK |
2937 | /* |
2938 | * This is the limit for transfers with a buswidth of 1, larger | |
2939 | * buswidths will have larger limits. | |
2940 | */ | |
2941 | ret = dma_set_max_seg_size(&adev->dev, 1900800); | |
2942 | if (ret) | |
2943 | dev_err(&adev->dev, "unable to set the seg size\n"); | |
2944 | ||
b3040e40 | 2945 | |
b3040e40 JB |
2946 | dev_info(&adev->dev, |
2947 | "Loaded driver for PL330 DMAC-%d\n", adev->periphid); | |
2948 | dev_info(&adev->dev, | |
2949 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
2950 | pi->pcfg.data_buf_dep, | |
2951 | pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan, | |
2952 | pi->pcfg.num_peri, pi->pcfg.num_events); | |
2953 | ||
2954 | return 0; | |
0b94c577 | 2955 | probe_err3: |
0b94c577 PV |
2956 | /* Idle the DMAC */ |
2957 | list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, | |
2958 | chan.device_node) { | |
2959 | ||
2960 | /* Remove the channel */ | |
2961 | list_del(&pch->chan.device_node); | |
2962 | ||
2963 | /* Flush the channel */ | |
2964 | pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); | |
2965 | pl330_free_chan_resources(&pch->chan); | |
2966 | } | |
b3040e40 | 2967 | probe_err2: |
e4d43c17 | 2968 | pl330_del(pi); |
b3040e40 JB |
2969 | |
2970 | return ret; | |
2971 | } | |
2972 | ||
4bf27b8b | 2973 | static int pl330_remove(struct amba_device *adev) |
b3040e40 JB |
2974 | { |
2975 | struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev); | |
2976 | struct dma_pl330_chan *pch, *_p; | |
2977 | struct pl330_info *pi; | |
b3040e40 JB |
2978 | |
2979 | if (!pdmac) | |
2980 | return 0; | |
2981 | ||
0b94c577 PV |
2982 | if (adev->dev.of_node) |
2983 | of_dma_controller_free(adev->dev.of_node); | |
421da89a | 2984 | |
0b94c577 | 2985 | dma_async_device_unregister(&pdmac->ddma); |
b3040e40 JB |
2986 | |
2987 | /* Idle the DMAC */ | |
2988 | list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, | |
2989 | chan.device_node) { | |
2990 | ||
2991 | /* Remove the channel */ | |
2992 | list_del(&pch->chan.device_node); | |
2993 | ||
2994 | /* Flush the channel */ | |
2995 | pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); | |
2996 | pl330_free_chan_resources(&pch->chan); | |
2997 | } | |
2998 | ||
2999 | pi = &pdmac->pif; | |
3000 | ||
3001 | pl330_del(pi); | |
3002 | ||
b3040e40 JB |
3003 | return 0; |
3004 | } | |
3005 | ||
3006 | static struct amba_id pl330_ids[] = { | |
3007 | { | |
3008 | .id = 0x00041330, | |
3009 | .mask = 0x000fffff, | |
3010 | }, | |
3011 | { 0, 0 }, | |
3012 | }; | |
3013 | ||
e8fa516a DM |
3014 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
3015 | ||
b3040e40 JB |
3016 | static struct amba_driver pl330_driver = { |
3017 | .drv = { | |
3018 | .owner = THIS_MODULE, | |
3019 | .name = "dma-pl330", | |
3020 | }, | |
3021 | .id_table = pl330_ids, | |
3022 | .probe = pl330_probe, | |
3023 | .remove = pl330_remove, | |
3024 | }; | |
3025 | ||
9e5ed094 | 3026 | module_amba_driver(pl330_driver); |
b3040e40 JB |
3027 | |
3028 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
3029 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); | |
3030 | MODULE_LICENSE("GPL"); |