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b7d861d9 BK |
1 | /* |
2 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
b3040e40 JB |
4 | * |
5 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
6 | * Jaswinder Singh <jassi.brar@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
b7d861d9 | 14 | #include <linux/kernel.h> |
b3040e40 JB |
15 | #include <linux/io.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/module.h> | |
b7d861d9 BK |
19 | #include <linux/string.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/dma-mapping.h> | |
b3040e40 | 23 | #include <linux/dmaengine.h> |
b3040e40 JB |
24 | #include <linux/amba/bus.h> |
25 | #include <linux/amba/pl330.h> | |
1b9bb715 | 26 | #include <linux/scatterlist.h> |
93ed5544 | 27 | #include <linux/of.h> |
a80258f9 | 28 | #include <linux/of_dma.h> |
bcc7fa95 | 29 | #include <linux/err.h> |
ae43b328 | 30 | #include <linux/pm_runtime.h> |
b3040e40 | 31 | |
d2ebfb33 | 32 | #include "dmaengine.h" |
b7d861d9 BK |
33 | #define PL330_MAX_CHAN 8 |
34 | #define PL330_MAX_IRQS 32 | |
35 | #define PL330_MAX_PERI 32 | |
36 | ||
f0564c7e LPC |
37 | enum pl330_cachectrl { |
38 | CCTRL0, /* Noncacheable and nonbufferable */ | |
39 | CCTRL1, /* Bufferable only */ | |
40 | CCTRL2, /* Cacheable, but do not allocate */ | |
41 | CCTRL3, /* Cacheable and bufferable, but do not allocate */ | |
42 | INVALID1, /* AWCACHE = 0x1000 */ | |
43 | INVALID2, | |
44 | CCTRL6, /* Cacheable write-through, allocate on writes only */ | |
45 | CCTRL7, /* Cacheable write-back, allocate on writes only */ | |
b7d861d9 BK |
46 | }; |
47 | ||
48 | enum pl330_byteswap { | |
49 | SWAP_NO, | |
50 | SWAP_2, | |
51 | SWAP_4, | |
52 | SWAP_8, | |
53 | SWAP_16, | |
54 | }; | |
55 | ||
b7d861d9 BK |
56 | /* Register and Bit field Definitions */ |
57 | #define DS 0x0 | |
58 | #define DS_ST_STOP 0x0 | |
59 | #define DS_ST_EXEC 0x1 | |
60 | #define DS_ST_CMISS 0x2 | |
61 | #define DS_ST_UPDTPC 0x3 | |
62 | #define DS_ST_WFE 0x4 | |
63 | #define DS_ST_ATBRR 0x5 | |
64 | #define DS_ST_QBUSY 0x6 | |
65 | #define DS_ST_WFP 0x7 | |
66 | #define DS_ST_KILL 0x8 | |
67 | #define DS_ST_CMPLT 0x9 | |
68 | #define DS_ST_FLTCMP 0xe | |
69 | #define DS_ST_FAULT 0xf | |
70 | ||
71 | #define DPC 0x4 | |
72 | #define INTEN 0x20 | |
73 | #define ES 0x24 | |
74 | #define INTSTATUS 0x28 | |
75 | #define INTCLR 0x2c | |
76 | #define FSM 0x30 | |
77 | #define FSC 0x34 | |
78 | #define FTM 0x38 | |
79 | ||
80 | #define _FTC 0x40 | |
81 | #define FTC(n) (_FTC + (n)*0x4) | |
82 | ||
83 | #define _CS 0x100 | |
84 | #define CS(n) (_CS + (n)*0x8) | |
85 | #define CS_CNS (1 << 21) | |
86 | ||
87 | #define _CPC 0x104 | |
88 | #define CPC(n) (_CPC + (n)*0x8) | |
89 | ||
90 | #define _SA 0x400 | |
91 | #define SA(n) (_SA + (n)*0x20) | |
92 | ||
93 | #define _DA 0x404 | |
94 | #define DA(n) (_DA + (n)*0x20) | |
95 | ||
96 | #define _CC 0x408 | |
97 | #define CC(n) (_CC + (n)*0x20) | |
98 | ||
99 | #define CC_SRCINC (1 << 0) | |
100 | #define CC_DSTINC (1 << 14) | |
101 | #define CC_SRCPRI (1 << 8) | |
102 | #define CC_DSTPRI (1 << 22) | |
103 | #define CC_SRCNS (1 << 9) | |
104 | #define CC_DSTNS (1 << 23) | |
105 | #define CC_SRCIA (1 << 10) | |
106 | #define CC_DSTIA (1 << 24) | |
107 | #define CC_SRCBRSTLEN_SHFT 4 | |
108 | #define CC_DSTBRSTLEN_SHFT 18 | |
109 | #define CC_SRCBRSTSIZE_SHFT 1 | |
110 | #define CC_DSTBRSTSIZE_SHFT 15 | |
111 | #define CC_SRCCCTRL_SHFT 11 | |
112 | #define CC_SRCCCTRL_MASK 0x7 | |
113 | #define CC_DSTCCTRL_SHFT 25 | |
114 | #define CC_DRCCCTRL_MASK 0x7 | |
115 | #define CC_SWAP_SHFT 28 | |
116 | ||
117 | #define _LC0 0x40c | |
118 | #define LC0(n) (_LC0 + (n)*0x20) | |
119 | ||
120 | #define _LC1 0x410 | |
121 | #define LC1(n) (_LC1 + (n)*0x20) | |
122 | ||
123 | #define DBGSTATUS 0xd00 | |
124 | #define DBG_BUSY (1 << 0) | |
125 | ||
126 | #define DBGCMD 0xd04 | |
127 | #define DBGINST0 0xd08 | |
128 | #define DBGINST1 0xd0c | |
129 | ||
130 | #define CR0 0xe00 | |
131 | #define CR1 0xe04 | |
132 | #define CR2 0xe08 | |
133 | #define CR3 0xe0c | |
134 | #define CR4 0xe10 | |
135 | #define CRD 0xe14 | |
136 | ||
137 | #define PERIPH_ID 0xfe0 | |
3ecf51a4 BK |
138 | #define PERIPH_REV_SHIFT 20 |
139 | #define PERIPH_REV_MASK 0xf | |
140 | #define PERIPH_REV_R0P0 0 | |
141 | #define PERIPH_REV_R1P0 1 | |
142 | #define PERIPH_REV_R1P1 2 | |
b7d861d9 BK |
143 | |
144 | #define CR0_PERIPH_REQ_SET (1 << 0) | |
145 | #define CR0_BOOT_EN_SET (1 << 1) | |
146 | #define CR0_BOOT_MAN_NS (1 << 2) | |
147 | #define CR0_NUM_CHANS_SHIFT 4 | |
148 | #define CR0_NUM_CHANS_MASK 0x7 | |
149 | #define CR0_NUM_PERIPH_SHIFT 12 | |
150 | #define CR0_NUM_PERIPH_MASK 0x1f | |
151 | #define CR0_NUM_EVENTS_SHIFT 17 | |
152 | #define CR0_NUM_EVENTS_MASK 0x1f | |
153 | ||
154 | #define CR1_ICACHE_LEN_SHIFT 0 | |
155 | #define CR1_ICACHE_LEN_MASK 0x7 | |
156 | #define CR1_NUM_ICACHELINES_SHIFT 4 | |
157 | #define CR1_NUM_ICACHELINES_MASK 0xf | |
158 | ||
159 | #define CRD_DATA_WIDTH_SHIFT 0 | |
160 | #define CRD_DATA_WIDTH_MASK 0x7 | |
161 | #define CRD_WR_CAP_SHIFT 4 | |
162 | #define CRD_WR_CAP_MASK 0x7 | |
163 | #define CRD_WR_Q_DEP_SHIFT 8 | |
164 | #define CRD_WR_Q_DEP_MASK 0xf | |
165 | #define CRD_RD_CAP_SHIFT 12 | |
166 | #define CRD_RD_CAP_MASK 0x7 | |
167 | #define CRD_RD_Q_DEP_SHIFT 16 | |
168 | #define CRD_RD_Q_DEP_MASK 0xf | |
169 | #define CRD_DATA_BUFF_SHIFT 20 | |
170 | #define CRD_DATA_BUFF_MASK 0x3ff | |
171 | ||
172 | #define PART 0x330 | |
173 | #define DESIGNER 0x41 | |
174 | #define REVISION 0x0 | |
175 | #define INTEG_CFG 0x0 | |
176 | #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) | |
177 | ||
b7d861d9 BK |
178 | #define PL330_STATE_STOPPED (1 << 0) |
179 | #define PL330_STATE_EXECUTING (1 << 1) | |
180 | #define PL330_STATE_WFE (1 << 2) | |
181 | #define PL330_STATE_FAULTING (1 << 3) | |
182 | #define PL330_STATE_COMPLETING (1 << 4) | |
183 | #define PL330_STATE_WFP (1 << 5) | |
184 | #define PL330_STATE_KILLING (1 << 6) | |
185 | #define PL330_STATE_FAULT_COMPLETING (1 << 7) | |
186 | #define PL330_STATE_CACHEMISS (1 << 8) | |
187 | #define PL330_STATE_UPDTPC (1 << 9) | |
188 | #define PL330_STATE_ATBARRIER (1 << 10) | |
189 | #define PL330_STATE_QUEUEBUSY (1 << 11) | |
190 | #define PL330_STATE_INVALID (1 << 15) | |
191 | ||
192 | #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | |
193 | | PL330_STATE_WFE | PL330_STATE_FAULTING) | |
194 | ||
195 | #define CMD_DMAADDH 0x54 | |
196 | #define CMD_DMAEND 0x00 | |
197 | #define CMD_DMAFLUSHP 0x35 | |
198 | #define CMD_DMAGO 0xa0 | |
199 | #define CMD_DMALD 0x04 | |
200 | #define CMD_DMALDP 0x25 | |
201 | #define CMD_DMALP 0x20 | |
202 | #define CMD_DMALPEND 0x28 | |
203 | #define CMD_DMAKILL 0x01 | |
204 | #define CMD_DMAMOV 0xbc | |
205 | #define CMD_DMANOP 0x18 | |
206 | #define CMD_DMARMB 0x12 | |
207 | #define CMD_DMASEV 0x34 | |
208 | #define CMD_DMAST 0x08 | |
209 | #define CMD_DMASTP 0x29 | |
210 | #define CMD_DMASTZ 0x0c | |
211 | #define CMD_DMAWFE 0x36 | |
212 | #define CMD_DMAWFP 0x30 | |
213 | #define CMD_DMAWMB 0x13 | |
214 | ||
215 | #define SZ_DMAADDH 3 | |
216 | #define SZ_DMAEND 1 | |
217 | #define SZ_DMAFLUSHP 2 | |
218 | #define SZ_DMALD 1 | |
219 | #define SZ_DMALDP 2 | |
220 | #define SZ_DMALP 2 | |
221 | #define SZ_DMALPEND 2 | |
222 | #define SZ_DMAKILL 1 | |
223 | #define SZ_DMAMOV 6 | |
224 | #define SZ_DMANOP 1 | |
225 | #define SZ_DMARMB 1 | |
226 | #define SZ_DMASEV 2 | |
227 | #define SZ_DMAST 1 | |
228 | #define SZ_DMASTP 2 | |
229 | #define SZ_DMASTZ 1 | |
230 | #define SZ_DMAWFE 2 | |
231 | #define SZ_DMAWFP 2 | |
232 | #define SZ_DMAWMB 1 | |
233 | #define SZ_DMAGO 6 | |
234 | ||
235 | #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) | |
236 | #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) | |
237 | ||
238 | #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) | |
239 | #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) | |
240 | ||
241 | /* | |
242 | * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req | |
243 | * at 1byte/burst for P<->M and M<->M respectively. | |
244 | * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req | |
245 | * should be enough for P<->M and M<->M respectively. | |
246 | */ | |
247 | #define MCODE_BUFF_PER_REQ 256 | |
248 | ||
b7d861d9 BK |
249 | /* Use this _only_ to wait on transient states */ |
250 | #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); | |
251 | ||
252 | #ifdef PL330_DEBUG_MCGEN | |
253 | static unsigned cmd_line; | |
254 | #define PL330_DBGCMD_DUMP(off, x...) do { \ | |
255 | printk("%x:", cmd_line); \ | |
256 | printk(x); \ | |
257 | cmd_line += off; \ | |
258 | } while (0) | |
259 | #define PL330_DBGMC_START(addr) (cmd_line = addr) | |
260 | #else | |
261 | #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) | |
262 | #define PL330_DBGMC_START(addr) do {} while (0) | |
263 | #endif | |
264 | ||
265 | /* The number of default descriptors */ | |
d2ebfb33 | 266 | |
b3040e40 JB |
267 | #define NR_DEFAULT_DESC 16 |
268 | ||
ae43b328 KK |
269 | /* Delay for runtime PM autosuspend, ms */ |
270 | #define PL330_AUTOSUSPEND_DELAY 20 | |
271 | ||
b7d861d9 BK |
272 | /* Populated by the PL330 core driver for DMA API driver's info */ |
273 | struct pl330_config { | |
274 | u32 periph_id; | |
b7d861d9 BK |
275 | #define DMAC_MODE_NS (1 << 0) |
276 | unsigned int mode; | |
277 | unsigned int data_bus_width:10; /* In number of bits */ | |
1f0a5cbf | 278 | unsigned int data_buf_dep:11; |
b7d861d9 BK |
279 | unsigned int num_chan:4; |
280 | unsigned int num_peri:6; | |
281 | u32 peri_ns; | |
282 | unsigned int num_events:6; | |
283 | u32 irq_ns; | |
284 | }; | |
285 | ||
b7d861d9 BK |
286 | /** |
287 | * Request Configuration. | |
288 | * The PL330 core does not modify this and uses the last | |
289 | * working configuration if the request doesn't provide any. | |
290 | * | |
291 | * The Client may want to provide this info only for the | |
292 | * first request and a request with new settings. | |
293 | */ | |
294 | struct pl330_reqcfg { | |
295 | /* Address Incrementing */ | |
296 | unsigned dst_inc:1; | |
297 | unsigned src_inc:1; | |
298 | ||
299 | /* | |
300 | * For now, the SRC & DST protection levels | |
301 | * and burst size/length are assumed same. | |
302 | */ | |
303 | bool nonsecure; | |
304 | bool privileged; | |
305 | bool insnaccess; | |
306 | unsigned brst_len:5; | |
307 | unsigned brst_size:3; /* in power of 2 */ | |
308 | ||
f0564c7e LPC |
309 | enum pl330_cachectrl dcctl; |
310 | enum pl330_cachectrl scctl; | |
b7d861d9 | 311 | enum pl330_byteswap swap; |
3ecf51a4 | 312 | struct pl330_config *pcfg; |
b7d861d9 BK |
313 | }; |
314 | ||
315 | /* | |
316 | * One cycle of DMAC operation. | |
317 | * There may be more than one xfer in a request. | |
318 | */ | |
319 | struct pl330_xfer { | |
320 | u32 src_addr; | |
321 | u32 dst_addr; | |
322 | /* Size to xfer */ | |
323 | u32 bytes; | |
b7d861d9 BK |
324 | }; |
325 | ||
326 | /* The xfer callbacks are made with one of these arguments. */ | |
327 | enum pl330_op_err { | |
328 | /* The all xfers in the request were success. */ | |
329 | PL330_ERR_NONE, | |
330 | /* If req aborted due to global error. */ | |
331 | PL330_ERR_ABORT, | |
332 | /* If req failed due to problem with Channel. */ | |
333 | PL330_ERR_FAIL, | |
334 | }; | |
335 | ||
b7d861d9 BK |
336 | enum dmamov_dst { |
337 | SAR = 0, | |
338 | CCR, | |
339 | DAR, | |
340 | }; | |
341 | ||
342 | enum pl330_dst { | |
343 | SRC = 0, | |
344 | DST, | |
345 | }; | |
346 | ||
347 | enum pl330_cond { | |
348 | SINGLE, | |
349 | BURST, | |
350 | ALWAYS, | |
351 | }; | |
352 | ||
9dc5a315 LPC |
353 | struct dma_pl330_desc; |
354 | ||
b7d861d9 BK |
355 | struct _pl330_req { |
356 | u32 mc_bus; | |
357 | void *mc_cpu; | |
9dc5a315 | 358 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
359 | }; |
360 | ||
361 | /* ToBeDone for tasklet */ | |
362 | struct _pl330_tbd { | |
363 | bool reset_dmac; | |
364 | bool reset_mngr; | |
365 | u8 reset_chan; | |
366 | }; | |
367 | ||
368 | /* A DMAC Thread */ | |
369 | struct pl330_thread { | |
370 | u8 id; | |
371 | int ev; | |
372 | /* If the channel is not yet acquired by any client */ | |
373 | bool free; | |
374 | /* Parent DMAC */ | |
375 | struct pl330_dmac *dmac; | |
376 | /* Only two at a time */ | |
377 | struct _pl330_req req[2]; | |
378 | /* Index of the last enqueued request */ | |
379 | unsigned lstenq; | |
380 | /* Index of the last submitted request or -1 if the DMA is stopped */ | |
381 | int req_running; | |
382 | }; | |
383 | ||
384 | enum pl330_dmac_state { | |
385 | UNINIT, | |
386 | INIT, | |
387 | DYING, | |
388 | }; | |
389 | ||
b3040e40 JB |
390 | enum desc_status { |
391 | /* In the DMAC pool */ | |
392 | FREE, | |
393 | /* | |
d73111c6 | 394 | * Allocated to some channel during prep_xxx |
b3040e40 JB |
395 | * Also may be sitting on the work_list. |
396 | */ | |
397 | PREP, | |
398 | /* | |
399 | * Sitting on the work_list and already submitted | |
400 | * to the PL330 core. Not more than two descriptors | |
401 | * of a channel can be BUSY at any time. | |
402 | */ | |
403 | BUSY, | |
404 | /* | |
405 | * Sitting on the channel work_list but xfer done | |
406 | * by PL330 core | |
407 | */ | |
408 | DONE, | |
409 | }; | |
410 | ||
411 | struct dma_pl330_chan { | |
412 | /* Schedule desc completion */ | |
413 | struct tasklet_struct task; | |
414 | ||
415 | /* DMA-Engine Channel */ | |
416 | struct dma_chan chan; | |
417 | ||
04abf5da LPC |
418 | /* List of submitted descriptors */ |
419 | struct list_head submitted_list; | |
420 | /* List of issued descriptors */ | |
b3040e40 | 421 | struct list_head work_list; |
39ff8613 LPC |
422 | /* List of completed descriptors */ |
423 | struct list_head completed_list; | |
b3040e40 JB |
424 | |
425 | /* Pointer to the DMAC that manages this channel, | |
426 | * NULL if the channel is available to be acquired. | |
427 | * As the parent, this DMAC also provides descriptors | |
428 | * to the channel. | |
429 | */ | |
f6f2421c | 430 | struct pl330_dmac *dmac; |
b3040e40 JB |
431 | |
432 | /* To protect channel manipulation */ | |
433 | spinlock_t lock; | |
434 | ||
65ad6060 LPC |
435 | /* |
436 | * Hardware channel thread of PL330 DMAC. NULL if the channel is | |
437 | * available. | |
b3040e40 | 438 | */ |
65ad6060 | 439 | struct pl330_thread *thread; |
1b9bb715 BK |
440 | |
441 | /* For D-to-M and M-to-D channels */ | |
442 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 443 | int burst_len; /* the number of burst */ |
1b9bb715 | 444 | dma_addr_t fifo_addr; |
42bc9cf4 BK |
445 | |
446 | /* for cyclic capability */ | |
447 | bool cyclic; | |
b3040e40 JB |
448 | }; |
449 | ||
f6f2421c | 450 | struct pl330_dmac { |
b3040e40 JB |
451 | /* DMA-Engine Device */ |
452 | struct dma_device ddma; | |
453 | ||
b714b84e LPC |
454 | /* Holds info about sg limitations */ |
455 | struct device_dma_parameters dma_parms; | |
456 | ||
b3040e40 JB |
457 | /* Pool of descriptors available for the DMAC's channels */ |
458 | struct list_head desc_pool; | |
459 | /* To protect desc_pool manipulation */ | |
460 | spinlock_t pool_lock; | |
461 | ||
f6f2421c LPC |
462 | /* Size of MicroCode buffers for each channel. */ |
463 | unsigned mcbufsz; | |
464 | /* ioremap'ed address of PL330 registers. */ | |
465 | void __iomem *base; | |
466 | /* Populated by the PL330 core driver during pl330_add */ | |
467 | struct pl330_config pcfg; | |
468 | ||
469 | spinlock_t lock; | |
470 | /* Maximum possible events/irqs */ | |
471 | int events[32]; | |
472 | /* BUS address of MicroCode buffer */ | |
473 | dma_addr_t mcode_bus; | |
474 | /* CPU address of MicroCode buffer */ | |
475 | void *mcode_cpu; | |
476 | /* List of all Channel threads */ | |
477 | struct pl330_thread *channels; | |
478 | /* Pointer to the MANAGER thread */ | |
479 | struct pl330_thread *manager; | |
480 | /* To handle bad news in interrupt */ | |
481 | struct tasklet_struct tasks; | |
482 | struct _pl330_tbd dmac_tbd; | |
483 | /* State of DMAC operation */ | |
484 | enum pl330_dmac_state state; | |
485 | /* Holds list of reqs with due callbacks */ | |
486 | struct list_head req_done; | |
487 | ||
b3040e40 | 488 | /* Peripheral channels connected to this DMAC */ |
70cbb163 | 489 | unsigned int num_peripherals; |
4e0e6109 | 490 | struct dma_pl330_chan *peripherals; /* keep at end */ |
b3040e40 JB |
491 | }; |
492 | ||
493 | struct dma_pl330_desc { | |
494 | /* To attach to a queue as child */ | |
495 | struct list_head node; | |
496 | ||
497 | /* Descriptor for the DMA Engine API */ | |
498 | struct dma_async_tx_descriptor txd; | |
499 | ||
500 | /* Xfer for PL330 core */ | |
501 | struct pl330_xfer px; | |
502 | ||
503 | struct pl330_reqcfg rqcfg; | |
b3040e40 JB |
504 | |
505 | enum desc_status status; | |
506 | ||
507 | /* The channel which currently holds this desc */ | |
508 | struct dma_pl330_chan *pchan; | |
9dc5a315 LPC |
509 | |
510 | enum dma_transfer_direction rqtype; | |
511 | /* Index of peripheral for the xfer. */ | |
512 | unsigned peri:5; | |
513 | /* Hook to attach to DMAC's list of reqs with due callback */ | |
514 | struct list_head rqd; | |
515 | }; | |
516 | ||
517 | struct _xfer_spec { | |
518 | u32 ccr; | |
519 | struct dma_pl330_desc *desc; | |
b3040e40 JB |
520 | }; |
521 | ||
b7d861d9 BK |
522 | static inline bool _queue_empty(struct pl330_thread *thrd) |
523 | { | |
8ed30a14 | 524 | return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL; |
b7d861d9 BK |
525 | } |
526 | ||
527 | static inline bool _queue_full(struct pl330_thread *thrd) | |
528 | { | |
8ed30a14 | 529 | return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; |
b7d861d9 BK |
530 | } |
531 | ||
532 | static inline bool is_manager(struct pl330_thread *thrd) | |
533 | { | |
fbbcd9be | 534 | return thrd->dmac->manager == thrd; |
b7d861d9 BK |
535 | } |
536 | ||
537 | /* If manager of the thread is in Non-Secure mode */ | |
538 | static inline bool _manager_ns(struct pl330_thread *thrd) | |
539 | { | |
f6f2421c | 540 | return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; |
b7d861d9 BK |
541 | } |
542 | ||
3ecf51a4 BK |
543 | static inline u32 get_revision(u32 periph_id) |
544 | { | |
545 | return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; | |
546 | } | |
547 | ||
b7d861d9 BK |
548 | static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], |
549 | enum pl330_dst da, u16 val) | |
550 | { | |
551 | if (dry_run) | |
552 | return SZ_DMAADDH; | |
553 | ||
554 | buf[0] = CMD_DMAADDH; | |
555 | buf[0] |= (da << 1); | |
556 | *((u16 *)&buf[1]) = val; | |
557 | ||
558 | PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", | |
559 | da == 1 ? "DA" : "SA", val); | |
560 | ||
561 | return SZ_DMAADDH; | |
562 | } | |
563 | ||
564 | static inline u32 _emit_END(unsigned dry_run, u8 buf[]) | |
565 | { | |
566 | if (dry_run) | |
567 | return SZ_DMAEND; | |
568 | ||
569 | buf[0] = CMD_DMAEND; | |
570 | ||
571 | PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); | |
572 | ||
573 | return SZ_DMAEND; | |
574 | } | |
575 | ||
576 | static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) | |
577 | { | |
578 | if (dry_run) | |
579 | return SZ_DMAFLUSHP; | |
580 | ||
581 | buf[0] = CMD_DMAFLUSHP; | |
582 | ||
583 | peri &= 0x1f; | |
584 | peri <<= 3; | |
585 | buf[1] = peri; | |
586 | ||
587 | PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); | |
588 | ||
589 | return SZ_DMAFLUSHP; | |
590 | } | |
591 | ||
592 | static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
593 | { | |
594 | if (dry_run) | |
595 | return SZ_DMALD; | |
596 | ||
597 | buf[0] = CMD_DMALD; | |
598 | ||
599 | if (cond == SINGLE) | |
600 | buf[0] |= (0 << 1) | (1 << 0); | |
601 | else if (cond == BURST) | |
602 | buf[0] |= (1 << 1) | (1 << 0); | |
603 | ||
604 | PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", | |
605 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
606 | ||
607 | return SZ_DMALD; | |
608 | } | |
609 | ||
610 | static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], | |
611 | enum pl330_cond cond, u8 peri) | |
612 | { | |
613 | if (dry_run) | |
614 | return SZ_DMALDP; | |
615 | ||
616 | buf[0] = CMD_DMALDP; | |
617 | ||
618 | if (cond == BURST) | |
619 | buf[0] |= (1 << 1); | |
620 | ||
621 | peri &= 0x1f; | |
622 | peri <<= 3; | |
623 | buf[1] = peri; | |
624 | ||
625 | PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", | |
626 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
627 | ||
628 | return SZ_DMALDP; | |
629 | } | |
630 | ||
631 | static inline u32 _emit_LP(unsigned dry_run, u8 buf[], | |
632 | unsigned loop, u8 cnt) | |
633 | { | |
634 | if (dry_run) | |
635 | return SZ_DMALP; | |
636 | ||
637 | buf[0] = CMD_DMALP; | |
638 | ||
639 | if (loop) | |
640 | buf[0] |= (1 << 1); | |
641 | ||
642 | cnt--; /* DMAC increments by 1 internally */ | |
643 | buf[1] = cnt; | |
644 | ||
645 | PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); | |
646 | ||
647 | return SZ_DMALP; | |
648 | } | |
649 | ||
650 | struct _arg_LPEND { | |
651 | enum pl330_cond cond; | |
652 | bool forever; | |
653 | unsigned loop; | |
654 | u8 bjump; | |
655 | }; | |
656 | ||
657 | static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], | |
658 | const struct _arg_LPEND *arg) | |
659 | { | |
660 | enum pl330_cond cond = arg->cond; | |
661 | bool forever = arg->forever; | |
662 | unsigned loop = arg->loop; | |
663 | u8 bjump = arg->bjump; | |
664 | ||
665 | if (dry_run) | |
666 | return SZ_DMALPEND; | |
667 | ||
668 | buf[0] = CMD_DMALPEND; | |
669 | ||
670 | if (loop) | |
671 | buf[0] |= (1 << 2); | |
672 | ||
673 | if (!forever) | |
674 | buf[0] |= (1 << 4); | |
675 | ||
676 | if (cond == SINGLE) | |
677 | buf[0] |= (0 << 1) | (1 << 0); | |
678 | else if (cond == BURST) | |
679 | buf[0] |= (1 << 1) | (1 << 0); | |
680 | ||
681 | buf[1] = bjump; | |
682 | ||
683 | PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", | |
684 | forever ? "FE" : "END", | |
685 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), | |
686 | loop ? '1' : '0', | |
687 | bjump); | |
688 | ||
689 | return SZ_DMALPEND; | |
690 | } | |
691 | ||
692 | static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) | |
693 | { | |
694 | if (dry_run) | |
695 | return SZ_DMAKILL; | |
696 | ||
697 | buf[0] = CMD_DMAKILL; | |
698 | ||
699 | return SZ_DMAKILL; | |
700 | } | |
701 | ||
702 | static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], | |
703 | enum dmamov_dst dst, u32 val) | |
704 | { | |
705 | if (dry_run) | |
706 | return SZ_DMAMOV; | |
707 | ||
708 | buf[0] = CMD_DMAMOV; | |
709 | buf[1] = dst; | |
710 | *((u32 *)&buf[2]) = val; | |
711 | ||
712 | PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", | |
713 | dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); | |
714 | ||
715 | return SZ_DMAMOV; | |
716 | } | |
717 | ||
718 | static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) | |
719 | { | |
720 | if (dry_run) | |
721 | return SZ_DMANOP; | |
722 | ||
723 | buf[0] = CMD_DMANOP; | |
724 | ||
725 | PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); | |
726 | ||
727 | return SZ_DMANOP; | |
728 | } | |
729 | ||
730 | static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) | |
731 | { | |
732 | if (dry_run) | |
733 | return SZ_DMARMB; | |
734 | ||
735 | buf[0] = CMD_DMARMB; | |
736 | ||
737 | PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); | |
738 | ||
739 | return SZ_DMARMB; | |
740 | } | |
741 | ||
742 | static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) | |
743 | { | |
744 | if (dry_run) | |
745 | return SZ_DMASEV; | |
746 | ||
747 | buf[0] = CMD_DMASEV; | |
748 | ||
749 | ev &= 0x1f; | |
750 | ev <<= 3; | |
751 | buf[1] = ev; | |
752 | ||
753 | PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); | |
754 | ||
755 | return SZ_DMASEV; | |
756 | } | |
757 | ||
758 | static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
759 | { | |
760 | if (dry_run) | |
761 | return SZ_DMAST; | |
762 | ||
763 | buf[0] = CMD_DMAST; | |
764 | ||
765 | if (cond == SINGLE) | |
766 | buf[0] |= (0 << 1) | (1 << 0); | |
767 | else if (cond == BURST) | |
768 | buf[0] |= (1 << 1) | (1 << 0); | |
769 | ||
770 | PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", | |
771 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
772 | ||
773 | return SZ_DMAST; | |
774 | } | |
775 | ||
776 | static inline u32 _emit_STP(unsigned dry_run, u8 buf[], | |
777 | enum pl330_cond cond, u8 peri) | |
778 | { | |
779 | if (dry_run) | |
780 | return SZ_DMASTP; | |
781 | ||
782 | buf[0] = CMD_DMASTP; | |
783 | ||
784 | if (cond == BURST) | |
785 | buf[0] |= (1 << 1); | |
786 | ||
787 | peri &= 0x1f; | |
788 | peri <<= 3; | |
789 | buf[1] = peri; | |
790 | ||
791 | PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", | |
792 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
793 | ||
794 | return SZ_DMASTP; | |
795 | } | |
796 | ||
797 | static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) | |
798 | { | |
799 | if (dry_run) | |
800 | return SZ_DMASTZ; | |
801 | ||
802 | buf[0] = CMD_DMASTZ; | |
803 | ||
804 | PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); | |
805 | ||
806 | return SZ_DMASTZ; | |
807 | } | |
808 | ||
809 | static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, | |
810 | unsigned invalidate) | |
811 | { | |
812 | if (dry_run) | |
813 | return SZ_DMAWFE; | |
814 | ||
815 | buf[0] = CMD_DMAWFE; | |
816 | ||
817 | ev &= 0x1f; | |
818 | ev <<= 3; | |
819 | buf[1] = ev; | |
820 | ||
821 | if (invalidate) | |
822 | buf[1] |= (1 << 1); | |
823 | ||
824 | PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", | |
825 | ev >> 3, invalidate ? ", I" : ""); | |
826 | ||
827 | return SZ_DMAWFE; | |
828 | } | |
829 | ||
830 | static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], | |
831 | enum pl330_cond cond, u8 peri) | |
832 | { | |
833 | if (dry_run) | |
834 | return SZ_DMAWFP; | |
835 | ||
836 | buf[0] = CMD_DMAWFP; | |
837 | ||
838 | if (cond == SINGLE) | |
839 | buf[0] |= (0 << 1) | (0 << 0); | |
840 | else if (cond == BURST) | |
841 | buf[0] |= (1 << 1) | (0 << 0); | |
842 | else | |
843 | buf[0] |= (0 << 1) | (1 << 0); | |
844 | ||
845 | peri &= 0x1f; | |
846 | peri <<= 3; | |
847 | buf[1] = peri; | |
848 | ||
849 | PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", | |
850 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); | |
851 | ||
852 | return SZ_DMAWFP; | |
853 | } | |
854 | ||
855 | static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) | |
856 | { | |
857 | if (dry_run) | |
858 | return SZ_DMAWMB; | |
859 | ||
860 | buf[0] = CMD_DMAWMB; | |
861 | ||
862 | PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); | |
863 | ||
864 | return SZ_DMAWMB; | |
865 | } | |
866 | ||
867 | struct _arg_GO { | |
868 | u8 chan; | |
869 | u32 addr; | |
870 | unsigned ns; | |
871 | }; | |
872 | ||
873 | static inline u32 _emit_GO(unsigned dry_run, u8 buf[], | |
874 | const struct _arg_GO *arg) | |
875 | { | |
876 | u8 chan = arg->chan; | |
877 | u32 addr = arg->addr; | |
878 | unsigned ns = arg->ns; | |
879 | ||
880 | if (dry_run) | |
881 | return SZ_DMAGO; | |
882 | ||
883 | buf[0] = CMD_DMAGO; | |
884 | buf[0] |= (ns << 1); | |
885 | ||
886 | buf[1] = chan & 0x7; | |
887 | ||
888 | *((u32 *)&buf[2]) = addr; | |
889 | ||
890 | return SZ_DMAGO; | |
891 | } | |
892 | ||
893 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
894 | ||
895 | /* Returns Time-Out */ | |
896 | static bool _until_dmac_idle(struct pl330_thread *thrd) | |
897 | { | |
f6f2421c | 898 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
899 | unsigned long loops = msecs_to_loops(5); |
900 | ||
901 | do { | |
902 | /* Until Manager is Idle */ | |
903 | if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) | |
904 | break; | |
905 | ||
906 | cpu_relax(); | |
907 | } while (--loops); | |
908 | ||
909 | if (!loops) | |
910 | return true; | |
911 | ||
912 | return false; | |
913 | } | |
914 | ||
915 | static inline void _execute_DBGINSN(struct pl330_thread *thrd, | |
916 | u8 insn[], bool as_manager) | |
917 | { | |
f6f2421c | 918 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
919 | u32 val; |
920 | ||
921 | val = (insn[0] << 16) | (insn[1] << 24); | |
922 | if (!as_manager) { | |
923 | val |= (1 << 0); | |
924 | val |= (thrd->id << 8); /* Channel Number */ | |
925 | } | |
926 | writel(val, regs + DBGINST0); | |
927 | ||
928 | val = *((u32 *)&insn[2]); | |
929 | writel(val, regs + DBGINST1); | |
930 | ||
931 | /* If timed out due to halted state-machine */ | |
932 | if (_until_dmac_idle(thrd)) { | |
f6f2421c | 933 | dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); |
b7d861d9 BK |
934 | return; |
935 | } | |
936 | ||
937 | /* Get going */ | |
938 | writel(0, regs + DBGCMD); | |
939 | } | |
940 | ||
b7d861d9 BK |
941 | static inline u32 _state(struct pl330_thread *thrd) |
942 | { | |
f6f2421c | 943 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
944 | u32 val; |
945 | ||
946 | if (is_manager(thrd)) | |
947 | val = readl(regs + DS) & 0xf; | |
948 | else | |
949 | val = readl(regs + CS(thrd->id)) & 0xf; | |
950 | ||
951 | switch (val) { | |
952 | case DS_ST_STOP: | |
953 | return PL330_STATE_STOPPED; | |
954 | case DS_ST_EXEC: | |
955 | return PL330_STATE_EXECUTING; | |
956 | case DS_ST_CMISS: | |
957 | return PL330_STATE_CACHEMISS; | |
958 | case DS_ST_UPDTPC: | |
959 | return PL330_STATE_UPDTPC; | |
960 | case DS_ST_WFE: | |
961 | return PL330_STATE_WFE; | |
962 | case DS_ST_FAULT: | |
963 | return PL330_STATE_FAULTING; | |
964 | case DS_ST_ATBRR: | |
965 | if (is_manager(thrd)) | |
966 | return PL330_STATE_INVALID; | |
967 | else | |
968 | return PL330_STATE_ATBARRIER; | |
969 | case DS_ST_QBUSY: | |
970 | if (is_manager(thrd)) | |
971 | return PL330_STATE_INVALID; | |
972 | else | |
973 | return PL330_STATE_QUEUEBUSY; | |
974 | case DS_ST_WFP: | |
975 | if (is_manager(thrd)) | |
976 | return PL330_STATE_INVALID; | |
977 | else | |
978 | return PL330_STATE_WFP; | |
979 | case DS_ST_KILL: | |
980 | if (is_manager(thrd)) | |
981 | return PL330_STATE_INVALID; | |
982 | else | |
983 | return PL330_STATE_KILLING; | |
984 | case DS_ST_CMPLT: | |
985 | if (is_manager(thrd)) | |
986 | return PL330_STATE_INVALID; | |
987 | else | |
988 | return PL330_STATE_COMPLETING; | |
989 | case DS_ST_FLTCMP: | |
990 | if (is_manager(thrd)) | |
991 | return PL330_STATE_INVALID; | |
992 | else | |
993 | return PL330_STATE_FAULT_COMPLETING; | |
994 | default: | |
995 | return PL330_STATE_INVALID; | |
996 | } | |
997 | } | |
998 | ||
999 | static void _stop(struct pl330_thread *thrd) | |
1000 | { | |
f6f2421c | 1001 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
1002 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; |
1003 | ||
1004 | if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) | |
1005 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1006 | ||
1007 | /* Return if nothing needs to be done */ | |
1008 | if (_state(thrd) == PL330_STATE_COMPLETING | |
1009 | || _state(thrd) == PL330_STATE_KILLING | |
1010 | || _state(thrd) == PL330_STATE_STOPPED) | |
1011 | return; | |
1012 | ||
1013 | _emit_KILL(0, insn); | |
1014 | ||
1015 | /* Stop generating interrupts for SEV */ | |
1016 | writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); | |
1017 | ||
1018 | _execute_DBGINSN(thrd, insn, is_manager(thrd)); | |
1019 | } | |
1020 | ||
1021 | /* Start doing req 'idx' of thread 'thrd' */ | |
1022 | static bool _trigger(struct pl330_thread *thrd) | |
1023 | { | |
f6f2421c | 1024 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 | 1025 | struct _pl330_req *req; |
9dc5a315 | 1026 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
1027 | struct _arg_GO go; |
1028 | unsigned ns; | |
1029 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; | |
1030 | int idx; | |
1031 | ||
1032 | /* Return if already ACTIVE */ | |
1033 | if (_state(thrd) != PL330_STATE_STOPPED) | |
1034 | return true; | |
1035 | ||
1036 | idx = 1 - thrd->lstenq; | |
8ed30a14 | 1037 | if (thrd->req[idx].desc != NULL) { |
b7d861d9 | 1038 | req = &thrd->req[idx]; |
8ed30a14 | 1039 | } else { |
b7d861d9 | 1040 | idx = thrd->lstenq; |
8ed30a14 | 1041 | if (thrd->req[idx].desc != NULL) |
b7d861d9 BK |
1042 | req = &thrd->req[idx]; |
1043 | else | |
1044 | req = NULL; | |
1045 | } | |
1046 | ||
1047 | /* Return if no request */ | |
8ed30a14 | 1048 | if (!req) |
b7d861d9 BK |
1049 | return true; |
1050 | ||
9dc5a315 | 1051 | desc = req->desc; |
b7d861d9 | 1052 | |
9dc5a315 | 1053 | ns = desc->rqcfg.nonsecure ? 1 : 0; |
b7d861d9 BK |
1054 | |
1055 | /* See 'Abort Sources' point-4 at Page 2-25 */ | |
1056 | if (_manager_ns(thrd) && !ns) | |
f6f2421c | 1057 | dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", |
b7d861d9 BK |
1058 | __func__, __LINE__); |
1059 | ||
1060 | go.chan = thrd->id; | |
1061 | go.addr = req->mc_bus; | |
1062 | go.ns = ns; | |
1063 | _emit_GO(0, insn, &go); | |
1064 | ||
1065 | /* Set to generate interrupts for SEV */ | |
1066 | writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); | |
1067 | ||
1068 | /* Only manager can execute GO */ | |
1069 | _execute_DBGINSN(thrd, insn, true); | |
1070 | ||
1071 | thrd->req_running = idx; | |
1072 | ||
1073 | return true; | |
1074 | } | |
1075 | ||
1076 | static bool _start(struct pl330_thread *thrd) | |
1077 | { | |
1078 | switch (_state(thrd)) { | |
1079 | case PL330_STATE_FAULT_COMPLETING: | |
1080 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1081 | ||
1082 | if (_state(thrd) == PL330_STATE_KILLING) | |
1083 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1084 | ||
1085 | case PL330_STATE_FAULTING: | |
1086 | _stop(thrd); | |
1087 | ||
1088 | case PL330_STATE_KILLING: | |
1089 | case PL330_STATE_COMPLETING: | |
1090 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1091 | ||
1092 | case PL330_STATE_STOPPED: | |
1093 | return _trigger(thrd); | |
1094 | ||
1095 | case PL330_STATE_WFP: | |
1096 | case PL330_STATE_QUEUEBUSY: | |
1097 | case PL330_STATE_ATBARRIER: | |
1098 | case PL330_STATE_UPDTPC: | |
1099 | case PL330_STATE_CACHEMISS: | |
1100 | case PL330_STATE_EXECUTING: | |
1101 | return true; | |
1102 | ||
1103 | case PL330_STATE_WFE: /* For RESUME, nothing yet */ | |
1104 | default: | |
1105 | return false; | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], | |
1110 | const struct _xfer_spec *pxs, int cyc) | |
1111 | { | |
1112 | int off = 0; | |
9dc5a315 | 1113 | struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; |
b7d861d9 | 1114 | |
3ecf51a4 BK |
1115 | /* check lock-up free version */ |
1116 | if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { | |
1117 | while (cyc--) { | |
1118 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1119 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1120 | } | |
1121 | } else { | |
1122 | while (cyc--) { | |
1123 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1124 | off += _emit_RMB(dry_run, &buf[off]); | |
1125 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1126 | off += _emit_WMB(dry_run, &buf[off]); | |
1127 | } | |
b7d861d9 BK |
1128 | } |
1129 | ||
1130 | return off; | |
1131 | } | |
1132 | ||
1133 | static inline int _ldst_devtomem(unsigned dry_run, u8 buf[], | |
1134 | const struct _xfer_spec *pxs, int cyc) | |
1135 | { | |
1136 | int off = 0; | |
1137 | ||
1138 | while (cyc--) { | |
9dc5a315 LPC |
1139 | off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri); |
1140 | off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->desc->peri); | |
b7d861d9 | 1141 | off += _emit_ST(dry_run, &buf[off], ALWAYS); |
9dc5a315 | 1142 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); |
b7d861d9 BK |
1143 | } |
1144 | ||
1145 | return off; | |
1146 | } | |
1147 | ||
1148 | static inline int _ldst_memtodev(unsigned dry_run, u8 buf[], | |
1149 | const struct _xfer_spec *pxs, int cyc) | |
1150 | { | |
1151 | int off = 0; | |
1152 | ||
1153 | while (cyc--) { | |
9dc5a315 | 1154 | off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri); |
b7d861d9 | 1155 | off += _emit_LD(dry_run, &buf[off], ALWAYS); |
9dc5a315 LPC |
1156 | off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->desc->peri); |
1157 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); | |
b7d861d9 BK |
1158 | } |
1159 | ||
1160 | return off; | |
1161 | } | |
1162 | ||
1163 | static int _bursts(unsigned dry_run, u8 buf[], | |
1164 | const struct _xfer_spec *pxs, int cyc) | |
1165 | { | |
1166 | int off = 0; | |
1167 | ||
9dc5a315 | 1168 | switch (pxs->desc->rqtype) { |
585a9d0b | 1169 | case DMA_MEM_TO_DEV: |
b7d861d9 BK |
1170 | off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); |
1171 | break; | |
585a9d0b | 1172 | case DMA_DEV_TO_MEM: |
b7d861d9 BK |
1173 | off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); |
1174 | break; | |
585a9d0b | 1175 | case DMA_MEM_TO_MEM: |
b7d861d9 BK |
1176 | off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); |
1177 | break; | |
1178 | default: | |
1179 | off += 0x40000000; /* Scare off the Client */ | |
1180 | break; | |
1181 | } | |
1182 | ||
1183 | return off; | |
1184 | } | |
1185 | ||
1186 | /* Returns bytes consumed and updates bursts */ | |
1187 | static inline int _loop(unsigned dry_run, u8 buf[], | |
1188 | unsigned long *bursts, const struct _xfer_spec *pxs) | |
1189 | { | |
1190 | int cyc, cycmax, szlp, szlpend, szbrst, off; | |
1191 | unsigned lcnt0, lcnt1, ljmp0, ljmp1; | |
1192 | struct _arg_LPEND lpend; | |
1193 | ||
1194 | /* Max iterations possible in DMALP is 256 */ | |
1195 | if (*bursts >= 256*256) { | |
1196 | lcnt1 = 256; | |
1197 | lcnt0 = 256; | |
1198 | cyc = *bursts / lcnt1 / lcnt0; | |
1199 | } else if (*bursts > 256) { | |
1200 | lcnt1 = 256; | |
1201 | lcnt0 = *bursts / lcnt1; | |
1202 | cyc = 1; | |
1203 | } else { | |
1204 | lcnt1 = *bursts; | |
1205 | lcnt0 = 0; | |
1206 | cyc = 1; | |
1207 | } | |
1208 | ||
1209 | szlp = _emit_LP(1, buf, 0, 0); | |
1210 | szbrst = _bursts(1, buf, pxs, 1); | |
1211 | ||
1212 | lpend.cond = ALWAYS; | |
1213 | lpend.forever = false; | |
1214 | lpend.loop = 0; | |
1215 | lpend.bjump = 0; | |
1216 | szlpend = _emit_LPEND(1, buf, &lpend); | |
1217 | ||
1218 | if (lcnt0) { | |
1219 | szlp *= 2; | |
1220 | szlpend *= 2; | |
1221 | } | |
1222 | ||
1223 | /* | |
1224 | * Max bursts that we can unroll due to limit on the | |
1225 | * size of backward jump that can be encoded in DMALPEND | |
1226 | * which is 8-bits and hence 255 | |
1227 | */ | |
1228 | cycmax = (255 - (szlp + szlpend)) / szbrst; | |
1229 | ||
1230 | cyc = (cycmax < cyc) ? cycmax : cyc; | |
1231 | ||
1232 | off = 0; | |
1233 | ||
1234 | if (lcnt0) { | |
1235 | off += _emit_LP(dry_run, &buf[off], 0, lcnt0); | |
1236 | ljmp0 = off; | |
1237 | } | |
1238 | ||
1239 | off += _emit_LP(dry_run, &buf[off], 1, lcnt1); | |
1240 | ljmp1 = off; | |
1241 | ||
1242 | off += _bursts(dry_run, &buf[off], pxs, cyc); | |
1243 | ||
1244 | lpend.cond = ALWAYS; | |
1245 | lpend.forever = false; | |
1246 | lpend.loop = 1; | |
1247 | lpend.bjump = off - ljmp1; | |
1248 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1249 | ||
1250 | if (lcnt0) { | |
1251 | lpend.cond = ALWAYS; | |
1252 | lpend.forever = false; | |
1253 | lpend.loop = 0; | |
1254 | lpend.bjump = off - ljmp0; | |
1255 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1256 | } | |
1257 | ||
1258 | *bursts = lcnt1 * cyc; | |
1259 | if (lcnt0) | |
1260 | *bursts *= lcnt0; | |
1261 | ||
1262 | return off; | |
1263 | } | |
1264 | ||
1265 | static inline int _setup_loops(unsigned dry_run, u8 buf[], | |
1266 | const struct _xfer_spec *pxs) | |
1267 | { | |
9dc5a315 | 1268 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1269 | u32 ccr = pxs->ccr; |
1270 | unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); | |
1271 | int off = 0; | |
1272 | ||
1273 | while (bursts) { | |
1274 | c = bursts; | |
1275 | off += _loop(dry_run, &buf[off], &c, pxs); | |
1276 | bursts -= c; | |
1277 | } | |
1278 | ||
1279 | return off; | |
1280 | } | |
1281 | ||
1282 | static inline int _setup_xfer(unsigned dry_run, u8 buf[], | |
1283 | const struct _xfer_spec *pxs) | |
1284 | { | |
9dc5a315 | 1285 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1286 | int off = 0; |
1287 | ||
1288 | /* DMAMOV SAR, x->src_addr */ | |
1289 | off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); | |
1290 | /* DMAMOV DAR, x->dst_addr */ | |
1291 | off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); | |
1292 | ||
1293 | /* Setup Loop(s) */ | |
1294 | off += _setup_loops(dry_run, &buf[off], pxs); | |
1295 | ||
1296 | return off; | |
1297 | } | |
1298 | ||
1299 | /* | |
1300 | * A req is a sequence of one or more xfer units. | |
1301 | * Returns the number of bytes taken to setup the MC for the req. | |
1302 | */ | |
1303 | static int _setup_req(unsigned dry_run, struct pl330_thread *thrd, | |
1304 | unsigned index, struct _xfer_spec *pxs) | |
1305 | { | |
1306 | struct _pl330_req *req = &thrd->req[index]; | |
1307 | struct pl330_xfer *x; | |
1308 | u8 *buf = req->mc_cpu; | |
1309 | int off = 0; | |
1310 | ||
1311 | PL330_DBGMC_START(req->mc_bus); | |
1312 | ||
1313 | /* DMAMOV CCR, ccr */ | |
1314 | off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); | |
1315 | ||
9dc5a315 | 1316 | x = &pxs->desc->px; |
d5cef121 LPC |
1317 | /* Error if xfer length is not aligned at burst size */ |
1318 | if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) | |
1319 | return -EINVAL; | |
b7d861d9 | 1320 | |
d5cef121 | 1321 | off += _setup_xfer(dry_run, &buf[off], pxs); |
b7d861d9 BK |
1322 | |
1323 | /* DMASEV peripheral/event */ | |
1324 | off += _emit_SEV(dry_run, &buf[off], thrd->ev); | |
1325 | /* DMAEND */ | |
1326 | off += _emit_END(dry_run, &buf[off]); | |
1327 | ||
1328 | return off; | |
1329 | } | |
1330 | ||
1331 | static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) | |
1332 | { | |
1333 | u32 ccr = 0; | |
1334 | ||
1335 | if (rqc->src_inc) | |
1336 | ccr |= CC_SRCINC; | |
1337 | ||
1338 | if (rqc->dst_inc) | |
1339 | ccr |= CC_DSTINC; | |
1340 | ||
1341 | /* We set same protection levels for Src and DST for now */ | |
1342 | if (rqc->privileged) | |
1343 | ccr |= CC_SRCPRI | CC_DSTPRI; | |
1344 | if (rqc->nonsecure) | |
1345 | ccr |= CC_SRCNS | CC_DSTNS; | |
1346 | if (rqc->insnaccess) | |
1347 | ccr |= CC_SRCIA | CC_DSTIA; | |
1348 | ||
1349 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); | |
1350 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); | |
1351 | ||
1352 | ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); | |
1353 | ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); | |
1354 | ||
1355 | ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); | |
1356 | ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); | |
1357 | ||
1358 | ccr |= (rqc->swap << CC_SWAP_SHFT); | |
1359 | ||
1360 | return ccr; | |
1361 | } | |
1362 | ||
b7d861d9 BK |
1363 | /* |
1364 | * Submit a list of xfers after which the client wants notification. | |
1365 | * Client is not notified after each xfer unit, just once after all | |
1366 | * xfer units are done or some error occurs. | |
1367 | */ | |
9dc5a315 LPC |
1368 | static int pl330_submit_req(struct pl330_thread *thrd, |
1369 | struct dma_pl330_desc *desc) | |
b7d861d9 | 1370 | { |
f6f2421c | 1371 | struct pl330_dmac *pl330 = thrd->dmac; |
b7d861d9 BK |
1372 | struct _xfer_spec xs; |
1373 | unsigned long flags; | |
b7d861d9 BK |
1374 | unsigned idx; |
1375 | u32 ccr; | |
1376 | int ret = 0; | |
1377 | ||
b7d861d9 BK |
1378 | if (pl330->state == DYING |
1379 | || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { | |
f6f2421c | 1380 | dev_info(thrd->dmac->ddma.dev, "%s:%d\n", |
b7d861d9 BK |
1381 | __func__, __LINE__); |
1382 | return -EAGAIN; | |
1383 | } | |
1384 | ||
1385 | /* If request for non-existing peripheral */ | |
9dc5a315 LPC |
1386 | if (desc->rqtype != DMA_MEM_TO_MEM && |
1387 | desc->peri >= pl330->pcfg.num_peri) { | |
f6f2421c | 1388 | dev_info(thrd->dmac->ddma.dev, |
b7d861d9 | 1389 | "%s:%d Invalid peripheral(%u)!\n", |
9dc5a315 | 1390 | __func__, __LINE__, desc->peri); |
b7d861d9 BK |
1391 | return -EINVAL; |
1392 | } | |
1393 | ||
1394 | spin_lock_irqsave(&pl330->lock, flags); | |
1395 | ||
1396 | if (_queue_full(thrd)) { | |
1397 | ret = -EAGAIN; | |
1398 | goto xfer_exit; | |
1399 | } | |
1400 | ||
9dc5a315 LPC |
1401 | /* Prefer Secure Channel */ |
1402 | if (!_manager_ns(thrd)) | |
1403 | desc->rqcfg.nonsecure = 0; | |
1404 | else | |
1405 | desc->rqcfg.nonsecure = 1; | |
b7d861d9 | 1406 | |
9dc5a315 | 1407 | ccr = _prepare_ccr(&desc->rqcfg); |
b7d861d9 | 1408 | |
8ed30a14 | 1409 | idx = thrd->req[0].desc == NULL ? 0 : 1; |
b7d861d9 BK |
1410 | |
1411 | xs.ccr = ccr; | |
9dc5a315 | 1412 | xs.desc = desc; |
b7d861d9 BK |
1413 | |
1414 | /* First dry run to check if req is acceptable */ | |
1415 | ret = _setup_req(1, thrd, idx, &xs); | |
1416 | if (ret < 0) | |
1417 | goto xfer_exit; | |
1418 | ||
f6f2421c LPC |
1419 | if (ret > pl330->mcbufsz / 2) { |
1420 | dev_info(pl330->ddma.dev, "%s:%d Trying increasing mcbufsz\n", | |
b7d861d9 BK |
1421 | __func__, __LINE__); |
1422 | ret = -ENOMEM; | |
1423 | goto xfer_exit; | |
1424 | } | |
1425 | ||
1426 | /* Hook the request */ | |
1427 | thrd->lstenq = idx; | |
9dc5a315 | 1428 | thrd->req[idx].desc = desc; |
be025329 | 1429 | _setup_req(0, thrd, idx, &xs); |
b7d861d9 BK |
1430 | |
1431 | ret = 0; | |
1432 | ||
1433 | xfer_exit: | |
1434 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1435 | ||
1436 | return ret; | |
1437 | } | |
1438 | ||
9dc5a315 | 1439 | static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) |
6079d38c | 1440 | { |
b1e51d77 | 1441 | struct dma_pl330_chan *pch; |
6079d38c LPC |
1442 | unsigned long flags; |
1443 | ||
b1e51d77 JMC |
1444 | if (!desc) |
1445 | return; | |
1446 | ||
1447 | pch = desc->pchan; | |
1448 | ||
6079d38c LPC |
1449 | /* If desc aborted */ |
1450 | if (!pch) | |
1451 | return; | |
1452 | ||
1453 | spin_lock_irqsave(&pch->lock, flags); | |
1454 | ||
1455 | desc->status = DONE; | |
1456 | ||
1457 | spin_unlock_irqrestore(&pch->lock, flags); | |
1458 | ||
1459 | tasklet_schedule(&pch->task); | |
1460 | } | |
1461 | ||
b7d861d9 BK |
1462 | static void pl330_dotask(unsigned long data) |
1463 | { | |
1464 | struct pl330_dmac *pl330 = (struct pl330_dmac *) data; | |
b7d861d9 BK |
1465 | unsigned long flags; |
1466 | int i; | |
1467 | ||
1468 | spin_lock_irqsave(&pl330->lock, flags); | |
1469 | ||
1470 | /* The DMAC itself gone nuts */ | |
1471 | if (pl330->dmac_tbd.reset_dmac) { | |
1472 | pl330->state = DYING; | |
1473 | /* Reset the manager too */ | |
1474 | pl330->dmac_tbd.reset_mngr = true; | |
1475 | /* Clear the reset flag */ | |
1476 | pl330->dmac_tbd.reset_dmac = false; | |
1477 | } | |
1478 | ||
1479 | if (pl330->dmac_tbd.reset_mngr) { | |
1480 | _stop(pl330->manager); | |
1481 | /* Reset all channels */ | |
f6f2421c | 1482 | pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; |
b7d861d9 BK |
1483 | /* Clear the reset flag */ |
1484 | pl330->dmac_tbd.reset_mngr = false; | |
1485 | } | |
1486 | ||
f6f2421c | 1487 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 BK |
1488 | |
1489 | if (pl330->dmac_tbd.reset_chan & (1 << i)) { | |
1490 | struct pl330_thread *thrd = &pl330->channels[i]; | |
f6f2421c | 1491 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1492 | enum pl330_op_err err; |
1493 | ||
1494 | _stop(thrd); | |
1495 | ||
1496 | if (readl(regs + FSC) & (1 << thrd->id)) | |
1497 | err = PL330_ERR_FAIL; | |
1498 | else | |
1499 | err = PL330_ERR_ABORT; | |
1500 | ||
1501 | spin_unlock_irqrestore(&pl330->lock, flags); | |
9dc5a315 LPC |
1502 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); |
1503 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); | |
b7d861d9 BK |
1504 | spin_lock_irqsave(&pl330->lock, flags); |
1505 | ||
9dc5a315 LPC |
1506 | thrd->req[0].desc = NULL; |
1507 | thrd->req[1].desc = NULL; | |
8ed30a14 | 1508 | thrd->req_running = -1; |
b7d861d9 BK |
1509 | |
1510 | /* Clear the reset flag */ | |
1511 | pl330->dmac_tbd.reset_chan &= ~(1 << i); | |
1512 | } | |
1513 | } | |
1514 | ||
1515 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1516 | ||
1517 | return; | |
1518 | } | |
1519 | ||
1520 | /* Returns 1 if state was updated, 0 otherwise */ | |
f6f2421c | 1521 | static int pl330_update(struct pl330_dmac *pl330) |
b7d861d9 | 1522 | { |
9dc5a315 | 1523 | struct dma_pl330_desc *descdone, *tmp; |
b7d861d9 BK |
1524 | unsigned long flags; |
1525 | void __iomem *regs; | |
1526 | u32 val; | |
1527 | int id, ev, ret = 0; | |
1528 | ||
f6f2421c | 1529 | regs = pl330->base; |
b7d861d9 BK |
1530 | |
1531 | spin_lock_irqsave(&pl330->lock, flags); | |
1532 | ||
1533 | val = readl(regs + FSM) & 0x1; | |
1534 | if (val) | |
1535 | pl330->dmac_tbd.reset_mngr = true; | |
1536 | else | |
1537 | pl330->dmac_tbd.reset_mngr = false; | |
1538 | ||
f6f2421c | 1539 | val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); |
b7d861d9 BK |
1540 | pl330->dmac_tbd.reset_chan |= val; |
1541 | if (val) { | |
1542 | int i = 0; | |
f6f2421c | 1543 | while (i < pl330->pcfg.num_chan) { |
b7d861d9 | 1544 | if (val & (1 << i)) { |
f6f2421c | 1545 | dev_info(pl330->ddma.dev, |
b7d861d9 BK |
1546 | "Reset Channel-%d\t CS-%x FTC-%x\n", |
1547 | i, readl(regs + CS(i)), | |
1548 | readl(regs + FTC(i))); | |
1549 | _stop(&pl330->channels[i]); | |
1550 | } | |
1551 | i++; | |
1552 | } | |
1553 | } | |
1554 | ||
1555 | /* Check which event happened i.e, thread notified */ | |
1556 | val = readl(regs + ES); | |
f6f2421c LPC |
1557 | if (pl330->pcfg.num_events < 32 |
1558 | && val & ~((1 << pl330->pcfg.num_events) - 1)) { | |
b7d861d9 | 1559 | pl330->dmac_tbd.reset_dmac = true; |
f6f2421c LPC |
1560 | dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, |
1561 | __LINE__); | |
b7d861d9 BK |
1562 | ret = 1; |
1563 | goto updt_exit; | |
1564 | } | |
1565 | ||
f6f2421c | 1566 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) { |
b7d861d9 BK |
1567 | if (val & (1 << ev)) { /* Event occurred */ |
1568 | struct pl330_thread *thrd; | |
1569 | u32 inten = readl(regs + INTEN); | |
1570 | int active; | |
1571 | ||
1572 | /* Clear the event */ | |
1573 | if (inten & (1 << ev)) | |
1574 | writel(1 << ev, regs + INTCLR); | |
1575 | ||
1576 | ret = 1; | |
1577 | ||
1578 | id = pl330->events[ev]; | |
1579 | ||
1580 | thrd = &pl330->channels[id]; | |
1581 | ||
1582 | active = thrd->req_running; | |
1583 | if (active == -1) /* Aborted */ | |
1584 | continue; | |
1585 | ||
fdec53d5 | 1586 | /* Detach the req */ |
9dc5a315 LPC |
1587 | descdone = thrd->req[active].desc; |
1588 | thrd->req[active].desc = NULL; | |
fdec53d5 | 1589 | |
b7d861d9 BK |
1590 | /* Get going again ASAP */ |
1591 | _start(thrd); | |
1592 | ||
1593 | /* For now, just make a list of callbacks to be done */ | |
9dc5a315 | 1594 | list_add_tail(&descdone->rqd, &pl330->req_done); |
b7d861d9 BK |
1595 | } |
1596 | } | |
1597 | ||
1598 | /* Now that we are in no hurry, do the callbacks */ | |
9dc5a315 LPC |
1599 | list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) { |
1600 | list_del(&descdone->rqd); | |
b7d861d9 | 1601 | spin_unlock_irqrestore(&pl330->lock, flags); |
9dc5a315 | 1602 | dma_pl330_rqcb(descdone, PL330_ERR_NONE); |
b7d861d9 BK |
1603 | spin_lock_irqsave(&pl330->lock, flags); |
1604 | } | |
1605 | ||
1606 | updt_exit: | |
1607 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1608 | ||
1609 | if (pl330->dmac_tbd.reset_dmac | |
1610 | || pl330->dmac_tbd.reset_mngr | |
1611 | || pl330->dmac_tbd.reset_chan) { | |
1612 | ret = 1; | |
1613 | tasklet_schedule(&pl330->tasks); | |
1614 | } | |
1615 | ||
1616 | return ret; | |
1617 | } | |
1618 | ||
b7d861d9 BK |
1619 | /* Reserve an event */ |
1620 | static inline int _alloc_event(struct pl330_thread *thrd) | |
1621 | { | |
1622 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1623 | int ev; |
1624 | ||
f6f2421c | 1625 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) |
b7d861d9 BK |
1626 | if (pl330->events[ev] == -1) { |
1627 | pl330->events[ev] = thrd->id; | |
1628 | return ev; | |
1629 | } | |
1630 | ||
1631 | return -1; | |
1632 | } | |
1633 | ||
f6f2421c | 1634 | static bool _chan_ns(const struct pl330_dmac *pl330, int i) |
b7d861d9 | 1635 | { |
f6f2421c | 1636 | return pl330->pcfg.irq_ns & (1 << i); |
b7d861d9 BK |
1637 | } |
1638 | ||
1639 | /* Upon success, returns IdentityToken for the | |
1640 | * allocated channel, NULL otherwise. | |
1641 | */ | |
f6f2421c | 1642 | static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) |
b7d861d9 BK |
1643 | { |
1644 | struct pl330_thread *thrd = NULL; | |
b7d861d9 BK |
1645 | unsigned long flags; |
1646 | int chans, i; | |
1647 | ||
b7d861d9 BK |
1648 | if (pl330->state == DYING) |
1649 | return NULL; | |
1650 | ||
f6f2421c | 1651 | chans = pl330->pcfg.num_chan; |
b7d861d9 BK |
1652 | |
1653 | spin_lock_irqsave(&pl330->lock, flags); | |
1654 | ||
1655 | for (i = 0; i < chans; i++) { | |
1656 | thrd = &pl330->channels[i]; | |
1657 | if ((thrd->free) && (!_manager_ns(thrd) || | |
f6f2421c | 1658 | _chan_ns(pl330, i))) { |
b7d861d9 BK |
1659 | thrd->ev = _alloc_event(thrd); |
1660 | if (thrd->ev >= 0) { | |
1661 | thrd->free = false; | |
1662 | thrd->lstenq = 1; | |
9dc5a315 | 1663 | thrd->req[0].desc = NULL; |
9dc5a315 | 1664 | thrd->req[1].desc = NULL; |
8ed30a14 | 1665 | thrd->req_running = -1; |
b7d861d9 BK |
1666 | break; |
1667 | } | |
1668 | } | |
1669 | thrd = NULL; | |
1670 | } | |
1671 | ||
1672 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1673 | ||
1674 | return thrd; | |
1675 | } | |
1676 | ||
1677 | /* Release an event */ | |
1678 | static inline void _free_event(struct pl330_thread *thrd, int ev) | |
1679 | { | |
1680 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1681 | |
1682 | /* If the event is valid and was held by the thread */ | |
f6f2421c | 1683 | if (ev >= 0 && ev < pl330->pcfg.num_events |
b7d861d9 BK |
1684 | && pl330->events[ev] == thrd->id) |
1685 | pl330->events[ev] = -1; | |
1686 | } | |
1687 | ||
65ad6060 | 1688 | static void pl330_release_channel(struct pl330_thread *thrd) |
b7d861d9 | 1689 | { |
b7d861d9 BK |
1690 | struct pl330_dmac *pl330; |
1691 | unsigned long flags; | |
1692 | ||
1693 | if (!thrd || thrd->free) | |
1694 | return; | |
1695 | ||
1696 | _stop(thrd); | |
1697 | ||
9dc5a315 LPC |
1698 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); |
1699 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); | |
b7d861d9 BK |
1700 | |
1701 | pl330 = thrd->dmac; | |
1702 | ||
1703 | spin_lock_irqsave(&pl330->lock, flags); | |
1704 | _free_event(thrd, thrd->ev); | |
1705 | thrd->free = true; | |
1706 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1707 | } | |
1708 | ||
1709 | /* Initialize the structure for PL330 configuration, that can be used | |
1710 | * by the client driver the make best use of the DMAC | |
1711 | */ | |
f6f2421c | 1712 | static void read_dmac_config(struct pl330_dmac *pl330) |
b7d861d9 | 1713 | { |
f6f2421c | 1714 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1715 | u32 val; |
1716 | ||
1717 | val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; | |
1718 | val &= CRD_DATA_WIDTH_MASK; | |
f6f2421c | 1719 | pl330->pcfg.data_bus_width = 8 * (1 << val); |
b7d861d9 BK |
1720 | |
1721 | val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; | |
1722 | val &= CRD_DATA_BUFF_MASK; | |
f6f2421c | 1723 | pl330->pcfg.data_buf_dep = val + 1; |
b7d861d9 BK |
1724 | |
1725 | val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; | |
1726 | val &= CR0_NUM_CHANS_MASK; | |
1727 | val += 1; | |
f6f2421c | 1728 | pl330->pcfg.num_chan = val; |
b7d861d9 BK |
1729 | |
1730 | val = readl(regs + CR0); | |
1731 | if (val & CR0_PERIPH_REQ_SET) { | |
1732 | val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; | |
1733 | val += 1; | |
f6f2421c LPC |
1734 | pl330->pcfg.num_peri = val; |
1735 | pl330->pcfg.peri_ns = readl(regs + CR4); | |
b7d861d9 | 1736 | } else { |
f6f2421c | 1737 | pl330->pcfg.num_peri = 0; |
b7d861d9 BK |
1738 | } |
1739 | ||
1740 | val = readl(regs + CR0); | |
1741 | if (val & CR0_BOOT_MAN_NS) | |
f6f2421c | 1742 | pl330->pcfg.mode |= DMAC_MODE_NS; |
b7d861d9 | 1743 | else |
f6f2421c | 1744 | pl330->pcfg.mode &= ~DMAC_MODE_NS; |
b7d861d9 BK |
1745 | |
1746 | val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; | |
1747 | val &= CR0_NUM_EVENTS_MASK; | |
1748 | val += 1; | |
f6f2421c | 1749 | pl330->pcfg.num_events = val; |
b7d861d9 | 1750 | |
f6f2421c | 1751 | pl330->pcfg.irq_ns = readl(regs + CR3); |
b7d861d9 BK |
1752 | } |
1753 | ||
1754 | static inline void _reset_thread(struct pl330_thread *thrd) | |
1755 | { | |
1756 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1757 | |
1758 | thrd->req[0].mc_cpu = pl330->mcode_cpu | |
f6f2421c | 1759 | + (thrd->id * pl330->mcbufsz); |
b7d861d9 | 1760 | thrd->req[0].mc_bus = pl330->mcode_bus |
f6f2421c | 1761 | + (thrd->id * pl330->mcbufsz); |
9dc5a315 | 1762 | thrd->req[0].desc = NULL; |
b7d861d9 BK |
1763 | |
1764 | thrd->req[1].mc_cpu = thrd->req[0].mc_cpu | |
f6f2421c | 1765 | + pl330->mcbufsz / 2; |
b7d861d9 | 1766 | thrd->req[1].mc_bus = thrd->req[0].mc_bus |
f6f2421c | 1767 | + pl330->mcbufsz / 2; |
9dc5a315 | 1768 | thrd->req[1].desc = NULL; |
8ed30a14 LPC |
1769 | |
1770 | thrd->req_running = -1; | |
b7d861d9 BK |
1771 | } |
1772 | ||
1773 | static int dmac_alloc_threads(struct pl330_dmac *pl330) | |
1774 | { | |
f6f2421c | 1775 | int chans = pl330->pcfg.num_chan; |
b7d861d9 BK |
1776 | struct pl330_thread *thrd; |
1777 | int i; | |
1778 | ||
1779 | /* Allocate 1 Manager and 'chans' Channel threads */ | |
1780 | pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), | |
1781 | GFP_KERNEL); | |
1782 | if (!pl330->channels) | |
1783 | return -ENOMEM; | |
1784 | ||
1785 | /* Init Channel threads */ | |
1786 | for (i = 0; i < chans; i++) { | |
1787 | thrd = &pl330->channels[i]; | |
1788 | thrd->id = i; | |
1789 | thrd->dmac = pl330; | |
1790 | _reset_thread(thrd); | |
1791 | thrd->free = true; | |
1792 | } | |
1793 | ||
1794 | /* MANAGER is indexed at the end */ | |
1795 | thrd = &pl330->channels[chans]; | |
1796 | thrd->id = chans; | |
1797 | thrd->dmac = pl330; | |
1798 | thrd->free = false; | |
1799 | pl330->manager = thrd; | |
1800 | ||
1801 | return 0; | |
1802 | } | |
1803 | ||
1804 | static int dmac_alloc_resources(struct pl330_dmac *pl330) | |
1805 | { | |
f6f2421c | 1806 | int chans = pl330->pcfg.num_chan; |
b7d861d9 | 1807 | int ret; |
b3040e40 | 1808 | |
b3040e40 | 1809 | /* |
b7d861d9 BK |
1810 | * Alloc MicroCode buffer for 'chans' Channel threads. |
1811 | * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) | |
b3040e40 | 1812 | */ |
f6f2421c LPC |
1813 | pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev, |
1814 | chans * pl330->mcbufsz, | |
b7d861d9 BK |
1815 | &pl330->mcode_bus, GFP_KERNEL); |
1816 | if (!pl330->mcode_cpu) { | |
f6f2421c | 1817 | dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", |
b7d861d9 BK |
1818 | __func__, __LINE__); |
1819 | return -ENOMEM; | |
1820 | } | |
1821 | ||
1822 | ret = dmac_alloc_threads(pl330); | |
1823 | if (ret) { | |
f6f2421c | 1824 | dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", |
b7d861d9 | 1825 | __func__, __LINE__); |
f6f2421c LPC |
1826 | dma_free_coherent(pl330->ddma.dev, |
1827 | chans * pl330->mcbufsz, | |
b7d861d9 BK |
1828 | pl330->mcode_cpu, pl330->mcode_bus); |
1829 | return ret; | |
1830 | } | |
1831 | ||
1832 | return 0; | |
1833 | } | |
1834 | ||
f6f2421c | 1835 | static int pl330_add(struct pl330_dmac *pl330) |
b7d861d9 | 1836 | { |
b7d861d9 BK |
1837 | void __iomem *regs; |
1838 | int i, ret; | |
1839 | ||
f6f2421c | 1840 | regs = pl330->base; |
b3040e40 | 1841 | |
b7d861d9 | 1842 | /* Check if we can handle this DMAC */ |
f6f2421c LPC |
1843 | if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { |
1844 | dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", | |
1845 | pl330->pcfg.periph_id); | |
b7d861d9 BK |
1846 | return -EINVAL; |
1847 | } | |
b3040e40 | 1848 | |
b7d861d9 | 1849 | /* Read the configuration of the DMAC */ |
f6f2421c | 1850 | read_dmac_config(pl330); |
b3040e40 | 1851 | |
f6f2421c LPC |
1852 | if (pl330->pcfg.num_events == 0) { |
1853 | dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", | |
b7d861d9 BK |
1854 | __func__, __LINE__); |
1855 | return -EINVAL; | |
1856 | } | |
b3040e40 | 1857 | |
b7d861d9 | 1858 | spin_lock_init(&pl330->lock); |
1b9bb715 | 1859 | |
b7d861d9 | 1860 | INIT_LIST_HEAD(&pl330->req_done); |
42bc9cf4 | 1861 | |
b7d861d9 | 1862 | /* Use default MC buffer size if not provided */ |
f6f2421c LPC |
1863 | if (!pl330->mcbufsz) |
1864 | pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; | |
b3040e40 | 1865 | |
b7d861d9 | 1866 | /* Mark all events as free */ |
f6f2421c | 1867 | for (i = 0; i < pl330->pcfg.num_events; i++) |
b7d861d9 | 1868 | pl330->events[i] = -1; |
b3040e40 | 1869 | |
b7d861d9 BK |
1870 | /* Allocate resources needed by the DMAC */ |
1871 | ret = dmac_alloc_resources(pl330); | |
1872 | if (ret) { | |
f6f2421c | 1873 | dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); |
b7d861d9 BK |
1874 | return ret; |
1875 | } | |
b3040e40 | 1876 | |
b7d861d9 | 1877 | tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); |
b3040e40 | 1878 | |
b7d861d9 | 1879 | pl330->state = INIT; |
a2f5203f | 1880 | |
b7d861d9 BK |
1881 | return 0; |
1882 | } | |
b3040e40 | 1883 | |
b7d861d9 BK |
1884 | static int dmac_free_threads(struct pl330_dmac *pl330) |
1885 | { | |
b7d861d9 BK |
1886 | struct pl330_thread *thrd; |
1887 | int i; | |
b3040e40 | 1888 | |
b7d861d9 | 1889 | /* Release Channel threads */ |
f6f2421c | 1890 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 | 1891 | thrd = &pl330->channels[i]; |
65ad6060 | 1892 | pl330_release_channel(thrd); |
b7d861d9 | 1893 | } |
b3040e40 | 1894 | |
b7d861d9 BK |
1895 | /* Free memory */ |
1896 | kfree(pl330->channels); | |
b3040e40 | 1897 | |
b7d861d9 BK |
1898 | return 0; |
1899 | } | |
b3040e40 | 1900 | |
f6f2421c | 1901 | static void pl330_del(struct pl330_dmac *pl330) |
b7d861d9 | 1902 | { |
b7d861d9 BK |
1903 | pl330->state = UNINIT; |
1904 | ||
1905 | tasklet_kill(&pl330->tasks); | |
1906 | ||
1907 | /* Free DMAC resources */ | |
f6f2421c | 1908 | dmac_free_threads(pl330); |
b7d861d9 | 1909 | |
f6f2421c LPC |
1910 | dma_free_coherent(pl330->ddma.dev, |
1911 | pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, | |
1912 | pl330->mcode_bus); | |
b7d861d9 | 1913 | } |
b3040e40 | 1914 | |
3e2ec13a TA |
1915 | /* forward declaration */ |
1916 | static struct amba_driver pl330_driver; | |
1917 | ||
b3040e40 JB |
1918 | static inline struct dma_pl330_chan * |
1919 | to_pchan(struct dma_chan *ch) | |
1920 | { | |
1921 | if (!ch) | |
1922 | return NULL; | |
1923 | ||
1924 | return container_of(ch, struct dma_pl330_chan, chan); | |
1925 | } | |
1926 | ||
1927 | static inline struct dma_pl330_desc * | |
1928 | to_desc(struct dma_async_tx_descriptor *tx) | |
1929 | { | |
1930 | return container_of(tx, struct dma_pl330_desc, txd); | |
1931 | } | |
1932 | ||
b3040e40 JB |
1933 | static inline void fill_queue(struct dma_pl330_chan *pch) |
1934 | { | |
1935 | struct dma_pl330_desc *desc; | |
1936 | int ret; | |
1937 | ||
1938 | list_for_each_entry(desc, &pch->work_list, node) { | |
1939 | ||
1940 | /* If already submitted */ | |
1941 | if (desc->status == BUSY) | |
30fb980b | 1942 | continue; |
b3040e40 | 1943 | |
9dc5a315 | 1944 | ret = pl330_submit_req(pch->thread, desc); |
b3040e40 JB |
1945 | if (!ret) { |
1946 | desc->status = BUSY; | |
b3040e40 JB |
1947 | } else if (ret == -EAGAIN) { |
1948 | /* QFull or DMAC Dying */ | |
1949 | break; | |
1950 | } else { | |
1951 | /* Unacceptable request */ | |
1952 | desc->status = DONE; | |
f6f2421c | 1953 | dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", |
b3040e40 JB |
1954 | __func__, __LINE__, desc->txd.cookie); |
1955 | tasklet_schedule(&pch->task); | |
1956 | } | |
1957 | } | |
1958 | } | |
1959 | ||
1960 | static void pl330_tasklet(unsigned long data) | |
1961 | { | |
1962 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
1963 | struct dma_pl330_desc *desc, *_dt; | |
1964 | unsigned long flags; | |
ae43b328 | 1965 | bool power_down = false; |
b3040e40 JB |
1966 | |
1967 | spin_lock_irqsave(&pch->lock, flags); | |
1968 | ||
1969 | /* Pick up ripe tomatoes */ | |
1970 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
1971 | if (desc->status == DONE) { | |
30c1dc0f | 1972 | if (!pch->cyclic) |
eab21585 | 1973 | dma_cookie_complete(&desc->txd); |
39ff8613 | 1974 | list_move_tail(&desc->node, &pch->completed_list); |
b3040e40 JB |
1975 | } |
1976 | ||
1977 | /* Try to submit a req imm. next to the last completed cookie */ | |
1978 | fill_queue(pch); | |
1979 | ||
ae43b328 KK |
1980 | if (list_empty(&pch->work_list)) { |
1981 | spin_lock(&pch->thread->dmac->lock); | |
1982 | _stop(pch->thread); | |
1983 | spin_unlock(&pch->thread->dmac->lock); | |
1984 | power_down = true; | |
1985 | } else { | |
1986 | /* Make sure the PL330 Channel thread is active */ | |
1987 | spin_lock(&pch->thread->dmac->lock); | |
1988 | _start(pch->thread); | |
1989 | spin_unlock(&pch->thread->dmac->lock); | |
1990 | } | |
b3040e40 | 1991 | |
39ff8613 LPC |
1992 | while (!list_empty(&pch->completed_list)) { |
1993 | dma_async_tx_callback callback; | |
1994 | void *callback_param; | |
b3040e40 | 1995 | |
39ff8613 LPC |
1996 | desc = list_first_entry(&pch->completed_list, |
1997 | struct dma_pl330_desc, node); | |
1998 | ||
1999 | callback = desc->txd.callback; | |
2000 | callback_param = desc->txd.callback_param; | |
2001 | ||
2002 | if (pch->cyclic) { | |
2003 | desc->status = PREP; | |
2004 | list_move_tail(&desc->node, &pch->work_list); | |
ae43b328 KK |
2005 | if (power_down) { |
2006 | spin_lock(&pch->thread->dmac->lock); | |
2007 | _start(pch->thread); | |
2008 | spin_unlock(&pch->thread->dmac->lock); | |
2009 | power_down = false; | |
2010 | } | |
39ff8613 LPC |
2011 | } else { |
2012 | desc->status = FREE; | |
2013 | list_move_tail(&desc->node, &pch->dmac->desc_pool); | |
2014 | } | |
2015 | ||
d38a8c62 DW |
2016 | dma_descriptor_unmap(&desc->txd); |
2017 | ||
39ff8613 LPC |
2018 | if (callback) { |
2019 | spin_unlock_irqrestore(&pch->lock, flags); | |
2020 | callback(callback_param); | |
2021 | spin_lock_irqsave(&pch->lock, flags); | |
2022 | } | |
2023 | } | |
2024 | spin_unlock_irqrestore(&pch->lock, flags); | |
ae43b328 KK |
2025 | |
2026 | /* If work list empty, power down */ | |
2027 | if (power_down) { | |
2028 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); | |
2029 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); | |
2030 | } | |
b3040e40 JB |
2031 | } |
2032 | ||
3e2ec13a TA |
2033 | bool pl330_filter(struct dma_chan *chan, void *param) |
2034 | { | |
cd072515 | 2035 | u8 *peri_id; |
3e2ec13a TA |
2036 | |
2037 | if (chan->device->dev->driver != &pl330_driver.drv) | |
2038 | return false; | |
2039 | ||
cd072515 | 2040 | peri_id = chan->private; |
2f986ec6 | 2041 | return *peri_id == (unsigned long)param; |
3e2ec13a TA |
2042 | } |
2043 | EXPORT_SYMBOL(pl330_filter); | |
2044 | ||
a80258f9 PV |
2045 | static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, |
2046 | struct of_dma *ofdma) | |
2047 | { | |
2048 | int count = dma_spec->args_count; | |
f6f2421c | 2049 | struct pl330_dmac *pl330 = ofdma->of_dma_data; |
70cbb163 | 2050 | unsigned int chan_id; |
a80258f9 | 2051 | |
f6f2421c LPC |
2052 | if (!pl330) |
2053 | return NULL; | |
2054 | ||
a80258f9 PV |
2055 | if (count != 1) |
2056 | return NULL; | |
2057 | ||
70cbb163 | 2058 | chan_id = dma_spec->args[0]; |
f6f2421c | 2059 | if (chan_id >= pl330->num_peripherals) |
70cbb163 | 2060 | return NULL; |
a80258f9 | 2061 | |
f6f2421c | 2062 | return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); |
a80258f9 PV |
2063 | } |
2064 | ||
b3040e40 JB |
2065 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
2066 | { | |
2067 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f6f2421c | 2068 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2069 | unsigned long flags; |
2070 | ||
2071 | spin_lock_irqsave(&pch->lock, flags); | |
2072 | ||
d3ee98cd | 2073 | dma_cookie_init(chan); |
42bc9cf4 | 2074 | pch->cyclic = false; |
b3040e40 | 2075 | |
f6f2421c | 2076 | pch->thread = pl330_request_channel(pl330); |
65ad6060 | 2077 | if (!pch->thread) { |
b3040e40 | 2078 | spin_unlock_irqrestore(&pch->lock, flags); |
02747885 | 2079 | return -ENOMEM; |
b3040e40 JB |
2080 | } |
2081 | ||
2082 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
2083 | ||
2084 | spin_unlock_irqrestore(&pch->lock, flags); | |
2085 | ||
2086 | return 1; | |
2087 | } | |
2088 | ||
740aa957 MR |
2089 | static int pl330_config(struct dma_chan *chan, |
2090 | struct dma_slave_config *slave_config) | |
2091 | { | |
2092 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2093 | ||
2094 | if (slave_config->direction == DMA_MEM_TO_DEV) { | |
2095 | if (slave_config->dst_addr) | |
2096 | pch->fifo_addr = slave_config->dst_addr; | |
2097 | if (slave_config->dst_addr_width) | |
2098 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
2099 | if (slave_config->dst_maxburst) | |
2100 | pch->burst_len = slave_config->dst_maxburst; | |
2101 | } else if (slave_config->direction == DMA_DEV_TO_MEM) { | |
2102 | if (slave_config->src_addr) | |
2103 | pch->fifo_addr = slave_config->src_addr; | |
2104 | if (slave_config->src_addr_width) | |
2105 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
2106 | if (slave_config->src_maxburst) | |
2107 | pch->burst_len = slave_config->src_maxburst; | |
2108 | } | |
2109 | ||
2110 | return 0; | |
2111 | } | |
2112 | ||
2113 | static int pl330_terminate_all(struct dma_chan *chan) | |
b3040e40 JB |
2114 | { |
2115 | struct dma_pl330_chan *pch = to_pchan(chan); | |
39ff8613 | 2116 | struct dma_pl330_desc *desc; |
b3040e40 | 2117 | unsigned long flags; |
f6f2421c | 2118 | struct pl330_dmac *pl330 = pch->dmac; |
ae43b886 | 2119 | LIST_HEAD(list); |
b3040e40 | 2120 | |
740aa957 MR |
2121 | spin_lock_irqsave(&pch->lock, flags); |
2122 | spin_lock(&pl330->lock); | |
2123 | _stop(pch->thread); | |
2124 | spin_unlock(&pl330->lock); | |
2125 | ||
2126 | pch->thread->req[0].desc = NULL; | |
2127 | pch->thread->req[1].desc = NULL; | |
2128 | pch->thread->req_running = -1; | |
2129 | ||
2130 | /* Mark all desc done */ | |
2131 | list_for_each_entry(desc, &pch->submitted_list, node) { | |
2132 | desc->status = FREE; | |
2133 | dma_cookie_complete(&desc->txd); | |
2134 | } | |
ae43b328 | 2135 | |
740aa957 MR |
2136 | list_for_each_entry(desc, &pch->work_list , node) { |
2137 | desc->status = FREE; | |
2138 | dma_cookie_complete(&desc->txd); | |
1d0c1d60 | 2139 | } |
b3040e40 | 2140 | |
740aa957 MR |
2141 | list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); |
2142 | list_splice_tail_init(&pch->work_list, &pl330->desc_pool); | |
2143 | list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); | |
2144 | spin_unlock_irqrestore(&pch->lock, flags); | |
2145 | ||
b3040e40 JB |
2146 | return 0; |
2147 | } | |
2148 | ||
2149 | static void pl330_free_chan_resources(struct dma_chan *chan) | |
2150 | { | |
2151 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2152 | unsigned long flags; | |
2153 | ||
b3040e40 JB |
2154 | tasklet_kill(&pch->task); |
2155 | ||
ae43b328 | 2156 | pm_runtime_get_sync(pch->dmac->ddma.dev); |
da331ba8 BZ |
2157 | spin_lock_irqsave(&pch->lock, flags); |
2158 | ||
65ad6060 LPC |
2159 | pl330_release_channel(pch->thread); |
2160 | pch->thread = NULL; | |
b3040e40 | 2161 | |
42bc9cf4 BK |
2162 | if (pch->cyclic) |
2163 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
2164 | ||
b3040e40 | 2165 | spin_unlock_irqrestore(&pch->lock, flags); |
ae43b328 KK |
2166 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); |
2167 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); | |
b3040e40 JB |
2168 | } |
2169 | ||
2170 | static enum dma_status | |
2171 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
2172 | struct dma_tx_state *txstate) | |
2173 | { | |
96a2af41 | 2174 | return dma_cookie_status(chan, cookie, txstate); |
b3040e40 JB |
2175 | } |
2176 | ||
2177 | static void pl330_issue_pending(struct dma_chan *chan) | |
2178 | { | |
04abf5da LPC |
2179 | struct dma_pl330_chan *pch = to_pchan(chan); |
2180 | unsigned long flags; | |
2181 | ||
2182 | spin_lock_irqsave(&pch->lock, flags); | |
ae43b328 KK |
2183 | if (list_empty(&pch->work_list)) { |
2184 | /* | |
2185 | * Warn on nothing pending. Empty submitted_list may | |
2186 | * break our pm_runtime usage counter as it is | |
2187 | * updated on work_list emptiness status. | |
2188 | */ | |
2189 | WARN_ON(list_empty(&pch->submitted_list)); | |
2190 | pm_runtime_get_sync(pch->dmac->ddma.dev); | |
2191 | } | |
04abf5da LPC |
2192 | list_splice_tail_init(&pch->submitted_list, &pch->work_list); |
2193 | spin_unlock_irqrestore(&pch->lock, flags); | |
2194 | ||
2195 | pl330_tasklet((unsigned long)pch); | |
b3040e40 JB |
2196 | } |
2197 | ||
2198 | /* | |
2199 | * We returned the last one of the circular list of descriptor(s) | |
2200 | * from prep_xxx, so the argument to submit corresponds to the last | |
2201 | * descriptor of the list. | |
2202 | */ | |
2203 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
2204 | { | |
2205 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
2206 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
2207 | dma_cookie_t cookie; | |
2208 | unsigned long flags; | |
2209 | ||
2210 | spin_lock_irqsave(&pch->lock, flags); | |
2211 | ||
2212 | /* Assign cookies to all nodes */ | |
b3040e40 JB |
2213 | while (!list_empty(&last->node)) { |
2214 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
fc514460 LPC |
2215 | if (pch->cyclic) { |
2216 | desc->txd.callback = last->txd.callback; | |
2217 | desc->txd.callback_param = last->txd.callback_param; | |
2218 | } | |
b3040e40 | 2219 | |
884485e1 | 2220 | dma_cookie_assign(&desc->txd); |
b3040e40 | 2221 | |
04abf5da | 2222 | list_move_tail(&desc->node, &pch->submitted_list); |
b3040e40 JB |
2223 | } |
2224 | ||
884485e1 | 2225 | cookie = dma_cookie_assign(&last->txd); |
04abf5da | 2226 | list_add_tail(&last->node, &pch->submitted_list); |
b3040e40 JB |
2227 | spin_unlock_irqrestore(&pch->lock, flags); |
2228 | ||
2229 | return cookie; | |
2230 | } | |
2231 | ||
2232 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
2233 | { | |
b3040e40 | 2234 | desc->rqcfg.swap = SWAP_NO; |
f0564c7e LPC |
2235 | desc->rqcfg.scctl = CCTRL0; |
2236 | desc->rqcfg.dcctl = CCTRL0; | |
b3040e40 JB |
2237 | desc->txd.tx_submit = pl330_tx_submit; |
2238 | ||
2239 | INIT_LIST_HEAD(&desc->node); | |
2240 | } | |
2241 | ||
2242 | /* Returns the number of descriptors added to the DMAC pool */ | |
f6f2421c | 2243 | static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count) |
b3040e40 JB |
2244 | { |
2245 | struct dma_pl330_desc *desc; | |
2246 | unsigned long flags; | |
2247 | int i; | |
2248 | ||
0baf8f6a | 2249 | desc = kcalloc(count, sizeof(*desc), flg); |
b3040e40 JB |
2250 | if (!desc) |
2251 | return 0; | |
2252 | ||
f6f2421c | 2253 | spin_lock_irqsave(&pl330->pool_lock, flags); |
b3040e40 JB |
2254 | |
2255 | for (i = 0; i < count; i++) { | |
2256 | _init_desc(&desc[i]); | |
f6f2421c | 2257 | list_add_tail(&desc[i].node, &pl330->desc_pool); |
b3040e40 JB |
2258 | } |
2259 | ||
f6f2421c | 2260 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
b3040e40 JB |
2261 | |
2262 | return count; | |
2263 | } | |
2264 | ||
f6f2421c | 2265 | static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330) |
b3040e40 JB |
2266 | { |
2267 | struct dma_pl330_desc *desc = NULL; | |
2268 | unsigned long flags; | |
2269 | ||
f6f2421c | 2270 | spin_lock_irqsave(&pl330->pool_lock, flags); |
b3040e40 | 2271 | |
f6f2421c LPC |
2272 | if (!list_empty(&pl330->desc_pool)) { |
2273 | desc = list_entry(pl330->desc_pool.next, | |
b3040e40 JB |
2274 | struct dma_pl330_desc, node); |
2275 | ||
2276 | list_del_init(&desc->node); | |
2277 | ||
2278 | desc->status = PREP; | |
2279 | desc->txd.callback = NULL; | |
2280 | } | |
2281 | ||
f6f2421c | 2282 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
b3040e40 JB |
2283 | |
2284 | return desc; | |
2285 | } | |
2286 | ||
2287 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
2288 | { | |
f6f2421c | 2289 | struct pl330_dmac *pl330 = pch->dmac; |
cd072515 | 2290 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
2291 | struct dma_pl330_desc *desc; |
2292 | ||
2293 | /* Pluck one desc from the pool of DMAC */ | |
f6f2421c | 2294 | desc = pluck_desc(pl330); |
b3040e40 JB |
2295 | |
2296 | /* If the DMAC pool is empty, alloc new */ | |
2297 | if (!desc) { | |
f6f2421c | 2298 | if (!add_desc(pl330, GFP_ATOMIC, 1)) |
b3040e40 JB |
2299 | return NULL; |
2300 | ||
2301 | /* Try again */ | |
f6f2421c | 2302 | desc = pluck_desc(pl330); |
b3040e40 | 2303 | if (!desc) { |
f6f2421c | 2304 | dev_err(pch->dmac->ddma.dev, |
b3040e40 JB |
2305 | "%s:%d ALERT!\n", __func__, __LINE__); |
2306 | return NULL; | |
2307 | } | |
2308 | } | |
2309 | ||
2310 | /* Initialize the descriptor */ | |
2311 | desc->pchan = pch; | |
2312 | desc->txd.cookie = 0; | |
2313 | async_tx_ack(&desc->txd); | |
2314 | ||
9dc5a315 | 2315 | desc->peri = peri_id ? pch->chan.chan_id : 0; |
f6f2421c | 2316 | desc->rqcfg.pcfg = &pch->dmac->pcfg; |
b3040e40 JB |
2317 | |
2318 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
2319 | ||
2320 | return desc; | |
2321 | } | |
2322 | ||
2323 | static inline void fill_px(struct pl330_xfer *px, | |
2324 | dma_addr_t dst, dma_addr_t src, size_t len) | |
2325 | { | |
b3040e40 JB |
2326 | px->bytes = len; |
2327 | px->dst_addr = dst; | |
2328 | px->src_addr = src; | |
2329 | } | |
2330 | ||
2331 | static struct dma_pl330_desc * | |
2332 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
2333 | dma_addr_t src, size_t len) | |
2334 | { | |
2335 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
2336 | ||
2337 | if (!desc) { | |
f6f2421c | 2338 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
b3040e40 JB |
2339 | __func__, __LINE__); |
2340 | return NULL; | |
2341 | } | |
2342 | ||
2343 | /* | |
2344 | * Ideally we should lookout for reqs bigger than | |
2345 | * those that can be programmed with 256 bytes of | |
2346 | * MC buffer, but considering a req size is seldom | |
2347 | * going to be word-unaligned and more than 200MB, | |
2348 | * we take it easy. | |
2349 | * Also, should the limit is reached we'd rather | |
2350 | * have the platform increase MC buffer size than | |
2351 | * complicating this API driver. | |
2352 | */ | |
2353 | fill_px(&desc->px, dst, src, len); | |
2354 | ||
2355 | return desc; | |
2356 | } | |
2357 | ||
2358 | /* Call after fixing burst size */ | |
2359 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
2360 | { | |
2361 | struct dma_pl330_chan *pch = desc->pchan; | |
f6f2421c | 2362 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2363 | int burst_len; |
2364 | ||
f6f2421c | 2365 | burst_len = pl330->pcfg.data_bus_width / 8; |
c27f9556 | 2366 | burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; |
b3040e40 JB |
2367 | burst_len >>= desc->rqcfg.brst_size; |
2368 | ||
2369 | /* src/dst_burst_len can't be more than 16 */ | |
2370 | if (burst_len > 16) | |
2371 | burst_len = 16; | |
2372 | ||
2373 | while (burst_len > 1) { | |
2374 | if (!(len % (burst_len << desc->rqcfg.brst_size))) | |
2375 | break; | |
2376 | burst_len--; | |
2377 | } | |
2378 | ||
2379 | return burst_len; | |
2380 | } | |
2381 | ||
42bc9cf4 BK |
2382 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
2383 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
185ecb5f | 2384 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 2385 | unsigned long flags) |
42bc9cf4 | 2386 | { |
fc514460 | 2387 | struct dma_pl330_desc *desc = NULL, *first = NULL; |
42bc9cf4 | 2388 | struct dma_pl330_chan *pch = to_pchan(chan); |
f6f2421c | 2389 | struct pl330_dmac *pl330 = pch->dmac; |
fc514460 | 2390 | unsigned int i; |
42bc9cf4 BK |
2391 | dma_addr_t dst; |
2392 | dma_addr_t src; | |
2393 | ||
fc514460 | 2394 | if (len % period_len != 0) |
42bc9cf4 | 2395 | return NULL; |
42bc9cf4 | 2396 | |
fc514460 | 2397 | if (!is_slave_direction(direction)) { |
f6f2421c | 2398 | dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", |
42bc9cf4 BK |
2399 | __func__, __LINE__); |
2400 | return NULL; | |
2401 | } | |
2402 | ||
fc514460 LPC |
2403 | for (i = 0; i < len / period_len; i++) { |
2404 | desc = pl330_get_desc(pch); | |
2405 | if (!desc) { | |
f6f2421c | 2406 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
fc514460 | 2407 | __func__, __LINE__); |
42bc9cf4 | 2408 | |
fc514460 LPC |
2409 | if (!first) |
2410 | return NULL; | |
2411 | ||
f6f2421c | 2412 | spin_lock_irqsave(&pl330->pool_lock, flags); |
fc514460 LPC |
2413 | |
2414 | while (!list_empty(&first->node)) { | |
2415 | desc = list_entry(first->node.next, | |
2416 | struct dma_pl330_desc, node); | |
f6f2421c | 2417 | list_move_tail(&desc->node, &pl330->desc_pool); |
fc514460 LPC |
2418 | } |
2419 | ||
f6f2421c | 2420 | list_move_tail(&first->node, &pl330->desc_pool); |
fc514460 | 2421 | |
f6f2421c | 2422 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
42bc9cf4 | 2423 | |
fc514460 LPC |
2424 | return NULL; |
2425 | } | |
2426 | ||
2427 | switch (direction) { | |
2428 | case DMA_MEM_TO_DEV: | |
2429 | desc->rqcfg.src_inc = 1; | |
2430 | desc->rqcfg.dst_inc = 0; | |
fc514460 LPC |
2431 | src = dma_addr; |
2432 | dst = pch->fifo_addr; | |
2433 | break; | |
2434 | case DMA_DEV_TO_MEM: | |
2435 | desc->rqcfg.src_inc = 0; | |
2436 | desc->rqcfg.dst_inc = 1; | |
fc514460 LPC |
2437 | src = pch->fifo_addr; |
2438 | dst = dma_addr; | |
2439 | break; | |
2440 | default: | |
2441 | break; | |
2442 | } | |
2443 | ||
9dc5a315 | 2444 | desc->rqtype = direction; |
fc514460 LPC |
2445 | desc->rqcfg.brst_size = pch->burst_sz; |
2446 | desc->rqcfg.brst_len = 1; | |
2447 | fill_px(&desc->px, dst, src, period_len); | |
2448 | ||
2449 | if (!first) | |
2450 | first = desc; | |
2451 | else | |
2452 | list_add_tail(&desc->node, &first->node); | |
2453 | ||
2454 | dma_addr += period_len; | |
2455 | } | |
2456 | ||
2457 | if (!desc) | |
2458 | return NULL; | |
2459 | ||
2460 | pch->cyclic = true; | |
2461 | desc->txd.flags = flags; | |
42bc9cf4 BK |
2462 | |
2463 | return &desc->txd; | |
2464 | } | |
2465 | ||
b3040e40 JB |
2466 | static struct dma_async_tx_descriptor * |
2467 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
2468 | dma_addr_t src, size_t len, unsigned long flags) | |
2469 | { | |
2470 | struct dma_pl330_desc *desc; | |
2471 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f6f2421c | 2472 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2473 | int burst; |
2474 | ||
4e0e6109 | 2475 | if (unlikely(!pch || !len)) |
b3040e40 JB |
2476 | return NULL; |
2477 | ||
b3040e40 JB |
2478 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); |
2479 | if (!desc) | |
2480 | return NULL; | |
2481 | ||
2482 | desc->rqcfg.src_inc = 1; | |
2483 | desc->rqcfg.dst_inc = 1; | |
9dc5a315 | 2484 | desc->rqtype = DMA_MEM_TO_MEM; |
b3040e40 JB |
2485 | |
2486 | /* Select max possible burst size */ | |
f6f2421c | 2487 | burst = pl330->pcfg.data_bus_width / 8; |
b3040e40 | 2488 | |
137bd110 JM |
2489 | /* |
2490 | * Make sure we use a burst size that aligns with all the memcpy | |
2491 | * parameters because our DMA programming algorithm doesn't cope with | |
2492 | * transfers which straddle an entry in the DMA device's MFIFO. | |
2493 | */ | |
2494 | while ((src | dst | len) & (burst - 1)) | |
b3040e40 | 2495 | burst /= 2; |
b3040e40 JB |
2496 | |
2497 | desc->rqcfg.brst_size = 0; | |
2498 | while (burst != (1 << desc->rqcfg.brst_size)) | |
2499 | desc->rqcfg.brst_size++; | |
2500 | ||
137bd110 JM |
2501 | /* |
2502 | * If burst size is smaller than bus width then make sure we only | |
2503 | * transfer one at a time to avoid a burst stradling an MFIFO entry. | |
2504 | */ | |
2505 | if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) | |
2506 | desc->rqcfg.brst_len = 1; | |
2507 | ||
b3040e40 JB |
2508 | desc->rqcfg.brst_len = get_burst_len(desc, len); |
2509 | ||
2510 | desc->txd.flags = flags; | |
2511 | ||
2512 | return &desc->txd; | |
2513 | } | |
2514 | ||
f6f2421c | 2515 | static void __pl330_giveback_desc(struct pl330_dmac *pl330, |
52a9d179 CP |
2516 | struct dma_pl330_desc *first) |
2517 | { | |
2518 | unsigned long flags; | |
2519 | struct dma_pl330_desc *desc; | |
2520 | ||
2521 | if (!first) | |
2522 | return; | |
2523 | ||
f6f2421c | 2524 | spin_lock_irqsave(&pl330->pool_lock, flags); |
52a9d179 CP |
2525 | |
2526 | while (!list_empty(&first->node)) { | |
2527 | desc = list_entry(first->node.next, | |
2528 | struct dma_pl330_desc, node); | |
f6f2421c | 2529 | list_move_tail(&desc->node, &pl330->desc_pool); |
52a9d179 CP |
2530 | } |
2531 | ||
f6f2421c | 2532 | list_move_tail(&first->node, &pl330->desc_pool); |
52a9d179 | 2533 | |
f6f2421c | 2534 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
52a9d179 CP |
2535 | } |
2536 | ||
b3040e40 JB |
2537 | static struct dma_async_tx_descriptor * |
2538 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 2539 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 2540 | unsigned long flg, void *context) |
b3040e40 JB |
2541 | { |
2542 | struct dma_pl330_desc *first, *desc = NULL; | |
2543 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 | 2544 | struct scatterlist *sg; |
1b9bb715 | 2545 | int i; |
b3040e40 JB |
2546 | dma_addr_t addr; |
2547 | ||
cd072515 | 2548 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 JB |
2549 | return NULL; |
2550 | ||
1b9bb715 | 2551 | addr = pch->fifo_addr; |
b3040e40 JB |
2552 | |
2553 | first = NULL; | |
2554 | ||
2555 | for_each_sg(sgl, sg, sg_len, i) { | |
2556 | ||
2557 | desc = pl330_get_desc(pch); | |
2558 | if (!desc) { | |
f6f2421c | 2559 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 | 2560 | |
f6f2421c | 2561 | dev_err(pch->dmac->ddma.dev, |
b3040e40 JB |
2562 | "%s:%d Unable to fetch desc\n", |
2563 | __func__, __LINE__); | |
f6f2421c | 2564 | __pl330_giveback_desc(pl330, first); |
b3040e40 JB |
2565 | |
2566 | return NULL; | |
2567 | } | |
2568 | ||
2569 | if (!first) | |
2570 | first = desc; | |
2571 | else | |
2572 | list_add_tail(&desc->node, &first->node); | |
2573 | ||
db8196df | 2574 | if (direction == DMA_MEM_TO_DEV) { |
b3040e40 JB |
2575 | desc->rqcfg.src_inc = 1; |
2576 | desc->rqcfg.dst_inc = 0; | |
2577 | fill_px(&desc->px, | |
2578 | addr, sg_dma_address(sg), sg_dma_len(sg)); | |
2579 | } else { | |
2580 | desc->rqcfg.src_inc = 0; | |
2581 | desc->rqcfg.dst_inc = 1; | |
2582 | fill_px(&desc->px, | |
2583 | sg_dma_address(sg), addr, sg_dma_len(sg)); | |
2584 | } | |
2585 | ||
1b9bb715 | 2586 | desc->rqcfg.brst_size = pch->burst_sz; |
b3040e40 | 2587 | desc->rqcfg.brst_len = 1; |
9dc5a315 | 2588 | desc->rqtype = direction; |
b3040e40 JB |
2589 | } |
2590 | ||
2591 | /* Return the last desc in the chain */ | |
2592 | desc->txd.flags = flg; | |
2593 | return &desc->txd; | |
2594 | } | |
2595 | ||
2596 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
2597 | { | |
2598 | if (pl330_update(data)) | |
2599 | return IRQ_HANDLED; | |
2600 | else | |
2601 | return IRQ_NONE; | |
2602 | } | |
2603 | ||
ca38ff13 LPC |
2604 | #define PL330_DMA_BUSWIDTHS \ |
2605 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
2606 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
2607 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
2608 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ | |
2609 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | |
2610 | ||
b816ccc5 KK |
2611 | /* |
2612 | * Runtime PM callbacks are provided by amba/bus.c driver. | |
2613 | * | |
2614 | * It is assumed here that IRQ safe runtime PM is chosen in probe and amba | |
2615 | * bus driver will only disable/enable the clock in runtime PM callbacks. | |
2616 | */ | |
2617 | static int __maybe_unused pl330_suspend(struct device *dev) | |
2618 | { | |
2619 | struct amba_device *pcdev = to_amba_device(dev); | |
2620 | ||
2621 | pm_runtime_disable(dev); | |
2622 | ||
2623 | if (!pm_runtime_status_suspended(dev)) { | |
2624 | /* amba did not disable the clock */ | |
2625 | amba_pclk_disable(pcdev); | |
2626 | } | |
2627 | amba_pclk_unprepare(pcdev); | |
2628 | ||
2629 | return 0; | |
2630 | } | |
2631 | ||
2632 | static int __maybe_unused pl330_resume(struct device *dev) | |
2633 | { | |
2634 | struct amba_device *pcdev = to_amba_device(dev); | |
2635 | int ret; | |
2636 | ||
2637 | ret = amba_pclk_prepare(pcdev); | |
2638 | if (ret) | |
2639 | return ret; | |
2640 | ||
2641 | if (!pm_runtime_status_suspended(dev)) | |
2642 | ret = amba_pclk_enable(pcdev); | |
2643 | ||
2644 | pm_runtime_enable(dev); | |
2645 | ||
2646 | return ret; | |
2647 | } | |
2648 | ||
2649 | static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume); | |
2650 | ||
463a1f8b | 2651 | static int |
aa25afad | 2652 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 JB |
2653 | { |
2654 | struct dma_pl330_platdata *pdat; | |
f6f2421c LPC |
2655 | struct pl330_config *pcfg; |
2656 | struct pl330_dmac *pl330; | |
0b94c577 | 2657 | struct dma_pl330_chan *pch, *_p; |
b3040e40 JB |
2658 | struct dma_device *pd; |
2659 | struct resource *res; | |
2660 | int i, ret, irq; | |
4e0e6109 | 2661 | int num_chan; |
b3040e40 | 2662 | |
d4adcc01 | 2663 | pdat = dev_get_platdata(&adev->dev); |
b3040e40 | 2664 | |
64113016 RK |
2665 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); |
2666 | if (ret) | |
2667 | return ret; | |
2668 | ||
b3040e40 | 2669 | /* Allocate a new DMAC and its Channels */ |
f6f2421c LPC |
2670 | pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); |
2671 | if (!pl330) { | |
b3040e40 JB |
2672 | dev_err(&adev->dev, "unable to allocate mem\n"); |
2673 | return -ENOMEM; | |
2674 | } | |
2675 | ||
cee42392 AJ |
2676 | pd = &pl330->ddma; |
2677 | pd->dev = &adev->dev; | |
2678 | ||
f6f2421c | 2679 | pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0; |
b3040e40 JB |
2680 | |
2681 | res = &adev->res; | |
f6f2421c LPC |
2682 | pl330->base = devm_ioremap_resource(&adev->dev, res); |
2683 | if (IS_ERR(pl330->base)) | |
2684 | return PTR_ERR(pl330->base); | |
b3040e40 | 2685 | |
f6f2421c | 2686 | amba_set_drvdata(adev, pl330); |
a2f5203f | 2687 | |
02808b42 | 2688 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
e98b3caf MS |
2689 | irq = adev->irq[i]; |
2690 | if (irq) { | |
2691 | ret = devm_request_irq(&adev->dev, irq, | |
2692 | pl330_irq_handler, 0, | |
f6f2421c | 2693 | dev_name(&adev->dev), pl330); |
e98b3caf MS |
2694 | if (ret) |
2695 | return ret; | |
2696 | } else { | |
2697 | break; | |
2698 | } | |
2699 | } | |
b3040e40 | 2700 | |
f6f2421c LPC |
2701 | pcfg = &pl330->pcfg; |
2702 | ||
2703 | pcfg->periph_id = adev->periphid; | |
2704 | ret = pl330_add(pl330); | |
b3040e40 | 2705 | if (ret) |
173e838c | 2706 | return ret; |
b3040e40 | 2707 | |
f6f2421c LPC |
2708 | INIT_LIST_HEAD(&pl330->desc_pool); |
2709 | spin_lock_init(&pl330->pool_lock); | |
b3040e40 JB |
2710 | |
2711 | /* Create a descriptor pool of default size */ | |
f6f2421c | 2712 | if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC)) |
b3040e40 JB |
2713 | dev_warn(&adev->dev, "unable to allocate desc\n"); |
2714 | ||
b3040e40 JB |
2715 | INIT_LIST_HEAD(&pd->channels); |
2716 | ||
2717 | /* Initialize channel parameters */ | |
c8473828 | 2718 | if (pdat) |
f6f2421c | 2719 | num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan); |
c8473828 | 2720 | else |
f6f2421c | 2721 | num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); |
c8473828 | 2722 | |
f6f2421c | 2723 | pl330->num_peripherals = num_chan; |
70cbb163 | 2724 | |
f6f2421c LPC |
2725 | pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); |
2726 | if (!pl330->peripherals) { | |
61c6e753 | 2727 | ret = -ENOMEM; |
f6f2421c | 2728 | dev_err(&adev->dev, "unable to allocate pl330->peripherals\n"); |
e4d43c17 | 2729 | goto probe_err2; |
61c6e753 | 2730 | } |
b3040e40 | 2731 | |
4e0e6109 | 2732 | for (i = 0; i < num_chan; i++) { |
f6f2421c | 2733 | pch = &pl330->peripherals[i]; |
93ed5544 TA |
2734 | if (!adev->dev.of_node) |
2735 | pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; | |
2736 | else | |
2737 | pch->chan.private = adev->dev.of_node; | |
b3040e40 | 2738 | |
04abf5da | 2739 | INIT_LIST_HEAD(&pch->submitted_list); |
b3040e40 | 2740 | INIT_LIST_HEAD(&pch->work_list); |
39ff8613 | 2741 | INIT_LIST_HEAD(&pch->completed_list); |
b3040e40 | 2742 | spin_lock_init(&pch->lock); |
65ad6060 | 2743 | pch->thread = NULL; |
b3040e40 | 2744 | pch->chan.device = pd; |
f6f2421c | 2745 | pch->dmac = pl330; |
b3040e40 JB |
2746 | |
2747 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
2748 | list_add_tail(&pch->chan.device_node, &pd->channels); |
2749 | } | |
2750 | ||
93ed5544 | 2751 | if (pdat) { |
cd072515 | 2752 | pd->cap_mask = pdat->cap_mask; |
93ed5544 | 2753 | } else { |
cd072515 | 2754 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
f6f2421c | 2755 | if (pcfg->num_peri) { |
93ed5544 TA |
2756 | dma_cap_set(DMA_SLAVE, pd->cap_mask); |
2757 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); | |
5557a419 | 2758 | dma_cap_set(DMA_PRIVATE, pd->cap_mask); |
93ed5544 TA |
2759 | } |
2760 | } | |
b3040e40 JB |
2761 | |
2762 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
2763 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
2764 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 2765 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
2766 | pd->device_tx_status = pl330_tx_status; |
2767 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
740aa957 MR |
2768 | pd->device_config = pl330_config; |
2769 | pd->device_terminate_all = pl330_terminate_all; | |
b3040e40 | 2770 | pd->device_issue_pending = pl330_issue_pending; |
dcabe456 MR |
2771 | pd->src_addr_widths = PL330_DMA_BUSWIDTHS; |
2772 | pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; | |
2773 | pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
2774 | pd->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; | |
b3040e40 JB |
2775 | |
2776 | ret = dma_async_device_register(pd); | |
2777 | if (ret) { | |
2778 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
0b94c577 PV |
2779 | goto probe_err3; |
2780 | } | |
2781 | ||
2782 | if (adev->dev.of_node) { | |
2783 | ret = of_dma_controller_register(adev->dev.of_node, | |
f6f2421c | 2784 | of_dma_pl330_xlate, pl330); |
0b94c577 PV |
2785 | if (ret) { |
2786 | dev_err(&adev->dev, | |
2787 | "unable to register DMA to the generic DT DMA helpers\n"); | |
2788 | } | |
b3040e40 | 2789 | } |
b714b84e | 2790 | |
f6f2421c | 2791 | adev->dev.dma_parms = &pl330->dma_parms; |
b714b84e | 2792 | |
dbaf6d85 VK |
2793 | /* |
2794 | * This is the limit for transfers with a buswidth of 1, larger | |
2795 | * buswidths will have larger limits. | |
2796 | */ | |
2797 | ret = dma_set_max_seg_size(&adev->dev, 1900800); | |
2798 | if (ret) | |
2799 | dev_err(&adev->dev, "unable to set the seg size\n"); | |
2800 | ||
b3040e40 | 2801 | |
b3040e40 | 2802 | dev_info(&adev->dev, |
1f0a5cbf | 2803 | "Loaded driver for PL330 DMAC-%x\n", adev->periphid); |
b3040e40 JB |
2804 | dev_info(&adev->dev, |
2805 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
f6f2421c LPC |
2806 | pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, |
2807 | pcfg->num_peri, pcfg->num_events); | |
b3040e40 | 2808 | |
ae43b328 KK |
2809 | pm_runtime_irq_safe(&adev->dev); |
2810 | pm_runtime_use_autosuspend(&adev->dev); | |
2811 | pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); | |
2812 | pm_runtime_mark_last_busy(&adev->dev); | |
2813 | pm_runtime_put_autosuspend(&adev->dev); | |
2814 | ||
b3040e40 | 2815 | return 0; |
0b94c577 | 2816 | probe_err3: |
0b94c577 | 2817 | /* Idle the DMAC */ |
f6f2421c | 2818 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
0b94c577 PV |
2819 | chan.device_node) { |
2820 | ||
2821 | /* Remove the channel */ | |
2822 | list_del(&pch->chan.device_node); | |
2823 | ||
2824 | /* Flush the channel */ | |
0f5ebabd | 2825 | if (pch->thread) { |
740aa957 | 2826 | pl330_terminate_all(&pch->chan); |
0f5ebabd KK |
2827 | pl330_free_chan_resources(&pch->chan); |
2828 | } | |
0b94c577 | 2829 | } |
b3040e40 | 2830 | probe_err2: |
f6f2421c | 2831 | pl330_del(pl330); |
b3040e40 JB |
2832 | |
2833 | return ret; | |
2834 | } | |
2835 | ||
4bf27b8b | 2836 | static int pl330_remove(struct amba_device *adev) |
b3040e40 | 2837 | { |
f6f2421c | 2838 | struct pl330_dmac *pl330 = amba_get_drvdata(adev); |
b3040e40 | 2839 | struct dma_pl330_chan *pch, *_p; |
b3040e40 | 2840 | |
ae43b328 KK |
2841 | pm_runtime_get_noresume(pl330->ddma.dev); |
2842 | ||
0b94c577 PV |
2843 | if (adev->dev.of_node) |
2844 | of_dma_controller_free(adev->dev.of_node); | |
421da89a | 2845 | |
f6f2421c | 2846 | dma_async_device_unregister(&pl330->ddma); |
b3040e40 JB |
2847 | |
2848 | /* Idle the DMAC */ | |
f6f2421c | 2849 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
b3040e40 JB |
2850 | chan.device_node) { |
2851 | ||
2852 | /* Remove the channel */ | |
2853 | list_del(&pch->chan.device_node); | |
2854 | ||
2855 | /* Flush the channel */ | |
6e4a2a83 | 2856 | if (pch->thread) { |
740aa957 | 2857 | pl330_terminate_all(&pch->chan); |
6e4a2a83 KK |
2858 | pl330_free_chan_resources(&pch->chan); |
2859 | } | |
b3040e40 JB |
2860 | } |
2861 | ||
f6f2421c | 2862 | pl330_del(pl330); |
b3040e40 | 2863 | |
b3040e40 JB |
2864 | return 0; |
2865 | } | |
2866 | ||
2867 | static struct amba_id pl330_ids[] = { | |
2868 | { | |
2869 | .id = 0x00041330, | |
2870 | .mask = 0x000fffff, | |
2871 | }, | |
2872 | { 0, 0 }, | |
2873 | }; | |
2874 | ||
e8fa516a DM |
2875 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
2876 | ||
b3040e40 JB |
2877 | static struct amba_driver pl330_driver = { |
2878 | .drv = { | |
2879 | .owner = THIS_MODULE, | |
2880 | .name = "dma-pl330", | |
b816ccc5 | 2881 | .pm = &pl330_pm, |
b3040e40 JB |
2882 | }, |
2883 | .id_table = pl330_ids, | |
2884 | .probe = pl330_probe, | |
2885 | .remove = pl330_remove, | |
2886 | }; | |
2887 | ||
9e5ed094 | 2888 | module_amba_driver(pl330_driver); |
b3040e40 | 2889 | |
046209f6 | 2890 | MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); |
b3040e40 JB |
2891 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); |
2892 | MODULE_LICENSE("GPL"); |