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Commit | Line | Data |
---|---|---|
d8902adc NI |
1 | /* |
2 | * Renesas SuperH DMA Engine support | |
3 | * | |
4 | * base is drivers/dma/flsdma.c | |
5 | * | |
ce3a1ab7 | 6 | * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
d8902adc NI |
7 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> |
8 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | |
9 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * - DMA of SuperH does not have Hardware DMA chain mode. | |
17 | * - MAX DMA size is 16MB. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/module.h> | |
5a0e3ad6 | 23 | #include <linux/slab.h> |
d8902adc NI |
24 | #include <linux/interrupt.h> |
25 | #include <linux/dmaengine.h> | |
26 | #include <linux/delay.h> | |
d8902adc | 27 | #include <linux/platform_device.h> |
20f2a3b5 | 28 | #include <linux/pm_runtime.h> |
b2623a61 | 29 | #include <linux/sh_dma.h> |
03aa18f5 PM |
30 | #include <linux/notifier.h> |
31 | #include <linux/kdebug.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <linux/rculist.h> | |
d2ebfb33 | 34 | |
e95be94b | 35 | #include "../dmaengine.h" |
d8902adc NI |
36 | #include "shdma.h" |
37 | ||
ce3a1ab7 | 38 | #define SH_DMAE_DRV_NAME "sh-dma-engine" |
d8902adc | 39 | |
8b1935e6 GL |
40 | /* Default MEMCPY transfer size = 2^2 = 4 bytes */ |
41 | #define LOG2_DEFAULT_XFER_SIZE 2 | |
ce3a1ab7 GL |
42 | #define SH_DMA_SLAVE_NUMBER 256 |
43 | #define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1) | |
d8902adc | 44 | |
03aa18f5 PM |
45 | /* |
46 | * Used for write-side mutual exclusion for the global device list, | |
2dc66667 | 47 | * read-side synchronization by way of RCU, and per-controller data. |
03aa18f5 PM |
48 | */ |
49 | static DEFINE_SPINLOCK(sh_dmae_lock); | |
50 | static LIST_HEAD(sh_dmae_devices); | |
51 | ||
ca8b3878 GL |
52 | /* |
53 | * Different DMAC implementations provide different ways to clear DMA channels: | |
54 | * (1) none - no CHCLR registers are available | |
55 | * (2) one CHCLR register per channel - 0 has to be written to it to clear | |
56 | * channel buffers | |
57 | * (3) one CHCLR per several channels - 1 has to be written to the bit, | |
58 | * corresponding to the specific channel to reset it | |
59 | */ | |
a28a94e8 | 60 | static void channel_clear(struct sh_dmae_chan *sh_dc) |
c11b46c3 GL |
61 | { |
62 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | |
ca8b3878 GL |
63 | const struct sh_dmae_channel *chan_pdata = shdev->pdata->channel + |
64 | sh_dc->shdma_chan.id; | |
65 | u32 val = shdev->pdata->chclr_bitwise ? 1 << chan_pdata->chclr_bit : 0; | |
c11b46c3 | 66 | |
ca8b3878 | 67 | __raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset); |
c11b46c3 | 68 | } |
3542a113 | 69 | |
d8902adc NI |
70 | static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) |
71 | { | |
115357e9 | 72 | __raw_writel(data, sh_dc->base + reg); |
d8902adc NI |
73 | } |
74 | ||
75 | static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) | |
76 | { | |
115357e9 | 77 | return __raw_readl(sh_dc->base + reg); |
027811b9 GL |
78 | } |
79 | ||
80 | static u16 dmaor_read(struct sh_dmae_device *shdev) | |
81 | { | |
115357e9 | 82 | void __iomem *addr = shdev->chan_reg + DMAOR; |
e76c3af8 KM |
83 | |
84 | if (shdev->pdata->dmaor_is_32bit) | |
85 | return __raw_readl(addr); | |
86 | else | |
87 | return __raw_readw(addr); | |
027811b9 GL |
88 | } |
89 | ||
90 | static void dmaor_write(struct sh_dmae_device *shdev, u16 data) | |
91 | { | |
115357e9 | 92 | void __iomem *addr = shdev->chan_reg + DMAOR; |
e76c3af8 KM |
93 | |
94 | if (shdev->pdata->dmaor_is_32bit) | |
95 | __raw_writel(data, addr); | |
96 | else | |
97 | __raw_writew(data, addr); | |
d8902adc NI |
98 | } |
99 | ||
5899a723 KM |
100 | static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data) |
101 | { | |
102 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | |
103 | ||
115357e9 | 104 | __raw_writel(data, sh_dc->base + shdev->chcr_offset); |
5899a723 KM |
105 | } |
106 | ||
107 | static u32 chcr_read(struct sh_dmae_chan *sh_dc) | |
108 | { | |
109 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | |
110 | ||
115357e9 | 111 | return __raw_readl(sh_dc->base + shdev->chcr_offset); |
d8902adc NI |
112 | } |
113 | ||
d8902adc NI |
114 | /* |
115 | * Reset DMA controller | |
116 | * | |
117 | * SH7780 has two DMAOR register | |
118 | */ | |
027811b9 | 119 | static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev) |
d8902adc | 120 | { |
2dc66667 GL |
121 | unsigned short dmaor; |
122 | unsigned long flags; | |
123 | ||
124 | spin_lock_irqsave(&sh_dmae_lock, flags); | |
d8902adc | 125 | |
2dc66667 | 126 | dmaor = dmaor_read(shdev); |
027811b9 | 127 | dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME)); |
2dc66667 GL |
128 | |
129 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
d8902adc NI |
130 | } |
131 | ||
027811b9 | 132 | static int sh_dmae_rst(struct sh_dmae_device *shdev) |
d8902adc NI |
133 | { |
134 | unsigned short dmaor; | |
2dc66667 | 135 | unsigned long flags; |
d8902adc | 136 | |
2dc66667 | 137 | spin_lock_irqsave(&sh_dmae_lock, flags); |
d8902adc | 138 | |
2dc66667 GL |
139 | dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME); |
140 | ||
c11b46c3 GL |
141 | if (shdev->pdata->chclr_present) { |
142 | int i; | |
143 | for (i = 0; i < shdev->pdata->channel_num; i++) { | |
144 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
145 | if (sh_chan) | |
a28a94e8 | 146 | channel_clear(sh_chan); |
c11b46c3 GL |
147 | } |
148 | } | |
149 | ||
2dc66667 GL |
150 | dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init); |
151 | ||
152 | dmaor = dmaor_read(shdev); | |
153 | ||
154 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
155 | ||
156 | if (dmaor & (DMAOR_AE | DMAOR_NMIF)) { | |
ce3a1ab7 | 157 | dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n"); |
2dc66667 | 158 | return -EIO; |
d8902adc | 159 | } |
c11b46c3 | 160 | if (shdev->pdata->dmaor_init & ~dmaor) |
ce3a1ab7 | 161 | dev_warn(shdev->shdma_dev.dma_dev.dev, |
c11b46c3 GL |
162 | "DMAOR=0x%x hasn't latched the initial value 0x%x.\n", |
163 | dmaor, shdev->pdata->dmaor_init); | |
d8902adc NI |
164 | return 0; |
165 | } | |
166 | ||
fc461857 | 167 | static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) |
d8902adc | 168 | { |
5899a723 | 169 | u32 chcr = chcr_read(sh_chan); |
fc461857 GL |
170 | |
171 | if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) | |
172 | return true; /* working */ | |
173 | ||
174 | return false; /* waiting */ | |
d8902adc NI |
175 | } |
176 | ||
8b1935e6 | 177 | static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) |
d8902adc | 178 | { |
c4e0dd78 | 179 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
2833c47e | 180 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
8b1935e6 GL |
181 | int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | |
182 | ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); | |
183 | ||
184 | if (cnt >= pdata->ts_shift_num) | |
185 | cnt = 0; | |
623b4ac4 | 186 | |
8b1935e6 GL |
187 | return pdata->ts_shift[cnt]; |
188 | } | |
189 | ||
190 | static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) | |
191 | { | |
c4e0dd78 | 192 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
2833c47e | 193 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
8b1935e6 GL |
194 | int i; |
195 | ||
196 | for (i = 0; i < pdata->ts_shift_num; i++) | |
197 | if (pdata->ts_shift[i] == l2size) | |
198 | break; | |
199 | ||
200 | if (i == pdata->ts_shift_num) | |
201 | i = 0; | |
202 | ||
203 | return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) | | |
204 | ((i << pdata->ts_high_shift) & pdata->ts_high_mask); | |
d8902adc NI |
205 | } |
206 | ||
3542a113 | 207 | static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) |
d8902adc | 208 | { |
3542a113 GL |
209 | sh_dmae_writel(sh_chan, hw->sar, SAR); |
210 | sh_dmae_writel(sh_chan, hw->dar, DAR); | |
cfefe997 | 211 | sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); |
d8902adc NI |
212 | } |
213 | ||
214 | static void dmae_start(struct sh_dmae_chan *sh_chan) | |
215 | { | |
67c6269e | 216 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
5899a723 | 217 | u32 chcr = chcr_read(sh_chan); |
d8902adc | 218 | |
260bf2c5 KM |
219 | if (shdev->pdata->needs_tend_set) |
220 | sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND); | |
221 | ||
67c6269e | 222 | chcr |= CHCR_DE | shdev->chcr_ie_bit; |
5899a723 | 223 | chcr_write(sh_chan, chcr & ~CHCR_TE); |
d8902adc NI |
224 | } |
225 | ||
cfefe997 GL |
226 | static void dmae_init(struct sh_dmae_chan *sh_chan) |
227 | { | |
8b1935e6 GL |
228 | /* |
229 | * Default configuration for dual address memory-memory transfer. | |
230 | * 0x400 represents auto-request. | |
231 | */ | |
232 | u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, | |
233 | LOG2_DEFAULT_XFER_SIZE); | |
234 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); | |
5899a723 | 235 | chcr_write(sh_chan, chcr); |
cfefe997 GL |
236 | } |
237 | ||
d8902adc NI |
238 | static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) |
239 | { | |
2dc66667 | 240 | /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */ |
fc461857 GL |
241 | if (dmae_is_busy(sh_chan)) |
242 | return -EBUSY; | |
d8902adc | 243 | |
8b1935e6 | 244 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); |
5899a723 | 245 | chcr_write(sh_chan, val); |
cfefe997 | 246 | |
d8902adc NI |
247 | return 0; |
248 | } | |
249 | ||
d8902adc NI |
250 | static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) |
251 | { | |
c4e0dd78 | 252 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
2833c47e | 253 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
ce3a1ab7 | 254 | const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id]; |
115357e9 | 255 | void __iomem *addr = shdev->dmars; |
090b9180 | 256 | unsigned int shift = chan_pdata->dmars_bit; |
fc461857 GL |
257 | |
258 | if (dmae_is_busy(sh_chan)) | |
259 | return -EBUSY; | |
d8902adc | 260 | |
260bf2c5 KM |
261 | if (pdata->no_dmars) |
262 | return 0; | |
263 | ||
26fc02ab MD |
264 | /* in the case of a missing DMARS resource use first memory window */ |
265 | if (!addr) | |
115357e9 GL |
266 | addr = shdev->chan_reg; |
267 | addr += chan_pdata->dmars; | |
26fc02ab | 268 | |
027811b9 GL |
269 | __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), |
270 | addr); | |
d8902adc NI |
271 | |
272 | return 0; | |
273 | } | |
274 | ||
ce3a1ab7 GL |
275 | static void sh_dmae_start_xfer(struct shdma_chan *schan, |
276 | struct shdma_desc *sdesc) | |
d8902adc | 277 | { |
ce3a1ab7 GL |
278 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
279 | shdma_chan); | |
280 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | |
281 | struct sh_dmae_desc, shdma_desc); | |
282 | dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n", | |
283 | sdesc->async_tx.cookie, sh_chan->shdma_chan.id, | |
284 | sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar); | |
285 | /* Get the ld start address from ld_queue */ | |
286 | dmae_set_reg(sh_chan, &sh_desc->hw); | |
287 | dmae_start(sh_chan); | |
d8902adc NI |
288 | } |
289 | ||
ce3a1ab7 | 290 | static bool sh_dmae_channel_busy(struct shdma_chan *schan) |
d8902adc | 291 | { |
ce3a1ab7 GL |
292 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
293 | shdma_chan); | |
294 | return dmae_is_busy(sh_chan); | |
d8902adc NI |
295 | } |
296 | ||
ce3a1ab7 | 297 | static void sh_dmae_setup_xfer(struct shdma_chan *schan, |
c2cdb7e4 | 298 | int slave_id) |
cfefe997 | 299 | { |
ce3a1ab7 GL |
300 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
301 | shdma_chan); | |
cfefe997 | 302 | |
c2cdb7e4 | 303 | if (slave_id >= 0) { |
ce3a1ab7 | 304 | const struct sh_dmae_slave_config *cfg = |
ecf90fbb | 305 | sh_chan->config; |
cfefe997 | 306 | |
ce3a1ab7 GL |
307 | dmae_set_dmars(sh_chan, cfg->mid_rid); |
308 | dmae_set_chcr(sh_chan, cfg->chcr); | |
fc461857 | 309 | } else { |
ce3a1ab7 | 310 | dmae_init(sh_chan); |
fc461857 | 311 | } |
fc461857 GL |
312 | } |
313 | ||
67eacc15 GL |
314 | /* |
315 | * Find a slave channel configuration from the contoller list by either a slave | |
316 | * ID in the non-DT case, or by a MID/RID value in the DT case | |
317 | */ | |
ce3a1ab7 | 318 | static const struct sh_dmae_slave_config *dmae_find_slave( |
67eacc15 | 319 | struct sh_dmae_chan *sh_chan, int match) |
fc461857 | 320 | { |
ce3a1ab7 | 321 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
2833c47e | 322 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
ce3a1ab7 | 323 | const struct sh_dmae_slave_config *cfg; |
fc461857 GL |
324 | int i; |
325 | ||
67eacc15 GL |
326 | if (!sh_chan->shdma_chan.dev->of_node) { |
327 | if (match >= SH_DMA_SLAVE_NUMBER) | |
328 | return NULL; | |
fc461857 | 329 | |
67eacc15 GL |
330 | for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++) |
331 | if (cfg->slave_id == match) | |
332 | return cfg; | |
333 | } else { | |
334 | for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++) | |
335 | if (cfg->mid_rid == match) { | |
336 | sh_chan->shdma_chan.slave_id = cfg->slave_id; | |
337 | return cfg; | |
338 | } | |
339 | } | |
fc461857 GL |
340 | |
341 | return NULL; | |
342 | } | |
343 | ||
ce3a1ab7 | 344 | static int sh_dmae_set_slave(struct shdma_chan *schan, |
1ff8df4f | 345 | int slave_id, bool try) |
fc461857 | 346 | { |
ce3a1ab7 GL |
347 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
348 | shdma_chan); | |
c2cdb7e4 | 349 | const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id); |
ce3a1ab7 | 350 | if (!cfg) |
7c1119bd | 351 | return -ENXIO; |
c014906a | 352 | |
1ff8df4f GL |
353 | if (!try) |
354 | sh_chan->config = cfg; | |
c3635c78 LW |
355 | |
356 | return 0; | |
cfefe997 GL |
357 | } |
358 | ||
ce3a1ab7 | 359 | static void dmae_halt(struct sh_dmae_chan *sh_chan) |
d8902adc | 360 | { |
ce3a1ab7 GL |
361 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
362 | u32 chcr = chcr_read(sh_chan); | |
3542a113 | 363 | |
ce3a1ab7 GL |
364 | chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit); |
365 | chcr_write(sh_chan, chcr); | |
3542a113 GL |
366 | } |
367 | ||
ce3a1ab7 GL |
368 | static int sh_dmae_desc_setup(struct shdma_chan *schan, |
369 | struct shdma_desc *sdesc, | |
370 | dma_addr_t src, dma_addr_t dst, size_t *len) | |
3542a113 | 371 | { |
ce3a1ab7 GL |
372 | struct sh_dmae_desc *sh_desc = container_of(sdesc, |
373 | struct sh_dmae_desc, shdma_desc); | |
d8902adc | 374 | |
ce3a1ab7 GL |
375 | if (*len > schan->max_xfer_len) |
376 | *len = schan->max_xfer_len; | |
d8902adc | 377 | |
ce3a1ab7 GL |
378 | sh_desc->hw.sar = src; |
379 | sh_desc->hw.dar = dst; | |
380 | sh_desc->hw.tcr = *len; | |
d8902adc | 381 | |
ce3a1ab7 | 382 | return 0; |
d8902adc NI |
383 | } |
384 | ||
ce3a1ab7 | 385 | static void sh_dmae_halt(struct shdma_chan *schan) |
d8902adc | 386 | { |
ce3a1ab7 GL |
387 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
388 | shdma_chan); | |
389 | dmae_halt(sh_chan); | |
d8902adc NI |
390 | } |
391 | ||
ce3a1ab7 | 392 | static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq) |
d8902adc | 393 | { |
ce3a1ab7 GL |
394 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
395 | shdma_chan); | |
d8902adc | 396 | |
ce3a1ab7 GL |
397 | if (!(chcr_read(sh_chan) & CHCR_TE)) |
398 | return false; | |
d8902adc | 399 | |
ce3a1ab7 GL |
400 | /* DMA stop */ |
401 | dmae_halt(sh_chan); | |
2dc66667 | 402 | |
ce3a1ab7 | 403 | return true; |
d8902adc NI |
404 | } |
405 | ||
4f46f8ac GL |
406 | static size_t sh_dmae_get_partial(struct shdma_chan *schan, |
407 | struct shdma_desc *sdesc) | |
408 | { | |
409 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, | |
410 | shdma_chan); | |
411 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | |
412 | struct sh_dmae_desc, shdma_desc); | |
413 | return (sh_desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) << | |
414 | sh_chan->xmit_shift; | |
415 | } | |
416 | ||
2dc66667 GL |
417 | /* Called from error IRQ or NMI */ |
418 | static bool sh_dmae_reset(struct sh_dmae_device *shdev) | |
d8902adc | 419 | { |
ce3a1ab7 | 420 | bool ret; |
d8902adc | 421 | |
47a4dc26 | 422 | /* halt the dma controller */ |
027811b9 | 423 | sh_dmae_ctl_stop(shdev); |
47a4dc26 GL |
424 | |
425 | /* We cannot detect, which channel caused the error, have to reset all */ | |
ce3a1ab7 | 426 | ret = shdma_reset(&shdev->shdma_dev); |
03aa18f5 | 427 | |
027811b9 | 428 | sh_dmae_rst(shdev); |
47a4dc26 | 429 | |
ce3a1ab7 | 430 | return ret; |
03aa18f5 PM |
431 | } |
432 | ||
433 | static irqreturn_t sh_dmae_err(int irq, void *data) | |
434 | { | |
ff7690b4 YS |
435 | struct sh_dmae_device *shdev = data; |
436 | ||
2dc66667 | 437 | if (!(dmaor_read(shdev) & DMAOR_AE)) |
ff7690b4 | 438 | return IRQ_NONE; |
2dc66667 | 439 | |
ce3a1ab7 | 440 | sh_dmae_reset(shdev); |
2dc66667 | 441 | return IRQ_HANDLED; |
d8902adc | 442 | } |
d8902adc | 443 | |
ce3a1ab7 GL |
444 | static bool sh_dmae_desc_completed(struct shdma_chan *schan, |
445 | struct shdma_desc *sdesc) | |
d8902adc | 446 | { |
ce3a1ab7 GL |
447 | struct sh_dmae_chan *sh_chan = container_of(schan, |
448 | struct sh_dmae_chan, shdma_chan); | |
449 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | |
450 | struct sh_dmae_desc, shdma_desc); | |
d8902adc | 451 | u32 sar_buf = sh_dmae_readl(sh_chan, SAR); |
cfefe997 | 452 | u32 dar_buf = sh_dmae_readl(sh_chan, DAR); |
86d61b33 | 453 | |
ce3a1ab7 GL |
454 | return (sdesc->direction == DMA_DEV_TO_MEM && |
455 | (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) || | |
456 | (sdesc->direction != DMA_DEV_TO_MEM && | |
457 | (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf); | |
d8902adc NI |
458 | } |
459 | ||
03aa18f5 PM |
460 | static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev) |
461 | { | |
03aa18f5 PM |
462 | /* Fast path out if NMIF is not asserted for this controller */ |
463 | if ((dmaor_read(shdev) & DMAOR_NMIF) == 0) | |
464 | return false; | |
465 | ||
2dc66667 | 466 | return sh_dmae_reset(shdev); |
03aa18f5 PM |
467 | } |
468 | ||
469 | static int sh_dmae_nmi_handler(struct notifier_block *self, | |
470 | unsigned long cmd, void *data) | |
471 | { | |
472 | struct sh_dmae_device *shdev; | |
473 | int ret = NOTIFY_DONE; | |
474 | bool triggered; | |
475 | ||
476 | /* | |
477 | * Only concern ourselves with NMI events. | |
478 | * | |
479 | * Normally we would check the die chain value, but as this needs | |
480 | * to be architecture independent, check for NMI context instead. | |
481 | */ | |
482 | if (!in_nmi()) | |
483 | return NOTIFY_DONE; | |
484 | ||
485 | rcu_read_lock(); | |
486 | list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) { | |
487 | /* | |
488 | * Only stop if one of the controllers has NMIF asserted, | |
489 | * we do not want to interfere with regular address error | |
490 | * handling or NMI events that don't concern the DMACs. | |
491 | */ | |
492 | triggered = sh_dmae_nmi_notify(shdev); | |
493 | if (triggered == true) | |
494 | ret = NOTIFY_OK; | |
495 | } | |
496 | rcu_read_unlock(); | |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
501 | static struct notifier_block sh_dmae_nmi_notifier __read_mostly = { | |
502 | .notifier_call = sh_dmae_nmi_handler, | |
503 | ||
504 | /* Run before NMI debug handler and KGDB */ | |
505 | .priority = 1, | |
506 | }; | |
507 | ||
463a1f8b | 508 | static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, |
027811b9 | 509 | int irq, unsigned long flags) |
d8902adc | 510 | { |
5bac942d | 511 | const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id]; |
ce3a1ab7 GL |
512 | struct shdma_dev *sdev = &shdev->shdma_dev; |
513 | struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev); | |
514 | struct sh_dmae_chan *sh_chan; | |
515 | struct shdma_chan *schan; | |
516 | int err; | |
d8902adc | 517 | |
c1c63a14 GL |
518 | sh_chan = devm_kzalloc(sdev->dma_dev.dev, sizeof(struct sh_dmae_chan), |
519 | GFP_KERNEL); | |
ce3a1ab7 GL |
520 | if (!sh_chan) { |
521 | dev_err(sdev->dma_dev.dev, | |
86d61b33 | 522 | "No free memory for allocating dma channels!\n"); |
d8902adc NI |
523 | return -ENOMEM; |
524 | } | |
525 | ||
ce3a1ab7 GL |
526 | schan = &sh_chan->shdma_chan; |
527 | schan->max_xfer_len = SH_DMA_TCR_MAX + 1; | |
8b1935e6 | 528 | |
ce3a1ab7 | 529 | shdma_chan_probe(sdev, schan, id); |
d8902adc | 530 | |
115357e9 | 531 | sh_chan->base = shdev->chan_reg + chan_pdata->offset; |
d8902adc | 532 | |
ce3a1ab7 | 533 | /* set up channel irq */ |
027811b9 | 534 | if (pdev->id >= 0) |
ce3a1ab7 GL |
535 | snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id), |
536 | "sh-dmae%d.%d", pdev->id, id); | |
027811b9 | 537 | else |
ce3a1ab7 GL |
538 | snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id), |
539 | "sh-dma%d", id); | |
d8902adc | 540 | |
ce3a1ab7 | 541 | err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id); |
d8902adc | 542 | if (err) { |
ce3a1ab7 GL |
543 | dev_err(sdev->dma_dev.dev, |
544 | "DMA channel %d request_irq error %d\n", | |
545 | id, err); | |
d8902adc NI |
546 | goto err_no_irq; |
547 | } | |
548 | ||
ce3a1ab7 | 549 | shdev->chan[id] = sh_chan; |
d8902adc NI |
550 | return 0; |
551 | ||
552 | err_no_irq: | |
553 | /* remove from dmaengine device node */ | |
ce3a1ab7 | 554 | shdma_chan_remove(schan); |
d8902adc NI |
555 | return err; |
556 | } | |
557 | ||
558 | static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) | |
559 | { | |
ce3a1ab7 GL |
560 | struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev; |
561 | struct shdma_chan *schan; | |
d8902adc NI |
562 | int i; |
563 | ||
ce3a1ab7 | 564 | shdma_for_each_chan(schan, &shdev->shdma_dev, i) { |
ce3a1ab7 | 565 | BUG_ON(!schan); |
027811b9 | 566 | |
ce3a1ab7 | 567 | shdma_chan_remove(schan); |
ce3a1ab7 GL |
568 | } |
569 | dma_dev->chancnt = 0; | |
570 | } | |
571 | ||
572 | static void sh_dmae_shutdown(struct platform_device *pdev) | |
573 | { | |
574 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
575 | sh_dmae_ctl_stop(shdev); | |
576 | } | |
577 | ||
578 | static int sh_dmae_runtime_suspend(struct device *dev) | |
579 | { | |
580 | return 0; | |
581 | } | |
582 | ||
583 | static int sh_dmae_runtime_resume(struct device *dev) | |
584 | { | |
585 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
586 | ||
587 | return sh_dmae_rst(shdev); | |
588 | } | |
589 | ||
590 | #ifdef CONFIG_PM | |
591 | static int sh_dmae_suspend(struct device *dev) | |
592 | { | |
593 | return 0; | |
594 | } | |
595 | ||
596 | static int sh_dmae_resume(struct device *dev) | |
597 | { | |
598 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
599 | int i, ret; | |
600 | ||
601 | ret = sh_dmae_rst(shdev); | |
602 | if (ret < 0) | |
603 | dev_err(dev, "Failed to reset!\n"); | |
604 | ||
605 | for (i = 0; i < shdev->pdata->channel_num; i++) { | |
606 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
ce3a1ab7 GL |
607 | |
608 | if (!sh_chan->shdma_chan.desc_num) | |
609 | continue; | |
610 | ||
c2cdb7e4 | 611 | if (sh_chan->shdma_chan.slave_id >= 0) { |
ecf90fbb | 612 | const struct sh_dmae_slave_config *cfg = sh_chan->config; |
ce3a1ab7 GL |
613 | dmae_set_dmars(sh_chan, cfg->mid_rid); |
614 | dmae_set_chcr(sh_chan, cfg->chcr); | |
615 | } else { | |
616 | dmae_init(sh_chan); | |
d8902adc NI |
617 | } |
618 | } | |
ce3a1ab7 GL |
619 | |
620 | return 0; | |
d8902adc | 621 | } |
ce3a1ab7 GL |
622 | #else |
623 | #define sh_dmae_suspend NULL | |
624 | #define sh_dmae_resume NULL | |
625 | #endif | |
d8902adc | 626 | |
ce3a1ab7 GL |
627 | const struct dev_pm_ops sh_dmae_pm = { |
628 | .suspend = sh_dmae_suspend, | |
629 | .resume = sh_dmae_resume, | |
630 | .runtime_suspend = sh_dmae_runtime_suspend, | |
631 | .runtime_resume = sh_dmae_runtime_resume, | |
632 | }; | |
633 | ||
634 | static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan) | |
635 | { | |
ecf90fbb GL |
636 | struct sh_dmae_chan *sh_chan = container_of(schan, |
637 | struct sh_dmae_chan, shdma_chan); | |
ce3a1ab7 GL |
638 | |
639 | /* | |
ecf90fbb GL |
640 | * Implicit BUG_ON(!sh_chan->config) |
641 | * This is an exclusive slave DMA operation, may only be called after a | |
642 | * successful slave configuration. | |
ce3a1ab7 | 643 | */ |
ecf90fbb | 644 | return sh_chan->config->addr; |
ce3a1ab7 GL |
645 | } |
646 | ||
647 | static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i) | |
648 | { | |
649 | return &((struct sh_dmae_desc *)buf)[i].shdma_desc; | |
650 | } | |
651 | ||
652 | static const struct shdma_ops sh_dmae_shdma_ops = { | |
653 | .desc_completed = sh_dmae_desc_completed, | |
654 | .halt_channel = sh_dmae_halt, | |
655 | .channel_busy = sh_dmae_channel_busy, | |
656 | .slave_addr = sh_dmae_slave_addr, | |
657 | .desc_setup = sh_dmae_desc_setup, | |
658 | .set_slave = sh_dmae_set_slave, | |
659 | .setup_xfer = sh_dmae_setup_xfer, | |
660 | .start_xfer = sh_dmae_start_xfer, | |
661 | .embedded_desc = sh_dmae_embedded_desc, | |
662 | .chan_irq = sh_dmae_chan_irq, | |
4f46f8ac | 663 | .get_partial = sh_dmae_get_partial, |
ce3a1ab7 GL |
664 | }; |
665 | ||
463a1f8b | 666 | static int sh_dmae_probe(struct platform_device *pdev) |
d8902adc | 667 | { |
2833c47e | 668 | const struct sh_dmae_pdata *pdata = pdev->dev.platform_data; |
027811b9 | 669 | unsigned long irqflags = IRQF_DISABLED, |
ce3a1ab7 GL |
670 | chan_flag[SH_DMAE_MAX_CHANNELS] = {}; |
671 | int errirq, chan_irq[SH_DMAE_MAX_CHANNELS]; | |
300e5f97 | 672 | int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0; |
d8902adc | 673 | struct sh_dmae_device *shdev; |
ce3a1ab7 | 674 | struct dma_device *dma_dev; |
027811b9 | 675 | struct resource *chan, *dmars, *errirq_res, *chanirq_res; |
d8902adc | 676 | |
56adf7e8 | 677 | /* get platform data */ |
027811b9 | 678 | if (!pdata || !pdata->channel_num) |
56adf7e8 DW |
679 | return -ENODEV; |
680 | ||
027811b9 | 681 | chan = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
26fc02ab | 682 | /* DMARS area is optional */ |
027811b9 GL |
683 | dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
684 | /* | |
685 | * IRQ resources: | |
686 | * 1. there always must be at least one IRQ IO-resource. On SH4 it is | |
687 | * the error IRQ, in which case it is the only IRQ in this resource: | |
688 | * start == end. If it is the only IRQ resource, all channels also | |
689 | * use the same IRQ. | |
690 | * 2. DMA channel IRQ resources can be specified one per resource or in | |
691 | * ranges (start != end) | |
692 | * 3. iff all events (channels and, optionally, error) on this | |
693 | * controller use the same IRQ, only one IRQ resource can be | |
694 | * specified, otherwise there must be one IRQ per channel, even if | |
695 | * some of them are equal | |
696 | * 4. if all IRQs on this controller are equal or if some specific IRQs | |
697 | * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be | |
698 | * requested with the IRQF_SHARED flag | |
699 | */ | |
700 | errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
701 | if (!chan || !errirq_res) | |
702 | return -ENODEV; | |
703 | ||
c1c63a14 GL |
704 | shdev = devm_kzalloc(&pdev->dev, sizeof(struct sh_dmae_device), |
705 | GFP_KERNEL); | |
d8902adc | 706 | if (!shdev) { |
027811b9 | 707 | dev_err(&pdev->dev, "Not enough memory\n"); |
c1c63a14 | 708 | return -ENOMEM; |
027811b9 GL |
709 | } |
710 | ||
ce3a1ab7 GL |
711 | dma_dev = &shdev->shdma_dev.dma_dev; |
712 | ||
c1c63a14 GL |
713 | shdev->chan_reg = devm_ioremap_resource(&pdev->dev, chan); |
714 | if (IS_ERR(shdev->chan_reg)) | |
715 | return PTR_ERR(shdev->chan_reg); | |
027811b9 | 716 | if (dmars) { |
c1c63a14 GL |
717 | shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars); |
718 | if (IS_ERR(shdev->dmars)) | |
719 | return PTR_ERR(shdev->dmars); | |
d8902adc NI |
720 | } |
721 | ||
ce3a1ab7 GL |
722 | if (!pdata->slave_only) |
723 | dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); | |
724 | if (pdata->slave && pdata->slave_num) | |
725 | dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); | |
726 | ||
727 | /* Default transfer size of 32 bytes requires 32-byte alignment */ | |
728 | dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE; | |
729 | ||
730 | shdev->shdma_dev.ops = &sh_dmae_shdma_ops; | |
731 | shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc); | |
732 | err = shdma_init(&pdev->dev, &shdev->shdma_dev, | |
733 | pdata->channel_num); | |
734 | if (err < 0) | |
735 | goto eshdma; | |
736 | ||
d8902adc | 737 | /* platform data */ |
fa74326c | 738 | shdev->pdata = pdata; |
d8902adc | 739 | |
5899a723 KM |
740 | if (pdata->chcr_offset) |
741 | shdev->chcr_offset = pdata->chcr_offset; | |
742 | else | |
743 | shdev->chcr_offset = CHCR; | |
744 | ||
67c6269e KM |
745 | if (pdata->chcr_ie_bit) |
746 | shdev->chcr_ie_bit = pdata->chcr_ie_bit; | |
747 | else | |
748 | shdev->chcr_ie_bit = CHCR_IE; | |
749 | ||
5c2de444 PM |
750 | platform_set_drvdata(pdev, shdev); |
751 | ||
20f2a3b5 | 752 | pm_runtime_enable(&pdev->dev); |
ce3a1ab7 GL |
753 | err = pm_runtime_get_sync(&pdev->dev); |
754 | if (err < 0) | |
755 | dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err); | |
20f2a3b5 | 756 | |
31705e21 | 757 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 758 | list_add_tail_rcu(&shdev->node, &sh_dmae_devices); |
31705e21 | 759 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 760 | |
2dc66667 | 761 | /* reset dma controller - only needed as a test */ |
027811b9 | 762 | err = sh_dmae_rst(shdev); |
d8902adc NI |
763 | if (err) |
764 | goto rst_err; | |
765 | ||
927a7c9c | 766 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
027811b9 GL |
767 | chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); |
768 | ||
769 | if (!chanirq_res) | |
770 | chanirq_res = errirq_res; | |
771 | else | |
772 | irqres++; | |
773 | ||
774 | if (chanirq_res == errirq_res || | |
775 | (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE) | |
d8902adc | 776 | irqflags = IRQF_SHARED; |
027811b9 GL |
777 | |
778 | errirq = errirq_res->start; | |
779 | ||
c1c63a14 GL |
780 | err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err, irqflags, |
781 | "DMAC Address Error", shdev); | |
027811b9 GL |
782 | if (err) { |
783 | dev_err(&pdev->dev, | |
784 | "DMA failed requesting irq #%d, error %d\n", | |
785 | errirq, err); | |
786 | goto eirq_err; | |
d8902adc NI |
787 | } |
788 | ||
027811b9 GL |
789 | #else |
790 | chanirq_res = errirq_res; | |
927a7c9c | 791 | #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */ |
027811b9 GL |
792 | |
793 | if (chanirq_res->start == chanirq_res->end && | |
794 | !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { | |
795 | /* Special case - all multiplexed */ | |
796 | for (; irq_cnt < pdata->channel_num; irq_cnt++) { | |
ce3a1ab7 | 797 | if (irq_cnt < SH_DMAE_MAX_CHANNELS) { |
300e5f97 MD |
798 | chan_irq[irq_cnt] = chanirq_res->start; |
799 | chan_flag[irq_cnt] = IRQF_SHARED; | |
800 | } else { | |
801 | irq_cap = 1; | |
802 | break; | |
803 | } | |
d8902adc | 804 | } |
027811b9 GL |
805 | } else { |
806 | do { | |
807 | for (i = chanirq_res->start; i <= chanirq_res->end; i++) { | |
ce3a1ab7 | 808 | if (irq_cnt >= SH_DMAE_MAX_CHANNELS) { |
dcee0bb7 MD |
809 | irq_cap = 1; |
810 | break; | |
811 | } | |
812 | ||
027811b9 GL |
813 | if ((errirq_res->flags & IORESOURCE_BITS) == |
814 | IORESOURCE_IRQ_SHAREABLE) | |
815 | chan_flag[irq_cnt] = IRQF_SHARED; | |
816 | else | |
817 | chan_flag[irq_cnt] = IRQF_DISABLED; | |
818 | dev_dbg(&pdev->dev, | |
819 | "Found IRQ %d for channel %d\n", | |
820 | i, irq_cnt); | |
821 | chan_irq[irq_cnt++] = i; | |
300e5f97 MD |
822 | } |
823 | ||
ce3a1ab7 | 824 | if (irq_cnt >= SH_DMAE_MAX_CHANNELS) |
300e5f97 | 825 | break; |
dcee0bb7 | 826 | |
027811b9 GL |
827 | chanirq_res = platform_get_resource(pdev, |
828 | IORESOURCE_IRQ, ++irqres); | |
829 | } while (irq_cnt < pdata->channel_num && chanirq_res); | |
d8902adc | 830 | } |
027811b9 | 831 | |
d8902adc | 832 | /* Create DMA Channel */ |
300e5f97 | 833 | for (i = 0; i < irq_cnt; i++) { |
027811b9 | 834 | err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]); |
d8902adc NI |
835 | if (err) |
836 | goto chan_probe_err; | |
837 | } | |
838 | ||
300e5f97 MD |
839 | if (irq_cap) |
840 | dev_notice(&pdev->dev, "Attempting to register %d DMA " | |
841 | "channels when a maximum of %d are supported.\n", | |
ce3a1ab7 | 842 | pdata->channel_num, SH_DMAE_MAX_CHANNELS); |
300e5f97 | 843 | |
20f2a3b5 GL |
844 | pm_runtime_put(&pdev->dev); |
845 | ||
ce3a1ab7 GL |
846 | err = dma_async_device_register(&shdev->shdma_dev.dma_dev); |
847 | if (err < 0) | |
848 | goto edmadevreg; | |
d8902adc NI |
849 | |
850 | return err; | |
851 | ||
ce3a1ab7 GL |
852 | edmadevreg: |
853 | pm_runtime_get(&pdev->dev); | |
854 | ||
d8902adc NI |
855 | chan_probe_err: |
856 | sh_dmae_chan_remove(shdev); | |
300e5f97 | 857 | |
927a7c9c | 858 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
d8902adc | 859 | eirq_err: |
027811b9 | 860 | #endif |
d8902adc | 861 | rst_err: |
31705e21 | 862 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 863 | list_del_rcu(&shdev->node); |
31705e21 | 864 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 865 | |
20f2a3b5 | 866 | pm_runtime_put(&pdev->dev); |
467017b8 GL |
867 | pm_runtime_disable(&pdev->dev); |
868 | ||
ce3a1ab7 GL |
869 | platform_set_drvdata(pdev, NULL); |
870 | shdma_cleanup(&shdev->shdma_dev); | |
871 | eshdma: | |
31705e21 | 872 | synchronize_rcu(); |
d8902adc | 873 | |
d8902adc NI |
874 | return err; |
875 | } | |
876 | ||
4bf27b8b | 877 | static int sh_dmae_remove(struct platform_device *pdev) |
d8902adc NI |
878 | { |
879 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
ce3a1ab7 | 880 | struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev; |
027811b9 GL |
881 | struct resource *res; |
882 | int errirq = platform_get_irq(pdev, 0); | |
d8902adc | 883 | |
ce3a1ab7 | 884 | dma_async_device_unregister(dma_dev); |
d8902adc | 885 | |
027811b9 GL |
886 | if (errirq > 0) |
887 | free_irq(errirq, shdev); | |
d8902adc | 888 | |
31705e21 | 889 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 890 | list_del_rcu(&shdev->node); |
31705e21 | 891 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 892 | |
20f2a3b5 GL |
893 | pm_runtime_disable(&pdev->dev); |
894 | ||
ce3a1ab7 GL |
895 | sh_dmae_chan_remove(shdev); |
896 | shdma_cleanup(&shdev->shdma_dev); | |
897 | ||
5c2de444 PM |
898 | platform_set_drvdata(pdev, NULL); |
899 | ||
31705e21 | 900 | synchronize_rcu(); |
027811b9 | 901 | |
d8902adc NI |
902 | return 0; |
903 | } | |
904 | ||
67eacc15 GL |
905 | static const struct of_device_id sh_dmae_of_match[] = { |
906 | { .compatible = "renesas,shdma", }, | |
907 | { } | |
908 | }; | |
909 | MODULE_DEVICE_TABLE(of, sh_dmae_of_match); | |
910 | ||
d8902adc | 911 | static struct platform_driver sh_dmae_driver = { |
ce3a1ab7 | 912 | .driver = { |
7a5c106a | 913 | .owner = THIS_MODULE, |
467017b8 | 914 | .pm = &sh_dmae_pm, |
ce3a1ab7 | 915 | .name = SH_DMAE_DRV_NAME, |
67eacc15 | 916 | .of_match_table = sh_dmae_of_match, |
d8902adc | 917 | }, |
a7d6e3ec | 918 | .remove = sh_dmae_remove, |
ce3a1ab7 | 919 | .shutdown = sh_dmae_shutdown, |
d8902adc NI |
920 | }; |
921 | ||
922 | static int __init sh_dmae_init(void) | |
923 | { | |
661382fe GL |
924 | /* Wire up NMI handling */ |
925 | int err = register_die_notifier(&sh_dmae_nmi_notifier); | |
926 | if (err) | |
927 | return err; | |
928 | ||
d8902adc NI |
929 | return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe); |
930 | } | |
931 | module_init(sh_dmae_init); | |
932 | ||
933 | static void __exit sh_dmae_exit(void) | |
934 | { | |
935 | platform_driver_unregister(&sh_dmae_driver); | |
661382fe GL |
936 | |
937 | unregister_die_notifier(&sh_dmae_nmi_notifier); | |
d8902adc NI |
938 | } |
939 | module_exit(sh_dmae_exit); | |
940 | ||
941 | MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>"); | |
942 | MODULE_DESCRIPTION("Renesas SH DMA Engine driver"); | |
943 | MODULE_LICENSE("GPL"); | |
ce3a1ab7 | 944 | MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME); |