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Commit | Line | Data |
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d8902adc NI |
1 | /* |
2 | * Renesas SuperH DMA Engine support | |
3 | * | |
4 | * base is drivers/dma/flsdma.c | |
5 | * | |
ce3a1ab7 | 6 | * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
d8902adc NI |
7 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> |
8 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | |
9 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * - DMA of SuperH does not have Hardware DMA chain mode. | |
17 | * - MAX DMA size is 16MB. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/module.h> | |
5a0e3ad6 | 23 | #include <linux/slab.h> |
d8902adc NI |
24 | #include <linux/interrupt.h> |
25 | #include <linux/dmaengine.h> | |
26 | #include <linux/delay.h> | |
d8902adc | 27 | #include <linux/platform_device.h> |
20f2a3b5 | 28 | #include <linux/pm_runtime.h> |
b2623a61 | 29 | #include <linux/sh_dma.h> |
03aa18f5 PM |
30 | #include <linux/notifier.h> |
31 | #include <linux/kdebug.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <linux/rculist.h> | |
d2ebfb33 | 34 | |
e95be94b | 35 | #include "../dmaengine.h" |
d8902adc NI |
36 | #include "shdma.h" |
37 | ||
ce3a1ab7 | 38 | #define SH_DMAE_DRV_NAME "sh-dma-engine" |
d8902adc | 39 | |
8b1935e6 GL |
40 | /* Default MEMCPY transfer size = 2^2 = 4 bytes */ |
41 | #define LOG2_DEFAULT_XFER_SIZE 2 | |
ce3a1ab7 GL |
42 | #define SH_DMA_SLAVE_NUMBER 256 |
43 | #define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1) | |
d8902adc | 44 | |
03aa18f5 PM |
45 | /* |
46 | * Used for write-side mutual exclusion for the global device list, | |
2dc66667 | 47 | * read-side synchronization by way of RCU, and per-controller data. |
03aa18f5 PM |
48 | */ |
49 | static DEFINE_SPINLOCK(sh_dmae_lock); | |
50 | static LIST_HEAD(sh_dmae_devices); | |
51 | ||
c11b46c3 GL |
52 | static void chclr_write(struct sh_dmae_chan *sh_dc, u32 data) |
53 | { | |
54 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | |
55 | ||
56 | __raw_writel(data, shdev->chan_reg + | |
ce3a1ab7 | 57 | shdev->pdata->channel[sh_dc->shdma_chan.id].chclr_offset); |
c11b46c3 | 58 | } |
3542a113 | 59 | |
d8902adc NI |
60 | static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) |
61 | { | |
027811b9 | 62 | __raw_writel(data, sh_dc->base + reg / sizeof(u32)); |
d8902adc NI |
63 | } |
64 | ||
65 | static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) | |
66 | { | |
027811b9 GL |
67 | return __raw_readl(sh_dc->base + reg / sizeof(u32)); |
68 | } | |
69 | ||
70 | static u16 dmaor_read(struct sh_dmae_device *shdev) | |
71 | { | |
e76c3af8 KM |
72 | u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32); |
73 | ||
74 | if (shdev->pdata->dmaor_is_32bit) | |
75 | return __raw_readl(addr); | |
76 | else | |
77 | return __raw_readw(addr); | |
027811b9 GL |
78 | } |
79 | ||
80 | static void dmaor_write(struct sh_dmae_device *shdev, u16 data) | |
81 | { | |
e76c3af8 KM |
82 | u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32); |
83 | ||
84 | if (shdev->pdata->dmaor_is_32bit) | |
85 | __raw_writel(data, addr); | |
86 | else | |
87 | __raw_writew(data, addr); | |
d8902adc NI |
88 | } |
89 | ||
5899a723 KM |
90 | static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data) |
91 | { | |
92 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | |
93 | ||
94 | __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32)); | |
95 | } | |
96 | ||
97 | static u32 chcr_read(struct sh_dmae_chan *sh_dc) | |
98 | { | |
99 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | |
100 | ||
101 | return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32)); | |
d8902adc NI |
102 | } |
103 | ||
d8902adc NI |
104 | /* |
105 | * Reset DMA controller | |
106 | * | |
107 | * SH7780 has two DMAOR register | |
108 | */ | |
027811b9 | 109 | static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev) |
d8902adc | 110 | { |
2dc66667 GL |
111 | unsigned short dmaor; |
112 | unsigned long flags; | |
113 | ||
114 | spin_lock_irqsave(&sh_dmae_lock, flags); | |
d8902adc | 115 | |
2dc66667 | 116 | dmaor = dmaor_read(shdev); |
027811b9 | 117 | dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME)); |
2dc66667 GL |
118 | |
119 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
d8902adc NI |
120 | } |
121 | ||
027811b9 | 122 | static int sh_dmae_rst(struct sh_dmae_device *shdev) |
d8902adc NI |
123 | { |
124 | unsigned short dmaor; | |
2dc66667 | 125 | unsigned long flags; |
d8902adc | 126 | |
2dc66667 | 127 | spin_lock_irqsave(&sh_dmae_lock, flags); |
d8902adc | 128 | |
2dc66667 GL |
129 | dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME); |
130 | ||
c11b46c3 GL |
131 | if (shdev->pdata->chclr_present) { |
132 | int i; | |
133 | for (i = 0; i < shdev->pdata->channel_num; i++) { | |
134 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
135 | if (sh_chan) | |
136 | chclr_write(sh_chan, 0); | |
137 | } | |
138 | } | |
139 | ||
2dc66667 GL |
140 | dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init); |
141 | ||
142 | dmaor = dmaor_read(shdev); | |
143 | ||
144 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
145 | ||
146 | if (dmaor & (DMAOR_AE | DMAOR_NMIF)) { | |
ce3a1ab7 | 147 | dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n"); |
2dc66667 | 148 | return -EIO; |
d8902adc | 149 | } |
c11b46c3 | 150 | if (shdev->pdata->dmaor_init & ~dmaor) |
ce3a1ab7 | 151 | dev_warn(shdev->shdma_dev.dma_dev.dev, |
c11b46c3 GL |
152 | "DMAOR=0x%x hasn't latched the initial value 0x%x.\n", |
153 | dmaor, shdev->pdata->dmaor_init); | |
d8902adc NI |
154 | return 0; |
155 | } | |
156 | ||
fc461857 | 157 | static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) |
d8902adc | 158 | { |
5899a723 | 159 | u32 chcr = chcr_read(sh_chan); |
fc461857 GL |
160 | |
161 | if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) | |
162 | return true; /* working */ | |
163 | ||
164 | return false; /* waiting */ | |
d8902adc NI |
165 | } |
166 | ||
8b1935e6 | 167 | static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) |
d8902adc | 168 | { |
c4e0dd78 | 169 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
8b1935e6 GL |
170 | struct sh_dmae_pdata *pdata = shdev->pdata; |
171 | int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | | |
172 | ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); | |
173 | ||
174 | if (cnt >= pdata->ts_shift_num) | |
175 | cnt = 0; | |
623b4ac4 | 176 | |
8b1935e6 GL |
177 | return pdata->ts_shift[cnt]; |
178 | } | |
179 | ||
180 | static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) | |
181 | { | |
c4e0dd78 | 182 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
8b1935e6 GL |
183 | struct sh_dmae_pdata *pdata = shdev->pdata; |
184 | int i; | |
185 | ||
186 | for (i = 0; i < pdata->ts_shift_num; i++) | |
187 | if (pdata->ts_shift[i] == l2size) | |
188 | break; | |
189 | ||
190 | if (i == pdata->ts_shift_num) | |
191 | i = 0; | |
192 | ||
193 | return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) | | |
194 | ((i << pdata->ts_high_shift) & pdata->ts_high_mask); | |
d8902adc NI |
195 | } |
196 | ||
3542a113 | 197 | static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) |
d8902adc | 198 | { |
3542a113 GL |
199 | sh_dmae_writel(sh_chan, hw->sar, SAR); |
200 | sh_dmae_writel(sh_chan, hw->dar, DAR); | |
cfefe997 | 201 | sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); |
d8902adc NI |
202 | } |
203 | ||
204 | static void dmae_start(struct sh_dmae_chan *sh_chan) | |
205 | { | |
67c6269e | 206 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
5899a723 | 207 | u32 chcr = chcr_read(sh_chan); |
d8902adc | 208 | |
260bf2c5 KM |
209 | if (shdev->pdata->needs_tend_set) |
210 | sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND); | |
211 | ||
67c6269e | 212 | chcr |= CHCR_DE | shdev->chcr_ie_bit; |
5899a723 | 213 | chcr_write(sh_chan, chcr & ~CHCR_TE); |
d8902adc NI |
214 | } |
215 | ||
cfefe997 GL |
216 | static void dmae_init(struct sh_dmae_chan *sh_chan) |
217 | { | |
8b1935e6 GL |
218 | /* |
219 | * Default configuration for dual address memory-memory transfer. | |
220 | * 0x400 represents auto-request. | |
221 | */ | |
222 | u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, | |
223 | LOG2_DEFAULT_XFER_SIZE); | |
224 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); | |
5899a723 | 225 | chcr_write(sh_chan, chcr); |
cfefe997 GL |
226 | } |
227 | ||
d8902adc NI |
228 | static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) |
229 | { | |
2dc66667 | 230 | /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */ |
fc461857 GL |
231 | if (dmae_is_busy(sh_chan)) |
232 | return -EBUSY; | |
d8902adc | 233 | |
8b1935e6 | 234 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); |
5899a723 | 235 | chcr_write(sh_chan, val); |
cfefe997 | 236 | |
d8902adc NI |
237 | return 0; |
238 | } | |
239 | ||
d8902adc NI |
240 | static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) |
241 | { | |
c4e0dd78 | 242 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
027811b9 | 243 | struct sh_dmae_pdata *pdata = shdev->pdata; |
ce3a1ab7 | 244 | const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id]; |
26fc02ab | 245 | u16 __iomem *addr = shdev->dmars; |
090b9180 | 246 | unsigned int shift = chan_pdata->dmars_bit; |
fc461857 GL |
247 | |
248 | if (dmae_is_busy(sh_chan)) | |
249 | return -EBUSY; | |
d8902adc | 250 | |
260bf2c5 KM |
251 | if (pdata->no_dmars) |
252 | return 0; | |
253 | ||
26fc02ab MD |
254 | /* in the case of a missing DMARS resource use first memory window */ |
255 | if (!addr) | |
256 | addr = (u16 __iomem *)shdev->chan_reg; | |
257 | addr += chan_pdata->dmars / sizeof(u16); | |
258 | ||
027811b9 GL |
259 | __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), |
260 | addr); | |
d8902adc NI |
261 | |
262 | return 0; | |
263 | } | |
264 | ||
ce3a1ab7 GL |
265 | static void sh_dmae_start_xfer(struct shdma_chan *schan, |
266 | struct shdma_desc *sdesc) | |
d8902adc | 267 | { |
ce3a1ab7 GL |
268 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
269 | shdma_chan); | |
270 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | |
271 | struct sh_dmae_desc, shdma_desc); | |
272 | dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n", | |
273 | sdesc->async_tx.cookie, sh_chan->shdma_chan.id, | |
274 | sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar); | |
275 | /* Get the ld start address from ld_queue */ | |
276 | dmae_set_reg(sh_chan, &sh_desc->hw); | |
277 | dmae_start(sh_chan); | |
d8902adc NI |
278 | } |
279 | ||
ce3a1ab7 | 280 | static bool sh_dmae_channel_busy(struct shdma_chan *schan) |
d8902adc | 281 | { |
ce3a1ab7 GL |
282 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
283 | shdma_chan); | |
284 | return dmae_is_busy(sh_chan); | |
d8902adc NI |
285 | } |
286 | ||
ce3a1ab7 | 287 | static void sh_dmae_setup_xfer(struct shdma_chan *schan, |
c2cdb7e4 | 288 | int slave_id) |
cfefe997 | 289 | { |
ce3a1ab7 GL |
290 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
291 | shdma_chan); | |
cfefe997 | 292 | |
c2cdb7e4 | 293 | if (slave_id >= 0) { |
ce3a1ab7 | 294 | const struct sh_dmae_slave_config *cfg = |
ecf90fbb | 295 | sh_chan->config; |
cfefe997 | 296 | |
ce3a1ab7 GL |
297 | dmae_set_dmars(sh_chan, cfg->mid_rid); |
298 | dmae_set_chcr(sh_chan, cfg->chcr); | |
fc461857 | 299 | } else { |
ce3a1ab7 | 300 | dmae_init(sh_chan); |
fc461857 | 301 | } |
fc461857 GL |
302 | } |
303 | ||
67eacc15 GL |
304 | /* |
305 | * Find a slave channel configuration from the contoller list by either a slave | |
306 | * ID in the non-DT case, or by a MID/RID value in the DT case | |
307 | */ | |
ce3a1ab7 | 308 | static const struct sh_dmae_slave_config *dmae_find_slave( |
67eacc15 | 309 | struct sh_dmae_chan *sh_chan, int match) |
fc461857 | 310 | { |
ce3a1ab7 GL |
311 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
312 | struct sh_dmae_pdata *pdata = shdev->pdata; | |
313 | const struct sh_dmae_slave_config *cfg; | |
fc461857 GL |
314 | int i; |
315 | ||
67eacc15 GL |
316 | if (!sh_chan->shdma_chan.dev->of_node) { |
317 | if (match >= SH_DMA_SLAVE_NUMBER) | |
318 | return NULL; | |
fc461857 | 319 | |
67eacc15 GL |
320 | for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++) |
321 | if (cfg->slave_id == match) | |
322 | return cfg; | |
323 | } else { | |
324 | for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++) | |
325 | if (cfg->mid_rid == match) { | |
326 | sh_chan->shdma_chan.slave_id = cfg->slave_id; | |
327 | return cfg; | |
328 | } | |
329 | } | |
fc461857 GL |
330 | |
331 | return NULL; | |
332 | } | |
333 | ||
ce3a1ab7 | 334 | static int sh_dmae_set_slave(struct shdma_chan *schan, |
1ff8df4f | 335 | int slave_id, bool try) |
fc461857 | 336 | { |
ce3a1ab7 GL |
337 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
338 | shdma_chan); | |
c2cdb7e4 | 339 | const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id); |
ce3a1ab7 | 340 | if (!cfg) |
7c1119bd | 341 | return -ENXIO; |
c014906a | 342 | |
1ff8df4f GL |
343 | if (!try) |
344 | sh_chan->config = cfg; | |
c3635c78 LW |
345 | |
346 | return 0; | |
cfefe997 GL |
347 | } |
348 | ||
ce3a1ab7 | 349 | static void dmae_halt(struct sh_dmae_chan *sh_chan) |
d8902adc | 350 | { |
ce3a1ab7 GL |
351 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
352 | u32 chcr = chcr_read(sh_chan); | |
3542a113 | 353 | |
ce3a1ab7 GL |
354 | chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit); |
355 | chcr_write(sh_chan, chcr); | |
3542a113 GL |
356 | } |
357 | ||
ce3a1ab7 GL |
358 | static int sh_dmae_desc_setup(struct shdma_chan *schan, |
359 | struct shdma_desc *sdesc, | |
360 | dma_addr_t src, dma_addr_t dst, size_t *len) | |
3542a113 | 361 | { |
ce3a1ab7 GL |
362 | struct sh_dmae_desc *sh_desc = container_of(sdesc, |
363 | struct sh_dmae_desc, shdma_desc); | |
d8902adc | 364 | |
ce3a1ab7 GL |
365 | if (*len > schan->max_xfer_len) |
366 | *len = schan->max_xfer_len; | |
d8902adc | 367 | |
ce3a1ab7 GL |
368 | sh_desc->hw.sar = src; |
369 | sh_desc->hw.dar = dst; | |
370 | sh_desc->hw.tcr = *len; | |
d8902adc | 371 | |
ce3a1ab7 | 372 | return 0; |
d8902adc NI |
373 | } |
374 | ||
ce3a1ab7 | 375 | static void sh_dmae_halt(struct shdma_chan *schan) |
d8902adc | 376 | { |
ce3a1ab7 GL |
377 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
378 | shdma_chan); | |
379 | dmae_halt(sh_chan); | |
d8902adc NI |
380 | } |
381 | ||
ce3a1ab7 | 382 | static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq) |
d8902adc | 383 | { |
ce3a1ab7 GL |
384 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
385 | shdma_chan); | |
d8902adc | 386 | |
ce3a1ab7 GL |
387 | if (!(chcr_read(sh_chan) & CHCR_TE)) |
388 | return false; | |
d8902adc | 389 | |
ce3a1ab7 GL |
390 | /* DMA stop */ |
391 | dmae_halt(sh_chan); | |
2dc66667 | 392 | |
ce3a1ab7 | 393 | return true; |
d8902adc NI |
394 | } |
395 | ||
4f46f8ac GL |
396 | static size_t sh_dmae_get_partial(struct shdma_chan *schan, |
397 | struct shdma_desc *sdesc) | |
398 | { | |
399 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, | |
400 | shdma_chan); | |
401 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | |
402 | struct sh_dmae_desc, shdma_desc); | |
3c4d9276 KM |
403 | return sh_desc->hw.tcr - |
404 | (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift); | |
4f46f8ac GL |
405 | } |
406 | ||
2dc66667 GL |
407 | /* Called from error IRQ or NMI */ |
408 | static bool sh_dmae_reset(struct sh_dmae_device *shdev) | |
d8902adc | 409 | { |
ce3a1ab7 | 410 | bool ret; |
d8902adc | 411 | |
47a4dc26 | 412 | /* halt the dma controller */ |
027811b9 | 413 | sh_dmae_ctl_stop(shdev); |
47a4dc26 GL |
414 | |
415 | /* We cannot detect, which channel caused the error, have to reset all */ | |
ce3a1ab7 | 416 | ret = shdma_reset(&shdev->shdma_dev); |
03aa18f5 | 417 | |
027811b9 | 418 | sh_dmae_rst(shdev); |
47a4dc26 | 419 | |
ce3a1ab7 | 420 | return ret; |
03aa18f5 PM |
421 | } |
422 | ||
423 | static irqreturn_t sh_dmae_err(int irq, void *data) | |
424 | { | |
ff7690b4 YS |
425 | struct sh_dmae_device *shdev = data; |
426 | ||
2dc66667 | 427 | if (!(dmaor_read(shdev) & DMAOR_AE)) |
ff7690b4 | 428 | return IRQ_NONE; |
2dc66667 | 429 | |
ce3a1ab7 | 430 | sh_dmae_reset(shdev); |
2dc66667 | 431 | return IRQ_HANDLED; |
d8902adc | 432 | } |
d8902adc | 433 | |
ce3a1ab7 GL |
434 | static bool sh_dmae_desc_completed(struct shdma_chan *schan, |
435 | struct shdma_desc *sdesc) | |
d8902adc | 436 | { |
ce3a1ab7 GL |
437 | struct sh_dmae_chan *sh_chan = container_of(schan, |
438 | struct sh_dmae_chan, shdma_chan); | |
439 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | |
440 | struct sh_dmae_desc, shdma_desc); | |
d8902adc | 441 | u32 sar_buf = sh_dmae_readl(sh_chan, SAR); |
cfefe997 | 442 | u32 dar_buf = sh_dmae_readl(sh_chan, DAR); |
86d61b33 | 443 | |
ce3a1ab7 GL |
444 | return (sdesc->direction == DMA_DEV_TO_MEM && |
445 | (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) || | |
446 | (sdesc->direction != DMA_DEV_TO_MEM && | |
447 | (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf); | |
d8902adc NI |
448 | } |
449 | ||
03aa18f5 PM |
450 | static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev) |
451 | { | |
03aa18f5 PM |
452 | /* Fast path out if NMIF is not asserted for this controller */ |
453 | if ((dmaor_read(shdev) & DMAOR_NMIF) == 0) | |
454 | return false; | |
455 | ||
2dc66667 | 456 | return sh_dmae_reset(shdev); |
03aa18f5 PM |
457 | } |
458 | ||
459 | static int sh_dmae_nmi_handler(struct notifier_block *self, | |
460 | unsigned long cmd, void *data) | |
461 | { | |
462 | struct sh_dmae_device *shdev; | |
463 | int ret = NOTIFY_DONE; | |
464 | bool triggered; | |
465 | ||
466 | /* | |
467 | * Only concern ourselves with NMI events. | |
468 | * | |
469 | * Normally we would check the die chain value, but as this needs | |
470 | * to be architecture independent, check for NMI context instead. | |
471 | */ | |
472 | if (!in_nmi()) | |
473 | return NOTIFY_DONE; | |
474 | ||
475 | rcu_read_lock(); | |
476 | list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) { | |
477 | /* | |
478 | * Only stop if one of the controllers has NMIF asserted, | |
479 | * we do not want to interfere with regular address error | |
480 | * handling or NMI events that don't concern the DMACs. | |
481 | */ | |
482 | triggered = sh_dmae_nmi_notify(shdev); | |
483 | if (triggered == true) | |
484 | ret = NOTIFY_OK; | |
485 | } | |
486 | rcu_read_unlock(); | |
487 | ||
488 | return ret; | |
489 | } | |
490 | ||
491 | static struct notifier_block sh_dmae_nmi_notifier __read_mostly = { | |
492 | .notifier_call = sh_dmae_nmi_handler, | |
493 | ||
494 | /* Run before NMI debug handler and KGDB */ | |
495 | .priority = 1, | |
496 | }; | |
497 | ||
463a1f8b | 498 | static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, |
027811b9 | 499 | int irq, unsigned long flags) |
d8902adc | 500 | { |
5bac942d | 501 | const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id]; |
ce3a1ab7 GL |
502 | struct shdma_dev *sdev = &shdev->shdma_dev; |
503 | struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev); | |
504 | struct sh_dmae_chan *sh_chan; | |
505 | struct shdma_chan *schan; | |
506 | int err; | |
d8902adc | 507 | |
ce3a1ab7 GL |
508 | sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL); |
509 | if (!sh_chan) { | |
510 | dev_err(sdev->dma_dev.dev, | |
86d61b33 | 511 | "No free memory for allocating dma channels!\n"); |
d8902adc NI |
512 | return -ENOMEM; |
513 | } | |
514 | ||
ce3a1ab7 GL |
515 | schan = &sh_chan->shdma_chan; |
516 | schan->max_xfer_len = SH_DMA_TCR_MAX + 1; | |
8b1935e6 | 517 | |
ce3a1ab7 | 518 | shdma_chan_probe(sdev, schan, id); |
d8902adc | 519 | |
ce3a1ab7 | 520 | sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32); |
d8902adc | 521 | |
ce3a1ab7 | 522 | /* set up channel irq */ |
027811b9 | 523 | if (pdev->id >= 0) |
ce3a1ab7 GL |
524 | snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id), |
525 | "sh-dmae%d.%d", pdev->id, id); | |
027811b9 | 526 | else |
ce3a1ab7 GL |
527 | snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id), |
528 | "sh-dma%d", id); | |
d8902adc | 529 | |
ce3a1ab7 | 530 | err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id); |
d8902adc | 531 | if (err) { |
ce3a1ab7 GL |
532 | dev_err(sdev->dma_dev.dev, |
533 | "DMA channel %d request_irq error %d\n", | |
534 | id, err); | |
d8902adc NI |
535 | goto err_no_irq; |
536 | } | |
537 | ||
ce3a1ab7 | 538 | shdev->chan[id] = sh_chan; |
d8902adc NI |
539 | return 0; |
540 | ||
541 | err_no_irq: | |
542 | /* remove from dmaengine device node */ | |
ce3a1ab7 GL |
543 | shdma_chan_remove(schan); |
544 | kfree(sh_chan); | |
d8902adc NI |
545 | return err; |
546 | } | |
547 | ||
548 | static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) | |
549 | { | |
ce3a1ab7 GL |
550 | struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev; |
551 | struct shdma_chan *schan; | |
d8902adc NI |
552 | int i; |
553 | ||
ce3a1ab7 GL |
554 | shdma_for_each_chan(schan, &shdev->shdma_dev, i) { |
555 | struct sh_dmae_chan *sh_chan = container_of(schan, | |
556 | struct sh_dmae_chan, shdma_chan); | |
557 | BUG_ON(!schan); | |
027811b9 | 558 | |
ce3a1ab7 | 559 | shdma_free_irq(&sh_chan->shdma_chan); |
d8902adc | 560 | |
ce3a1ab7 GL |
561 | shdma_chan_remove(schan); |
562 | kfree(sh_chan); | |
563 | } | |
564 | dma_dev->chancnt = 0; | |
565 | } | |
566 | ||
567 | static void sh_dmae_shutdown(struct platform_device *pdev) | |
568 | { | |
569 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
570 | sh_dmae_ctl_stop(shdev); | |
571 | } | |
572 | ||
573 | static int sh_dmae_runtime_suspend(struct device *dev) | |
574 | { | |
575 | return 0; | |
576 | } | |
577 | ||
578 | static int sh_dmae_runtime_resume(struct device *dev) | |
579 | { | |
580 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
581 | ||
582 | return sh_dmae_rst(shdev); | |
583 | } | |
584 | ||
585 | #ifdef CONFIG_PM | |
586 | static int sh_dmae_suspend(struct device *dev) | |
587 | { | |
588 | return 0; | |
589 | } | |
590 | ||
591 | static int sh_dmae_resume(struct device *dev) | |
592 | { | |
593 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
594 | int i, ret; | |
595 | ||
596 | ret = sh_dmae_rst(shdev); | |
597 | if (ret < 0) | |
598 | dev_err(dev, "Failed to reset!\n"); | |
599 | ||
600 | for (i = 0; i < shdev->pdata->channel_num; i++) { | |
601 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
ce3a1ab7 GL |
602 | |
603 | if (!sh_chan->shdma_chan.desc_num) | |
604 | continue; | |
605 | ||
c2cdb7e4 | 606 | if (sh_chan->shdma_chan.slave_id >= 0) { |
ecf90fbb | 607 | const struct sh_dmae_slave_config *cfg = sh_chan->config; |
ce3a1ab7 GL |
608 | dmae_set_dmars(sh_chan, cfg->mid_rid); |
609 | dmae_set_chcr(sh_chan, cfg->chcr); | |
610 | } else { | |
611 | dmae_init(sh_chan); | |
d8902adc NI |
612 | } |
613 | } | |
ce3a1ab7 GL |
614 | |
615 | return 0; | |
d8902adc | 616 | } |
ce3a1ab7 GL |
617 | #else |
618 | #define sh_dmae_suspend NULL | |
619 | #define sh_dmae_resume NULL | |
620 | #endif | |
d8902adc | 621 | |
ce3a1ab7 GL |
622 | const struct dev_pm_ops sh_dmae_pm = { |
623 | .suspend = sh_dmae_suspend, | |
624 | .resume = sh_dmae_resume, | |
625 | .runtime_suspend = sh_dmae_runtime_suspend, | |
626 | .runtime_resume = sh_dmae_runtime_resume, | |
627 | }; | |
628 | ||
629 | static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan) | |
630 | { | |
ecf90fbb GL |
631 | struct sh_dmae_chan *sh_chan = container_of(schan, |
632 | struct sh_dmae_chan, shdma_chan); | |
ce3a1ab7 GL |
633 | |
634 | /* | |
ecf90fbb GL |
635 | * Implicit BUG_ON(!sh_chan->config) |
636 | * This is an exclusive slave DMA operation, may only be called after a | |
637 | * successful slave configuration. | |
ce3a1ab7 | 638 | */ |
ecf90fbb | 639 | return sh_chan->config->addr; |
ce3a1ab7 GL |
640 | } |
641 | ||
642 | static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i) | |
643 | { | |
644 | return &((struct sh_dmae_desc *)buf)[i].shdma_desc; | |
645 | } | |
646 | ||
647 | static const struct shdma_ops sh_dmae_shdma_ops = { | |
648 | .desc_completed = sh_dmae_desc_completed, | |
649 | .halt_channel = sh_dmae_halt, | |
650 | .channel_busy = sh_dmae_channel_busy, | |
651 | .slave_addr = sh_dmae_slave_addr, | |
652 | .desc_setup = sh_dmae_desc_setup, | |
653 | .set_slave = sh_dmae_set_slave, | |
654 | .setup_xfer = sh_dmae_setup_xfer, | |
655 | .start_xfer = sh_dmae_start_xfer, | |
656 | .embedded_desc = sh_dmae_embedded_desc, | |
657 | .chan_irq = sh_dmae_chan_irq, | |
4f46f8ac | 658 | .get_partial = sh_dmae_get_partial, |
ce3a1ab7 GL |
659 | }; |
660 | ||
463a1f8b | 661 | static int sh_dmae_probe(struct platform_device *pdev) |
d8902adc | 662 | { |
027811b9 GL |
663 | struct sh_dmae_pdata *pdata = pdev->dev.platform_data; |
664 | unsigned long irqflags = IRQF_DISABLED, | |
ce3a1ab7 GL |
665 | chan_flag[SH_DMAE_MAX_CHANNELS] = {}; |
666 | int errirq, chan_irq[SH_DMAE_MAX_CHANNELS]; | |
300e5f97 | 667 | int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0; |
d8902adc | 668 | struct sh_dmae_device *shdev; |
ce3a1ab7 | 669 | struct dma_device *dma_dev; |
027811b9 | 670 | struct resource *chan, *dmars, *errirq_res, *chanirq_res; |
d8902adc | 671 | |
56adf7e8 | 672 | /* get platform data */ |
027811b9 | 673 | if (!pdata || !pdata->channel_num) |
56adf7e8 DW |
674 | return -ENODEV; |
675 | ||
027811b9 | 676 | chan = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
26fc02ab | 677 | /* DMARS area is optional */ |
027811b9 GL |
678 | dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
679 | /* | |
680 | * IRQ resources: | |
681 | * 1. there always must be at least one IRQ IO-resource. On SH4 it is | |
682 | * the error IRQ, in which case it is the only IRQ in this resource: | |
683 | * start == end. If it is the only IRQ resource, all channels also | |
684 | * use the same IRQ. | |
685 | * 2. DMA channel IRQ resources can be specified one per resource or in | |
686 | * ranges (start != end) | |
687 | * 3. iff all events (channels and, optionally, error) on this | |
688 | * controller use the same IRQ, only one IRQ resource can be | |
689 | * specified, otherwise there must be one IRQ per channel, even if | |
690 | * some of them are equal | |
691 | * 4. if all IRQs on this controller are equal or if some specific IRQs | |
692 | * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be | |
693 | * requested with the IRQF_SHARED flag | |
694 | */ | |
695 | errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
696 | if (!chan || !errirq_res) | |
697 | return -ENODEV; | |
698 | ||
699 | if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) { | |
700 | dev_err(&pdev->dev, "DMAC register region already claimed\n"); | |
701 | return -EBUSY; | |
702 | } | |
703 | ||
704 | if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) { | |
705 | dev_err(&pdev->dev, "DMAC DMARS region already claimed\n"); | |
706 | err = -EBUSY; | |
707 | goto ermrdmars; | |
708 | } | |
709 | ||
710 | err = -ENOMEM; | |
d8902adc NI |
711 | shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL); |
712 | if (!shdev) { | |
027811b9 GL |
713 | dev_err(&pdev->dev, "Not enough memory\n"); |
714 | goto ealloc; | |
715 | } | |
716 | ||
ce3a1ab7 GL |
717 | dma_dev = &shdev->shdma_dev.dma_dev; |
718 | ||
027811b9 GL |
719 | shdev->chan_reg = ioremap(chan->start, resource_size(chan)); |
720 | if (!shdev->chan_reg) | |
721 | goto emapchan; | |
722 | if (dmars) { | |
723 | shdev->dmars = ioremap(dmars->start, resource_size(dmars)); | |
724 | if (!shdev->dmars) | |
725 | goto emapdmars; | |
d8902adc NI |
726 | } |
727 | ||
ce3a1ab7 GL |
728 | if (!pdata->slave_only) |
729 | dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); | |
730 | if (pdata->slave && pdata->slave_num) | |
731 | dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); | |
732 | ||
733 | /* Default transfer size of 32 bytes requires 32-byte alignment */ | |
734 | dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE; | |
735 | ||
736 | shdev->shdma_dev.ops = &sh_dmae_shdma_ops; | |
737 | shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc); | |
738 | err = shdma_init(&pdev->dev, &shdev->shdma_dev, | |
739 | pdata->channel_num); | |
740 | if (err < 0) | |
741 | goto eshdma; | |
742 | ||
d8902adc | 743 | /* platform data */ |
fa74326c | 744 | shdev->pdata = pdata; |
d8902adc | 745 | |
5899a723 KM |
746 | if (pdata->chcr_offset) |
747 | shdev->chcr_offset = pdata->chcr_offset; | |
748 | else | |
749 | shdev->chcr_offset = CHCR; | |
750 | ||
67c6269e KM |
751 | if (pdata->chcr_ie_bit) |
752 | shdev->chcr_ie_bit = pdata->chcr_ie_bit; | |
753 | else | |
754 | shdev->chcr_ie_bit = CHCR_IE; | |
755 | ||
5c2de444 PM |
756 | platform_set_drvdata(pdev, shdev); |
757 | ||
20f2a3b5 | 758 | pm_runtime_enable(&pdev->dev); |
ce3a1ab7 GL |
759 | err = pm_runtime_get_sync(&pdev->dev); |
760 | if (err < 0) | |
761 | dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err); | |
20f2a3b5 | 762 | |
31705e21 | 763 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 764 | list_add_tail_rcu(&shdev->node, &sh_dmae_devices); |
31705e21 | 765 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 766 | |
2dc66667 | 767 | /* reset dma controller - only needed as a test */ |
027811b9 | 768 | err = sh_dmae_rst(shdev); |
d8902adc NI |
769 | if (err) |
770 | goto rst_err; | |
771 | ||
927a7c9c | 772 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
027811b9 GL |
773 | chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); |
774 | ||
775 | if (!chanirq_res) | |
776 | chanirq_res = errirq_res; | |
777 | else | |
778 | irqres++; | |
779 | ||
780 | if (chanirq_res == errirq_res || | |
781 | (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE) | |
d8902adc | 782 | irqflags = IRQF_SHARED; |
027811b9 GL |
783 | |
784 | errirq = errirq_res->start; | |
785 | ||
786 | err = request_irq(errirq, sh_dmae_err, irqflags, | |
787 | "DMAC Address Error", shdev); | |
788 | if (err) { | |
789 | dev_err(&pdev->dev, | |
790 | "DMA failed requesting irq #%d, error %d\n", | |
791 | errirq, err); | |
792 | goto eirq_err; | |
d8902adc NI |
793 | } |
794 | ||
027811b9 GL |
795 | #else |
796 | chanirq_res = errirq_res; | |
927a7c9c | 797 | #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */ |
027811b9 GL |
798 | |
799 | if (chanirq_res->start == chanirq_res->end && | |
800 | !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { | |
801 | /* Special case - all multiplexed */ | |
802 | for (; irq_cnt < pdata->channel_num; irq_cnt++) { | |
ce3a1ab7 | 803 | if (irq_cnt < SH_DMAE_MAX_CHANNELS) { |
300e5f97 MD |
804 | chan_irq[irq_cnt] = chanirq_res->start; |
805 | chan_flag[irq_cnt] = IRQF_SHARED; | |
806 | } else { | |
807 | irq_cap = 1; | |
808 | break; | |
809 | } | |
d8902adc | 810 | } |
027811b9 GL |
811 | } else { |
812 | do { | |
813 | for (i = chanirq_res->start; i <= chanirq_res->end; i++) { | |
ce3a1ab7 | 814 | if (irq_cnt >= SH_DMAE_MAX_CHANNELS) { |
dcee0bb7 MD |
815 | irq_cap = 1; |
816 | break; | |
817 | } | |
818 | ||
027811b9 GL |
819 | if ((errirq_res->flags & IORESOURCE_BITS) == |
820 | IORESOURCE_IRQ_SHAREABLE) | |
821 | chan_flag[irq_cnt] = IRQF_SHARED; | |
822 | else | |
823 | chan_flag[irq_cnt] = IRQF_DISABLED; | |
824 | dev_dbg(&pdev->dev, | |
825 | "Found IRQ %d for channel %d\n", | |
826 | i, irq_cnt); | |
827 | chan_irq[irq_cnt++] = i; | |
300e5f97 MD |
828 | } |
829 | ||
ce3a1ab7 | 830 | if (irq_cnt >= SH_DMAE_MAX_CHANNELS) |
300e5f97 | 831 | break; |
dcee0bb7 | 832 | |
027811b9 GL |
833 | chanirq_res = platform_get_resource(pdev, |
834 | IORESOURCE_IRQ, ++irqres); | |
835 | } while (irq_cnt < pdata->channel_num && chanirq_res); | |
d8902adc | 836 | } |
027811b9 | 837 | |
d8902adc | 838 | /* Create DMA Channel */ |
300e5f97 | 839 | for (i = 0; i < irq_cnt; i++) { |
027811b9 | 840 | err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]); |
d8902adc NI |
841 | if (err) |
842 | goto chan_probe_err; | |
843 | } | |
844 | ||
300e5f97 MD |
845 | if (irq_cap) |
846 | dev_notice(&pdev->dev, "Attempting to register %d DMA " | |
847 | "channels when a maximum of %d are supported.\n", | |
ce3a1ab7 | 848 | pdata->channel_num, SH_DMAE_MAX_CHANNELS); |
300e5f97 | 849 | |
20f2a3b5 GL |
850 | pm_runtime_put(&pdev->dev); |
851 | ||
ce3a1ab7 GL |
852 | err = dma_async_device_register(&shdev->shdma_dev.dma_dev); |
853 | if (err < 0) | |
854 | goto edmadevreg; | |
d8902adc NI |
855 | |
856 | return err; | |
857 | ||
ce3a1ab7 GL |
858 | edmadevreg: |
859 | pm_runtime_get(&pdev->dev); | |
860 | ||
d8902adc NI |
861 | chan_probe_err: |
862 | sh_dmae_chan_remove(shdev); | |
300e5f97 | 863 | |
927a7c9c | 864 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
027811b9 | 865 | free_irq(errirq, shdev); |
d8902adc | 866 | eirq_err: |
027811b9 | 867 | #endif |
d8902adc | 868 | rst_err: |
31705e21 | 869 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 870 | list_del_rcu(&shdev->node); |
31705e21 | 871 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 872 | |
20f2a3b5 | 873 | pm_runtime_put(&pdev->dev); |
467017b8 GL |
874 | pm_runtime_disable(&pdev->dev); |
875 | ||
ce3a1ab7 GL |
876 | platform_set_drvdata(pdev, NULL); |
877 | shdma_cleanup(&shdev->shdma_dev); | |
878 | eshdma: | |
027811b9 GL |
879 | if (dmars) |
880 | iounmap(shdev->dmars); | |
881 | emapdmars: | |
882 | iounmap(shdev->chan_reg); | |
31705e21 | 883 | synchronize_rcu(); |
027811b9 | 884 | emapchan: |
d8902adc | 885 | kfree(shdev); |
027811b9 GL |
886 | ealloc: |
887 | if (dmars) | |
888 | release_mem_region(dmars->start, resource_size(dmars)); | |
889 | ermrdmars: | |
890 | release_mem_region(chan->start, resource_size(chan)); | |
d8902adc | 891 | |
d8902adc NI |
892 | return err; |
893 | } | |
894 | ||
4bf27b8b | 895 | static int sh_dmae_remove(struct platform_device *pdev) |
d8902adc NI |
896 | { |
897 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
ce3a1ab7 | 898 | struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev; |
027811b9 GL |
899 | struct resource *res; |
900 | int errirq = platform_get_irq(pdev, 0); | |
d8902adc | 901 | |
ce3a1ab7 | 902 | dma_async_device_unregister(dma_dev); |
d8902adc | 903 | |
027811b9 GL |
904 | if (errirq > 0) |
905 | free_irq(errirq, shdev); | |
d8902adc | 906 | |
31705e21 | 907 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 908 | list_del_rcu(&shdev->node); |
31705e21 | 909 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 910 | |
20f2a3b5 GL |
911 | pm_runtime_disable(&pdev->dev); |
912 | ||
ce3a1ab7 GL |
913 | sh_dmae_chan_remove(shdev); |
914 | shdma_cleanup(&shdev->shdma_dev); | |
915 | ||
027811b9 GL |
916 | if (shdev->dmars) |
917 | iounmap(shdev->dmars); | |
918 | iounmap(shdev->chan_reg); | |
919 | ||
5c2de444 PM |
920 | platform_set_drvdata(pdev, NULL); |
921 | ||
31705e21 | 922 | synchronize_rcu(); |
d8902adc NI |
923 | kfree(shdev); |
924 | ||
027811b9 GL |
925 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
926 | if (res) | |
927 | release_mem_region(res->start, resource_size(res)); | |
928 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
929 | if (res) | |
930 | release_mem_region(res->start, resource_size(res)); | |
931 | ||
d8902adc NI |
932 | return 0; |
933 | } | |
934 | ||
67eacc15 GL |
935 | static const struct of_device_id sh_dmae_of_match[] = { |
936 | { .compatible = "renesas,shdma", }, | |
937 | { } | |
938 | }; | |
939 | MODULE_DEVICE_TABLE(of, sh_dmae_of_match); | |
940 | ||
d8902adc | 941 | static struct platform_driver sh_dmae_driver = { |
ce3a1ab7 | 942 | .driver = { |
7a5c106a | 943 | .owner = THIS_MODULE, |
467017b8 | 944 | .pm = &sh_dmae_pm, |
ce3a1ab7 | 945 | .name = SH_DMAE_DRV_NAME, |
67eacc15 | 946 | .of_match_table = sh_dmae_of_match, |
d8902adc | 947 | }, |
a7d6e3ec | 948 | .remove = sh_dmae_remove, |
ce3a1ab7 | 949 | .shutdown = sh_dmae_shutdown, |
d8902adc NI |
950 | }; |
951 | ||
952 | static int __init sh_dmae_init(void) | |
953 | { | |
661382fe GL |
954 | /* Wire up NMI handling */ |
955 | int err = register_die_notifier(&sh_dmae_nmi_notifier); | |
956 | if (err) | |
957 | return err; | |
958 | ||
d8902adc NI |
959 | return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe); |
960 | } | |
961 | module_init(sh_dmae_init); | |
962 | ||
963 | static void __exit sh_dmae_exit(void) | |
964 | { | |
965 | platform_driver_unregister(&sh_dmae_driver); | |
661382fe GL |
966 | |
967 | unregister_die_notifier(&sh_dmae_nmi_notifier); | |
d8902adc NI |
968 | } |
969 | module_exit(sh_dmae_exit); | |
970 | ||
971 | MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>"); | |
972 | MODULE_DESCRIPTION("Renesas SH DMA Engine driver"); | |
973 | MODULE_LICENSE("GPL"); | |
ce3a1ab7 | 974 | MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME); |