projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| d8902adc NI |
1 | /* |
| 2 | * Renesas SuperH DMA Engine support | |
| 3 | * | |
| 4 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
| 5 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | |
| 6 | * | |
| 7 | * This is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License as published by | |
| 9 | * the Free Software Foundation; either version 2 of the License, or | |
| 10 | * (at your option) any later version. | |
| 11 | * | |
| 12 | */ | |
| 13 | #ifndef __DMA_SHDMA_H | |
| 14 | #define __DMA_SHDMA_H | |
| 15 | ||
| ecf90fbb | 16 | #include <linux/sh_dma.h> |
| ce3a1ab7 | 17 | #include <linux/shdma-base.h> |
| d8902adc | 18 | #include <linux/dmaengine.h> |
| 3542a113 GL |
19 | #include <linux/interrupt.h> |
| 20 | #include <linux/list.h> | |
| d8902adc | 21 | |
| ce3a1ab7 GL |
22 | #define SH_DMAE_MAX_CHANNELS 20 |
| 23 | #define SH_DMAE_TCR_MAX 0x00FFFFFF /* 16MB */ | |
| d8902adc | 24 | |
| 3542a113 GL |
25 | struct device; |
| 26 | ||
| d8902adc | 27 | struct sh_dmae_chan { |
| ce3a1ab7 | 28 | struct shdma_chan shdma_chan; |
| ecf90fbb | 29 | const struct sh_dmae_slave_config *config; /* Slave DMA configuration */ |
| cfefe997 | 30 | int xmit_shift; /* log_2(bytes_per_xfer) */ |
| 027811b9 | 31 | u32 __iomem *base; |
| 86d61b33 | 32 | char dev_id[16]; /* unique name per DMAC of channel */ |
| 467017b8 | 33 | int pm_error; |
| d8902adc NI |
34 | }; |
| 35 | ||
| 36 | struct sh_dmae_device { | |
| ce3a1ab7 GL |
37 | struct shdma_dev shdma_dev; |
| 38 | struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS]; | |
| 027811b9 | 39 | struct sh_dmae_pdata *pdata; |
| 03aa18f5 | 40 | struct list_head node; |
| 027811b9 GL |
41 | u32 __iomem *chan_reg; |
| 42 | u16 __iomem *dmars; | |
| 5899a723 | 43 | unsigned int chcr_offset; |
| 67c6269e | 44 | u32 chcr_ie_bit; |
| d8902adc NI |
45 | }; |
| 46 | ||
| ce3a1ab7 GL |
47 | struct sh_dmae_regs { |
| 48 | u32 sar; /* SAR / source address */ | |
| 49 | u32 dar; /* DAR / destination address */ | |
| 50 | u32 tcr; /* TCR / transfer count */ | |
| 51 | }; | |
| 52 | ||
| 53 | struct sh_dmae_desc { | |
| 54 | struct sh_dmae_regs hw; | |
| 55 | struct shdma_desc shdma_desc; | |
| 56 | }; | |
| 57 | ||
| 58 | #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan) | |
| d8902adc NI |
59 | #define to_sh_desc(lh) container_of(lh, struct sh_desc, node) |
| 60 | #define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx) | |
| ce3a1ab7 GL |
61 | #define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\ |
| 62 | struct sh_dmae_device, shdma_dev.dma_dev) | |
| d8902adc NI |
63 | |
| 64 | #endif /* __DMA_SHDMA_H */ |