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Commit | Line | Data |
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d8902adc NI |
1 | /* |
2 | * Renesas SuperH DMA Engine support | |
3 | * | |
4 | * base is drivers/dma/flsdma.c | |
5 | * | |
6 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
7 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | |
8 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
9 | * | |
10 | * This is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * - DMA of SuperH does not have Hardware DMA chain mode. | |
16 | * - MAX DMA size is 16MB. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/dmaengine.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/dma-mapping.h> | |
d8902adc NI |
26 | #include <linux/platform_device.h> |
27 | #include <cpu/dma.h> | |
28 | #include <asm/dma-sh.h> | |
29 | #include "shdma.h" | |
30 | ||
31 | /* DMA descriptor control */ | |
3542a113 GL |
32 | enum sh_dmae_desc_status { |
33 | DESC_IDLE, | |
34 | DESC_PREPARED, | |
35 | DESC_SUBMITTED, | |
36 | DESC_COMPLETED, /* completed, have to call callback */ | |
37 | DESC_WAITING, /* callback called, waiting for ack / re-submit */ | |
38 | }; | |
d8902adc NI |
39 | |
40 | #define NR_DESCS_PER_CHANNEL 32 | |
41 | /* | |
42 | * Define the default configuration for dual address memory-memory transfer. | |
43 | * The 0x400 value represents auto-request, external->external. | |
44 | * | |
45 | * And this driver set 4byte burst mode. | |
46 | * If you want to change mode, you need to change RS_DEFAULT of value. | |
47 | * (ex 1byte burst mode -> (RS_DUAL & ~TS_32) | |
48 | */ | |
49 | #define RS_DEFAULT (RS_DUAL) | |
50 | ||
cfefe997 GL |
51 | /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */ |
52 | static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)]; | |
53 | ||
3542a113 GL |
54 | static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all); |
55 | ||
d8902adc NI |
56 | static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) |
57 | { | |
027811b9 | 58 | __raw_writel(data, sh_dc->base + reg / sizeof(u32)); |
d8902adc NI |
59 | } |
60 | ||
61 | static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) | |
62 | { | |
027811b9 GL |
63 | return __raw_readl(sh_dc->base + reg / sizeof(u32)); |
64 | } | |
65 | ||
66 | static u16 dmaor_read(struct sh_dmae_device *shdev) | |
67 | { | |
68 | return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32)); | |
69 | } | |
70 | ||
71 | static void dmaor_write(struct sh_dmae_device *shdev, u16 data) | |
72 | { | |
73 | __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32)); | |
d8902adc NI |
74 | } |
75 | ||
d8902adc NI |
76 | /* |
77 | * Reset DMA controller | |
78 | * | |
79 | * SH7780 has two DMAOR register | |
80 | */ | |
027811b9 | 81 | static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev) |
d8902adc | 82 | { |
027811b9 | 83 | unsigned short dmaor = dmaor_read(shdev); |
d8902adc | 84 | |
027811b9 | 85 | dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME)); |
d8902adc NI |
86 | } |
87 | ||
027811b9 | 88 | static int sh_dmae_rst(struct sh_dmae_device *shdev) |
d8902adc NI |
89 | { |
90 | unsigned short dmaor; | |
91 | ||
027811b9 GL |
92 | sh_dmae_ctl_stop(shdev); |
93 | dmaor = dmaor_read(shdev) | DMAOR_INIT; | |
d8902adc | 94 | |
027811b9 GL |
95 | dmaor_write(shdev, dmaor); |
96 | if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) { | |
47a4dc26 | 97 | pr_warning("dma-sh: Can't initialize DMAOR.\n"); |
d8902adc NI |
98 | return -EINVAL; |
99 | } | |
100 | return 0; | |
101 | } | |
102 | ||
fc461857 | 103 | static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) |
d8902adc NI |
104 | { |
105 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
fc461857 GL |
106 | |
107 | if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) | |
108 | return true; /* working */ | |
109 | ||
110 | return false; /* waiting */ | |
d8902adc NI |
111 | } |
112 | ||
623b4ac4 | 113 | static unsigned int ts_shift[] = TS_SHIFT; |
cfefe997 | 114 | static inline unsigned int calc_xmit_shift(u32 chcr) |
d8902adc | 115 | { |
623b4ac4 GL |
116 | int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) | |
117 | ((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT); | |
118 | ||
119 | return ts_shift[cnt]; | |
d8902adc NI |
120 | } |
121 | ||
3542a113 | 122 | static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) |
d8902adc | 123 | { |
3542a113 GL |
124 | sh_dmae_writel(sh_chan, hw->sar, SAR); |
125 | sh_dmae_writel(sh_chan, hw->dar, DAR); | |
cfefe997 | 126 | sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); |
d8902adc NI |
127 | } |
128 | ||
129 | static void dmae_start(struct sh_dmae_chan *sh_chan) | |
130 | { | |
131 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
132 | ||
86d61b33 | 133 | chcr |= CHCR_DE | CHCR_IE; |
cfefe997 | 134 | sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR); |
d8902adc NI |
135 | } |
136 | ||
137 | static void dmae_halt(struct sh_dmae_chan *sh_chan) | |
138 | { | |
139 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
140 | ||
141 | chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); | |
142 | sh_dmae_writel(sh_chan, chcr, CHCR); | |
143 | } | |
144 | ||
cfefe997 GL |
145 | static void dmae_init(struct sh_dmae_chan *sh_chan) |
146 | { | |
147 | u32 chcr = RS_DEFAULT; /* default is DUAL mode */ | |
148 | sh_chan->xmit_shift = calc_xmit_shift(chcr); | |
149 | sh_dmae_writel(sh_chan, chcr, CHCR); | |
150 | } | |
151 | ||
d8902adc NI |
152 | static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) |
153 | { | |
d8902adc | 154 | /* When DMA was working, can not set data to CHCR */ |
fc461857 GL |
155 | if (dmae_is_busy(sh_chan)) |
156 | return -EBUSY; | |
d8902adc | 157 | |
cfefe997 | 158 | sh_chan->xmit_shift = calc_xmit_shift(val); |
d8902adc | 159 | sh_dmae_writel(sh_chan, val, CHCR); |
cfefe997 | 160 | |
d8902adc NI |
161 | return 0; |
162 | } | |
163 | ||
d8902adc NI |
164 | static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) |
165 | { | |
027811b9 GL |
166 | struct sh_dmae_device *shdev = container_of(sh_chan->common.device, |
167 | struct sh_dmae_device, common); | |
168 | struct sh_dmae_pdata *pdata = shdev->pdata; | |
169 | struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id]; | |
170 | u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16); | |
171 | int shift = chan_pdata->dmars_bit; | |
fc461857 GL |
172 | |
173 | if (dmae_is_busy(sh_chan)) | |
174 | return -EBUSY; | |
d8902adc | 175 | |
027811b9 GL |
176 | __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), |
177 | addr); | |
d8902adc NI |
178 | |
179 | return 0; | |
180 | } | |
181 | ||
182 | static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx) | |
183 | { | |
3542a113 | 184 | struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c; |
d8902adc | 185 | struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan); |
3542a113 | 186 | dma_async_tx_callback callback = tx->callback; |
d8902adc NI |
187 | dma_cookie_t cookie; |
188 | ||
189 | spin_lock_bh(&sh_chan->desc_lock); | |
190 | ||
191 | cookie = sh_chan->common.cookie; | |
192 | cookie++; | |
193 | if (cookie < 0) | |
194 | cookie = 1; | |
195 | ||
3542a113 GL |
196 | sh_chan->common.cookie = cookie; |
197 | tx->cookie = cookie; | |
198 | ||
199 | /* Mark all chunks of this descriptor as submitted, move to the queue */ | |
200 | list_for_each_entry_safe(chunk, c, desc->node.prev, node) { | |
201 | /* | |
202 | * All chunks are on the global ld_free, so, we have to find | |
203 | * the end of the chain ourselves | |
204 | */ | |
205 | if (chunk != desc && (chunk->mark == DESC_IDLE || | |
206 | chunk->async_tx.cookie > 0 || | |
207 | chunk->async_tx.cookie == -EBUSY || | |
208 | &chunk->node == &sh_chan->ld_free)) | |
209 | break; | |
210 | chunk->mark = DESC_SUBMITTED; | |
211 | /* Callback goes to the last chunk */ | |
212 | chunk->async_tx.callback = NULL; | |
213 | chunk->cookie = cookie; | |
214 | list_move_tail(&chunk->node, &sh_chan->ld_queue); | |
215 | last = chunk; | |
216 | } | |
d8902adc | 217 | |
3542a113 GL |
218 | last->async_tx.callback = callback; |
219 | last->async_tx.callback_param = tx->callback_param; | |
220 | ||
221 | dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n", | |
222 | tx->cookie, &last->async_tx, sh_chan->id, | |
223 | desc->hw.sar, desc->hw.tcr, desc->hw.dar); | |
d8902adc NI |
224 | |
225 | spin_unlock_bh(&sh_chan->desc_lock); | |
226 | ||
227 | return cookie; | |
228 | } | |
229 | ||
3542a113 | 230 | /* Called with desc_lock held */ |
d8902adc NI |
231 | static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan) |
232 | { | |
3542a113 | 233 | struct sh_desc *desc; |
d8902adc | 234 | |
3542a113 GL |
235 | list_for_each_entry(desc, &sh_chan->ld_free, node) |
236 | if (desc->mark != DESC_PREPARED) { | |
237 | BUG_ON(desc->mark != DESC_IDLE); | |
d8902adc | 238 | list_del(&desc->node); |
3542a113 | 239 | return desc; |
d8902adc | 240 | } |
d8902adc | 241 | |
3542a113 | 242 | return NULL; |
d8902adc NI |
243 | } |
244 | ||
cfefe997 GL |
245 | static struct sh_dmae_slave_config *sh_dmae_find_slave( |
246 | struct sh_dmae_chan *sh_chan, enum sh_dmae_slave_chan_id slave_id) | |
247 | { | |
248 | struct dma_device *dma_dev = sh_chan->common.device; | |
249 | struct sh_dmae_device *shdev = container_of(dma_dev, | |
250 | struct sh_dmae_device, common); | |
027811b9 | 251 | struct sh_dmae_pdata *pdata = shdev->pdata; |
cfefe997 GL |
252 | int i; |
253 | ||
254 | if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER) | |
255 | return NULL; | |
256 | ||
027811b9 GL |
257 | for (i = 0; i < pdata->slave_num; i++) |
258 | if (pdata->slave[i].slave_id == slave_id) | |
259 | return pdata->slave + i; | |
cfefe997 GL |
260 | |
261 | return NULL; | |
262 | } | |
263 | ||
d8902adc NI |
264 | static int sh_dmae_alloc_chan_resources(struct dma_chan *chan) |
265 | { | |
266 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
267 | struct sh_desc *desc; | |
cfefe997 GL |
268 | struct sh_dmae_slave *param = chan->private; |
269 | ||
270 | /* | |
271 | * This relies on the guarantee from dmaengine that alloc_chan_resources | |
272 | * never runs concurrently with itself or free_chan_resources. | |
273 | */ | |
274 | if (param) { | |
275 | struct sh_dmae_slave_config *cfg; | |
276 | ||
277 | cfg = sh_dmae_find_slave(sh_chan, param->slave_id); | |
278 | if (!cfg) | |
279 | return -EINVAL; | |
280 | ||
281 | if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) | |
282 | return -EBUSY; | |
283 | ||
284 | param->config = cfg; | |
285 | ||
286 | dmae_set_dmars(sh_chan, cfg->mid_rid); | |
287 | dmae_set_chcr(sh_chan, cfg->chcr); | |
288 | } else { | |
289 | if ((sh_dmae_readl(sh_chan, CHCR) & 0x700) != 0x400) | |
290 | dmae_set_chcr(sh_chan, RS_DEFAULT); | |
291 | } | |
d8902adc NI |
292 | |
293 | spin_lock_bh(&sh_chan->desc_lock); | |
294 | while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
295 | spin_unlock_bh(&sh_chan->desc_lock); | |
296 | desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL); | |
297 | if (!desc) { | |
298 | spin_lock_bh(&sh_chan->desc_lock); | |
299 | break; | |
300 | } | |
301 | dma_async_tx_descriptor_init(&desc->async_tx, | |
302 | &sh_chan->common); | |
303 | desc->async_tx.tx_submit = sh_dmae_tx_submit; | |
3542a113 | 304 | desc->mark = DESC_IDLE; |
d8902adc NI |
305 | |
306 | spin_lock_bh(&sh_chan->desc_lock); | |
3542a113 | 307 | list_add(&desc->node, &sh_chan->ld_free); |
d8902adc NI |
308 | sh_chan->descs_allocated++; |
309 | } | |
310 | spin_unlock_bh(&sh_chan->desc_lock); | |
311 | ||
312 | return sh_chan->descs_allocated; | |
313 | } | |
314 | ||
315 | /* | |
316 | * sh_dma_free_chan_resources - Free all resources of the channel. | |
317 | */ | |
318 | static void sh_dmae_free_chan_resources(struct dma_chan *chan) | |
319 | { | |
320 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
321 | struct sh_desc *desc, *_desc; | |
322 | LIST_HEAD(list); | |
323 | ||
cfefe997 GL |
324 | dmae_halt(sh_chan); |
325 | ||
3542a113 GL |
326 | /* Prepared and not submitted descriptors can still be on the queue */ |
327 | if (!list_empty(&sh_chan->ld_queue)) | |
328 | sh_dmae_chan_ld_cleanup(sh_chan, true); | |
329 | ||
cfefe997 GL |
330 | if (chan->private) { |
331 | /* The caller is holding dma_list_mutex */ | |
332 | struct sh_dmae_slave *param = chan->private; | |
333 | clear_bit(param->slave_id, sh_dmae_slave_used); | |
334 | } | |
335 | ||
d8902adc NI |
336 | spin_lock_bh(&sh_chan->desc_lock); |
337 | ||
338 | list_splice_init(&sh_chan->ld_free, &list); | |
339 | sh_chan->descs_allocated = 0; | |
340 | ||
341 | spin_unlock_bh(&sh_chan->desc_lock); | |
342 | ||
343 | list_for_each_entry_safe(desc, _desc, &list, node) | |
344 | kfree(desc); | |
345 | } | |
346 | ||
cfefe997 | 347 | /** |
fc461857 GL |
348 | * sh_dmae_add_desc - get, set up and return one transfer descriptor |
349 | * @sh_chan: DMA channel | |
350 | * @flags: DMA transfer flags | |
351 | * @dest: destination DMA address, incremented when direction equals | |
352 | * DMA_FROM_DEVICE or DMA_BIDIRECTIONAL | |
353 | * @src: source DMA address, incremented when direction equals | |
354 | * DMA_TO_DEVICE or DMA_BIDIRECTIONAL | |
355 | * @len: DMA transfer length | |
356 | * @first: if NULL, set to the current descriptor and cookie set to -EBUSY | |
357 | * @direction: needed for slave DMA to decide which address to keep constant, | |
358 | * equals DMA_BIDIRECTIONAL for MEMCPY | |
359 | * Returns 0 or an error | |
360 | * Locks: called with desc_lock held | |
361 | */ | |
362 | static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan, | |
363 | unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len, | |
364 | struct sh_desc **first, enum dma_data_direction direction) | |
d8902adc | 365 | { |
fc461857 | 366 | struct sh_desc *new; |
d8902adc NI |
367 | size_t copy_size; |
368 | ||
fc461857 | 369 | if (!*len) |
d8902adc NI |
370 | return NULL; |
371 | ||
fc461857 GL |
372 | /* Allocate the link descriptor from the free list */ |
373 | new = sh_dmae_get_desc(sh_chan); | |
374 | if (!new) { | |
375 | dev_err(sh_chan->dev, "No free link descriptor available\n"); | |
d8902adc | 376 | return NULL; |
fc461857 | 377 | } |
d8902adc | 378 | |
fc461857 GL |
379 | copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1); |
380 | ||
381 | new->hw.sar = *src; | |
382 | new->hw.dar = *dest; | |
383 | new->hw.tcr = copy_size; | |
384 | ||
385 | if (!*first) { | |
386 | /* First desc */ | |
387 | new->async_tx.cookie = -EBUSY; | |
388 | *first = new; | |
389 | } else { | |
390 | /* Other desc - invisible to the user */ | |
391 | new->async_tx.cookie = -EINVAL; | |
392 | } | |
393 | ||
cfefe997 GL |
394 | dev_dbg(sh_chan->dev, |
395 | "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n", | |
fc461857 | 396 | copy_size, *len, *src, *dest, &new->async_tx, |
cfefe997 | 397 | new->async_tx.cookie, sh_chan->xmit_shift); |
fc461857 GL |
398 | |
399 | new->mark = DESC_PREPARED; | |
400 | new->async_tx.flags = flags; | |
cfefe997 | 401 | new->direction = direction; |
fc461857 GL |
402 | |
403 | *len -= copy_size; | |
404 | if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE) | |
405 | *src += copy_size; | |
406 | if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE) | |
407 | *dest += copy_size; | |
408 | ||
409 | return new; | |
410 | } | |
411 | ||
412 | /* | |
413 | * sh_dmae_prep_sg - prepare transfer descriptors from an SG list | |
414 | * | |
415 | * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also | |
416 | * converted to scatter-gather to guarantee consistent locking and a correct | |
417 | * list manipulation. For slave DMA direction carries the usual meaning, and, | |
418 | * logically, the SG list is RAM and the addr variable contains slave address, | |
419 | * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL | |
420 | * and the SG list contains only one element and points at the source buffer. | |
421 | */ | |
422 | static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan, | |
423 | struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr, | |
424 | enum dma_data_direction direction, unsigned long flags) | |
425 | { | |
426 | struct scatterlist *sg; | |
427 | struct sh_desc *first = NULL, *new = NULL /* compiler... */; | |
428 | LIST_HEAD(tx_list); | |
429 | int chunks = 0; | |
430 | int i; | |
431 | ||
432 | if (!sg_len) | |
433 | return NULL; | |
434 | ||
435 | for_each_sg(sgl, sg, sg_len, i) | |
436 | chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) / | |
437 | (SH_DMA_TCR_MAX + 1); | |
d8902adc | 438 | |
3542a113 GL |
439 | /* Have to lock the whole loop to protect against concurrent release */ |
440 | spin_lock_bh(&sh_chan->desc_lock); | |
441 | ||
442 | /* | |
443 | * Chaining: | |
444 | * first descriptor is what user is dealing with in all API calls, its | |
445 | * cookie is at first set to -EBUSY, at tx-submit to a positive | |
446 | * number | |
447 | * if more than one chunk is needed further chunks have cookie = -EINVAL | |
448 | * the last chunk, if not equal to the first, has cookie = -ENOSPC | |
449 | * all chunks are linked onto the tx_list head with their .node heads | |
450 | * only during this function, then they are immediately spliced | |
451 | * back onto the free list in form of a chain | |
452 | */ | |
fc461857 GL |
453 | for_each_sg(sgl, sg, sg_len, i) { |
454 | dma_addr_t sg_addr = sg_dma_address(sg); | |
455 | size_t len = sg_dma_len(sg); | |
456 | ||
457 | if (!len) | |
458 | goto err_get_desc; | |
459 | ||
460 | do { | |
461 | dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n", | |
462 | i, sg, len, (unsigned long long)sg_addr); | |
463 | ||
464 | if (direction == DMA_FROM_DEVICE) | |
465 | new = sh_dmae_add_desc(sh_chan, flags, | |
466 | &sg_addr, addr, &len, &first, | |
467 | direction); | |
468 | else | |
469 | new = sh_dmae_add_desc(sh_chan, flags, | |
470 | addr, &sg_addr, &len, &first, | |
471 | direction); | |
472 | if (!new) | |
473 | goto err_get_desc; | |
474 | ||
475 | new->chunks = chunks--; | |
476 | list_add_tail(&new->node, &tx_list); | |
477 | } while (len); | |
478 | } | |
d8902adc | 479 | |
3542a113 GL |
480 | if (new != first) |
481 | new->async_tx.cookie = -ENOSPC; | |
d8902adc | 482 | |
3542a113 GL |
483 | /* Put them back on the free list, so, they don't get lost */ |
484 | list_splice_tail(&tx_list, &sh_chan->ld_free); | |
d8902adc | 485 | |
3542a113 | 486 | spin_unlock_bh(&sh_chan->desc_lock); |
d8902adc | 487 | |
3542a113 | 488 | return &first->async_tx; |
fc461857 GL |
489 | |
490 | err_get_desc: | |
491 | list_for_each_entry(new, &tx_list, node) | |
492 | new->mark = DESC_IDLE; | |
493 | list_splice(&tx_list, &sh_chan->ld_free); | |
494 | ||
495 | spin_unlock_bh(&sh_chan->desc_lock); | |
496 | ||
497 | return NULL; | |
498 | } | |
499 | ||
500 | static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy( | |
501 | struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, | |
502 | size_t len, unsigned long flags) | |
503 | { | |
504 | struct sh_dmae_chan *sh_chan; | |
505 | struct scatterlist sg; | |
506 | ||
507 | if (!chan || !len) | |
508 | return NULL; | |
509 | ||
cfefe997 GL |
510 | chan->private = NULL; |
511 | ||
fc461857 GL |
512 | sh_chan = to_sh_chan(chan); |
513 | ||
514 | sg_init_table(&sg, 1); | |
515 | sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len, | |
516 | offset_in_page(dma_src)); | |
517 | sg_dma_address(&sg) = dma_src; | |
518 | sg_dma_len(&sg) = len; | |
519 | ||
520 | return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL, | |
521 | flags); | |
d8902adc NI |
522 | } |
523 | ||
cfefe997 GL |
524 | static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg( |
525 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
526 | enum dma_data_direction direction, unsigned long flags) | |
527 | { | |
528 | struct sh_dmae_slave *param; | |
529 | struct sh_dmae_chan *sh_chan; | |
530 | ||
531 | if (!chan) | |
532 | return NULL; | |
533 | ||
534 | sh_chan = to_sh_chan(chan); | |
535 | param = chan->private; | |
536 | ||
537 | /* Someone calling slave DMA on a public channel? */ | |
538 | if (!param || !sg_len) { | |
539 | dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n", | |
540 | __func__, param, sg_len, param ? param->slave_id : -1); | |
541 | return NULL; | |
542 | } | |
543 | ||
544 | /* | |
545 | * if (param != NULL), this is a successfully requested slave channel, | |
546 | * therefore param->config != NULL too. | |
547 | */ | |
548 | return sh_dmae_prep_sg(sh_chan, sgl, sg_len, ¶m->config->addr, | |
549 | direction, flags); | |
550 | } | |
551 | ||
552 | static void sh_dmae_terminate_all(struct dma_chan *chan) | |
553 | { | |
554 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
555 | ||
556 | if (!chan) | |
557 | return; | |
558 | ||
559 | sh_dmae_chan_ld_cleanup(sh_chan, true); | |
560 | } | |
561 | ||
3542a113 | 562 | static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all) |
d8902adc NI |
563 | { |
564 | struct sh_desc *desc, *_desc; | |
3542a113 GL |
565 | /* Is the "exposed" head of a chain acked? */ |
566 | bool head_acked = false; | |
567 | dma_cookie_t cookie = 0; | |
568 | dma_async_tx_callback callback = NULL; | |
569 | void *param = NULL; | |
d8902adc NI |
570 | |
571 | spin_lock_bh(&sh_chan->desc_lock); | |
572 | list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) { | |
3542a113 GL |
573 | struct dma_async_tx_descriptor *tx = &desc->async_tx; |
574 | ||
575 | BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie); | |
576 | BUG_ON(desc->mark != DESC_SUBMITTED && | |
577 | desc->mark != DESC_COMPLETED && | |
578 | desc->mark != DESC_WAITING); | |
579 | ||
580 | /* | |
581 | * queue is ordered, and we use this loop to (1) clean up all | |
582 | * completed descriptors, and to (2) update descriptor flags of | |
583 | * any chunks in a (partially) completed chain | |
584 | */ | |
585 | if (!all && desc->mark == DESC_SUBMITTED && | |
586 | desc->cookie != cookie) | |
d8902adc NI |
587 | break; |
588 | ||
3542a113 GL |
589 | if (tx->cookie > 0) |
590 | cookie = tx->cookie; | |
d8902adc | 591 | |
3542a113 | 592 | if (desc->mark == DESC_COMPLETED && desc->chunks == 1) { |
cfefe997 GL |
593 | if (sh_chan->completed_cookie != desc->cookie - 1) |
594 | dev_dbg(sh_chan->dev, | |
595 | "Completing cookie %d, expected %d\n", | |
596 | desc->cookie, | |
597 | sh_chan->completed_cookie + 1); | |
3542a113 GL |
598 | sh_chan->completed_cookie = desc->cookie; |
599 | } | |
d8902adc | 600 | |
3542a113 GL |
601 | /* Call callback on the last chunk */ |
602 | if (desc->mark == DESC_COMPLETED && tx->callback) { | |
603 | desc->mark = DESC_WAITING; | |
604 | callback = tx->callback; | |
605 | param = tx->callback_param; | |
606 | dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n", | |
607 | tx->cookie, tx, sh_chan->id); | |
608 | BUG_ON(desc->chunks != 1); | |
609 | break; | |
610 | } | |
d8902adc | 611 | |
3542a113 GL |
612 | if (tx->cookie > 0 || tx->cookie == -EBUSY) { |
613 | if (desc->mark == DESC_COMPLETED) { | |
614 | BUG_ON(tx->cookie < 0); | |
615 | desc->mark = DESC_WAITING; | |
616 | } | |
617 | head_acked = async_tx_test_ack(tx); | |
618 | } else { | |
619 | switch (desc->mark) { | |
620 | case DESC_COMPLETED: | |
621 | desc->mark = DESC_WAITING; | |
622 | /* Fall through */ | |
623 | case DESC_WAITING: | |
624 | if (head_acked) | |
625 | async_tx_ack(&desc->async_tx); | |
626 | } | |
627 | } | |
628 | ||
629 | dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n", | |
630 | tx, tx->cookie); | |
631 | ||
632 | if (((desc->mark == DESC_COMPLETED || | |
633 | desc->mark == DESC_WAITING) && | |
634 | async_tx_test_ack(&desc->async_tx)) || all) { | |
635 | /* Remove from ld_queue list */ | |
636 | desc->mark = DESC_IDLE; | |
637 | list_move(&desc->node, &sh_chan->ld_free); | |
d8902adc NI |
638 | } |
639 | } | |
640 | spin_unlock_bh(&sh_chan->desc_lock); | |
3542a113 GL |
641 | |
642 | if (callback) | |
643 | callback(param); | |
644 | ||
645 | return callback; | |
646 | } | |
647 | ||
648 | /* | |
649 | * sh_chan_ld_cleanup - Clean up link descriptors | |
650 | * | |
651 | * This function cleans up the ld_queue of DMA channel. | |
652 | */ | |
653 | static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all) | |
654 | { | |
655 | while (__ld_cleanup(sh_chan, all)) | |
656 | ; | |
d8902adc NI |
657 | } |
658 | ||
659 | static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan) | |
660 | { | |
47a4dc26 | 661 | struct sh_desc *desc; |
d8902adc | 662 | |
3542a113 | 663 | spin_lock_bh(&sh_chan->desc_lock); |
d8902adc | 664 | /* DMA work check */ |
3542a113 GL |
665 | if (dmae_is_busy(sh_chan)) { |
666 | spin_unlock_bh(&sh_chan->desc_lock); | |
d8902adc | 667 | return; |
3542a113 | 668 | } |
d8902adc | 669 | |
cfefe997 | 670 | /* Find the first not transferred desciptor */ |
47a4dc26 GL |
671 | list_for_each_entry(desc, &sh_chan->ld_queue, node) |
672 | if (desc->mark == DESC_SUBMITTED) { | |
3542a113 | 673 | /* Get the ld start address from ld_queue */ |
47a4dc26 | 674 | dmae_set_reg(sh_chan, &desc->hw); |
3542a113 GL |
675 | dmae_start(sh_chan); |
676 | break; | |
677 | } | |
678 | ||
679 | spin_unlock_bh(&sh_chan->desc_lock); | |
d8902adc NI |
680 | } |
681 | ||
682 | static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan) | |
683 | { | |
684 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
685 | sh_chan_xfer_ld_queue(sh_chan); | |
686 | } | |
687 | ||
688 | static enum dma_status sh_dmae_is_complete(struct dma_chan *chan, | |
689 | dma_cookie_t cookie, | |
690 | dma_cookie_t *done, | |
691 | dma_cookie_t *used) | |
692 | { | |
693 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
694 | dma_cookie_t last_used; | |
695 | dma_cookie_t last_complete; | |
47a4dc26 | 696 | enum dma_status status; |
d8902adc | 697 | |
3542a113 | 698 | sh_dmae_chan_ld_cleanup(sh_chan, false); |
d8902adc NI |
699 | |
700 | last_used = chan->cookie; | |
701 | last_complete = sh_chan->completed_cookie; | |
3542a113 | 702 | BUG_ON(last_complete < 0); |
d8902adc NI |
703 | |
704 | if (done) | |
705 | *done = last_complete; | |
706 | ||
707 | if (used) | |
708 | *used = last_used; | |
709 | ||
47a4dc26 GL |
710 | spin_lock_bh(&sh_chan->desc_lock); |
711 | ||
712 | status = dma_async_is_complete(cookie, last_complete, last_used); | |
713 | ||
714 | /* | |
715 | * If we don't find cookie on the queue, it has been aborted and we have | |
716 | * to report error | |
717 | */ | |
718 | if (status != DMA_SUCCESS) { | |
719 | struct sh_desc *desc; | |
720 | status = DMA_ERROR; | |
721 | list_for_each_entry(desc, &sh_chan->ld_queue, node) | |
722 | if (desc->cookie == cookie) { | |
723 | status = DMA_IN_PROGRESS; | |
724 | break; | |
725 | } | |
726 | } | |
727 | ||
728 | spin_unlock_bh(&sh_chan->desc_lock); | |
729 | ||
730 | return status; | |
d8902adc NI |
731 | } |
732 | ||
733 | static irqreturn_t sh_dmae_interrupt(int irq, void *data) | |
734 | { | |
735 | irqreturn_t ret = IRQ_NONE; | |
736 | struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data; | |
737 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
738 | ||
739 | if (chcr & CHCR_TE) { | |
740 | /* DMA stop */ | |
741 | dmae_halt(sh_chan); | |
742 | ||
743 | ret = IRQ_HANDLED; | |
744 | tasklet_schedule(&sh_chan->tasklet); | |
745 | } | |
746 | ||
747 | return ret; | |
748 | } | |
749 | ||
750 | #if defined(CONFIG_CPU_SH4) | |
751 | static irqreturn_t sh_dmae_err(int irq, void *data) | |
752 | { | |
d8902adc | 753 | struct sh_dmae_device *shdev = (struct sh_dmae_device *)data; |
47a4dc26 | 754 | int i; |
d8902adc | 755 | |
47a4dc26 | 756 | /* halt the dma controller */ |
027811b9 | 757 | sh_dmae_ctl_stop(shdev); |
47a4dc26 GL |
758 | |
759 | /* We cannot detect, which channel caused the error, have to reset all */ | |
760 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
761 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
762 | if (sh_chan) { | |
763 | struct sh_desc *desc; | |
764 | /* Stop the channel */ | |
765 | dmae_halt(sh_chan); | |
766 | /* Complete all */ | |
767 | list_for_each_entry(desc, &sh_chan->ld_queue, node) { | |
768 | struct dma_async_tx_descriptor *tx = &desc->async_tx; | |
769 | desc->mark = DESC_IDLE; | |
770 | if (tx->callback) | |
771 | tx->callback(tx->callback_param); | |
d8902adc | 772 | } |
47a4dc26 | 773 | list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free); |
d8902adc | 774 | } |
d8902adc | 775 | } |
027811b9 | 776 | sh_dmae_rst(shdev); |
47a4dc26 GL |
777 | |
778 | return IRQ_HANDLED; | |
d8902adc NI |
779 | } |
780 | #endif | |
781 | ||
782 | static void dmae_do_tasklet(unsigned long data) | |
783 | { | |
784 | struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data; | |
3542a113 | 785 | struct sh_desc *desc; |
d8902adc | 786 | u32 sar_buf = sh_dmae_readl(sh_chan, SAR); |
cfefe997 | 787 | u32 dar_buf = sh_dmae_readl(sh_chan, DAR); |
86d61b33 | 788 | |
3542a113 GL |
789 | spin_lock(&sh_chan->desc_lock); |
790 | list_for_each_entry(desc, &sh_chan->ld_queue, node) { | |
cfefe997 GL |
791 | if (desc->mark == DESC_SUBMITTED && |
792 | ((desc->direction == DMA_FROM_DEVICE && | |
793 | (desc->hw.dar + desc->hw.tcr) == dar_buf) || | |
794 | (desc->hw.sar + desc->hw.tcr) == sar_buf)) { | |
3542a113 GL |
795 | dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n", |
796 | desc->async_tx.cookie, &desc->async_tx, | |
797 | desc->hw.dar); | |
798 | desc->mark = DESC_COMPLETED; | |
d8902adc NI |
799 | break; |
800 | } | |
801 | } | |
3542a113 | 802 | spin_unlock(&sh_chan->desc_lock); |
d8902adc | 803 | |
d8902adc NI |
804 | /* Next desc */ |
805 | sh_chan_xfer_ld_queue(sh_chan); | |
3542a113 | 806 | sh_dmae_chan_ld_cleanup(sh_chan, false); |
d8902adc NI |
807 | } |
808 | ||
027811b9 GL |
809 | static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, |
810 | int irq, unsigned long flags) | |
d8902adc NI |
811 | { |
812 | int err; | |
027811b9 GL |
813 | struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id]; |
814 | struct platform_device *pdev = to_platform_device(shdev->common.dev); | |
d8902adc NI |
815 | struct sh_dmae_chan *new_sh_chan; |
816 | ||
817 | /* alloc channel */ | |
818 | new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL); | |
819 | if (!new_sh_chan) { | |
86d61b33 GL |
820 | dev_err(shdev->common.dev, |
821 | "No free memory for allocating dma channels!\n"); | |
d8902adc NI |
822 | return -ENOMEM; |
823 | } | |
824 | ||
825 | new_sh_chan->dev = shdev->common.dev; | |
826 | new_sh_chan->id = id; | |
027811b9 GL |
827 | new_sh_chan->irq = irq; |
828 | new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32); | |
d8902adc NI |
829 | |
830 | /* Init DMA tasklet */ | |
831 | tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet, | |
832 | (unsigned long)new_sh_chan); | |
833 | ||
834 | /* Init the channel */ | |
835 | dmae_init(new_sh_chan); | |
836 | ||
837 | spin_lock_init(&new_sh_chan->desc_lock); | |
838 | ||
839 | /* Init descripter manage list */ | |
840 | INIT_LIST_HEAD(&new_sh_chan->ld_queue); | |
841 | INIT_LIST_HEAD(&new_sh_chan->ld_free); | |
842 | ||
843 | /* copy struct dma_device */ | |
844 | new_sh_chan->common.device = &shdev->common; | |
845 | ||
846 | /* Add the channel to DMA device channel list */ | |
847 | list_add_tail(&new_sh_chan->common.device_node, | |
848 | &shdev->common.channels); | |
849 | shdev->common.chancnt++; | |
850 | ||
027811b9 GL |
851 | if (pdev->id >= 0) |
852 | snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), | |
853 | "sh-dmae%d.%d", pdev->id, new_sh_chan->id); | |
854 | else | |
855 | snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), | |
856 | "sh-dma%d", new_sh_chan->id); | |
d8902adc NI |
857 | |
858 | /* set up channel irq */ | |
027811b9 | 859 | err = request_irq(irq, &sh_dmae_interrupt, flags, |
86d61b33 | 860 | new_sh_chan->dev_id, new_sh_chan); |
d8902adc NI |
861 | if (err) { |
862 | dev_err(shdev->common.dev, "DMA channel %d request_irq error " | |
863 | "with return %d\n", id, err); | |
864 | goto err_no_irq; | |
865 | } | |
866 | ||
d8902adc NI |
867 | shdev->chan[id] = new_sh_chan; |
868 | return 0; | |
869 | ||
870 | err_no_irq: | |
871 | /* remove from dmaengine device node */ | |
872 | list_del(&new_sh_chan->common.device_node); | |
873 | kfree(new_sh_chan); | |
874 | return err; | |
875 | } | |
876 | ||
877 | static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) | |
878 | { | |
879 | int i; | |
880 | ||
881 | for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) { | |
882 | if (shdev->chan[i]) { | |
027811b9 GL |
883 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; |
884 | ||
885 | free_irq(sh_chan->irq, sh_chan); | |
d8902adc | 886 | |
027811b9 GL |
887 | list_del(&sh_chan->common.device_node); |
888 | kfree(sh_chan); | |
d8902adc NI |
889 | shdev->chan[i] = NULL; |
890 | } | |
891 | } | |
892 | shdev->common.chancnt = 0; | |
893 | } | |
894 | ||
895 | static int __init sh_dmae_probe(struct platform_device *pdev) | |
896 | { | |
027811b9 GL |
897 | struct sh_dmae_pdata *pdata = pdev->dev.platform_data; |
898 | unsigned long irqflags = IRQF_DISABLED, | |
899 | chan_flag[MAX_DMA_CHANNELS] = {}; | |
900 | int errirq, chan_irq[MAX_DMA_CHANNELS]; | |
901 | int err, i, irq_cnt = 0, irqres = 0; | |
d8902adc | 902 | struct sh_dmae_device *shdev; |
027811b9 | 903 | struct resource *chan, *dmars, *errirq_res, *chanirq_res; |
d8902adc | 904 | |
56adf7e8 | 905 | /* get platform data */ |
027811b9 | 906 | if (!pdata || !pdata->channel_num) |
56adf7e8 DW |
907 | return -ENODEV; |
908 | ||
027811b9 GL |
909 | chan = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
910 | /* DMARS area is optional, if absent, this controller cannot do slave DMA */ | |
911 | dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
912 | /* | |
913 | * IRQ resources: | |
914 | * 1. there always must be at least one IRQ IO-resource. On SH4 it is | |
915 | * the error IRQ, in which case it is the only IRQ in this resource: | |
916 | * start == end. If it is the only IRQ resource, all channels also | |
917 | * use the same IRQ. | |
918 | * 2. DMA channel IRQ resources can be specified one per resource or in | |
919 | * ranges (start != end) | |
920 | * 3. iff all events (channels and, optionally, error) on this | |
921 | * controller use the same IRQ, only one IRQ resource can be | |
922 | * specified, otherwise there must be one IRQ per channel, even if | |
923 | * some of them are equal | |
924 | * 4. if all IRQs on this controller are equal or if some specific IRQs | |
925 | * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be | |
926 | * requested with the IRQF_SHARED flag | |
927 | */ | |
928 | errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
929 | if (!chan || !errirq_res) | |
930 | return -ENODEV; | |
931 | ||
932 | if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) { | |
933 | dev_err(&pdev->dev, "DMAC register region already claimed\n"); | |
934 | return -EBUSY; | |
935 | } | |
936 | ||
937 | if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) { | |
938 | dev_err(&pdev->dev, "DMAC DMARS region already claimed\n"); | |
939 | err = -EBUSY; | |
940 | goto ermrdmars; | |
941 | } | |
942 | ||
943 | err = -ENOMEM; | |
d8902adc NI |
944 | shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL); |
945 | if (!shdev) { | |
027811b9 GL |
946 | dev_err(&pdev->dev, "Not enough memory\n"); |
947 | goto ealloc; | |
948 | } | |
949 | ||
950 | shdev->chan_reg = ioremap(chan->start, resource_size(chan)); | |
951 | if (!shdev->chan_reg) | |
952 | goto emapchan; | |
953 | if (dmars) { | |
954 | shdev->dmars = ioremap(dmars->start, resource_size(dmars)); | |
955 | if (!shdev->dmars) | |
956 | goto emapdmars; | |
d8902adc NI |
957 | } |
958 | ||
d8902adc | 959 | /* platform data */ |
027811b9 | 960 | shdev->pdata = pdata; |
d8902adc NI |
961 | |
962 | /* reset dma controller */ | |
027811b9 | 963 | err = sh_dmae_rst(shdev); |
d8902adc NI |
964 | if (err) |
965 | goto rst_err; | |
966 | ||
d8902adc NI |
967 | INIT_LIST_HEAD(&shdev->common.channels); |
968 | ||
969 | dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask); | |
027811b9 GL |
970 | if (dmars) |
971 | dma_cap_set(DMA_SLAVE, shdev->common.cap_mask); | |
cfefe997 | 972 | |
d8902adc NI |
973 | shdev->common.device_alloc_chan_resources |
974 | = sh_dmae_alloc_chan_resources; | |
975 | shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources; | |
976 | shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy; | |
977 | shdev->common.device_is_tx_complete = sh_dmae_is_complete; | |
978 | shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending; | |
cfefe997 GL |
979 | |
980 | /* Compulsory for DMA_SLAVE fields */ | |
981 | shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg; | |
982 | shdev->common.device_terminate_all = sh_dmae_terminate_all; | |
983 | ||
d8902adc | 984 | shdev->common.dev = &pdev->dev; |
ddb4f0f0 GL |
985 | /* Default transfer size of 32 bytes requires 32-byte alignment */ |
986 | shdev->common.copy_align = 5; | |
d8902adc NI |
987 | |
988 | #if defined(CONFIG_CPU_SH4) | |
027811b9 GL |
989 | chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); |
990 | ||
991 | if (!chanirq_res) | |
992 | chanirq_res = errirq_res; | |
993 | else | |
994 | irqres++; | |
995 | ||
996 | if (chanirq_res == errirq_res || | |
997 | (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE) | |
d8902adc | 998 | irqflags = IRQF_SHARED; |
027811b9 GL |
999 | |
1000 | errirq = errirq_res->start; | |
1001 | ||
1002 | err = request_irq(errirq, sh_dmae_err, irqflags, | |
1003 | "DMAC Address Error", shdev); | |
1004 | if (err) { | |
1005 | dev_err(&pdev->dev, | |
1006 | "DMA failed requesting irq #%d, error %d\n", | |
1007 | errirq, err); | |
1008 | goto eirq_err; | |
d8902adc NI |
1009 | } |
1010 | ||
027811b9 GL |
1011 | #else |
1012 | chanirq_res = errirq_res; | |
1013 | #endif /* CONFIG_CPU_SH4 */ | |
1014 | ||
1015 | if (chanirq_res->start == chanirq_res->end && | |
1016 | !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { | |
1017 | /* Special case - all multiplexed */ | |
1018 | for (; irq_cnt < pdata->channel_num; irq_cnt++) { | |
1019 | chan_irq[irq_cnt] = chanirq_res->start; | |
1020 | chan_flag[irq_cnt] = IRQF_SHARED; | |
d8902adc | 1021 | } |
027811b9 GL |
1022 | } else { |
1023 | do { | |
1024 | for (i = chanirq_res->start; i <= chanirq_res->end; i++) { | |
1025 | if ((errirq_res->flags & IORESOURCE_BITS) == | |
1026 | IORESOURCE_IRQ_SHAREABLE) | |
1027 | chan_flag[irq_cnt] = IRQF_SHARED; | |
1028 | else | |
1029 | chan_flag[irq_cnt] = IRQF_DISABLED; | |
1030 | dev_dbg(&pdev->dev, | |
1031 | "Found IRQ %d for channel %d\n", | |
1032 | i, irq_cnt); | |
1033 | chan_irq[irq_cnt++] = i; | |
1034 | } | |
1035 | chanirq_res = platform_get_resource(pdev, | |
1036 | IORESOURCE_IRQ, ++irqres); | |
1037 | } while (irq_cnt < pdata->channel_num && chanirq_res); | |
d8902adc | 1038 | } |
027811b9 GL |
1039 | |
1040 | if (irq_cnt < pdata->channel_num) | |
1041 | goto eirqres; | |
d8902adc NI |
1042 | |
1043 | /* Create DMA Channel */ | |
027811b9 GL |
1044 | for (i = 0; i < pdata->channel_num; i++) { |
1045 | err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]); | |
d8902adc NI |
1046 | if (err) |
1047 | goto chan_probe_err; | |
1048 | } | |
1049 | ||
1050 | platform_set_drvdata(pdev, shdev); | |
1051 | dma_async_device_register(&shdev->common); | |
1052 | ||
1053 | return err; | |
1054 | ||
1055 | chan_probe_err: | |
1056 | sh_dmae_chan_remove(shdev); | |
027811b9 GL |
1057 | eirqres: |
1058 | #if defined(CONFIG_CPU_SH4) | |
1059 | free_irq(errirq, shdev); | |
d8902adc | 1060 | eirq_err: |
027811b9 | 1061 | #endif |
d8902adc | 1062 | rst_err: |
027811b9 GL |
1063 | if (dmars) |
1064 | iounmap(shdev->dmars); | |
1065 | emapdmars: | |
1066 | iounmap(shdev->chan_reg); | |
1067 | emapchan: | |
d8902adc | 1068 | kfree(shdev); |
027811b9 GL |
1069 | ealloc: |
1070 | if (dmars) | |
1071 | release_mem_region(dmars->start, resource_size(dmars)); | |
1072 | ermrdmars: | |
1073 | release_mem_region(chan->start, resource_size(chan)); | |
d8902adc | 1074 | |
d8902adc NI |
1075 | return err; |
1076 | } | |
1077 | ||
1078 | static int __exit sh_dmae_remove(struct platform_device *pdev) | |
1079 | { | |
1080 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
027811b9 GL |
1081 | struct resource *res; |
1082 | int errirq = platform_get_irq(pdev, 0); | |
d8902adc NI |
1083 | |
1084 | dma_async_device_unregister(&shdev->common); | |
1085 | ||
027811b9 GL |
1086 | if (errirq > 0) |
1087 | free_irq(errirq, shdev); | |
d8902adc NI |
1088 | |
1089 | /* channel data remove */ | |
1090 | sh_dmae_chan_remove(shdev); | |
1091 | ||
027811b9 GL |
1092 | if (shdev->dmars) |
1093 | iounmap(shdev->dmars); | |
1094 | iounmap(shdev->chan_reg); | |
1095 | ||
d8902adc NI |
1096 | kfree(shdev); |
1097 | ||
027811b9 GL |
1098 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1099 | if (res) | |
1100 | release_mem_region(res->start, resource_size(res)); | |
1101 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1102 | if (res) | |
1103 | release_mem_region(res->start, resource_size(res)); | |
1104 | ||
d8902adc NI |
1105 | return 0; |
1106 | } | |
1107 | ||
1108 | static void sh_dmae_shutdown(struct platform_device *pdev) | |
1109 | { | |
1110 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
027811b9 | 1111 | sh_dmae_ctl_stop(shdev); |
d8902adc NI |
1112 | } |
1113 | ||
1114 | static struct platform_driver sh_dmae_driver = { | |
1115 | .remove = __exit_p(sh_dmae_remove), | |
1116 | .shutdown = sh_dmae_shutdown, | |
1117 | .driver = { | |
1118 | .name = "sh-dma-engine", | |
1119 | }, | |
1120 | }; | |
1121 | ||
1122 | static int __init sh_dmae_init(void) | |
1123 | { | |
1124 | return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe); | |
1125 | } | |
1126 | module_init(sh_dmae_init); | |
1127 | ||
1128 | static void __exit sh_dmae_exit(void) | |
1129 | { | |
1130 | platform_driver_unregister(&sh_dmae_driver); | |
1131 | } | |
1132 | module_exit(sh_dmae_exit); | |
1133 | ||
1134 | MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>"); | |
1135 | MODULE_DESCRIPTION("Renesas SH DMA Engine driver"); | |
1136 | MODULE_LICENSE("GPL"); |