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dmaengine: sprd: Fix block length overflow
[mirror_ubuntu-hirsute-kernel.git] / drivers / dma / sprd-dma.c
CommitLineData
9b3b8171
BW		 1/*
2 * Copyright (C) 2017 Spreadtrum Communications Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <linux/clk.h>
8#include <linux/dma-mapping.h>
ab42ddb9 9#include <linux/dma/sprd-dma.h>
9b3b8171
BW		 10#include <linux/errno.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_dma.h>
18#include <linux/of_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/slab.h>
21
22#include "virt-dma.h"
23
24#define SPRD_DMA_CHN_REG_OFFSET 0x1000
25#define SPRD_DMA_CHN_REG_LENGTH 0x40
26#define SPRD_DMA_MEMCPY_MIN_SIZE 64
27
28/* DMA global registers definition */
29#define SPRD_DMA_GLB_PAUSE 0x0
30#define SPRD_DMA_GLB_FRAG_WAIT 0x4
31#define SPRD_DMA_GLB_REQ_PEND0_EN 0x8
32#define SPRD_DMA_GLB_REQ_PEND1_EN 0xc
33#define SPRD_DMA_GLB_INT_RAW_STS 0x10
34#define SPRD_DMA_GLB_INT_MSK_STS 0x14
35#define SPRD_DMA_GLB_REQ_STS 0x18
36#define SPRD_DMA_GLB_CHN_EN_STS 0x1c
37#define SPRD_DMA_GLB_DEBUG_STS 0x20
38#define SPRD_DMA_GLB_ARB_SEL_STS 0x24
770399df
EL		 39#define SPRD_DMA_GLB_2STAGE_GRP1 0x28
40#define SPRD_DMA_GLB_2STAGE_GRP2 0x2c
9b3b8171
BW		 41#define SPRD_DMA_GLB_REQ_UID(uid) (0x4 * ((uid) - 1))
42#define SPRD_DMA_GLB_REQ_UID_OFFSET 0x2000
43
44/* DMA channel registers definition */
45#define SPRD_DMA_CHN_PAUSE 0x0
46#define SPRD_DMA_CHN_REQ 0x4
47#define SPRD_DMA_CHN_CFG 0x8
48#define SPRD_DMA_CHN_INTC 0xc
49#define SPRD_DMA_CHN_SRC_ADDR 0x10
50#define SPRD_DMA_CHN_DES_ADDR 0x14
51#define SPRD_DMA_CHN_FRG_LEN 0x18
52#define SPRD_DMA_CHN_BLK_LEN 0x1c
53#define SPRD_DMA_CHN_TRSC_LEN 0x20
54#define SPRD_DMA_CHN_TRSF_STEP 0x24
55#define SPRD_DMA_CHN_WARP_PTR 0x28
56#define SPRD_DMA_CHN_WARP_TO 0x2c
57#define SPRD_DMA_CHN_LLIST_PTR 0x30
58#define SPRD_DMA_CHN_FRAG_STEP 0x34
59#define SPRD_DMA_CHN_SRC_BLK_STEP 0x38
60#define SPRD_DMA_CHN_DES_BLK_STEP 0x3c
61
770399df
EL		 62/* SPRD_DMA_GLB_2STAGE_GRP register definition */
63#define SPRD_DMA_GLB_2STAGE_EN BIT(24)
64#define SPRD_DMA_GLB_CHN_INT_MASK GENMASK(23, 20)
65#define SPRD_DMA_GLB_LIST_DONE_TRG BIT(19)
66#define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18)
67#define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17)
68#define SPRD_DMA_GLB_FRAG_DONE_TRG BIT(16)
69#define SPRD_DMA_GLB_TRG_OFFSET 16
70#define SPRD_DMA_GLB_DEST_CHN_MASK GENMASK(13, 8)
71#define SPRD_DMA_GLB_DEST_CHN_OFFSET 8
72#define SPRD_DMA_GLB_SRC_CHN_MASK GENMASK(5, 0)
73
9b3b8171
BW		 74/* SPRD_DMA_CHN_INTC register definition */
75#define SPRD_DMA_INT_MASK GENMASK(4, 0)
76#define SPRD_DMA_INT_CLR_OFFSET 24
77#define SPRD_DMA_FRAG_INT_EN BIT(0)
78#define SPRD_DMA_BLK_INT_EN BIT(1)
79#define SPRD_DMA_TRANS_INT_EN BIT(2)
80#define SPRD_DMA_LIST_INT_EN BIT(3)
81#define SPRD_DMA_CFG_ERR_INT_EN BIT(4)
82
83/* SPRD_DMA_CHN_CFG register definition */
84#define SPRD_DMA_CHN_EN BIT(0)
4ac69546 85#define SPRD_DMA_LINKLIST_EN BIT(4)
9b3b8171
BW		 86#define SPRD_DMA_WAIT_BDONE_OFFSET 24
87#define SPRD_DMA_DONOT_WAIT_BDONE 1
88
89/* SPRD_DMA_CHN_REQ register definition */
90#define SPRD_DMA_REQ_EN BIT(0)
91
92/* SPRD_DMA_CHN_PAUSE register definition */
93#define SPRD_DMA_PAUSE_EN BIT(0)
94#define SPRD_DMA_PAUSE_STS BIT(2)
95#define SPRD_DMA_PAUSE_CNT 0x2000
96
97/* DMA_CHN_WARP_* register definition */
98#define SPRD_DMA_HIGH_ADDR_MASK GENMASK(31, 28)
99#define SPRD_DMA_LOW_ADDR_MASK GENMASK(31, 0)
100#define SPRD_DMA_HIGH_ADDR_OFFSET 4
101
102/* SPRD_DMA_CHN_INTC register definition */
103#define SPRD_DMA_FRAG_INT_STS BIT(16)
104#define SPRD_DMA_BLK_INT_STS BIT(17)
105#define SPRD_DMA_TRSC_INT_STS BIT(18)
106#define SPRD_DMA_LIST_INT_STS BIT(19)
107#define SPRD_DMA_CFGERR_INT_STS BIT(20)
108#define SPRD_DMA_CHN_INT_STS \
109 (SPRD_DMA_FRAG_INT_STS | SPRD_DMA_BLK_INT_STS | \
110 SPRD_DMA_TRSC_INT_STS | SPRD_DMA_LIST_INT_STS | \
111 SPRD_DMA_CFGERR_INT_STS)
112
113/* SPRD_DMA_CHN_FRG_LEN register definition */
114#define SPRD_DMA_SRC_DATAWIDTH_OFFSET 30
115#define SPRD_DMA_DES_DATAWIDTH_OFFSET 28
116#define SPRD_DMA_SWT_MODE_OFFSET 26
117#define SPRD_DMA_REQ_MODE_OFFSET 24
118#define SPRD_DMA_REQ_MODE_MASK GENMASK(1, 0)
119#define SPRD_DMA_FIX_SEL_OFFSET 21
120#define SPRD_DMA_FIX_EN_OFFSET 20
4ac69546 121#define SPRD_DMA_LLIST_END BIT(19)
9b3b8171
BW		 122#define SPRD_DMA_FRG_LEN_MASK GENMASK(16, 0)
123
124/* SPRD_DMA_CHN_BLK_LEN register definition */
125#define SPRD_DMA_BLK_LEN_MASK GENMASK(16, 0)
126
127/* SPRD_DMA_CHN_TRSC_LEN register definition */
128#define SPRD_DMA_TRSC_LEN_MASK GENMASK(27, 0)
129
130/* SPRD_DMA_CHN_TRSF_STEP register definition */
131#define SPRD_DMA_DEST_TRSF_STEP_OFFSET 16
132#define SPRD_DMA_SRC_TRSF_STEP_OFFSET 0
133#define SPRD_DMA_TRSF_STEP_MASK GENMASK(15, 0)
134
770399df
EL		 135/* define DMA channel mode & trigger mode mask */
136#define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0)
137#define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0)
138
6b1d255e
EL		 139/* define the DMA transfer step type */
140#define SPRD_DMA_NONE_STEP 0
141#define SPRD_DMA_BYTE_STEP 1
142#define SPRD_DMA_SHORT_STEP 2
143#define SPRD_DMA_WORD_STEP 4
144#define SPRD_DMA_DWORD_STEP 8
145
9b3b8171
BW		 146#define SPRD_DMA_SOFTWARE_UID 0
147
d7c33cf8
BW		 148/* dma data width values */
149enum sprd_dma_datawidth {
150 SPRD_DMA_DATAWIDTH_1_BYTE,
151 SPRD_DMA_DATAWIDTH_2_BYTES,
152 SPRD_DMA_DATAWIDTH_4_BYTES,
153 SPRD_DMA_DATAWIDTH_8_BYTES,
9b3b8171
BW		 154};
155
156/* dma channel hardware configuration */
157struct sprd_dma_chn_hw {
158 u32 pause;
159 u32 req;
160 u32 cfg;
161 u32 intc;
162 u32 src_addr;
163 u32 des_addr;
164 u32 frg_len;
165 u32 blk_len;
166 u32 trsc_len;
167 u32 trsf_step;
168 u32 wrap_ptr;
169 u32 wrap_to;
170 u32 llist_ptr;
171 u32 frg_step;
172 u32 src_blk_step;
173 u32 des_blk_step;
174};
175
176/* dma request description */
177struct sprd_dma_desc {
178 struct virt_dma_desc vd;
179 struct sprd_dma_chn_hw chn_hw;
d762ab33 180 enum dma_transfer_direction dir;
9b3b8171
BW		 181};
182
183/* dma channel description */
184struct sprd_dma_chn {
185 struct virt_dma_chan vc;
186 void __iomem *chn_base;
4ac69546 187 struct sprd_dma_linklist linklist;
ca1b7d3d 188 struct dma_slave_config slave_cfg;
9b3b8171
BW		 189 u32 chn_num;
190 u32 dev_id;
770399df
EL		 191 enum sprd_dma_chn_mode chn_mode;
192 enum sprd_dma_trg_mode trg_mode;
9b3b8171
BW		 193 struct sprd_dma_desc *cur_desc;
194};
195
196/* SPRD dma device */
197struct sprd_dma_dev {
198 struct dma_device dma_dev;
199 void __iomem *glb_base;
200 struct clk *clk;
201 struct clk *ashb_clk;
202 int irq;
203 u32 total_chns;
204 struct sprd_dma_chn channels[0];
205};
206
207static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param);
208static struct of_dma_filter_info sprd_dma_info = {
209 .filter_fn = sprd_dma_filter_fn,
210};
211
212static inline struct sprd_dma_chn *to_sprd_dma_chan(struct dma_chan *c)
213{
214 return container_of(c, struct sprd_dma_chn, vc.chan);
215}
216
217static inline struct sprd_dma_dev *to_sprd_dma_dev(struct dma_chan *c)
218{
219 struct sprd_dma_chn *schan = to_sprd_dma_chan(c);
220
221 return container_of(schan, struct sprd_dma_dev, channels[c->chan_id]);
222}
223
224static inline struct sprd_dma_desc *to_sprd_dma_desc(struct virt_dma_desc *vd)
225{
226 return container_of(vd, struct sprd_dma_desc, vd);
227}
228
770399df
EL		 229static void sprd_dma_glb_update(struct sprd_dma_dev *sdev, u32 reg,
230 u32 mask, u32 val)
231{
232 u32 orig = readl(sdev->glb_base + reg);
233 u32 tmp;
234
235 tmp = (orig & ~mask) | val;
236 writel(tmp, sdev->glb_base + reg);
237}
238
9b3b8171
BW		 239static void sprd_dma_chn_update(struct sprd_dma_chn *schan, u32 reg,
240 u32 mask, u32 val)
241{
242 u32 orig = readl(schan->chn_base + reg);
243 u32 tmp;
244
245 tmp = (orig & ~mask) | val;
246 writel(tmp, schan->chn_base + reg);
247}
248
249static int sprd_dma_enable(struct sprd_dma_dev *sdev)
250{
251 int ret;
252
253 ret = clk_prepare_enable(sdev->clk);
254 if (ret)
255 return ret;
256
257 /*
258 * The ashb_clk is optional and only for AGCP DMA controller, so we
259 * need add one condition to check if the ashb_clk need enable.
260 */
261 if (!IS_ERR(sdev->ashb_clk))
262 ret = clk_prepare_enable(sdev->ashb_clk);
263
264 return ret;
265}
266
267static void sprd_dma_disable(struct sprd_dma_dev *sdev)
268{
269 clk_disable_unprepare(sdev->clk);
270
271 /*
272 * Need to check if we need disable the optional ashb_clk for AGCP DMA.
273 */
274 if (!IS_ERR(sdev->ashb_clk))
275 clk_disable_unprepare(sdev->ashb_clk);
276}
277
278static void sprd_dma_set_uid(struct sprd_dma_chn *schan)
279{
280 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
281 u32 dev_id = schan->dev_id;
282
283 if (dev_id != SPRD_DMA_SOFTWARE_UID) {
284 u32 uid_offset = SPRD_DMA_GLB_REQ_UID_OFFSET +
285 SPRD_DMA_GLB_REQ_UID(dev_id);
286
287 writel(schan->chn_num + 1, sdev->glb_base + uid_offset);
288 }
289}
290
291static void sprd_dma_unset_uid(struct sprd_dma_chn *schan)
292{
293 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
294 u32 dev_id = schan->dev_id;
295
296 if (dev_id != SPRD_DMA_SOFTWARE_UID) {
297 u32 uid_offset = SPRD_DMA_GLB_REQ_UID_OFFSET +
298 SPRD_DMA_GLB_REQ_UID(dev_id);
299
300 writel(0, sdev->glb_base + uid_offset);
301 }
302}
303
304static void sprd_dma_clear_int(struct sprd_dma_chn *schan)
305{
306 sprd_dma_chn_update(schan, SPRD_DMA_CHN_INTC,
307 SPRD_DMA_INT_MASK << SPRD_DMA_INT_CLR_OFFSET,
308 SPRD_DMA_INT_MASK << SPRD_DMA_INT_CLR_OFFSET);
309}
310
311static void sprd_dma_enable_chn(struct sprd_dma_chn *schan)
312{
313 sprd_dma_chn_update(schan, SPRD_DMA_CHN_CFG, SPRD_DMA_CHN_EN,
314 SPRD_DMA_CHN_EN);
315}
316
317static void sprd_dma_disable_chn(struct sprd_dma_chn *schan)
318{
319 sprd_dma_chn_update(schan, SPRD_DMA_CHN_CFG, SPRD_DMA_CHN_EN, 0);
320}
321
322static void sprd_dma_soft_request(struct sprd_dma_chn *schan)
323{
324 sprd_dma_chn_update(schan, SPRD_DMA_CHN_REQ, SPRD_DMA_REQ_EN,
325 SPRD_DMA_REQ_EN);
326}
327
328static void sprd_dma_pause_resume(struct sprd_dma_chn *schan, bool enable)
329{
330 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
331 u32 pause, timeout = SPRD_DMA_PAUSE_CNT;
332
333 if (enable) {
334 sprd_dma_chn_update(schan, SPRD_DMA_CHN_PAUSE,
335 SPRD_DMA_PAUSE_EN, SPRD_DMA_PAUSE_EN);
336
337 do {
338 pause = readl(schan->chn_base + SPRD_DMA_CHN_PAUSE);
339 if (pause & SPRD_DMA_PAUSE_STS)
340 break;
341
342 cpu_relax();
343 } while (--timeout > 0);
344
345 if (!timeout)
346 dev_warn(sdev->dma_dev.dev,
347 "pause dma controller timeout\n");
348 } else {
349 sprd_dma_chn_update(schan, SPRD_DMA_CHN_PAUSE,
350 SPRD_DMA_PAUSE_EN, 0);
351 }
352}
353
354static void sprd_dma_stop_and_disable(struct sprd_dma_chn *schan)
355{
356 u32 cfg = readl(schan->chn_base + SPRD_DMA_CHN_CFG);
357
358 if (!(cfg & SPRD_DMA_CHN_EN))
359 return;
360
361 sprd_dma_pause_resume(schan, true);
362 sprd_dma_disable_chn(schan);
363}
364
d762ab33
EL		 365static unsigned long sprd_dma_get_src_addr(struct sprd_dma_chn *schan)
366{
367 unsigned long addr, addr_high;
368
369 addr = readl(schan->chn_base + SPRD_DMA_CHN_SRC_ADDR);
370 addr_high = readl(schan->chn_base + SPRD_DMA_CHN_WARP_PTR) &
371 SPRD_DMA_HIGH_ADDR_MASK;
372
373 return addr | (addr_high << SPRD_DMA_HIGH_ADDR_OFFSET);
374}
375
9b3b8171
BW		 376static unsigned long sprd_dma_get_dst_addr(struct sprd_dma_chn *schan)
377{
378 unsigned long addr, addr_high;
379
380 addr = readl(schan->chn_base + SPRD_DMA_CHN_DES_ADDR);
381 addr_high = readl(schan->chn_base + SPRD_DMA_CHN_WARP_TO) &
382 SPRD_DMA_HIGH_ADDR_MASK;
383
384 return addr | (addr_high << SPRD_DMA_HIGH_ADDR_OFFSET);
385}
386
387static enum sprd_dma_int_type sprd_dma_get_int_type(struct sprd_dma_chn *schan)
388{
389 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
390 u32 intc_sts = readl(schan->chn_base + SPRD_DMA_CHN_INTC) &
391 SPRD_DMA_CHN_INT_STS;
392
393 switch (intc_sts) {
394 case SPRD_DMA_CFGERR_INT_STS:
395 return SPRD_DMA_CFGERR_INT;
396
397 case SPRD_DMA_LIST_INT_STS:
398 return SPRD_DMA_LIST_INT;
399
400 case SPRD_DMA_TRSC_INT_STS:
401 return SPRD_DMA_TRANS_INT;
402
403 case SPRD_DMA_BLK_INT_STS:
404 return SPRD_DMA_BLK_INT;
405
406 case SPRD_DMA_FRAG_INT_STS:
407 return SPRD_DMA_FRAG_INT;
408
409 default:
410 dev_warn(sdev->dma_dev.dev, "incorrect dma interrupt type\n");
411 return SPRD_DMA_NO_INT;
412 }
413}
414
415static enum sprd_dma_req_mode sprd_dma_get_req_type(struct sprd_dma_chn *schan)
416{
417 u32 frag_reg = readl(schan->chn_base + SPRD_DMA_CHN_FRG_LEN);
418
419 return (frag_reg >> SPRD_DMA_REQ_MODE_OFFSET) & SPRD_DMA_REQ_MODE_MASK;
420}
421
770399df
EL		 422static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
423{
424 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
425 u32 val, chn = schan->chn_num + 1;
426
427 switch (schan->chn_mode) {
428 case SPRD_DMA_SRC_CHN0:
429 val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
430 val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
431 val |= SPRD_DMA_GLB_2STAGE_EN;
432 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
433 break;
434
435 case SPRD_DMA_SRC_CHN1:
436 val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
437 val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
438 val |= SPRD_DMA_GLB_2STAGE_EN;
439 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
440 break;
441
442 case SPRD_DMA_DST_CHN0:
443 val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
444 SPRD_DMA_GLB_DEST_CHN_MASK;
445 val |= SPRD_DMA_GLB_2STAGE_EN;
446 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
447 break;
448
449 case SPRD_DMA_DST_CHN1:
450 val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
451 SPRD_DMA_GLB_DEST_CHN_MASK;
452 val |= SPRD_DMA_GLB_2STAGE_EN;
453 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
454 break;
455
456 default:
457 dev_err(sdev->dma_dev.dev, "invalid channel mode setting %d\n",
458 schan->chn_mode);
459 return -EINVAL;
460 }
461
462 return 0;
463}
464
9b3b8171
BW		 465static void sprd_dma_set_chn_config(struct sprd_dma_chn *schan,
466 struct sprd_dma_desc *sdesc)
467{
468 struct sprd_dma_chn_hw *cfg = &sdesc->chn_hw;
469
470 writel(cfg->pause, schan->chn_base + SPRD_DMA_CHN_PAUSE);
471 writel(cfg->cfg, schan->chn_base + SPRD_DMA_CHN_CFG);
472 writel(cfg->intc, schan->chn_base + SPRD_DMA_CHN_INTC);
473 writel(cfg->src_addr, schan->chn_base + SPRD_DMA_CHN_SRC_ADDR);
474 writel(cfg->des_addr, schan->chn_base + SPRD_DMA_CHN_DES_ADDR);
475 writel(cfg->frg_len, schan->chn_base + SPRD_DMA_CHN_FRG_LEN);
476 writel(cfg->blk_len, schan->chn_base + SPRD_DMA_CHN_BLK_LEN);
477 writel(cfg->trsc_len, schan->chn_base + SPRD_DMA_CHN_TRSC_LEN);
478 writel(cfg->trsf_step, schan->chn_base + SPRD_DMA_CHN_TRSF_STEP);
479 writel(cfg->wrap_ptr, schan->chn_base + SPRD_DMA_CHN_WARP_PTR);
480 writel(cfg->wrap_to, schan->chn_base + SPRD_DMA_CHN_WARP_TO);
481 writel(cfg->llist_ptr, schan->chn_base + SPRD_DMA_CHN_LLIST_PTR);
482 writel(cfg->frg_step, schan->chn_base + SPRD_DMA_CHN_FRAG_STEP);
483 writel(cfg->src_blk_step, schan->chn_base + SPRD_DMA_CHN_SRC_BLK_STEP);
484 writel(cfg->des_blk_step, schan->chn_base + SPRD_DMA_CHN_DES_BLK_STEP);
485 writel(cfg->req, schan->chn_base + SPRD_DMA_CHN_REQ);
486}
487
488static void sprd_dma_start(struct sprd_dma_chn *schan)
489{
490 struct virt_dma_desc *vd = vchan_next_desc(&schan->vc);
491
492 if (!vd)
493 return;
494
495 list_del(&vd->node);
496 schan->cur_desc = to_sprd_dma_desc(vd);
497
770399df
EL		 498 /*
499 * Set 2-stage configuration if the channel starts one 2-stage
500 * transfer.
501 */
502 if (schan->chn_mode && sprd_dma_set_2stage_config(schan))
503 return;
504
9b3b8171
BW		 505 /*
506 * Copy the DMA configuration from DMA descriptor to this hardware
507 * channel.
508 */
509 sprd_dma_set_chn_config(schan, schan->cur_desc);
510 sprd_dma_set_uid(schan);
511 sprd_dma_enable_chn(schan);
512
3d626a97
EL		 513 if (schan->dev_id == SPRD_DMA_SOFTWARE_UID &&
514 schan->chn_mode != SPRD_DMA_DST_CHN0 &&
515 schan->chn_mode != SPRD_DMA_DST_CHN1)
9b3b8171
BW		 516 sprd_dma_soft_request(schan);
517}
518
519static void sprd_dma_stop(struct sprd_dma_chn *schan)
520{
521 sprd_dma_stop_and_disable(schan);
522 sprd_dma_unset_uid(schan);
523 sprd_dma_clear_int(schan);
0e5d7b1e 524 schan->cur_desc = NULL;
9b3b8171
BW		 525}
526
527static bool sprd_dma_check_trans_done(struct sprd_dma_desc *sdesc,
528 enum sprd_dma_int_type int_type,
529 enum sprd_dma_req_mode req_mode)
530{
531 if (int_type == SPRD_DMA_NO_INT)
532 return false;
533
534 if (int_type >= req_mode + 1)
535 return true;
536 else
537 return false;
538}
539
540static irqreturn_t dma_irq_handle(int irq, void *dev_id)
541{
542 struct sprd_dma_dev *sdev = (struct sprd_dma_dev *)dev_id;
543 u32 irq_status = readl(sdev->glb_base + SPRD_DMA_GLB_INT_MSK_STS);
544 struct sprd_dma_chn *schan;
545 struct sprd_dma_desc *sdesc;
546 enum sprd_dma_req_mode req_type;
547 enum sprd_dma_int_type int_type;
97dbd6ea 548 bool trans_done = false, cyclic = false;
9b3b8171
BW		 549 u32 i;
550
551 while (irq_status) {
552 i = __ffs(irq_status);
553 irq_status &= (irq_status - 1);
554 schan = &sdev->channels[i];
555
556 spin_lock(&schan->vc.lock);
58152b0e
BW		 557
558 sdesc = schan->cur_desc;
559 if (!sdesc) {
560 spin_unlock(&schan->vc.lock);
561 return IRQ_HANDLED;
562 }
563
9b3b8171
BW		 564 int_type = sprd_dma_get_int_type(schan);
565 req_type = sprd_dma_get_req_type(schan);
566 sprd_dma_clear_int(schan);
567
97dbd6ea
EL		 568 /* cyclic mode schedule callback */
569 cyclic = schan->linklist.phy_addr ? true : false;
570 if (cyclic == true) {
571 vchan_cyclic_callback(&sdesc->vd);
572 } else {
573 /* Check if the dma request descriptor is done. */
574 trans_done = sprd_dma_check_trans_done(sdesc, int_type,
575 req_type);
576 if (trans_done == true) {
577 vchan_cookie_complete(&sdesc->vd);
578 schan->cur_desc = NULL;
579 sprd_dma_start(schan);
580 }
9b3b8171
BW		 581 }
582 spin_unlock(&schan->vc.lock);
583 }
584
585 return IRQ_HANDLED;
586}
587
588static int sprd_dma_alloc_chan_resources(struct dma_chan *chan)
589{
ffb5be7c 590 return pm_runtime_get_sync(chan->device->dev);
9b3b8171
BW		 591}
592
593static void sprd_dma_free_chan_resources(struct dma_chan *chan)
594{
595 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
596 unsigned long flags;
597
598 spin_lock_irqsave(&schan->vc.lock, flags);
599 sprd_dma_stop(schan);
600 spin_unlock_irqrestore(&schan->vc.lock, flags);
601
602 vchan_free_chan_resources(&schan->vc);
603 pm_runtime_put(chan->device->dev);
604}
605
606static enum dma_status sprd_dma_tx_status(struct dma_chan *chan,
607 dma_cookie_t cookie,
608 struct dma_tx_state *txstate)
609{
610 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
611 struct virt_dma_desc *vd;
612 unsigned long flags;
613 enum dma_status ret;
614 u32 pos;
615
616 ret = dma_cookie_status(chan, cookie, txstate);
617 if (ret == DMA_COMPLETE || !txstate)
618 return ret;
619
620 spin_lock_irqsave(&schan->vc.lock, flags);
621 vd = vchan_find_desc(&schan->vc, cookie);
622 if (vd) {
623 struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd);
624 struct sprd_dma_chn_hw *hw = &sdesc->chn_hw;
625
626 if (hw->trsc_len > 0)
627 pos = hw->trsc_len;
628 else if (hw->blk_len > 0)
629 pos = hw->blk_len;
630 else if (hw->frg_len > 0)
631 pos = hw->frg_len;
632 else
633 pos = 0;
634 } else if (schan->cur_desc && schan->cur_desc->vd.tx.cookie == cookie) {
16d0f85e 635 struct sprd_dma_desc *sdesc = schan->cur_desc;
d762ab33
EL		 636
637 if (sdesc->dir == DMA_DEV_TO_MEM)
638 pos = sprd_dma_get_dst_addr(schan);
639 else
640 pos = sprd_dma_get_src_addr(schan);
9b3b8171
BW		 641 } else {
642 pos = 0;
643 }
644 spin_unlock_irqrestore(&schan->vc.lock, flags);
645
646 dma_set_residue(txstate, pos);
647 return ret;
648}
649
650static void sprd_dma_issue_pending(struct dma_chan *chan)
651{
652 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
653 unsigned long flags;
654
655 spin_lock_irqsave(&schan->vc.lock, flags);
656 if (vchan_issue_pending(&schan->vc) && !schan->cur_desc)
657 sprd_dma_start(schan);
658 spin_unlock_irqrestore(&schan->vc.lock, flags);
659}
660
ca1b7d3d
EL		 661static int sprd_dma_get_datawidth(enum dma_slave_buswidth buswidth)
662{
663 switch (buswidth) {
664 case DMA_SLAVE_BUSWIDTH_1_BYTE:
665 case DMA_SLAVE_BUSWIDTH_2_BYTES:
666 case DMA_SLAVE_BUSWIDTH_4_BYTES:
667 case DMA_SLAVE_BUSWIDTH_8_BYTES:
668 return ffs(buswidth) - 1;
669
670 default:
671 return -EINVAL;
672 }
673}
674
675static int sprd_dma_get_step(enum dma_slave_buswidth buswidth)
676{
677 switch (buswidth) {
678 case DMA_SLAVE_BUSWIDTH_1_BYTE:
679 case DMA_SLAVE_BUSWIDTH_2_BYTES:
680 case DMA_SLAVE_BUSWIDTH_4_BYTES:
681 case DMA_SLAVE_BUSWIDTH_8_BYTES:
682 return buswidth;
683
684 default:
685 return -EINVAL;
686 }
687}
688
689static int sprd_dma_fill_desc(struct dma_chan *chan,
4ac69546
EL		 690 struct sprd_dma_chn_hw *hw,
691 unsigned int sglen, int sg_index,
ca1b7d3d
EL		 692 dma_addr_t src, dma_addr_t dst, u32 len,
693 enum dma_transfer_direction dir,
694 unsigned long flags,
695 struct dma_slave_config *slave_cfg)
9b3b8171
BW		 696{
697 struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan);
ca1b7d3d 698 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
770399df 699 enum sprd_dma_chn_mode chn_mode = schan->chn_mode;
ca1b7d3d
EL		 700 u32 req_mode = (flags >> SPRD_DMA_REQ_SHIFT) & SPRD_DMA_REQ_MODE_MASK;
701 u32 int_mode = flags & SPRD_DMA_INT_MASK;
702 int src_datawidth, dst_datawidth, src_step, dst_step;
703 u32 temp, fix_mode = 0, fix_en = 0;
704
705 if (dir == DMA_MEM_TO_DEV) {
706 src_step = sprd_dma_get_step(slave_cfg->src_addr_width);
707 if (src_step < 0) {
708 dev_err(sdev->dma_dev.dev, "invalid source step\n");
709 return src_step;
710 }
770399df
EL		 711
712 /*
713 * For 2-stage transfer, destination channel step can not be 0,
714 * since destination device is AON IRAM.
715 */
716 if (chn_mode == SPRD_DMA_DST_CHN0 ||
717 chn_mode == SPRD_DMA_DST_CHN1)
718 dst_step = src_step;
719 else
720 dst_step = SPRD_DMA_NONE_STEP;
9b3b8171 721 } else {
ca1b7d3d
EL		 722 dst_step = sprd_dma_get_step(slave_cfg->dst_addr_width);
723 if (dst_step < 0) {
724 dev_err(sdev->dma_dev.dev, "invalid destination step\n");
725 return dst_step;
726 }
727 src_step = SPRD_DMA_NONE_STEP;
9b3b8171
BW		 728 }
729
ca1b7d3d
EL		 730 src_datawidth = sprd_dma_get_datawidth(slave_cfg->src_addr_width);
731 if (src_datawidth < 0) {
732 dev_err(sdev->dma_dev.dev, "invalid source datawidth\n");
733 return src_datawidth;
9b3b8171
BW		 734 }
735
ca1b7d3d
EL		 736 dst_datawidth = sprd_dma_get_datawidth(slave_cfg->dst_addr_width);
737 if (dst_datawidth < 0) {
738 dev_err(sdev->dma_dev.dev, "invalid destination datawidth\n");
739 return dst_datawidth;
740 }
741
742 if (slave_cfg->slave_id)
743 schan->dev_id = slave_cfg->slave_id;
744
9b3b8171 745 hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET;
9b3b8171 746
ca1b7d3d
EL		 747 /*
748 * wrap_ptr and wrap_to will save the high 4 bits source address and
749 * destination address.
750 */
751 hw->wrap_ptr = (src >> SPRD_DMA_HIGH_ADDR_OFFSET) & SPRD_DMA_HIGH_ADDR_MASK;
752 hw->wrap_to = (dst >> SPRD_DMA_HIGH_ADDR_OFFSET) & SPRD_DMA_HIGH_ADDR_MASK;
753 hw->src_addr = src & SPRD_DMA_LOW_ADDR_MASK;
754 hw->des_addr = dst & SPRD_DMA_LOW_ADDR_MASK;
9b3b8171 755
ca1b7d3d
EL		 756 /*
757 * If the src step and dst step both are 0 or both are not 0, that means
758 * we can not enable the fix mode. If one is 0 and another one is not,
759 * we can enable the fix mode.
760 */
761 if ((src_step != 0 && dst_step != 0) || (src_step | dst_step) == 0) {
9b3b8171
BW		 762 fix_en = 0;
763 } else {
764 fix_en = 1;
765 if (src_step)
766 fix_mode = 1;
767 else
768 fix_mode = 0;
769 }
770
ca1b7d3d 771 hw->intc = int_mode | SPRD_DMA_CFG_ERR_INT_EN;
9b3b8171 772
ca1b7d3d
EL		 773 temp = src_datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET;
774 temp |= dst_datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET;
775 temp |= req_mode << SPRD_DMA_REQ_MODE_OFFSET;
776 temp |= fix_mode << SPRD_DMA_FIX_SEL_OFFSET;
777 temp |= fix_en << SPRD_DMA_FIX_EN_OFFSET;
778 temp |= slave_cfg->src_maxburst & SPRD_DMA_FRG_LEN_MASK;
779 hw->frg_len = temp;
9b3b8171 780
89d03b3c 781 hw->blk_len = slave_cfg->src_maxburst & SPRD_DMA_BLK_LEN_MASK;
ca1b7d3d 782 hw->trsc_len = len & SPRD_DMA_TRSC_LEN_MASK;
9b3b8171 783
ca1b7d3d
EL		 784 temp = (dst_step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_DEST_TRSF_STEP_OFFSET;
785 temp |= (src_step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_SRC_TRSF_STEP_OFFSET;
786 hw->trsf_step = temp;
9b3b8171 787
4ac69546
EL		 788 /* link-list configuration */
789 if (schan->linklist.phy_addr) {
4ac69546
EL		 790 hw->cfg |= SPRD_DMA_LINKLIST_EN;
791
792 /* link-list index */
13e89979
EL		 793 temp = sglen ? (sg_index + 1) % sglen : 0;
794
4ac69546
EL		 795 /* Next link-list configuration's physical address offset */
796 temp = temp * sizeof(*hw) + SPRD_DMA_CHN_SRC_ADDR;
797 /*
798 * Set the link-list pointer point to next link-list
799 * configuration's physical address.
800 */
801 hw->llist_ptr = schan->linklist.phy_addr + temp;
802 } else {
803 hw->llist_ptr = 0;
804 }
805
ca1b7d3d
EL		 806 hw->frg_step = 0;
807 hw->src_blk_step = 0;
808 hw->des_blk_step = 0;
809 return 0;
810}
9b3b8171 811
4ac69546
EL		 812static int sprd_dma_fill_linklist_desc(struct dma_chan *chan,
813 unsigned int sglen, int sg_index,
814 dma_addr_t src, dma_addr_t dst, u32 len,
815 enum dma_transfer_direction dir,
816 unsigned long flags,
817 struct dma_slave_config *slave_cfg)
818{
819 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
820 struct sprd_dma_chn_hw *hw;
821
822 if (!schan->linklist.virt_addr)
823 return -EINVAL;
824
825 hw = (struct sprd_dma_chn_hw *)(schan->linklist.virt_addr +
826 sg_index * sizeof(*hw));
827
828 return sprd_dma_fill_desc(chan, hw, sglen, sg_index, src, dst, len,
829 dir, flags, slave_cfg);
830}
831
1ab8da11 832static struct dma_async_tx_descriptor *
9b3b8171
BW		 833sprd_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
834 size_t len, unsigned long flags)
835{
836 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
837 struct sprd_dma_desc *sdesc;
32fa2013
EL		 838 struct sprd_dma_chn_hw *hw;
839 enum sprd_dma_datawidth datawidth;
840 u32 step, temp;
9b3b8171 841
9b3b8171
BW		 842 sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT);
843 if (!sdesc)
844 return NULL;
9b3b8171 845
32fa2013 846 hw = &sdesc->chn_hw;
9b3b8171 847
32fa2013
EL		 848 hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET;
849 hw->intc = SPRD_DMA_TRANS_INT | SPRD_DMA_CFG_ERR_INT_EN;
850 hw->src_addr = src & SPRD_DMA_LOW_ADDR_MASK;
851 hw->des_addr = dest & SPRD_DMA_LOW_ADDR_MASK;
852 hw->wrap_ptr = (src >> SPRD_DMA_HIGH_ADDR_OFFSET) &
853 SPRD_DMA_HIGH_ADDR_MASK;
854 hw->wrap_to = (dest >> SPRD_DMA_HIGH_ADDR_OFFSET) &
855 SPRD_DMA_HIGH_ADDR_MASK;
856
857 if (IS_ALIGNED(len, 8)) {
858 datawidth = SPRD_DMA_DATAWIDTH_8_BYTES;
859 step = SPRD_DMA_DWORD_STEP;
860 } else if (IS_ALIGNED(len, 4)) {
861 datawidth = SPRD_DMA_DATAWIDTH_4_BYTES;
862 step = SPRD_DMA_WORD_STEP;
863 } else if (IS_ALIGNED(len, 2)) {
864 datawidth = SPRD_DMA_DATAWIDTH_2_BYTES;
865 step = SPRD_DMA_SHORT_STEP;
866 } else {
867 datawidth = SPRD_DMA_DATAWIDTH_1_BYTE;
868 step = SPRD_DMA_BYTE_STEP;
9b3b8171
BW		 869 }
870
32fa2013
EL		 871 temp = datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET;
872 temp |= datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET;
873 temp |= SPRD_DMA_TRANS_REQ << SPRD_DMA_REQ_MODE_OFFSET;
874 temp |= len & SPRD_DMA_FRG_LEN_MASK;
875 hw->frg_len = temp;
9b3b8171 876
32fa2013
EL		 877 hw->blk_len = len & SPRD_DMA_BLK_LEN_MASK;
878 hw->trsc_len = len & SPRD_DMA_TRSC_LEN_MASK;
9b3b8171 879
32fa2013
EL		 880 temp = (step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_DEST_TRSF_STEP_OFFSET;
881 temp |= (step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_SRC_TRSF_STEP_OFFSET;
882 hw->trsf_step = temp;
883
9b3b8171 884 return vchan_tx_prep(&schan->vc, &sdesc->vd, flags);
9b3b8171
BW		 885}
886
1ab8da11 887static struct dma_async_tx_descriptor *
ca1b7d3d
EL		 888sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
889 unsigned int sglen, enum dma_transfer_direction dir,
890 unsigned long flags, void *context)
9b3b8171
BW		 891{
892 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
ca1b7d3d
EL		 893 struct dma_slave_config *slave_cfg = &schan->slave_cfg;
894 dma_addr_t src = 0, dst = 0;
9b3b8171 895 struct sprd_dma_desc *sdesc;
ca1b7d3d
EL		 896 struct scatterlist *sg;
897 u32 len = 0;
898 int ret, i;
899
4ac69546 900 if (!is_slave_direction(dir))
ca1b7d3d 901 return NULL;
9b3b8171 902
4ac69546
EL		 903 if (context) {
904 struct sprd_dma_linklist *ll_cfg =
905 (struct sprd_dma_linklist *)context;
906
907 schan->linklist.phy_addr = ll_cfg->phy_addr;
908 schan->linklist.virt_addr = ll_cfg->virt_addr;
909 } else {
910 schan->linklist.phy_addr = 0;
911 schan->linklist.virt_addr = 0;
912 }
913
9b3b8171
BW		 914 sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT);
915 if (!sdesc)
916 return NULL;
917
d762ab33
EL		 918 sdesc->dir = dir;
919
ca1b7d3d
EL		 920 for_each_sg(sgl, sg, sglen, i) {
921 len = sg_dma_len(sg);
922
923 if (dir == DMA_MEM_TO_DEV) {
924 src = sg_dma_address(sg);
925 dst = slave_cfg->dst_addr;
926 } else {
927 src = slave_cfg->src_addr;
928 dst = sg_dma_address(sg);
929 }
4ac69546
EL		 930
931 /*
932 * The link-list mode needs at least 2 link-list
933 * configurations. If there is only one sg, it doesn't
934 * need to fill the link-list configuration.
935 */
936 if (sglen < 2)
937 break;
938
939 ret = sprd_dma_fill_linklist_desc(chan, sglen, i, src, dst, len,
940 dir, flags, slave_cfg);
941 if (ret) {
942 kfree(sdesc);
943 return NULL;
944 }
ca1b7d3d
EL		 945 }
946
770399df
EL		 947 /* Set channel mode and trigger mode for 2-stage transfer */
948 schan->chn_mode =
949 (flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK;
950 schan->trg_mode =
951 (flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK;
952
4ac69546
EL		 953 ret = sprd_dma_fill_desc(chan, &sdesc->chn_hw, 0, 0, src, dst, len,
954 dir, flags, slave_cfg);
9b3b8171
BW		 955 if (ret) {
956 kfree(sdesc);
957 return NULL;
958 }
959
960 return vchan_tx_prep(&schan->vc, &sdesc->vd, flags);
961}
962
ca1b7d3d
EL		 963static int sprd_dma_slave_config(struct dma_chan *chan,
964 struct dma_slave_config *config)
965{
966 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
967 struct dma_slave_config *slave_cfg = &schan->slave_cfg;
968
ca1b7d3d
EL		 969 memcpy(slave_cfg, config, sizeof(*config));
970 return 0;
971}
972
9b3b8171
BW		 973static int sprd_dma_pause(struct dma_chan *chan)
974{
975 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
976 unsigned long flags;
977
978 spin_lock_irqsave(&schan->vc.lock, flags);
979 sprd_dma_pause_resume(schan, true);
980 spin_unlock_irqrestore(&schan->vc.lock, flags);
981
982 return 0;
983}
984
985static int sprd_dma_resume(struct dma_chan *chan)
986{
987 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
988 unsigned long flags;
989
990 spin_lock_irqsave(&schan->vc.lock, flags);
991 sprd_dma_pause_resume(schan, false);
992 spin_unlock_irqrestore(&schan->vc.lock, flags);
993
994 return 0;
995}
996
997static int sprd_dma_terminate_all(struct dma_chan *chan)
998{
999 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
1000 unsigned long flags;
1001 LIST_HEAD(head);
1002
1003 spin_lock_irqsave(&schan->vc.lock, flags);
1004 sprd_dma_stop(schan);
1005
1006 vchan_get_all_descriptors(&schan->vc, &head);
1007 spin_unlock_irqrestore(&schan->vc.lock, flags);
1008
1009 vchan_dma_desc_free_list(&schan->vc, &head);
1010 return 0;
1011}
1012
1013static void sprd_dma_free_desc(struct virt_dma_desc *vd)
1014{
1015 struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd);
1016
1017 kfree(sdesc);
1018}
1019
1020static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param)
1021{
1022 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
ffb5be7c 1023 u32 slave_id = *(u32 *)param;
9b3b8171 1024
ffb5be7c
BW		 1025 schan->dev_id = slave_id;
1026 return true;
9b3b8171
BW		 1027}
1028
1029static int sprd_dma_probe(struct platform_device *pdev)
1030{
1031 struct device_node *np = pdev->dev.of_node;
1032 struct sprd_dma_dev *sdev;
1033 struct sprd_dma_chn *dma_chn;
1034 struct resource *res;
1035 u32 chn_count;
1036 int ret, i;
1037
1038 ret = device_property_read_u32(&pdev->dev, "#dma-channels", &chn_count);
1039 if (ret) {
1040 dev_err(&pdev->dev, "get dma channels count failed\n");
1041 return ret;
1042 }
1043
0ed2dd03
KC		 1044 sdev = devm_kzalloc(&pdev->dev,
1045 struct_size(sdev, channels, chn_count),
9b3b8171
BW		 1046 GFP_KERNEL);
1047 if (!sdev)
1048 return -ENOMEM;
1049
1050 sdev->clk = devm_clk_get(&pdev->dev, "enable");
1051 if (IS_ERR(sdev->clk)) {
1052 dev_err(&pdev->dev, "get enable clock failed\n");
1053 return PTR_ERR(sdev->clk);
1054 }
1055
1056 /* ashb clock is optional for AGCP DMA */
1057 sdev->ashb_clk = devm_clk_get(&pdev->dev, "ashb_eb");
1058 if (IS_ERR(sdev->ashb_clk))
1059 dev_warn(&pdev->dev, "no optional ashb eb clock\n");
1060
1061 /*
1062 * We have three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
1063 * DMA controller, it can or do not request the irq, which will save
1064 * system power without resuming system by DMA interrupts if AGCP DMA
1065 * does not request the irq. Thus the DMA interrupts property should
1066 * be optional.
1067 */
1068 sdev->irq = platform_get_irq(pdev, 0);
1069 if (sdev->irq > 0) {
1070 ret = devm_request_irq(&pdev->dev, sdev->irq, dma_irq_handle,
1071 0, "sprd_dma", (void *)sdev);
1072 if (ret < 0) {
1073 dev_err(&pdev->dev, "request dma irq failed\n");
1074 return ret;
1075 }
1076 } else {
1077 dev_warn(&pdev->dev, "no interrupts for the dma controller\n");
1078 }
1079
1080 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
e7f063ae 1081 sdev->glb_base = devm_ioremap_resource(&pdev->dev, res);
fd8d26ad
DC		 1082 if (IS_ERR(sdev->glb_base))
1083 return PTR_ERR(sdev->glb_base);
9b3b8171
BW		 1084
1085 dma_cap_set(DMA_MEMCPY, sdev->dma_dev.cap_mask);
1086 sdev->total_chns = chn_count;
1087 sdev->dma_dev.chancnt = chn_count;
1088 INIT_LIST_HEAD(&sdev->dma_dev.channels);
1089 INIT_LIST_HEAD(&sdev->dma_dev.global_node);
1090 sdev->dma_dev.dev = &pdev->dev;
1091 sdev->dma_dev.device_alloc_chan_resources = sprd_dma_alloc_chan_resources;
1092 sdev->dma_dev.device_free_chan_resources = sprd_dma_free_chan_resources;
1093 sdev->dma_dev.device_tx_status = sprd_dma_tx_status;
1094 sdev->dma_dev.device_issue_pending = sprd_dma_issue_pending;
1095 sdev->dma_dev.device_prep_dma_memcpy = sprd_dma_prep_dma_memcpy;
ca1b7d3d
EL		 1096 sdev->dma_dev.device_prep_slave_sg = sprd_dma_prep_slave_sg;
1097 sdev->dma_dev.device_config = sprd_dma_slave_config;
9b3b8171
BW		 1098 sdev->dma_dev.device_pause = sprd_dma_pause;
1099 sdev->dma_dev.device_resume = sprd_dma_resume;
1100 sdev->dma_dev.device_terminate_all = sprd_dma_terminate_all;
1101
1102 for (i = 0; i < chn_count; i++) {
1103 dma_chn = &sdev->channels[i];
1104 dma_chn->chn_num = i;
1105 dma_chn->cur_desc = NULL;
1106 /* get each channel's registers base address. */
1107 dma_chn->chn_base = sdev->glb_base + SPRD_DMA_CHN_REG_OFFSET +
1108 SPRD_DMA_CHN_REG_LENGTH * i;
1109
1110 dma_chn->vc.desc_free = sprd_dma_free_desc;
1111 vchan_init(&dma_chn->vc, &sdev->dma_dev);
1112 }
1113
1114 platform_set_drvdata(pdev, sdev);
1115 ret = sprd_dma_enable(sdev);
1116 if (ret)
1117 return ret;
1118
1119 pm_runtime_set_active(&pdev->dev);
1120 pm_runtime_enable(&pdev->dev);
1121
1122 ret = pm_runtime_get_sync(&pdev->dev);
1123 if (ret < 0)
1124 goto err_rpm;
1125
1126 ret = dma_async_device_register(&sdev->dma_dev);
1127 if (ret < 0) {
1128 dev_err(&pdev->dev, "register dma device failed:%d\n", ret);
1129 goto err_register;
1130 }
1131
1132 sprd_dma_info.dma_cap = sdev->dma_dev.cap_mask;
1133 ret = of_dma_controller_register(np, of_dma_simple_xlate,
1134 &sprd_dma_info);
1135 if (ret)
1136 goto err_of_register;
1137
1138 pm_runtime_put(&pdev->dev);
1139 return 0;
1140
1141err_of_register:
1142 dma_async_device_unregister(&sdev->dma_dev);
1143err_register:
1144 pm_runtime_put_noidle(&pdev->dev);
1145 pm_runtime_disable(&pdev->dev);
1146err_rpm:
1147 sprd_dma_disable(sdev);
1148 return ret;
1149}
1150
1151static int sprd_dma_remove(struct platform_device *pdev)
1152{
1153 struct sprd_dma_dev *sdev = platform_get_drvdata(pdev);
1154 struct sprd_dma_chn *c, *cn;
1155 int ret;
1156
1157 ret = pm_runtime_get_sync(&pdev->dev);
1158 if (ret < 0)
1159 return ret;
1160
1161 /* explicitly free the irq */
1162 if (sdev->irq > 0)
1163 devm_free_irq(&pdev->dev, sdev->irq, sdev);
1164
1165 list_for_each_entry_safe(c, cn, &sdev->dma_dev.channels,
1166 vc.chan.device_node) {
1167 list_del(&c->vc.chan.device_node);
1168 tasklet_kill(&c->vc.task);
1169 }
1170
1171 of_dma_controller_free(pdev->dev.of_node);
1172 dma_async_device_unregister(&sdev->dma_dev);
1173 sprd_dma_disable(sdev);
1174
1175 pm_runtime_put_noidle(&pdev->dev);
1176 pm_runtime_disable(&pdev->dev);
1177 return 0;
1178}
1179
1180static const struct of_device_id sprd_dma_match[] = {
1181 { .compatible = "sprd,sc9860-dma", },
1182 {},
1183};
1184
1185static int __maybe_unused sprd_dma_runtime_suspend(struct device *dev)
1186{
1187 struct sprd_dma_dev *sdev = dev_get_drvdata(dev);
1188
1189 sprd_dma_disable(sdev);
1190 return 0;
1191}
1192
1193static int __maybe_unused sprd_dma_runtime_resume(struct device *dev)
1194{
1195 struct sprd_dma_dev *sdev = dev_get_drvdata(dev);
1196 int ret;
1197
1198 ret = sprd_dma_enable(sdev);
1199 if (ret)
1200 dev_err(sdev->dma_dev.dev, "enable dma failed\n");
1201
1202 return ret;
1203}
1204
1205static const struct dev_pm_ops sprd_dma_pm_ops = {
1206 SET_RUNTIME_PM_OPS(sprd_dma_runtime_suspend,
1207 sprd_dma_runtime_resume,
1208 NULL)
1209};
1210
1211static struct platform_driver sprd_dma_driver = {
1212 .probe = sprd_dma_probe,
1213 .remove = sprd_dma_remove,
1214 .driver = {
1215 .name = "sprd-dma",
1216 .of_match_table = sprd_dma_match,
1217 .pm = &sprd_dma_pm_ops,
1218 },
1219};
1220module_platform_driver(sprd_dma_driver);
1221
1222MODULE_LICENSE("GPL v2");
1223MODULE_DESCRIPTION("DMA driver for Spreadtrum");
1224MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
53197123 1225MODULE_AUTHOR("Eric Long <eric.long@spreadtrum.com>");
9b3b8171 1226MODULE_ALIAS("platform:sprd-dma");
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