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8d318a50 | 1 | /* |
d49278e3 PF |
2 | * Copyright (C) Ericsson AB 2007-2008 |
3 | * Copyright (C) ST-Ericsson SA 2008-2010 | |
661385f9 | 4 | * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson |
767a9675 | 5 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson |
8d318a50 | 6 | * License terms: GNU General Public License (GPL) version 2 |
8d318a50 LW |
7 | */ |
8 | ||
b7f080cf | 9 | #include <linux/dma-mapping.h> |
8d318a50 LW |
10 | #include <linux/kernel.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/dmaengine.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
698e4732 | 16 | #include <linux/err.h> |
f4b89764 | 17 | #include <linux/amba/bus.h> |
8d318a50 LW |
18 | |
19 | #include <plat/ste_dma40.h> | |
20 | ||
21 | #include "ste_dma40_ll.h" | |
22 | ||
23 | #define D40_NAME "dma40" | |
24 | ||
25 | #define D40_PHY_CHAN -1 | |
26 | ||
27 | /* For masking out/in 2 bit channel positions */ | |
28 | #define D40_CHAN_POS(chan) (2 * (chan / 2)) | |
29 | #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan)) | |
30 | ||
31 | /* Maximum iterations taken before giving up suspending a channel */ | |
32 | #define D40_SUSPEND_MAX_IT 500 | |
33 | ||
508849ad LW |
34 | /* Hardware requirement on LCLA alignment */ |
35 | #define LCLA_ALIGNMENT 0x40000 | |
698e4732 JA |
36 | |
37 | /* Max number of links per event group */ | |
38 | #define D40_LCLA_LINK_PER_EVENT_GRP 128 | |
39 | #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP | |
40 | ||
508849ad LW |
41 | /* Attempts before giving up to trying to get pages that are aligned */ |
42 | #define MAX_LCLA_ALLOC_ATTEMPTS 256 | |
43 | ||
44 | /* Bit markings for allocation map */ | |
8d318a50 LW |
45 | #define D40_ALLOC_FREE (1 << 31) |
46 | #define D40_ALLOC_PHY (1 << 30) | |
47 | #define D40_ALLOC_LOG_FREE 0 | |
48 | ||
8d318a50 LW |
49 | /** |
50 | * enum 40_command - The different commands and/or statuses. | |
51 | * | |
52 | * @D40_DMA_STOP: DMA channel command STOP or status STOPPED, | |
53 | * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN. | |
54 | * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible. | |
55 | * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED. | |
56 | */ | |
57 | enum d40_command { | |
58 | D40_DMA_STOP = 0, | |
59 | D40_DMA_RUN = 1, | |
60 | D40_DMA_SUSPEND_REQ = 2, | |
61 | D40_DMA_SUSPENDED = 3 | |
62 | }; | |
63 | ||
64 | /** | |
65 | * struct d40_lli_pool - Structure for keeping LLIs in memory | |
66 | * | |
67 | * @base: Pointer to memory area when the pre_alloc_lli's are not large | |
68 | * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if | |
69 | * pre_alloc_lli is used. | |
b00f938c | 70 | * @dma_addr: DMA address, if mapped |
8d318a50 LW |
71 | * @size: The size in bytes of the memory at base or the size of pre_alloc_lli. |
72 | * @pre_alloc_lli: Pre allocated area for the most common case of transfers, | |
73 | * one buffer to one buffer. | |
74 | */ | |
75 | struct d40_lli_pool { | |
76 | void *base; | |
508849ad | 77 | int size; |
b00f938c | 78 | dma_addr_t dma_addr; |
8d318a50 | 79 | /* Space for dst and src, plus an extra for padding */ |
508849ad | 80 | u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)]; |
8d318a50 LW |
81 | }; |
82 | ||
83 | /** | |
84 | * struct d40_desc - A descriptor is one DMA job. | |
85 | * | |
86 | * @lli_phy: LLI settings for physical channel. Both src and dst= | |
87 | * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if | |
88 | * lli_len equals one. | |
89 | * @lli_log: Same as above but for logical channels. | |
90 | * @lli_pool: The pool with two entries pre-allocated. | |
941b77a3 | 91 | * @lli_len: Number of llis of current descriptor. |
25985edc | 92 | * @lli_current: Number of transferred llis. |
698e4732 | 93 | * @lcla_alloc: Number of LCLA entries allocated. |
8d318a50 LW |
94 | * @txd: DMA engine struct. Used for among other things for communication |
95 | * during a transfer. | |
96 | * @node: List entry. | |
8d318a50 | 97 | * @is_in_client_list: true if the client owns this descriptor. |
aa182ae2 | 98 | * the previous one. |
8d318a50 LW |
99 | * |
100 | * This descriptor is used for both logical and physical transfers. | |
101 | */ | |
8d318a50 LW |
102 | struct d40_desc { |
103 | /* LLI physical */ | |
104 | struct d40_phy_lli_bidir lli_phy; | |
105 | /* LLI logical */ | |
106 | struct d40_log_lli_bidir lli_log; | |
107 | ||
108 | struct d40_lli_pool lli_pool; | |
941b77a3 | 109 | int lli_len; |
698e4732 JA |
110 | int lli_current; |
111 | int lcla_alloc; | |
8d318a50 LW |
112 | |
113 | struct dma_async_tx_descriptor txd; | |
114 | struct list_head node; | |
115 | ||
8d318a50 | 116 | bool is_in_client_list; |
0c842b55 | 117 | bool cyclic; |
8d318a50 LW |
118 | }; |
119 | ||
120 | /** | |
121 | * struct d40_lcla_pool - LCLA pool settings and data. | |
122 | * | |
508849ad LW |
123 | * @base: The virtual address of LCLA. 18 bit aligned. |
124 | * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used. | |
125 | * This pointer is only there for clean-up on error. | |
126 | * @pages: The number of pages needed for all physical channels. | |
127 | * Only used later for clean-up on error | |
8d318a50 | 128 | * @lock: Lock to protect the content in this struct. |
698e4732 | 129 | * @alloc_map: big map over which LCLA entry is own by which job. |
8d318a50 LW |
130 | */ |
131 | struct d40_lcla_pool { | |
132 | void *base; | |
026cbc42 | 133 | dma_addr_t dma_addr; |
508849ad LW |
134 | void *base_unaligned; |
135 | int pages; | |
8d318a50 | 136 | spinlock_t lock; |
698e4732 | 137 | struct d40_desc **alloc_map; |
8d318a50 LW |
138 | }; |
139 | ||
140 | /** | |
141 | * struct d40_phy_res - struct for handling eventlines mapped to physical | |
142 | * channels. | |
143 | * | |
144 | * @lock: A lock protection this entity. | |
145 | * @num: The physical channel number of this entity. | |
146 | * @allocated_src: Bit mapped to show which src event line's are mapped to | |
147 | * this physical channel. Can also be free or physically allocated. | |
148 | * @allocated_dst: Same as for src but is dst. | |
149 | * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as | |
767a9675 | 150 | * event line number. |
8d318a50 LW |
151 | */ |
152 | struct d40_phy_res { | |
153 | spinlock_t lock; | |
154 | int num; | |
155 | u32 allocated_src; | |
156 | u32 allocated_dst; | |
157 | }; | |
158 | ||
159 | struct d40_base; | |
160 | ||
161 | /** | |
162 | * struct d40_chan - Struct that describes a channel. | |
163 | * | |
164 | * @lock: A spinlock to protect this struct. | |
165 | * @log_num: The logical number, if any of this channel. | |
166 | * @completed: Starts with 1, after first interrupt it is set to dma engine's | |
167 | * current cookie. | |
168 | * @pending_tx: The number of pending transfers. Used between interrupt handler | |
169 | * and tasklet. | |
170 | * @busy: Set to true when transfer is ongoing on this channel. | |
2a614340 JA |
171 | * @phy_chan: Pointer to physical channel which this instance runs on. If this |
172 | * point is NULL, then the channel is not allocated. | |
8d318a50 LW |
173 | * @chan: DMA engine handle. |
174 | * @tasklet: Tasklet that gets scheduled from interrupt context to complete a | |
175 | * transfer and call client callback. | |
176 | * @client: Cliented owned descriptor list. | |
da063d26 | 177 | * @pending_queue: Submitted jobs, to be issued by issue_pending() |
8d318a50 LW |
178 | * @active: Active descriptor. |
179 | * @queue: Queued jobs. | |
8d318a50 | 180 | * @dma_cfg: The client configuration of this dma channel. |
ce2ca125 | 181 | * @configured: whether the dma_cfg configuration is valid |
8d318a50 LW |
182 | * @base: Pointer to the device instance struct. |
183 | * @src_def_cfg: Default cfg register setting for src. | |
184 | * @dst_def_cfg: Default cfg register setting for dst. | |
185 | * @log_def: Default logical channel settings. | |
186 | * @lcla: Space for one dst src pair for logical channel transfers. | |
187 | * @lcpa: Pointer to dst and src lcpa settings. | |
ae752bf4 | 188 | * @runtime_addr: runtime configured address. |
189 | * @runtime_direction: runtime configured direction. | |
8d318a50 LW |
190 | * |
191 | * This struct can either "be" a logical or a physical channel. | |
192 | */ | |
193 | struct d40_chan { | |
194 | spinlock_t lock; | |
195 | int log_num; | |
196 | /* ID of the most recent completed transfer */ | |
197 | int completed; | |
198 | int pending_tx; | |
199 | bool busy; | |
200 | struct d40_phy_res *phy_chan; | |
201 | struct dma_chan chan; | |
202 | struct tasklet_struct tasklet; | |
203 | struct list_head client; | |
a8f3067b | 204 | struct list_head pending_queue; |
8d318a50 LW |
205 | struct list_head active; |
206 | struct list_head queue; | |
8d318a50 | 207 | struct stedma40_chan_cfg dma_cfg; |
ce2ca125 | 208 | bool configured; |
8d318a50 LW |
209 | struct d40_base *base; |
210 | /* Default register configurations */ | |
211 | u32 src_def_cfg; | |
212 | u32 dst_def_cfg; | |
213 | struct d40_def_lcsp log_def; | |
8d318a50 | 214 | struct d40_log_lli_full *lcpa; |
95e1400f LW |
215 | /* Runtime reconfiguration */ |
216 | dma_addr_t runtime_addr; | |
217 | enum dma_data_direction runtime_direction; | |
8d318a50 LW |
218 | }; |
219 | ||
220 | /** | |
221 | * struct d40_base - The big global struct, one for each probe'd instance. | |
222 | * | |
223 | * @interrupt_lock: Lock used to make sure one interrupt is handle a time. | |
224 | * @execmd_lock: Lock for execute command usage since several channels share | |
225 | * the same physical register. | |
226 | * @dev: The device structure. | |
227 | * @virtbase: The virtual base address of the DMA's register. | |
f4185592 | 228 | * @rev: silicon revision detected. |
8d318a50 LW |
229 | * @clk: Pointer to the DMA clock structure. |
230 | * @phy_start: Physical memory start of the DMA registers. | |
231 | * @phy_size: Size of the DMA register map. | |
232 | * @irq: The IRQ number. | |
233 | * @num_phy_chans: The number of physical channels. Read from HW. This | |
234 | * is the number of available channels for this driver, not counting "Secure | |
235 | * mode" allocated physical channels. | |
236 | * @num_log_chans: The number of logical channels. Calculated from | |
237 | * num_phy_chans. | |
238 | * @dma_both: dma_device channels that can do both memcpy and slave transfers. | |
239 | * @dma_slave: dma_device channels that can do only do slave transfers. | |
240 | * @dma_memcpy: dma_device channels that can do only do memcpy transfers. | |
8d318a50 LW |
241 | * @log_chans: Room for all possible logical channels in system. |
242 | * @lookup_log_chans: Used to map interrupt number to logical channel. Points | |
243 | * to log_chans entries. | |
244 | * @lookup_phy_chans: Used to map interrupt number to physical channel. Points | |
245 | * to phy_chans entries. | |
246 | * @plat_data: Pointer to provided platform_data which is the driver | |
247 | * configuration. | |
248 | * @phy_res: Vector containing all physical channels. | |
249 | * @lcla_pool: lcla pool settings and data. | |
250 | * @lcpa_base: The virtual mapped address of LCPA. | |
251 | * @phy_lcpa: The physical address of the LCPA. | |
252 | * @lcpa_size: The size of the LCPA area. | |
c675b1b4 | 253 | * @desc_slab: cache for descriptors. |
8d318a50 LW |
254 | */ |
255 | struct d40_base { | |
256 | spinlock_t interrupt_lock; | |
257 | spinlock_t execmd_lock; | |
258 | struct device *dev; | |
259 | void __iomem *virtbase; | |
f4185592 | 260 | u8 rev:4; |
8d318a50 LW |
261 | struct clk *clk; |
262 | phys_addr_t phy_start; | |
263 | resource_size_t phy_size; | |
264 | int irq; | |
265 | int num_phy_chans; | |
266 | int num_log_chans; | |
267 | struct dma_device dma_both; | |
268 | struct dma_device dma_slave; | |
269 | struct dma_device dma_memcpy; | |
270 | struct d40_chan *phy_chans; | |
271 | struct d40_chan *log_chans; | |
272 | struct d40_chan **lookup_log_chans; | |
273 | struct d40_chan **lookup_phy_chans; | |
274 | struct stedma40_platform_data *plat_data; | |
275 | /* Physical half channels */ | |
276 | struct d40_phy_res *phy_res; | |
277 | struct d40_lcla_pool lcla_pool; | |
278 | void *lcpa_base; | |
279 | dma_addr_t phy_lcpa; | |
280 | resource_size_t lcpa_size; | |
c675b1b4 | 281 | struct kmem_cache *desc_slab; |
8d318a50 LW |
282 | }; |
283 | ||
284 | /** | |
285 | * struct d40_interrupt_lookup - lookup table for interrupt handler | |
286 | * | |
287 | * @src: Interrupt mask register. | |
288 | * @clr: Interrupt clear register. | |
289 | * @is_error: true if this is an error interrupt. | |
290 | * @offset: start delta in the lookup_log_chans in d40_base. If equals to | |
291 | * D40_PHY_CHAN, the lookup_phy_chans shall be used instead. | |
292 | */ | |
293 | struct d40_interrupt_lookup { | |
294 | u32 src; | |
295 | u32 clr; | |
296 | bool is_error; | |
297 | int offset; | |
298 | }; | |
299 | ||
300 | /** | |
301 | * struct d40_reg_val - simple lookup struct | |
302 | * | |
303 | * @reg: The register. | |
304 | * @val: The value that belongs to the register in reg. | |
305 | */ | |
306 | struct d40_reg_val { | |
307 | unsigned int reg; | |
308 | unsigned int val; | |
309 | }; | |
310 | ||
262d2915 RV |
311 | static struct device *chan2dev(struct d40_chan *d40c) |
312 | { | |
313 | return &d40c->chan.dev->device; | |
314 | } | |
315 | ||
724a8577 RV |
316 | static bool chan_is_physical(struct d40_chan *chan) |
317 | { | |
318 | return chan->log_num == D40_PHY_CHAN; | |
319 | } | |
320 | ||
321 | static bool chan_is_logical(struct d40_chan *chan) | |
322 | { | |
323 | return !chan_is_physical(chan); | |
324 | } | |
325 | ||
8ca84687 RV |
326 | static void __iomem *chan_base(struct d40_chan *chan) |
327 | { | |
328 | return chan->base->virtbase + D40_DREG_PCBASE + | |
329 | chan->phy_chan->num * D40_DREG_PCDELTA; | |
330 | } | |
331 | ||
6db5a8ba RV |
332 | #define d40_err(dev, format, arg...) \ |
333 | dev_err(dev, "[%s] " format, __func__, ## arg) | |
334 | ||
335 | #define chan_err(d40c, format, arg...) \ | |
336 | d40_err(chan2dev(d40c), format, ## arg) | |
337 | ||
b00f938c | 338 | static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d, |
dbd88788 | 339 | int lli_len) |
8d318a50 | 340 | { |
dbd88788 | 341 | bool is_log = chan_is_logical(d40c); |
8d318a50 LW |
342 | u32 align; |
343 | void *base; | |
344 | ||
345 | if (is_log) | |
346 | align = sizeof(struct d40_log_lli); | |
347 | else | |
348 | align = sizeof(struct d40_phy_lli); | |
349 | ||
350 | if (lli_len == 1) { | |
351 | base = d40d->lli_pool.pre_alloc_lli; | |
352 | d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli); | |
353 | d40d->lli_pool.base = NULL; | |
354 | } else { | |
594ece4d | 355 | d40d->lli_pool.size = lli_len * 2 * align; |
8d318a50 LW |
356 | |
357 | base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); | |
358 | d40d->lli_pool.base = base; | |
359 | ||
360 | if (d40d->lli_pool.base == NULL) | |
361 | return -ENOMEM; | |
362 | } | |
363 | ||
364 | if (is_log) { | |
d924abad | 365 | d40d->lli_log.src = PTR_ALIGN(base, align); |
594ece4d | 366 | d40d->lli_log.dst = d40d->lli_log.src + lli_len; |
b00f938c RV |
367 | |
368 | d40d->lli_pool.dma_addr = 0; | |
8d318a50 | 369 | } else { |
d924abad | 370 | d40d->lli_phy.src = PTR_ALIGN(base, align); |
594ece4d | 371 | d40d->lli_phy.dst = d40d->lli_phy.src + lli_len; |
b00f938c RV |
372 | |
373 | d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev, | |
374 | d40d->lli_phy.src, | |
375 | d40d->lli_pool.size, | |
376 | DMA_TO_DEVICE); | |
377 | ||
378 | if (dma_mapping_error(d40c->base->dev, | |
379 | d40d->lli_pool.dma_addr)) { | |
380 | kfree(d40d->lli_pool.base); | |
381 | d40d->lli_pool.base = NULL; | |
382 | d40d->lli_pool.dma_addr = 0; | |
383 | return -ENOMEM; | |
384 | } | |
8d318a50 LW |
385 | } |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
b00f938c | 390 | static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d) |
8d318a50 | 391 | { |
b00f938c RV |
392 | if (d40d->lli_pool.dma_addr) |
393 | dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr, | |
394 | d40d->lli_pool.size, DMA_TO_DEVICE); | |
395 | ||
8d318a50 LW |
396 | kfree(d40d->lli_pool.base); |
397 | d40d->lli_pool.base = NULL; | |
398 | d40d->lli_pool.size = 0; | |
399 | d40d->lli_log.src = NULL; | |
400 | d40d->lli_log.dst = NULL; | |
401 | d40d->lli_phy.src = NULL; | |
402 | d40d->lli_phy.dst = NULL; | |
8d318a50 LW |
403 | } |
404 | ||
698e4732 JA |
405 | static int d40_lcla_alloc_one(struct d40_chan *d40c, |
406 | struct d40_desc *d40d) | |
407 | { | |
408 | unsigned long flags; | |
409 | int i; | |
410 | int ret = -EINVAL; | |
411 | int p; | |
412 | ||
413 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); | |
414 | ||
415 | p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP; | |
416 | ||
417 | /* | |
418 | * Allocate both src and dst at the same time, therefore the half | |
419 | * start on 1 since 0 can't be used since zero is used as end marker. | |
420 | */ | |
421 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { | |
422 | if (!d40c->base->lcla_pool.alloc_map[p + i]) { | |
423 | d40c->base->lcla_pool.alloc_map[p + i] = d40d; | |
424 | d40d->lcla_alloc++; | |
425 | ret = i; | |
426 | break; | |
427 | } | |
428 | } | |
429 | ||
430 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); | |
431 | ||
432 | return ret; | |
433 | } | |
434 | ||
435 | static int d40_lcla_free_all(struct d40_chan *d40c, | |
436 | struct d40_desc *d40d) | |
437 | { | |
438 | unsigned long flags; | |
439 | int i; | |
440 | int ret = -EINVAL; | |
441 | ||
724a8577 | 442 | if (chan_is_physical(d40c)) |
698e4732 JA |
443 | return 0; |
444 | ||
445 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); | |
446 | ||
447 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { | |
448 | if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * | |
449 | D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) { | |
450 | d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * | |
451 | D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL; | |
452 | d40d->lcla_alloc--; | |
453 | if (d40d->lcla_alloc == 0) { | |
454 | ret = 0; | |
455 | break; | |
456 | } | |
457 | } | |
458 | } | |
459 | ||
460 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); | |
461 | ||
462 | return ret; | |
463 | ||
464 | } | |
465 | ||
8d318a50 LW |
466 | static void d40_desc_remove(struct d40_desc *d40d) |
467 | { | |
468 | list_del(&d40d->node); | |
469 | } | |
470 | ||
471 | static struct d40_desc *d40_desc_get(struct d40_chan *d40c) | |
472 | { | |
a2c15fa4 | 473 | struct d40_desc *desc = NULL; |
8d318a50 LW |
474 | |
475 | if (!list_empty(&d40c->client)) { | |
a2c15fa4 RV |
476 | struct d40_desc *d; |
477 | struct d40_desc *_d; | |
478 | ||
8d318a50 LW |
479 | list_for_each_entry_safe(d, _d, &d40c->client, node) |
480 | if (async_tx_test_ack(&d->txd)) { | |
8d318a50 | 481 | d40_desc_remove(d); |
a2c15fa4 RV |
482 | desc = d; |
483 | memset(desc, 0, sizeof(*desc)); | |
c675b1b4 | 484 | break; |
8d318a50 | 485 | } |
8d318a50 | 486 | } |
a2c15fa4 RV |
487 | |
488 | if (!desc) | |
489 | desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT); | |
490 | ||
491 | if (desc) | |
492 | INIT_LIST_HEAD(&desc->node); | |
493 | ||
494 | return desc; | |
8d318a50 LW |
495 | } |
496 | ||
497 | static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d) | |
498 | { | |
698e4732 | 499 | |
b00f938c | 500 | d40_pool_lli_free(d40c, d40d); |
698e4732 | 501 | d40_lcla_free_all(d40c, d40d); |
c675b1b4 | 502 | kmem_cache_free(d40c->base->desc_slab, d40d); |
8d318a50 LW |
503 | } |
504 | ||
505 | static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc) | |
506 | { | |
507 | list_add_tail(&desc->node, &d40c->active); | |
508 | } | |
509 | ||
1c4b0927 RV |
510 | static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc) |
511 | { | |
512 | struct d40_phy_lli *lli_dst = desc->lli_phy.dst; | |
513 | struct d40_phy_lli *lli_src = desc->lli_phy.src; | |
514 | void __iomem *base = chan_base(chan); | |
515 | ||
516 | writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); | |
517 | writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT); | |
518 | writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR); | |
519 | writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK); | |
520 | ||
521 | writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); | |
522 | writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT); | |
523 | writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR); | |
524 | writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK); | |
525 | } | |
526 | ||
e65889c7 | 527 | static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc) |
698e4732 | 528 | { |
e65889c7 RV |
529 | struct d40_lcla_pool *pool = &chan->base->lcla_pool; |
530 | struct d40_log_lli_bidir *lli = &desc->lli_log; | |
531 | int lli_current = desc->lli_current; | |
532 | int lli_len = desc->lli_len; | |
0c842b55 | 533 | bool cyclic = desc->cyclic; |
e65889c7 | 534 | int curr_lcla = -EINVAL; |
0c842b55 RV |
535 | int first_lcla = 0; |
536 | bool linkback; | |
e65889c7 | 537 | |
0c842b55 RV |
538 | /* |
539 | * We may have partially running cyclic transfers, in case we did't get | |
540 | * enough LCLA entries. | |
541 | */ | |
542 | linkback = cyclic && lli_current == 0; | |
543 | ||
544 | /* | |
545 | * For linkback, we need one LCLA even with only one link, because we | |
546 | * can't link back to the one in LCPA space | |
547 | */ | |
548 | if (linkback || (lli_len - lli_current > 1)) { | |
e65889c7 | 549 | curr_lcla = d40_lcla_alloc_one(chan, desc); |
0c842b55 RV |
550 | first_lcla = curr_lcla; |
551 | } | |
552 | ||
553 | /* | |
554 | * For linkback, we normally load the LCPA in the loop since we need to | |
555 | * link it to the second LCLA and not the first. However, if we | |
556 | * couldn't even get a first LCLA, then we have to run in LCPA and | |
557 | * reload manually. | |
558 | */ | |
559 | if (!linkback || curr_lcla == -EINVAL) { | |
560 | unsigned int flags = 0; | |
e65889c7 | 561 | |
0c842b55 RV |
562 | if (curr_lcla == -EINVAL) |
563 | flags |= LLI_TERM_INT; | |
e65889c7 | 564 | |
0c842b55 RV |
565 | d40_log_lli_lcpa_write(chan->lcpa, |
566 | &lli->dst[lli_current], | |
567 | &lli->src[lli_current], | |
568 | curr_lcla, | |
569 | flags); | |
570 | lli_current++; | |
571 | } | |
6045f0bb RV |
572 | |
573 | if (curr_lcla < 0) | |
574 | goto out; | |
575 | ||
e65889c7 RV |
576 | for (; lli_current < lli_len; lli_current++) { |
577 | unsigned int lcla_offset = chan->phy_chan->num * 1024 + | |
578 | 8 * curr_lcla * 2; | |
579 | struct d40_log_lli *lcla = pool->base + lcla_offset; | |
0c842b55 | 580 | unsigned int flags = 0; |
e65889c7 RV |
581 | int next_lcla; |
582 | ||
583 | if (lli_current + 1 < lli_len) | |
584 | next_lcla = d40_lcla_alloc_one(chan, desc); | |
585 | else | |
0c842b55 RV |
586 | next_lcla = linkback ? first_lcla : -EINVAL; |
587 | ||
588 | if (cyclic || next_lcla == -EINVAL) | |
589 | flags |= LLI_TERM_INT; | |
e65889c7 | 590 | |
0c842b55 RV |
591 | if (linkback && curr_lcla == first_lcla) { |
592 | /* First link goes in both LCPA and LCLA */ | |
593 | d40_log_lli_lcpa_write(chan->lcpa, | |
594 | &lli->dst[lli_current], | |
595 | &lli->src[lli_current], | |
596 | next_lcla, flags); | |
597 | } | |
598 | ||
599 | /* | |
600 | * One unused LCLA in the cyclic case if the very first | |
601 | * next_lcla fails... | |
602 | */ | |
e65889c7 RV |
603 | d40_log_lli_lcla_write(lcla, |
604 | &lli->dst[lli_current], | |
605 | &lli->src[lli_current], | |
0c842b55 | 606 | next_lcla, flags); |
e65889c7 RV |
607 | |
608 | dma_sync_single_range_for_device(chan->base->dev, | |
609 | pool->dma_addr, lcla_offset, | |
610 | 2 * sizeof(struct d40_log_lli), | |
611 | DMA_TO_DEVICE); | |
612 | ||
613 | curr_lcla = next_lcla; | |
614 | ||
0c842b55 | 615 | if (curr_lcla == -EINVAL || curr_lcla == first_lcla) { |
e65889c7 RV |
616 | lli_current++; |
617 | break; | |
618 | } | |
619 | } | |
620 | ||
6045f0bb | 621 | out: |
e65889c7 RV |
622 | desc->lli_current = lli_current; |
623 | } | |
698e4732 | 624 | |
e65889c7 RV |
625 | static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d) |
626 | { | |
724a8577 | 627 | if (chan_is_physical(d40c)) { |
1c4b0927 | 628 | d40_phy_lli_load(d40c, d40d); |
698e4732 | 629 | d40d->lli_current = d40d->lli_len; |
e65889c7 RV |
630 | } else |
631 | d40_log_lli_to_lcxa(d40c, d40d); | |
698e4732 JA |
632 | } |
633 | ||
8d318a50 LW |
634 | static struct d40_desc *d40_first_active_get(struct d40_chan *d40c) |
635 | { | |
636 | struct d40_desc *d; | |
637 | ||
638 | if (list_empty(&d40c->active)) | |
639 | return NULL; | |
640 | ||
641 | d = list_first_entry(&d40c->active, | |
642 | struct d40_desc, | |
643 | node); | |
644 | return d; | |
645 | } | |
646 | ||
7404368c | 647 | /* remove desc from current queue and add it to the pending_queue */ |
8d318a50 LW |
648 | static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc) |
649 | { | |
7404368c PF |
650 | d40_desc_remove(desc); |
651 | desc->is_in_client_list = false; | |
a8f3067b PF |
652 | list_add_tail(&desc->node, &d40c->pending_queue); |
653 | } | |
654 | ||
655 | static struct d40_desc *d40_first_pending(struct d40_chan *d40c) | |
656 | { | |
657 | struct d40_desc *d; | |
658 | ||
659 | if (list_empty(&d40c->pending_queue)) | |
660 | return NULL; | |
661 | ||
662 | d = list_first_entry(&d40c->pending_queue, | |
663 | struct d40_desc, | |
664 | node); | |
665 | return d; | |
8d318a50 LW |
666 | } |
667 | ||
668 | static struct d40_desc *d40_first_queued(struct d40_chan *d40c) | |
669 | { | |
670 | struct d40_desc *d; | |
671 | ||
672 | if (list_empty(&d40c->queue)) | |
673 | return NULL; | |
674 | ||
675 | d = list_first_entry(&d40c->queue, | |
676 | struct d40_desc, | |
677 | node); | |
678 | return d; | |
679 | } | |
680 | ||
d49278e3 PF |
681 | static int d40_psize_2_burst_size(bool is_log, int psize) |
682 | { | |
683 | if (is_log) { | |
684 | if (psize == STEDMA40_PSIZE_LOG_1) | |
685 | return 1; | |
686 | } else { | |
687 | if (psize == STEDMA40_PSIZE_PHY_1) | |
688 | return 1; | |
689 | } | |
690 | ||
691 | return 2 << psize; | |
692 | } | |
693 | ||
694 | /* | |
695 | * The dma only supports transmitting packages up to | |
696 | * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of | |
697 | * dma elements required to send the entire sg list | |
698 | */ | |
699 | static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2) | |
700 | { | |
701 | int dmalen; | |
702 | u32 max_w = max(data_width1, data_width2); | |
703 | u32 min_w = min(data_width1, data_width2); | |
704 | u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w); | |
705 | ||
706 | if (seg_max > STEDMA40_MAX_SEG_SIZE) | |
707 | seg_max -= (1 << max_w); | |
708 | ||
709 | if (!IS_ALIGNED(size, 1 << max_w)) | |
710 | return -EINVAL; | |
711 | ||
712 | if (size <= seg_max) | |
713 | dmalen = 1; | |
714 | else { | |
715 | dmalen = size / seg_max; | |
716 | if (dmalen * seg_max < size) | |
717 | dmalen++; | |
718 | } | |
719 | return dmalen; | |
720 | } | |
721 | ||
722 | static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len, | |
723 | u32 data_width1, u32 data_width2) | |
724 | { | |
725 | struct scatterlist *sg; | |
726 | int i; | |
727 | int len = 0; | |
728 | int ret; | |
729 | ||
730 | for_each_sg(sgl, sg, sg_len, i) { | |
731 | ret = d40_size_2_dmalen(sg_dma_len(sg), | |
732 | data_width1, data_width2); | |
733 | if (ret < 0) | |
734 | return ret; | |
735 | len += ret; | |
736 | } | |
737 | return len; | |
738 | } | |
8d318a50 | 739 | |
d49278e3 | 740 | /* Support functions for logical channels */ |
8d318a50 LW |
741 | |
742 | static int d40_channel_execute_command(struct d40_chan *d40c, | |
743 | enum d40_command command) | |
744 | { | |
767a9675 JA |
745 | u32 status; |
746 | int i; | |
8d318a50 LW |
747 | void __iomem *active_reg; |
748 | int ret = 0; | |
749 | unsigned long flags; | |
1d392a7b | 750 | u32 wmask; |
8d318a50 LW |
751 | |
752 | spin_lock_irqsave(&d40c->base->execmd_lock, flags); | |
753 | ||
754 | if (d40c->phy_chan->num % 2 == 0) | |
755 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; | |
756 | else | |
757 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; | |
758 | ||
759 | if (command == D40_DMA_SUSPEND_REQ) { | |
760 | status = (readl(active_reg) & | |
761 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
762 | D40_CHAN_POS(d40c->phy_chan->num); | |
763 | ||
764 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) | |
765 | goto done; | |
766 | } | |
767 | ||
1d392a7b JA |
768 | wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num)); |
769 | writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)), | |
770 | active_reg); | |
8d318a50 LW |
771 | |
772 | if (command == D40_DMA_SUSPEND_REQ) { | |
773 | ||
774 | for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) { | |
775 | status = (readl(active_reg) & | |
776 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
777 | D40_CHAN_POS(d40c->phy_chan->num); | |
778 | ||
779 | cpu_relax(); | |
780 | /* | |
781 | * Reduce the number of bus accesses while | |
782 | * waiting for the DMA to suspend. | |
783 | */ | |
784 | udelay(3); | |
785 | ||
786 | if (status == D40_DMA_STOP || | |
787 | status == D40_DMA_SUSPENDED) | |
788 | break; | |
789 | } | |
790 | ||
791 | if (i == D40_SUSPEND_MAX_IT) { | |
6db5a8ba RV |
792 | chan_err(d40c, |
793 | "unable to suspend the chl %d (log: %d) status %x\n", | |
794 | d40c->phy_chan->num, d40c->log_num, | |
8d318a50 LW |
795 | status); |
796 | dump_stack(); | |
797 | ret = -EBUSY; | |
798 | } | |
799 | ||
800 | } | |
801 | done: | |
802 | spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); | |
803 | return ret; | |
804 | } | |
805 | ||
806 | static void d40_term_all(struct d40_chan *d40c) | |
807 | { | |
808 | struct d40_desc *d40d; | |
7404368c | 809 | struct d40_desc *_d; |
8d318a50 LW |
810 | |
811 | /* Release active descriptors */ | |
812 | while ((d40d = d40_first_active_get(d40c))) { | |
813 | d40_desc_remove(d40d); | |
8d318a50 LW |
814 | d40_desc_free(d40c, d40d); |
815 | } | |
816 | ||
817 | /* Release queued descriptors waiting for transfer */ | |
818 | while ((d40d = d40_first_queued(d40c))) { | |
819 | d40_desc_remove(d40d); | |
8d318a50 LW |
820 | d40_desc_free(d40c, d40d); |
821 | } | |
822 | ||
a8f3067b PF |
823 | /* Release pending descriptors */ |
824 | while ((d40d = d40_first_pending(d40c))) { | |
825 | d40_desc_remove(d40d); | |
826 | d40_desc_free(d40c, d40d); | |
827 | } | |
8d318a50 | 828 | |
7404368c PF |
829 | /* Release client owned descriptors */ |
830 | if (!list_empty(&d40c->client)) | |
831 | list_for_each_entry_safe(d40d, _d, &d40c->client, node) { | |
832 | d40_desc_remove(d40d); | |
833 | d40_desc_free(d40c, d40d); | |
834 | } | |
835 | ||
836 | ||
8d318a50 LW |
837 | d40c->pending_tx = 0; |
838 | d40c->busy = false; | |
839 | } | |
840 | ||
262d2915 RV |
841 | static void __d40_config_set_event(struct d40_chan *d40c, bool enable, |
842 | u32 event, int reg) | |
843 | { | |
8ca84687 | 844 | void __iomem *addr = chan_base(d40c) + reg; |
262d2915 RV |
845 | int tries; |
846 | ||
847 | if (!enable) { | |
848 | writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) | |
849 | | ~D40_EVENTLINE_MASK(event), addr); | |
850 | return; | |
851 | } | |
852 | ||
853 | /* | |
854 | * The hardware sometimes doesn't register the enable when src and dst | |
855 | * event lines are active on the same logical channel. Retry to ensure | |
856 | * it does. Usually only one retry is sufficient. | |
857 | */ | |
858 | tries = 100; | |
859 | while (--tries) { | |
860 | writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) | |
861 | | ~D40_EVENTLINE_MASK(event), addr); | |
862 | ||
863 | if (readl(addr) & D40_EVENTLINE_MASK(event)) | |
864 | break; | |
865 | } | |
866 | ||
867 | if (tries != 99) | |
868 | dev_dbg(chan2dev(d40c), | |
869 | "[%s] workaround enable S%cLNK (%d tries)\n", | |
870 | __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D', | |
871 | 100 - tries); | |
872 | ||
873 | WARN_ON(!tries); | |
874 | } | |
875 | ||
8d318a50 LW |
876 | static void d40_config_set_event(struct d40_chan *d40c, bool do_enable) |
877 | { | |
8d318a50 LW |
878 | unsigned long flags; |
879 | ||
8d318a50 LW |
880 | spin_lock_irqsave(&d40c->phy_chan->lock, flags); |
881 | ||
882 | /* Enable event line connected to device (or memcpy) */ | |
883 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || | |
884 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) { | |
885 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
886 | ||
262d2915 RV |
887 | __d40_config_set_event(d40c, do_enable, event, |
888 | D40_CHAN_REG_SSLNK); | |
8d318a50 | 889 | } |
262d2915 | 890 | |
8d318a50 LW |
891 | if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) { |
892 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
893 | ||
262d2915 RV |
894 | __d40_config_set_event(d40c, do_enable, event, |
895 | D40_CHAN_REG_SDLNK); | |
8d318a50 LW |
896 | } |
897 | ||
898 | spin_unlock_irqrestore(&d40c->phy_chan->lock, flags); | |
899 | } | |
900 | ||
a5ebca47 | 901 | static u32 d40_chan_has_events(struct d40_chan *d40c) |
8d318a50 | 902 | { |
8ca84687 | 903 | void __iomem *chanbase = chan_base(d40c); |
be8cb7df | 904 | u32 val; |
8d318a50 | 905 | |
8ca84687 RV |
906 | val = readl(chanbase + D40_CHAN_REG_SSLNK); |
907 | val |= readl(chanbase + D40_CHAN_REG_SDLNK); | |
be8cb7df | 908 | |
a5ebca47 | 909 | return val; |
8d318a50 LW |
910 | } |
911 | ||
20a5b6d0 RV |
912 | static u32 d40_get_prmo(struct d40_chan *d40c) |
913 | { | |
914 | static const unsigned int phy_map[] = { | |
915 | [STEDMA40_PCHAN_BASIC_MODE] | |
916 | = D40_DREG_PRMO_PCHAN_BASIC, | |
917 | [STEDMA40_PCHAN_MODULO_MODE] | |
918 | = D40_DREG_PRMO_PCHAN_MODULO, | |
919 | [STEDMA40_PCHAN_DOUBLE_DST_MODE] | |
920 | = D40_DREG_PRMO_PCHAN_DOUBLE_DST, | |
921 | }; | |
922 | static const unsigned int log_map[] = { | |
923 | [STEDMA40_LCHAN_SRC_PHY_DST_LOG] | |
924 | = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG, | |
925 | [STEDMA40_LCHAN_SRC_LOG_DST_PHY] | |
926 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY, | |
927 | [STEDMA40_LCHAN_SRC_LOG_DST_LOG] | |
928 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG, | |
929 | }; | |
930 | ||
724a8577 | 931 | if (chan_is_physical(d40c)) |
20a5b6d0 RV |
932 | return phy_map[d40c->dma_cfg.mode_opt]; |
933 | else | |
934 | return log_map[d40c->dma_cfg.mode_opt]; | |
935 | } | |
936 | ||
b55912c6 | 937 | static void d40_config_write(struct d40_chan *d40c) |
8d318a50 LW |
938 | { |
939 | u32 addr_base; | |
940 | u32 var; | |
8d318a50 LW |
941 | |
942 | /* Odd addresses are even addresses + 4 */ | |
943 | addr_base = (d40c->phy_chan->num % 2) * 4; | |
944 | /* Setup channel mode to logical or physical */ | |
724a8577 | 945 | var = ((u32)(chan_is_logical(d40c)) + 1) << |
8d318a50 LW |
946 | D40_CHAN_POS(d40c->phy_chan->num); |
947 | writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); | |
948 | ||
949 | /* Setup operational mode option register */ | |
20a5b6d0 | 950 | var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num); |
8d318a50 LW |
951 | |
952 | writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); | |
953 | ||
724a8577 | 954 | if (chan_is_logical(d40c)) { |
8ca84687 RV |
955 | int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) |
956 | & D40_SREG_ELEM_LOG_LIDX_MASK; | |
957 | void __iomem *chanbase = chan_base(d40c); | |
958 | ||
8d318a50 | 959 | /* Set default config for CFG reg */ |
8ca84687 RV |
960 | writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG); |
961 | writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG); | |
8d318a50 | 962 | |
b55912c6 | 963 | /* Set LIDX for lcla */ |
8ca84687 RV |
964 | writel(lidx, chanbase + D40_CHAN_REG_SSELT); |
965 | writel(lidx, chanbase + D40_CHAN_REG_SDELT); | |
8d318a50 | 966 | } |
8d318a50 LW |
967 | } |
968 | ||
aa182ae2 JA |
969 | static u32 d40_residue(struct d40_chan *d40c) |
970 | { | |
971 | u32 num_elt; | |
972 | ||
724a8577 | 973 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
974 | num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK) |
975 | >> D40_MEM_LCSP2_ECNT_POS; | |
8ca84687 RV |
976 | else { |
977 | u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT); | |
978 | num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK) | |
979 | >> D40_SREG_ELEM_PHY_ECNT_POS; | |
980 | } | |
981 | ||
aa182ae2 JA |
982 | return num_elt * (1 << d40c->dma_cfg.dst_info.data_width); |
983 | } | |
984 | ||
985 | static bool d40_tx_is_linked(struct d40_chan *d40c) | |
986 | { | |
987 | bool is_link; | |
988 | ||
724a8577 | 989 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
990 | is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK; |
991 | else | |
8ca84687 RV |
992 | is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK) |
993 | & D40_SREG_LNK_PHYS_LNK_MASK; | |
994 | ||
aa182ae2 JA |
995 | return is_link; |
996 | } | |
997 | ||
86eb5fb6 | 998 | static int d40_pause(struct d40_chan *d40c) |
aa182ae2 | 999 | { |
aa182ae2 JA |
1000 | int res = 0; |
1001 | unsigned long flags; | |
1002 | ||
3ac012af JA |
1003 | if (!d40c->busy) |
1004 | return 0; | |
1005 | ||
aa182ae2 JA |
1006 | spin_lock_irqsave(&d40c->lock, flags); |
1007 | ||
1008 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); | |
1009 | if (res == 0) { | |
724a8577 | 1010 | if (chan_is_logical(d40c)) { |
aa182ae2 JA |
1011 | d40_config_set_event(d40c, false); |
1012 | /* Resume the other logical channels if any */ | |
1013 | if (d40_chan_has_events(d40c)) | |
1014 | res = d40_channel_execute_command(d40c, | |
1015 | D40_DMA_RUN); | |
1016 | } | |
1017 | } | |
1018 | ||
1019 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1020 | return res; | |
1021 | } | |
1022 | ||
86eb5fb6 | 1023 | static int d40_resume(struct d40_chan *d40c) |
aa182ae2 | 1024 | { |
aa182ae2 JA |
1025 | int res = 0; |
1026 | unsigned long flags; | |
1027 | ||
3ac012af JA |
1028 | if (!d40c->busy) |
1029 | return 0; | |
1030 | ||
aa182ae2 JA |
1031 | spin_lock_irqsave(&d40c->lock, flags); |
1032 | ||
1033 | if (d40c->base->rev == 0) | |
724a8577 | 1034 | if (chan_is_logical(d40c)) { |
aa182ae2 JA |
1035 | res = d40_channel_execute_command(d40c, |
1036 | D40_DMA_SUSPEND_REQ); | |
1037 | goto no_suspend; | |
1038 | } | |
1039 | ||
1040 | /* If bytes left to transfer or linked tx resume job */ | |
1041 | if (d40_residue(d40c) || d40_tx_is_linked(d40c)) { | |
1042 | ||
724a8577 | 1043 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
1044 | d40_config_set_event(d40c, true); |
1045 | ||
1046 | res = d40_channel_execute_command(d40c, D40_DMA_RUN); | |
1047 | } | |
1048 | ||
1049 | no_suspend: | |
1050 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1051 | return res; | |
1052 | } | |
1053 | ||
86eb5fb6 RV |
1054 | static int d40_terminate_all(struct d40_chan *chan) |
1055 | { | |
1056 | unsigned long flags; | |
1057 | int ret = 0; | |
1058 | ||
1059 | ret = d40_pause(chan); | |
1060 | if (!ret && chan_is_physical(chan)) | |
1061 | ret = d40_channel_execute_command(chan, D40_DMA_STOP); | |
1062 | ||
1063 | spin_lock_irqsave(&chan->lock, flags); | |
1064 | d40_term_all(chan); | |
1065 | spin_unlock_irqrestore(&chan->lock, flags); | |
1066 | ||
1067 | return ret; | |
1068 | } | |
1069 | ||
8d318a50 LW |
1070 | static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx) |
1071 | { | |
1072 | struct d40_chan *d40c = container_of(tx->chan, | |
1073 | struct d40_chan, | |
1074 | chan); | |
1075 | struct d40_desc *d40d = container_of(tx, struct d40_desc, txd); | |
1076 | unsigned long flags; | |
1077 | ||
1078 | spin_lock_irqsave(&d40c->lock, flags); | |
1079 | ||
aa182ae2 JA |
1080 | d40c->chan.cookie++; |
1081 | ||
1082 | if (d40c->chan.cookie < 0) | |
1083 | d40c->chan.cookie = 1; | |
1084 | ||
1085 | d40d->txd.cookie = d40c->chan.cookie; | |
1086 | ||
8d318a50 LW |
1087 | d40_desc_queue(d40c, d40d); |
1088 | ||
1089 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1090 | ||
1091 | return tx->cookie; | |
1092 | } | |
1093 | ||
1094 | static int d40_start(struct d40_chan *d40c) | |
1095 | { | |
f4185592 LW |
1096 | if (d40c->base->rev == 0) { |
1097 | int err; | |
1098 | ||
724a8577 | 1099 | if (chan_is_logical(d40c)) { |
f4185592 LW |
1100 | err = d40_channel_execute_command(d40c, |
1101 | D40_DMA_SUSPEND_REQ); | |
1102 | if (err) | |
1103 | return err; | |
1104 | } | |
1105 | } | |
1106 | ||
724a8577 | 1107 | if (chan_is_logical(d40c)) |
8d318a50 | 1108 | d40_config_set_event(d40c, true); |
8d318a50 | 1109 | |
0c32269d | 1110 | return d40_channel_execute_command(d40c, D40_DMA_RUN); |
8d318a50 LW |
1111 | } |
1112 | ||
1113 | static struct d40_desc *d40_queue_start(struct d40_chan *d40c) | |
1114 | { | |
1115 | struct d40_desc *d40d; | |
1116 | int err; | |
1117 | ||
1118 | /* Start queued jobs, if any */ | |
1119 | d40d = d40_first_queued(d40c); | |
1120 | ||
1121 | if (d40d != NULL) { | |
1122 | d40c->busy = true; | |
1123 | ||
1124 | /* Remove from queue */ | |
1125 | d40_desc_remove(d40d); | |
1126 | ||
1127 | /* Add to active queue */ | |
1128 | d40_desc_submit(d40c, d40d); | |
1129 | ||
7d83a854 RV |
1130 | /* Initiate DMA job */ |
1131 | d40_desc_load(d40c, d40d); | |
8d318a50 | 1132 | |
7d83a854 RV |
1133 | /* Start dma job */ |
1134 | err = d40_start(d40c); | |
8d318a50 | 1135 | |
7d83a854 RV |
1136 | if (err) |
1137 | return NULL; | |
8d318a50 LW |
1138 | } |
1139 | ||
1140 | return d40d; | |
1141 | } | |
1142 | ||
1143 | /* called from interrupt context */ | |
1144 | static void dma_tc_handle(struct d40_chan *d40c) | |
1145 | { | |
1146 | struct d40_desc *d40d; | |
1147 | ||
8d318a50 LW |
1148 | /* Get first active entry from list */ |
1149 | d40d = d40_first_active_get(d40c); | |
1150 | ||
1151 | if (d40d == NULL) | |
1152 | return; | |
1153 | ||
0c842b55 RV |
1154 | if (d40d->cyclic) { |
1155 | /* | |
1156 | * If this was a paritially loaded list, we need to reloaded | |
1157 | * it, and only when the list is completed. We need to check | |
1158 | * for done because the interrupt will hit for every link, and | |
1159 | * not just the last one. | |
1160 | */ | |
1161 | if (d40d->lli_current < d40d->lli_len | |
1162 | && !d40_tx_is_linked(d40c) | |
1163 | && !d40_residue(d40c)) { | |
1164 | d40_lcla_free_all(d40c, d40d); | |
1165 | d40_desc_load(d40c, d40d); | |
1166 | (void) d40_start(d40c); | |
8d318a50 | 1167 | |
0c842b55 RV |
1168 | if (d40d->lli_current == d40d->lli_len) |
1169 | d40d->lli_current = 0; | |
1170 | } | |
1171 | } else { | |
1172 | d40_lcla_free_all(d40c, d40d); | |
8d318a50 | 1173 | |
0c842b55 RV |
1174 | if (d40d->lli_current < d40d->lli_len) { |
1175 | d40_desc_load(d40c, d40d); | |
1176 | /* Start dma job */ | |
1177 | (void) d40_start(d40c); | |
1178 | return; | |
1179 | } | |
1180 | ||
1181 | if (d40_queue_start(d40c) == NULL) | |
1182 | d40c->busy = false; | |
1183 | } | |
8d318a50 LW |
1184 | |
1185 | d40c->pending_tx++; | |
1186 | tasklet_schedule(&d40c->tasklet); | |
1187 | ||
1188 | } | |
1189 | ||
1190 | static void dma_tasklet(unsigned long data) | |
1191 | { | |
1192 | struct d40_chan *d40c = (struct d40_chan *) data; | |
767a9675 | 1193 | struct d40_desc *d40d; |
8d318a50 LW |
1194 | unsigned long flags; |
1195 | dma_async_tx_callback callback; | |
1196 | void *callback_param; | |
1197 | ||
1198 | spin_lock_irqsave(&d40c->lock, flags); | |
1199 | ||
1200 | /* Get first active entry from list */ | |
767a9675 | 1201 | d40d = d40_first_active_get(d40c); |
767a9675 | 1202 | if (d40d == NULL) |
8d318a50 LW |
1203 | goto err; |
1204 | ||
0c842b55 RV |
1205 | if (!d40d->cyclic) |
1206 | d40c->completed = d40d->txd.cookie; | |
8d318a50 LW |
1207 | |
1208 | /* | |
1209 | * If terminating a channel pending_tx is set to zero. | |
1210 | * This prevents any finished active jobs to return to the client. | |
1211 | */ | |
1212 | if (d40c->pending_tx == 0) { | |
1213 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1214 | return; | |
1215 | } | |
1216 | ||
1217 | /* Callback to client */ | |
767a9675 JA |
1218 | callback = d40d->txd.callback; |
1219 | callback_param = d40d->txd.callback_param; | |
1220 | ||
0c842b55 RV |
1221 | if (!d40d->cyclic) { |
1222 | if (async_tx_test_ack(&d40d->txd)) { | |
767a9675 | 1223 | d40_desc_remove(d40d); |
0c842b55 RV |
1224 | d40_desc_free(d40c, d40d); |
1225 | } else { | |
1226 | if (!d40d->is_in_client_list) { | |
1227 | d40_desc_remove(d40d); | |
1228 | d40_lcla_free_all(d40c, d40d); | |
1229 | list_add_tail(&d40d->node, &d40c->client); | |
1230 | d40d->is_in_client_list = true; | |
1231 | } | |
8d318a50 LW |
1232 | } |
1233 | } | |
1234 | ||
1235 | d40c->pending_tx--; | |
1236 | ||
1237 | if (d40c->pending_tx) | |
1238 | tasklet_schedule(&d40c->tasklet); | |
1239 | ||
1240 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1241 | ||
767a9675 | 1242 | if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT)) |
8d318a50 LW |
1243 | callback(callback_param); |
1244 | ||
1245 | return; | |
1246 | ||
1247 | err: | |
25985edc | 1248 | /* Rescue manoeuvre if receiving double interrupts */ |
8d318a50 LW |
1249 | if (d40c->pending_tx > 0) |
1250 | d40c->pending_tx--; | |
1251 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1252 | } | |
1253 | ||
1254 | static irqreturn_t d40_handle_interrupt(int irq, void *data) | |
1255 | { | |
1256 | static const struct d40_interrupt_lookup il[] = { | |
1257 | {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0}, | |
1258 | {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32}, | |
1259 | {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64}, | |
1260 | {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96}, | |
1261 | {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0}, | |
1262 | {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32}, | |
1263 | {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64}, | |
1264 | {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96}, | |
1265 | {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN}, | |
1266 | {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN}, | |
1267 | }; | |
1268 | ||
1269 | int i; | |
1270 | u32 regs[ARRAY_SIZE(il)]; | |
8d318a50 LW |
1271 | u32 idx; |
1272 | u32 row; | |
1273 | long chan = -1; | |
1274 | struct d40_chan *d40c; | |
1275 | unsigned long flags; | |
1276 | struct d40_base *base = data; | |
1277 | ||
1278 | spin_lock_irqsave(&base->interrupt_lock, flags); | |
1279 | ||
1280 | /* Read interrupt status of both logical and physical channels */ | |
1281 | for (i = 0; i < ARRAY_SIZE(il); i++) | |
1282 | regs[i] = readl(base->virtbase + il[i].src); | |
1283 | ||
1284 | for (;;) { | |
1285 | ||
1286 | chan = find_next_bit((unsigned long *)regs, | |
1287 | BITS_PER_LONG * ARRAY_SIZE(il), chan + 1); | |
1288 | ||
1289 | /* No more set bits found? */ | |
1290 | if (chan == BITS_PER_LONG * ARRAY_SIZE(il)) | |
1291 | break; | |
1292 | ||
1293 | row = chan / BITS_PER_LONG; | |
1294 | idx = chan & (BITS_PER_LONG - 1); | |
1295 | ||
1296 | /* ACK interrupt */ | |
1b00348d | 1297 | writel(1 << idx, base->virtbase + il[row].clr); |
8d318a50 LW |
1298 | |
1299 | if (il[row].offset == D40_PHY_CHAN) | |
1300 | d40c = base->lookup_phy_chans[idx]; | |
1301 | else | |
1302 | d40c = base->lookup_log_chans[il[row].offset + idx]; | |
1303 | spin_lock(&d40c->lock); | |
1304 | ||
1305 | if (!il[row].is_error) | |
1306 | dma_tc_handle(d40c); | |
1307 | else | |
6db5a8ba RV |
1308 | d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n", |
1309 | chan, il[row].offset, idx); | |
8d318a50 LW |
1310 | |
1311 | spin_unlock(&d40c->lock); | |
1312 | } | |
1313 | ||
1314 | spin_unlock_irqrestore(&base->interrupt_lock, flags); | |
1315 | ||
1316 | return IRQ_HANDLED; | |
1317 | } | |
1318 | ||
8d318a50 LW |
1319 | static int d40_validate_conf(struct d40_chan *d40c, |
1320 | struct stedma40_chan_cfg *conf) | |
1321 | { | |
1322 | int res = 0; | |
1323 | u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type); | |
1324 | u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type); | |
38bdbf02 | 1325 | bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; |
8d318a50 | 1326 | |
0747c7ba | 1327 | if (!conf->dir) { |
6db5a8ba | 1328 | chan_err(d40c, "Invalid direction.\n"); |
0747c7ba LW |
1329 | res = -EINVAL; |
1330 | } | |
1331 | ||
1332 | if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY && | |
1333 | d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 && | |
1334 | d40c->runtime_addr == 0) { | |
1335 | ||
6db5a8ba RV |
1336 | chan_err(d40c, "Invalid TX channel address (%d)\n", |
1337 | conf->dst_dev_type); | |
0747c7ba LW |
1338 | res = -EINVAL; |
1339 | } | |
1340 | ||
1341 | if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY && | |
1342 | d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 && | |
1343 | d40c->runtime_addr == 0) { | |
6db5a8ba RV |
1344 | chan_err(d40c, "Invalid RX channel address (%d)\n", |
1345 | conf->src_dev_type); | |
0747c7ba LW |
1346 | res = -EINVAL; |
1347 | } | |
1348 | ||
1349 | if (conf->dir == STEDMA40_MEM_TO_PERIPH && | |
8d318a50 | 1350 | dst_event_group == STEDMA40_DEV_DST_MEMORY) { |
6db5a8ba | 1351 | chan_err(d40c, "Invalid dst\n"); |
8d318a50 LW |
1352 | res = -EINVAL; |
1353 | } | |
1354 | ||
0747c7ba | 1355 | if (conf->dir == STEDMA40_PERIPH_TO_MEM && |
8d318a50 | 1356 | src_event_group == STEDMA40_DEV_SRC_MEMORY) { |
6db5a8ba | 1357 | chan_err(d40c, "Invalid src\n"); |
8d318a50 LW |
1358 | res = -EINVAL; |
1359 | } | |
1360 | ||
1361 | if (src_event_group == STEDMA40_DEV_SRC_MEMORY && | |
1362 | dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) { | |
6db5a8ba | 1363 | chan_err(d40c, "No event line\n"); |
8d318a50 LW |
1364 | res = -EINVAL; |
1365 | } | |
1366 | ||
1367 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH && | |
1368 | (src_event_group != dst_event_group)) { | |
6db5a8ba | 1369 | chan_err(d40c, "Invalid event group\n"); |
8d318a50 LW |
1370 | res = -EINVAL; |
1371 | } | |
1372 | ||
1373 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) { | |
1374 | /* | |
1375 | * DMAC HW supports it. Will be added to this driver, | |
1376 | * in case any dma client requires it. | |
1377 | */ | |
6db5a8ba | 1378 | chan_err(d40c, "periph to periph not supported\n"); |
8d318a50 LW |
1379 | res = -EINVAL; |
1380 | } | |
1381 | ||
d49278e3 PF |
1382 | if (d40_psize_2_burst_size(is_log, conf->src_info.psize) * |
1383 | (1 << conf->src_info.data_width) != | |
1384 | d40_psize_2_burst_size(is_log, conf->dst_info.psize) * | |
1385 | (1 << conf->dst_info.data_width)) { | |
1386 | /* | |
1387 | * The DMAC hardware only supports | |
1388 | * src (burst x width) == dst (burst x width) | |
1389 | */ | |
1390 | ||
6db5a8ba | 1391 | chan_err(d40c, "src (burst x width) != dst (burst x width)\n"); |
d49278e3 PF |
1392 | res = -EINVAL; |
1393 | } | |
1394 | ||
8d318a50 LW |
1395 | return res; |
1396 | } | |
1397 | ||
1398 | static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src, | |
4aed79b2 | 1399 | int log_event_line, bool is_log) |
8d318a50 LW |
1400 | { |
1401 | unsigned long flags; | |
1402 | spin_lock_irqsave(&phy->lock, flags); | |
4aed79b2 | 1403 | if (!is_log) { |
8d318a50 LW |
1404 | /* Physical interrupts are masked per physical full channel */ |
1405 | if (phy->allocated_src == D40_ALLOC_FREE && | |
1406 | phy->allocated_dst == D40_ALLOC_FREE) { | |
1407 | phy->allocated_dst = D40_ALLOC_PHY; | |
1408 | phy->allocated_src = D40_ALLOC_PHY; | |
1409 | goto found; | |
1410 | } else | |
1411 | goto not_found; | |
1412 | } | |
1413 | ||
1414 | /* Logical channel */ | |
1415 | if (is_src) { | |
1416 | if (phy->allocated_src == D40_ALLOC_PHY) | |
1417 | goto not_found; | |
1418 | ||
1419 | if (phy->allocated_src == D40_ALLOC_FREE) | |
1420 | phy->allocated_src = D40_ALLOC_LOG_FREE; | |
1421 | ||
1422 | if (!(phy->allocated_src & (1 << log_event_line))) { | |
1423 | phy->allocated_src |= 1 << log_event_line; | |
1424 | goto found; | |
1425 | } else | |
1426 | goto not_found; | |
1427 | } else { | |
1428 | if (phy->allocated_dst == D40_ALLOC_PHY) | |
1429 | goto not_found; | |
1430 | ||
1431 | if (phy->allocated_dst == D40_ALLOC_FREE) | |
1432 | phy->allocated_dst = D40_ALLOC_LOG_FREE; | |
1433 | ||
1434 | if (!(phy->allocated_dst & (1 << log_event_line))) { | |
1435 | phy->allocated_dst |= 1 << log_event_line; | |
1436 | goto found; | |
1437 | } else | |
1438 | goto not_found; | |
1439 | } | |
1440 | ||
1441 | not_found: | |
1442 | spin_unlock_irqrestore(&phy->lock, flags); | |
1443 | return false; | |
1444 | found: | |
1445 | spin_unlock_irqrestore(&phy->lock, flags); | |
1446 | return true; | |
1447 | } | |
1448 | ||
1449 | static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, | |
1450 | int log_event_line) | |
1451 | { | |
1452 | unsigned long flags; | |
1453 | bool is_free = false; | |
1454 | ||
1455 | spin_lock_irqsave(&phy->lock, flags); | |
1456 | if (!log_event_line) { | |
8d318a50 LW |
1457 | phy->allocated_dst = D40_ALLOC_FREE; |
1458 | phy->allocated_src = D40_ALLOC_FREE; | |
1459 | is_free = true; | |
1460 | goto out; | |
1461 | } | |
1462 | ||
1463 | /* Logical channel */ | |
1464 | if (is_src) { | |
1465 | phy->allocated_src &= ~(1 << log_event_line); | |
1466 | if (phy->allocated_src == D40_ALLOC_LOG_FREE) | |
1467 | phy->allocated_src = D40_ALLOC_FREE; | |
1468 | } else { | |
1469 | phy->allocated_dst &= ~(1 << log_event_line); | |
1470 | if (phy->allocated_dst == D40_ALLOC_LOG_FREE) | |
1471 | phy->allocated_dst = D40_ALLOC_FREE; | |
1472 | } | |
1473 | ||
1474 | is_free = ((phy->allocated_src | phy->allocated_dst) == | |
1475 | D40_ALLOC_FREE); | |
1476 | ||
1477 | out: | |
1478 | spin_unlock_irqrestore(&phy->lock, flags); | |
1479 | ||
1480 | return is_free; | |
1481 | } | |
1482 | ||
1483 | static int d40_allocate_channel(struct d40_chan *d40c) | |
1484 | { | |
1485 | int dev_type; | |
1486 | int event_group; | |
1487 | int event_line; | |
1488 | struct d40_phy_res *phys; | |
1489 | int i; | |
1490 | int j; | |
1491 | int log_num; | |
1492 | bool is_src; | |
38bdbf02 | 1493 | bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL; |
8d318a50 LW |
1494 | |
1495 | phys = d40c->base->phy_res; | |
1496 | ||
1497 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { | |
1498 | dev_type = d40c->dma_cfg.src_dev_type; | |
1499 | log_num = 2 * dev_type; | |
1500 | is_src = true; | |
1501 | } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || | |
1502 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1503 | /* dst event lines are used for logical memcpy */ | |
1504 | dev_type = d40c->dma_cfg.dst_dev_type; | |
1505 | log_num = 2 * dev_type + 1; | |
1506 | is_src = false; | |
1507 | } else | |
1508 | return -EINVAL; | |
1509 | ||
1510 | event_group = D40_TYPE_TO_GROUP(dev_type); | |
1511 | event_line = D40_TYPE_TO_EVENT(dev_type); | |
1512 | ||
1513 | if (!is_log) { | |
1514 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1515 | /* Find physical half channel */ | |
1516 | for (i = 0; i < d40c->base->num_phy_chans; i++) { | |
1517 | ||
4aed79b2 MM |
1518 | if (d40_alloc_mask_set(&phys[i], is_src, |
1519 | 0, is_log)) | |
8d318a50 LW |
1520 | goto found_phy; |
1521 | } | |
1522 | } else | |
1523 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { | |
1524 | int phy_num = j + event_group * 2; | |
1525 | for (i = phy_num; i < phy_num + 2; i++) { | |
508849ad LW |
1526 | if (d40_alloc_mask_set(&phys[i], |
1527 | is_src, | |
1528 | 0, | |
1529 | is_log)) | |
8d318a50 LW |
1530 | goto found_phy; |
1531 | } | |
1532 | } | |
1533 | return -EINVAL; | |
1534 | found_phy: | |
1535 | d40c->phy_chan = &phys[i]; | |
1536 | d40c->log_num = D40_PHY_CHAN; | |
1537 | goto out; | |
1538 | } | |
1539 | if (dev_type == -1) | |
1540 | return -EINVAL; | |
1541 | ||
1542 | /* Find logical channel */ | |
1543 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { | |
1544 | int phy_num = j + event_group * 2; | |
1545 | /* | |
1546 | * Spread logical channels across all available physical rather | |
1547 | * than pack every logical channel at the first available phy | |
1548 | * channels. | |
1549 | */ | |
1550 | if (is_src) { | |
1551 | for (i = phy_num; i < phy_num + 2; i++) { | |
1552 | if (d40_alloc_mask_set(&phys[i], is_src, | |
4aed79b2 | 1553 | event_line, is_log)) |
8d318a50 LW |
1554 | goto found_log; |
1555 | } | |
1556 | } else { | |
1557 | for (i = phy_num + 1; i >= phy_num; i--) { | |
1558 | if (d40_alloc_mask_set(&phys[i], is_src, | |
4aed79b2 | 1559 | event_line, is_log)) |
8d318a50 LW |
1560 | goto found_log; |
1561 | } | |
1562 | } | |
1563 | } | |
1564 | return -EINVAL; | |
1565 | ||
1566 | found_log: | |
1567 | d40c->phy_chan = &phys[i]; | |
1568 | d40c->log_num = log_num; | |
1569 | out: | |
1570 | ||
1571 | if (is_log) | |
1572 | d40c->base->lookup_log_chans[d40c->log_num] = d40c; | |
1573 | else | |
1574 | d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; | |
1575 | ||
1576 | return 0; | |
1577 | ||
1578 | } | |
1579 | ||
8d318a50 LW |
1580 | static int d40_config_memcpy(struct d40_chan *d40c) |
1581 | { | |
1582 | dma_cap_mask_t cap = d40c->chan.device->cap_mask; | |
1583 | ||
1584 | if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { | |
1585 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log; | |
1586 | d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY; | |
1587 | d40c->dma_cfg.dst_dev_type = d40c->base->plat_data-> | |
1588 | memcpy[d40c->chan.chan_id]; | |
1589 | ||
1590 | } else if (dma_has_cap(DMA_MEMCPY, cap) && | |
1591 | dma_has_cap(DMA_SLAVE, cap)) { | |
1592 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy; | |
1593 | } else { | |
6db5a8ba | 1594 | chan_err(d40c, "No memcpy\n"); |
8d318a50 LW |
1595 | return -EINVAL; |
1596 | } | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
1601 | ||
1602 | static int d40_free_dma(struct d40_chan *d40c) | |
1603 | { | |
1604 | ||
1605 | int res = 0; | |
d181b3a8 | 1606 | u32 event; |
8d318a50 LW |
1607 | struct d40_phy_res *phy = d40c->phy_chan; |
1608 | bool is_src; | |
1609 | ||
1610 | /* Terminate all queued and active transfers */ | |
1611 | d40_term_all(d40c); | |
1612 | ||
1613 | if (phy == NULL) { | |
6db5a8ba | 1614 | chan_err(d40c, "phy == null\n"); |
8d318a50 LW |
1615 | return -EINVAL; |
1616 | } | |
1617 | ||
1618 | if (phy->allocated_src == D40_ALLOC_FREE && | |
1619 | phy->allocated_dst == D40_ALLOC_FREE) { | |
6db5a8ba | 1620 | chan_err(d40c, "channel already free\n"); |
8d318a50 LW |
1621 | return -EINVAL; |
1622 | } | |
1623 | ||
8d318a50 LW |
1624 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
1625 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1626 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
8d318a50 LW |
1627 | is_src = false; |
1628 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { | |
1629 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
8d318a50 LW |
1630 | is_src = true; |
1631 | } else { | |
6db5a8ba | 1632 | chan_err(d40c, "Unknown direction\n"); |
8d318a50 LW |
1633 | return -EINVAL; |
1634 | } | |
1635 | ||
d181b3a8 JA |
1636 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); |
1637 | if (res) { | |
6db5a8ba | 1638 | chan_err(d40c, "suspend failed\n"); |
d181b3a8 JA |
1639 | return res; |
1640 | } | |
1641 | ||
724a8577 | 1642 | if (chan_is_logical(d40c)) { |
d181b3a8 | 1643 | /* Release logical channel, deactivate the event line */ |
8d318a50 | 1644 | |
d181b3a8 | 1645 | d40_config_set_event(d40c, false); |
8d318a50 LW |
1646 | d40c->base->lookup_log_chans[d40c->log_num] = NULL; |
1647 | ||
1648 | /* | |
1649 | * Check if there are more logical allocation | |
1650 | * on this phy channel. | |
1651 | */ | |
1652 | if (!d40_alloc_mask_free(phy, is_src, event)) { | |
1653 | /* Resume the other logical channels if any */ | |
1654 | if (d40_chan_has_events(d40c)) { | |
1655 | res = d40_channel_execute_command(d40c, | |
1656 | D40_DMA_RUN); | |
1657 | if (res) { | |
6db5a8ba RV |
1658 | chan_err(d40c, |
1659 | "Executing RUN command\n"); | |
8d318a50 LW |
1660 | return res; |
1661 | } | |
1662 | } | |
1663 | return 0; | |
1664 | } | |
d181b3a8 JA |
1665 | } else { |
1666 | (void) d40_alloc_mask_free(phy, is_src, 0); | |
1667 | } | |
8d318a50 LW |
1668 | |
1669 | /* Release physical channel */ | |
1670 | res = d40_channel_execute_command(d40c, D40_DMA_STOP); | |
1671 | if (res) { | |
6db5a8ba | 1672 | chan_err(d40c, "Failed to stop channel\n"); |
8d318a50 LW |
1673 | return res; |
1674 | } | |
1675 | d40c->phy_chan = NULL; | |
ce2ca125 | 1676 | d40c->configured = false; |
8d318a50 LW |
1677 | d40c->base->lookup_phy_chans[phy->num] = NULL; |
1678 | ||
1679 | return 0; | |
8d318a50 LW |
1680 | } |
1681 | ||
a5ebca47 JA |
1682 | static bool d40_is_paused(struct d40_chan *d40c) |
1683 | { | |
8ca84687 | 1684 | void __iomem *chanbase = chan_base(d40c); |
a5ebca47 JA |
1685 | bool is_paused = false; |
1686 | unsigned long flags; | |
1687 | void __iomem *active_reg; | |
1688 | u32 status; | |
1689 | u32 event; | |
a5ebca47 JA |
1690 | |
1691 | spin_lock_irqsave(&d40c->lock, flags); | |
1692 | ||
724a8577 | 1693 | if (chan_is_physical(d40c)) { |
a5ebca47 JA |
1694 | if (d40c->phy_chan->num % 2 == 0) |
1695 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; | |
1696 | else | |
1697 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; | |
1698 | ||
1699 | status = (readl(active_reg) & | |
1700 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
1701 | D40_CHAN_POS(d40c->phy_chan->num); | |
1702 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) | |
1703 | is_paused = true; | |
1704 | ||
1705 | goto _exit; | |
1706 | } | |
1707 | ||
a5ebca47 | 1708 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
9dbfbd35 | 1709 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
a5ebca47 | 1710 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); |
8ca84687 | 1711 | status = readl(chanbase + D40_CHAN_REG_SDLNK); |
9dbfbd35 | 1712 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
a5ebca47 | 1713 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); |
8ca84687 | 1714 | status = readl(chanbase + D40_CHAN_REG_SSLNK); |
9dbfbd35 | 1715 | } else { |
6db5a8ba | 1716 | chan_err(d40c, "Unknown direction\n"); |
a5ebca47 JA |
1717 | goto _exit; |
1718 | } | |
9dbfbd35 | 1719 | |
a5ebca47 JA |
1720 | status = (status & D40_EVENTLINE_MASK(event)) >> |
1721 | D40_EVENTLINE_POS(event); | |
1722 | ||
1723 | if (status != D40_DMA_RUN) | |
1724 | is_paused = true; | |
a5ebca47 JA |
1725 | _exit: |
1726 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1727 | return is_paused; | |
1728 | ||
1729 | } | |
1730 | ||
1731 | ||
8d318a50 LW |
1732 | static u32 stedma40_residue(struct dma_chan *chan) |
1733 | { | |
1734 | struct d40_chan *d40c = | |
1735 | container_of(chan, struct d40_chan, chan); | |
1736 | u32 bytes_left; | |
1737 | unsigned long flags; | |
1738 | ||
1739 | spin_lock_irqsave(&d40c->lock, flags); | |
1740 | bytes_left = d40_residue(d40c); | |
1741 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1742 | ||
1743 | return bytes_left; | |
1744 | } | |
1745 | ||
3e3a0763 RV |
1746 | static int |
1747 | d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc, | |
1748 | struct scatterlist *sg_src, struct scatterlist *sg_dst, | |
822c5676 RV |
1749 | unsigned int sg_len, dma_addr_t src_dev_addr, |
1750 | dma_addr_t dst_dev_addr) | |
3e3a0763 RV |
1751 | { |
1752 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
1753 | struct stedma40_half_channel_info *src_info = &cfg->src_info; | |
1754 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; | |
5ed04b85 | 1755 | int ret; |
3e3a0763 | 1756 | |
5ed04b85 RV |
1757 | ret = d40_log_sg_to_lli(sg_src, sg_len, |
1758 | src_dev_addr, | |
1759 | desc->lli_log.src, | |
1760 | chan->log_def.lcsp1, | |
1761 | src_info->data_width, | |
1762 | dst_info->data_width); | |
1763 | ||
1764 | ret = d40_log_sg_to_lli(sg_dst, sg_len, | |
1765 | dst_dev_addr, | |
1766 | desc->lli_log.dst, | |
1767 | chan->log_def.lcsp3, | |
1768 | dst_info->data_width, | |
1769 | src_info->data_width); | |
1770 | ||
1771 | return ret < 0 ? ret : 0; | |
3e3a0763 RV |
1772 | } |
1773 | ||
1774 | static int | |
1775 | d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc, | |
1776 | struct scatterlist *sg_src, struct scatterlist *sg_dst, | |
822c5676 RV |
1777 | unsigned int sg_len, dma_addr_t src_dev_addr, |
1778 | dma_addr_t dst_dev_addr) | |
3e3a0763 | 1779 | { |
3e3a0763 RV |
1780 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
1781 | struct stedma40_half_channel_info *src_info = &cfg->src_info; | |
1782 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; | |
0c842b55 | 1783 | unsigned long flags = 0; |
3e3a0763 RV |
1784 | int ret; |
1785 | ||
0c842b55 RV |
1786 | if (desc->cyclic) |
1787 | flags |= LLI_CYCLIC | LLI_TERM_INT; | |
1788 | ||
3e3a0763 RV |
1789 | ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr, |
1790 | desc->lli_phy.src, | |
1791 | virt_to_phys(desc->lli_phy.src), | |
1792 | chan->src_def_cfg, | |
0c842b55 | 1793 | src_info, dst_info, flags); |
3e3a0763 RV |
1794 | |
1795 | ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr, | |
1796 | desc->lli_phy.dst, | |
1797 | virt_to_phys(desc->lli_phy.dst), | |
1798 | chan->dst_def_cfg, | |
0c842b55 | 1799 | dst_info, src_info, flags); |
3e3a0763 RV |
1800 | |
1801 | dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr, | |
1802 | desc->lli_pool.size, DMA_TO_DEVICE); | |
1803 | ||
1804 | return ret < 0 ? ret : 0; | |
1805 | } | |
1806 | ||
1807 | ||
5f81158f RV |
1808 | static struct d40_desc * |
1809 | d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg, | |
1810 | unsigned int sg_len, unsigned long dma_flags) | |
1811 | { | |
1812 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
1813 | struct d40_desc *desc; | |
dbd88788 | 1814 | int ret; |
5f81158f RV |
1815 | |
1816 | desc = d40_desc_get(chan); | |
1817 | if (!desc) | |
1818 | return NULL; | |
1819 | ||
1820 | desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width, | |
1821 | cfg->dst_info.data_width); | |
1822 | if (desc->lli_len < 0) { | |
1823 | chan_err(chan, "Unaligned size\n"); | |
dbd88788 RV |
1824 | goto err; |
1825 | } | |
5f81158f | 1826 | |
dbd88788 RV |
1827 | ret = d40_pool_lli_alloc(chan, desc, desc->lli_len); |
1828 | if (ret < 0) { | |
1829 | chan_err(chan, "Could not allocate lli\n"); | |
1830 | goto err; | |
5f81158f RV |
1831 | } |
1832 | ||
dbd88788 | 1833 | |
5f81158f RV |
1834 | desc->lli_current = 0; |
1835 | desc->txd.flags = dma_flags; | |
1836 | desc->txd.tx_submit = d40_tx_submit; | |
1837 | ||
1838 | dma_async_tx_descriptor_init(&desc->txd, &chan->chan); | |
1839 | ||
1840 | return desc; | |
dbd88788 RV |
1841 | |
1842 | err: | |
1843 | d40_desc_free(chan, desc); | |
1844 | return NULL; | |
5f81158f RV |
1845 | } |
1846 | ||
cade1d30 RV |
1847 | static dma_addr_t |
1848 | d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction) | |
8d318a50 | 1849 | { |
cade1d30 RV |
1850 | struct stedma40_platform_data *plat = chan->base->plat_data; |
1851 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
711b9cea | 1852 | dma_addr_t addr = 0; |
cade1d30 RV |
1853 | |
1854 | if (chan->runtime_addr) | |
1855 | return chan->runtime_addr; | |
1856 | ||
1857 | if (direction == DMA_FROM_DEVICE) | |
1858 | addr = plat->dev_rx[cfg->src_dev_type]; | |
1859 | else if (direction == DMA_TO_DEVICE) | |
1860 | addr = plat->dev_tx[cfg->dst_dev_type]; | |
1861 | ||
1862 | return addr; | |
1863 | } | |
1864 | ||
1865 | static struct dma_async_tx_descriptor * | |
1866 | d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, | |
1867 | struct scatterlist *sg_dst, unsigned int sg_len, | |
1868 | enum dma_data_direction direction, unsigned long dma_flags) | |
1869 | { | |
1870 | struct d40_chan *chan = container_of(dchan, struct d40_chan, chan); | |
822c5676 RV |
1871 | dma_addr_t src_dev_addr = 0; |
1872 | dma_addr_t dst_dev_addr = 0; | |
cade1d30 | 1873 | struct d40_desc *desc; |
2a614340 | 1874 | unsigned long flags; |
cade1d30 | 1875 | int ret; |
8d318a50 | 1876 | |
cade1d30 RV |
1877 | if (!chan->phy_chan) { |
1878 | chan_err(chan, "Cannot prepare unallocated channel\n"); | |
1879 | return NULL; | |
0d0f6b8b JA |
1880 | } |
1881 | ||
0c842b55 | 1882 | |
cade1d30 | 1883 | spin_lock_irqsave(&chan->lock, flags); |
8d318a50 | 1884 | |
cade1d30 RV |
1885 | desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags); |
1886 | if (desc == NULL) | |
8d318a50 LW |
1887 | goto err; |
1888 | ||
0c842b55 RV |
1889 | if (sg_next(&sg_src[sg_len - 1]) == sg_src) |
1890 | desc->cyclic = true; | |
1891 | ||
822c5676 RV |
1892 | if (direction != DMA_NONE) { |
1893 | dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); | |
1894 | ||
1895 | if (direction == DMA_FROM_DEVICE) | |
1896 | src_dev_addr = dev_addr; | |
1897 | else if (direction == DMA_TO_DEVICE) | |
1898 | dst_dev_addr = dev_addr; | |
1899 | } | |
cade1d30 RV |
1900 | |
1901 | if (chan_is_logical(chan)) | |
1902 | ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst, | |
822c5676 | 1903 | sg_len, src_dev_addr, dst_dev_addr); |
cade1d30 RV |
1904 | else |
1905 | ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst, | |
822c5676 | 1906 | sg_len, src_dev_addr, dst_dev_addr); |
cade1d30 RV |
1907 | |
1908 | if (ret) { | |
1909 | chan_err(chan, "Failed to prepare %s sg job: %d\n", | |
1910 | chan_is_logical(chan) ? "log" : "phy", ret); | |
1911 | goto err; | |
8d318a50 LW |
1912 | } |
1913 | ||
cade1d30 RV |
1914 | spin_unlock_irqrestore(&chan->lock, flags); |
1915 | ||
1916 | return &desc->txd; | |
8d318a50 | 1917 | |
8d318a50 | 1918 | err: |
cade1d30 RV |
1919 | if (desc) |
1920 | d40_desc_free(chan, desc); | |
1921 | spin_unlock_irqrestore(&chan->lock, flags); | |
8d318a50 LW |
1922 | return NULL; |
1923 | } | |
8d318a50 LW |
1924 | |
1925 | bool stedma40_filter(struct dma_chan *chan, void *data) | |
1926 | { | |
1927 | struct stedma40_chan_cfg *info = data; | |
1928 | struct d40_chan *d40c = | |
1929 | container_of(chan, struct d40_chan, chan); | |
1930 | int err; | |
1931 | ||
1932 | if (data) { | |
1933 | err = d40_validate_conf(d40c, info); | |
1934 | if (!err) | |
1935 | d40c->dma_cfg = *info; | |
1936 | } else | |
1937 | err = d40_config_memcpy(d40c); | |
1938 | ||
ce2ca125 RV |
1939 | if (!err) |
1940 | d40c->configured = true; | |
1941 | ||
8d318a50 LW |
1942 | return err == 0; |
1943 | } | |
1944 | EXPORT_SYMBOL(stedma40_filter); | |
1945 | ||
ac2c0a38 RV |
1946 | static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src) |
1947 | { | |
1948 | bool realtime = d40c->dma_cfg.realtime; | |
1949 | bool highprio = d40c->dma_cfg.high_priority; | |
1950 | u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1; | |
1951 | u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1; | |
1952 | u32 event = D40_TYPE_TO_EVENT(dev_type); | |
1953 | u32 group = D40_TYPE_TO_GROUP(dev_type); | |
1954 | u32 bit = 1 << event; | |
1955 | ||
1956 | /* Destination event lines are stored in the upper halfword */ | |
1957 | if (!src) | |
1958 | bit <<= 16; | |
1959 | ||
1960 | writel(bit, d40c->base->virtbase + prioreg + group * 4); | |
1961 | writel(bit, d40c->base->virtbase + rtreg + group * 4); | |
1962 | } | |
1963 | ||
1964 | static void d40_set_prio_realtime(struct d40_chan *d40c) | |
1965 | { | |
1966 | if (d40c->base->rev < 3) | |
1967 | return; | |
1968 | ||
1969 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || | |
1970 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) | |
1971 | __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true); | |
1972 | ||
1973 | if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) || | |
1974 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) | |
1975 | __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false); | |
1976 | } | |
1977 | ||
8d318a50 LW |
1978 | /* DMA ENGINE functions */ |
1979 | static int d40_alloc_chan_resources(struct dma_chan *chan) | |
1980 | { | |
1981 | int err; | |
1982 | unsigned long flags; | |
1983 | struct d40_chan *d40c = | |
1984 | container_of(chan, struct d40_chan, chan); | |
ef1872ec | 1985 | bool is_free_phy; |
8d318a50 LW |
1986 | spin_lock_irqsave(&d40c->lock, flags); |
1987 | ||
1988 | d40c->completed = chan->cookie = 1; | |
1989 | ||
ce2ca125 RV |
1990 | /* If no dma configuration is set use default configuration (memcpy) */ |
1991 | if (!d40c->configured) { | |
8d318a50 | 1992 | err = d40_config_memcpy(d40c); |
ff0b12ba | 1993 | if (err) { |
6db5a8ba | 1994 | chan_err(d40c, "Failed to configure memcpy channel\n"); |
ff0b12ba JA |
1995 | goto fail; |
1996 | } | |
8d318a50 | 1997 | } |
ef1872ec | 1998 | is_free_phy = (d40c->phy_chan == NULL); |
8d318a50 LW |
1999 | |
2000 | err = d40_allocate_channel(d40c); | |
2001 | if (err) { | |
6db5a8ba | 2002 | chan_err(d40c, "Failed to allocate channel\n"); |
ff0b12ba | 2003 | goto fail; |
8d318a50 LW |
2004 | } |
2005 | ||
ef1872ec LW |
2006 | /* Fill in basic CFG register values */ |
2007 | d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, | |
724a8577 | 2008 | &d40c->dst_def_cfg, chan_is_logical(d40c)); |
ef1872ec | 2009 | |
ac2c0a38 RV |
2010 | d40_set_prio_realtime(d40c); |
2011 | ||
724a8577 | 2012 | if (chan_is_logical(d40c)) { |
ef1872ec LW |
2013 | d40_log_cfg(&d40c->dma_cfg, |
2014 | &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); | |
2015 | ||
2016 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) | |
2017 | d40c->lcpa = d40c->base->lcpa_base + | |
2018 | d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE; | |
2019 | else | |
2020 | d40c->lcpa = d40c->base->lcpa_base + | |
2021 | d40c->dma_cfg.dst_dev_type * | |
2022 | D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; | |
2023 | } | |
2024 | ||
2025 | /* | |
2026 | * Only write channel configuration to the DMA if the physical | |
2027 | * resource is free. In case of multiple logical channels | |
2028 | * on the same physical resource, only the first write is necessary. | |
2029 | */ | |
b55912c6 JA |
2030 | if (is_free_phy) |
2031 | d40_config_write(d40c); | |
ff0b12ba | 2032 | fail: |
8d318a50 | 2033 | spin_unlock_irqrestore(&d40c->lock, flags); |
ff0b12ba | 2034 | return err; |
8d318a50 LW |
2035 | } |
2036 | ||
2037 | static void d40_free_chan_resources(struct dma_chan *chan) | |
2038 | { | |
2039 | struct d40_chan *d40c = | |
2040 | container_of(chan, struct d40_chan, chan); | |
2041 | int err; | |
2042 | unsigned long flags; | |
2043 | ||
0d0f6b8b | 2044 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2045 | chan_err(d40c, "Cannot free unallocated channel\n"); |
0d0f6b8b JA |
2046 | return; |
2047 | } | |
2048 | ||
2049 | ||
8d318a50 LW |
2050 | spin_lock_irqsave(&d40c->lock, flags); |
2051 | ||
2052 | err = d40_free_dma(d40c); | |
2053 | ||
2054 | if (err) | |
6db5a8ba | 2055 | chan_err(d40c, "Failed to free channel\n"); |
8d318a50 LW |
2056 | spin_unlock_irqrestore(&d40c->lock, flags); |
2057 | } | |
2058 | ||
2059 | static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan, | |
2060 | dma_addr_t dst, | |
2061 | dma_addr_t src, | |
2062 | size_t size, | |
2a614340 | 2063 | unsigned long dma_flags) |
8d318a50 | 2064 | { |
95944c6e RV |
2065 | struct scatterlist dst_sg; |
2066 | struct scatterlist src_sg; | |
8d318a50 | 2067 | |
95944c6e RV |
2068 | sg_init_table(&dst_sg, 1); |
2069 | sg_init_table(&src_sg, 1); | |
8d318a50 | 2070 | |
95944c6e RV |
2071 | sg_dma_address(&dst_sg) = dst; |
2072 | sg_dma_address(&src_sg) = src; | |
8d318a50 | 2073 | |
95944c6e RV |
2074 | sg_dma_len(&dst_sg) = size; |
2075 | sg_dma_len(&src_sg) = size; | |
8d318a50 | 2076 | |
cade1d30 | 2077 | return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags); |
8d318a50 LW |
2078 | } |
2079 | ||
0d688662 | 2080 | static struct dma_async_tx_descriptor * |
cade1d30 RV |
2081 | d40_prep_memcpy_sg(struct dma_chan *chan, |
2082 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
2083 | struct scatterlist *src_sg, unsigned int src_nents, | |
2084 | unsigned long dma_flags) | |
0d688662 IS |
2085 | { |
2086 | if (dst_nents != src_nents) | |
2087 | return NULL; | |
2088 | ||
cade1d30 | 2089 | return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags); |
00ac0341 RV |
2090 | } |
2091 | ||
8d318a50 LW |
2092 | static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan, |
2093 | struct scatterlist *sgl, | |
2094 | unsigned int sg_len, | |
2095 | enum dma_data_direction direction, | |
2a614340 | 2096 | unsigned long dma_flags) |
8d318a50 | 2097 | { |
00ac0341 RV |
2098 | if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) |
2099 | return NULL; | |
2100 | ||
cade1d30 | 2101 | return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags); |
8d318a50 LW |
2102 | } |
2103 | ||
0c842b55 RV |
2104 | static struct dma_async_tx_descriptor * |
2105 | dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, | |
2106 | size_t buf_len, size_t period_len, | |
2107 | enum dma_data_direction direction) | |
2108 | { | |
2109 | unsigned int periods = buf_len / period_len; | |
2110 | struct dma_async_tx_descriptor *txd; | |
2111 | struct scatterlist *sg; | |
2112 | int i; | |
2113 | ||
79ca7ec3 | 2114 | sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT); |
0c842b55 RV |
2115 | for (i = 0; i < periods; i++) { |
2116 | sg_dma_address(&sg[i]) = dma_addr; | |
2117 | sg_dma_len(&sg[i]) = period_len; | |
2118 | dma_addr += period_len; | |
2119 | } | |
2120 | ||
2121 | sg[periods].offset = 0; | |
2122 | sg[periods].length = 0; | |
2123 | sg[periods].page_link = | |
2124 | ((unsigned long)sg | 0x01) & ~0x02; | |
2125 | ||
2126 | txd = d40_prep_sg(chan, sg, sg, periods, direction, | |
2127 | DMA_PREP_INTERRUPT); | |
2128 | ||
2129 | kfree(sg); | |
2130 | ||
2131 | return txd; | |
2132 | } | |
2133 | ||
8d318a50 LW |
2134 | static enum dma_status d40_tx_status(struct dma_chan *chan, |
2135 | dma_cookie_t cookie, | |
2136 | struct dma_tx_state *txstate) | |
2137 | { | |
2138 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2139 | dma_cookie_t last_used; | |
2140 | dma_cookie_t last_complete; | |
2141 | int ret; | |
2142 | ||
0d0f6b8b | 2143 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2144 | chan_err(d40c, "Cannot read status of unallocated channel\n"); |
0d0f6b8b JA |
2145 | return -EINVAL; |
2146 | } | |
2147 | ||
8d318a50 LW |
2148 | last_complete = d40c->completed; |
2149 | last_used = chan->cookie; | |
2150 | ||
a5ebca47 JA |
2151 | if (d40_is_paused(d40c)) |
2152 | ret = DMA_PAUSED; | |
2153 | else | |
2154 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
8d318a50 | 2155 | |
a5ebca47 JA |
2156 | dma_set_tx_state(txstate, last_complete, last_used, |
2157 | stedma40_residue(chan)); | |
8d318a50 LW |
2158 | |
2159 | return ret; | |
2160 | } | |
2161 | ||
2162 | static void d40_issue_pending(struct dma_chan *chan) | |
2163 | { | |
2164 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2165 | unsigned long flags; | |
2166 | ||
0d0f6b8b | 2167 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2168 | chan_err(d40c, "Channel is not allocated!\n"); |
0d0f6b8b JA |
2169 | return; |
2170 | } | |
2171 | ||
8d318a50 LW |
2172 | spin_lock_irqsave(&d40c->lock, flags); |
2173 | ||
a8f3067b PF |
2174 | list_splice_tail_init(&d40c->pending_queue, &d40c->queue); |
2175 | ||
2176 | /* Busy means that queued jobs are already being processed */ | |
8d318a50 LW |
2177 | if (!d40c->busy) |
2178 | (void) d40_queue_start(d40c); | |
2179 | ||
2180 | spin_unlock_irqrestore(&d40c->lock, flags); | |
2181 | } | |
2182 | ||
98ca5289 RV |
2183 | static int |
2184 | dma40_config_to_halfchannel(struct d40_chan *d40c, | |
2185 | struct stedma40_half_channel_info *info, | |
2186 | enum dma_slave_buswidth width, | |
2187 | u32 maxburst) | |
2188 | { | |
2189 | enum stedma40_periph_data_width addr_width; | |
2190 | int psize; | |
2191 | ||
2192 | switch (width) { | |
2193 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
2194 | addr_width = STEDMA40_BYTE_WIDTH; | |
2195 | break; | |
2196 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
2197 | addr_width = STEDMA40_HALFWORD_WIDTH; | |
2198 | break; | |
2199 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
2200 | addr_width = STEDMA40_WORD_WIDTH; | |
2201 | break; | |
2202 | case DMA_SLAVE_BUSWIDTH_8_BYTES: | |
2203 | addr_width = STEDMA40_DOUBLEWORD_WIDTH; | |
2204 | break; | |
2205 | default: | |
2206 | dev_err(d40c->base->dev, | |
2207 | "illegal peripheral address width " | |
2208 | "requested (%d)\n", | |
2209 | width); | |
2210 | return -EINVAL; | |
2211 | } | |
2212 | ||
2213 | if (chan_is_logical(d40c)) { | |
2214 | if (maxburst >= 16) | |
2215 | psize = STEDMA40_PSIZE_LOG_16; | |
2216 | else if (maxburst >= 8) | |
2217 | psize = STEDMA40_PSIZE_LOG_8; | |
2218 | else if (maxburst >= 4) | |
2219 | psize = STEDMA40_PSIZE_LOG_4; | |
2220 | else | |
2221 | psize = STEDMA40_PSIZE_LOG_1; | |
2222 | } else { | |
2223 | if (maxburst >= 16) | |
2224 | psize = STEDMA40_PSIZE_PHY_16; | |
2225 | else if (maxburst >= 8) | |
2226 | psize = STEDMA40_PSIZE_PHY_8; | |
2227 | else if (maxburst >= 4) | |
2228 | psize = STEDMA40_PSIZE_PHY_4; | |
2229 | else | |
2230 | psize = STEDMA40_PSIZE_PHY_1; | |
2231 | } | |
2232 | ||
2233 | info->data_width = addr_width; | |
2234 | info->psize = psize; | |
2235 | info->flow_ctrl = STEDMA40_NO_FLOW_CTRL; | |
2236 | ||
2237 | return 0; | |
2238 | } | |
2239 | ||
95e1400f | 2240 | /* Runtime reconfiguration extension */ |
98ca5289 RV |
2241 | static int d40_set_runtime_config(struct dma_chan *chan, |
2242 | struct dma_slave_config *config) | |
95e1400f LW |
2243 | { |
2244 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2245 | struct stedma40_chan_cfg *cfg = &d40c->dma_cfg; | |
98ca5289 | 2246 | enum dma_slave_buswidth src_addr_width, dst_addr_width; |
95e1400f | 2247 | dma_addr_t config_addr; |
98ca5289 RV |
2248 | u32 src_maxburst, dst_maxburst; |
2249 | int ret; | |
2250 | ||
2251 | src_addr_width = config->src_addr_width; | |
2252 | src_maxburst = config->src_maxburst; | |
2253 | dst_addr_width = config->dst_addr_width; | |
2254 | dst_maxburst = config->dst_maxburst; | |
95e1400f LW |
2255 | |
2256 | if (config->direction == DMA_FROM_DEVICE) { | |
2257 | dma_addr_t dev_addr_rx = | |
2258 | d40c->base->plat_data->dev_rx[cfg->src_dev_type]; | |
2259 | ||
2260 | config_addr = config->src_addr; | |
2261 | if (dev_addr_rx) | |
2262 | dev_dbg(d40c->base->dev, | |
2263 | "channel has a pre-wired RX address %08x " | |
2264 | "overriding with %08x\n", | |
2265 | dev_addr_rx, config_addr); | |
2266 | if (cfg->dir != STEDMA40_PERIPH_TO_MEM) | |
2267 | dev_dbg(d40c->base->dev, | |
2268 | "channel was not configured for peripheral " | |
2269 | "to memory transfer (%d) overriding\n", | |
2270 | cfg->dir); | |
2271 | cfg->dir = STEDMA40_PERIPH_TO_MEM; | |
2272 | ||
98ca5289 RV |
2273 | /* Configure the memory side */ |
2274 | if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
2275 | dst_addr_width = src_addr_width; | |
2276 | if (dst_maxburst == 0) | |
2277 | dst_maxburst = src_maxburst; | |
95e1400f LW |
2278 | |
2279 | } else if (config->direction == DMA_TO_DEVICE) { | |
2280 | dma_addr_t dev_addr_tx = | |
2281 | d40c->base->plat_data->dev_tx[cfg->dst_dev_type]; | |
2282 | ||
2283 | config_addr = config->dst_addr; | |
2284 | if (dev_addr_tx) | |
2285 | dev_dbg(d40c->base->dev, | |
2286 | "channel has a pre-wired TX address %08x " | |
2287 | "overriding with %08x\n", | |
2288 | dev_addr_tx, config_addr); | |
2289 | if (cfg->dir != STEDMA40_MEM_TO_PERIPH) | |
2290 | dev_dbg(d40c->base->dev, | |
2291 | "channel was not configured for memory " | |
2292 | "to peripheral transfer (%d) overriding\n", | |
2293 | cfg->dir); | |
2294 | cfg->dir = STEDMA40_MEM_TO_PERIPH; | |
2295 | ||
98ca5289 RV |
2296 | /* Configure the memory side */ |
2297 | if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
2298 | src_addr_width = dst_addr_width; | |
2299 | if (src_maxburst == 0) | |
2300 | src_maxburst = dst_maxburst; | |
95e1400f LW |
2301 | } else { |
2302 | dev_err(d40c->base->dev, | |
2303 | "unrecognized channel direction %d\n", | |
2304 | config->direction); | |
98ca5289 | 2305 | return -EINVAL; |
95e1400f LW |
2306 | } |
2307 | ||
98ca5289 | 2308 | if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) { |
95e1400f | 2309 | dev_err(d40c->base->dev, |
98ca5289 RV |
2310 | "src/dst width/maxburst mismatch: %d*%d != %d*%d\n", |
2311 | src_maxburst, | |
2312 | src_addr_width, | |
2313 | dst_maxburst, | |
2314 | dst_addr_width); | |
2315 | return -EINVAL; | |
95e1400f LW |
2316 | } |
2317 | ||
98ca5289 RV |
2318 | ret = dma40_config_to_halfchannel(d40c, &cfg->src_info, |
2319 | src_addr_width, | |
2320 | src_maxburst); | |
2321 | if (ret) | |
2322 | return ret; | |
95e1400f | 2323 | |
98ca5289 RV |
2324 | ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info, |
2325 | dst_addr_width, | |
2326 | dst_maxburst); | |
2327 | if (ret) | |
2328 | return ret; | |
95e1400f | 2329 | |
a59670a4 | 2330 | /* Fill in register values */ |
724a8577 | 2331 | if (chan_is_logical(d40c)) |
a59670a4 PF |
2332 | d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); |
2333 | else | |
2334 | d40_phy_cfg(cfg, &d40c->src_def_cfg, | |
2335 | &d40c->dst_def_cfg, false); | |
2336 | ||
95e1400f LW |
2337 | /* These settings will take precedence later */ |
2338 | d40c->runtime_addr = config_addr; | |
2339 | d40c->runtime_direction = config->direction; | |
2340 | dev_dbg(d40c->base->dev, | |
98ca5289 RV |
2341 | "configured channel %s for %s, data width %d/%d, " |
2342 | "maxburst %d/%d elements, LE, no flow control\n", | |
95e1400f LW |
2343 | dma_chan_name(chan), |
2344 | (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", | |
98ca5289 RV |
2345 | src_addr_width, dst_addr_width, |
2346 | src_maxburst, dst_maxburst); | |
2347 | ||
2348 | return 0; | |
95e1400f LW |
2349 | } |
2350 | ||
05827630 LW |
2351 | static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
2352 | unsigned long arg) | |
8d318a50 | 2353 | { |
8d318a50 LW |
2354 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
2355 | ||
0d0f6b8b | 2356 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2357 | chan_err(d40c, "Channel is not allocated!\n"); |
0d0f6b8b JA |
2358 | return -EINVAL; |
2359 | } | |
2360 | ||
8d318a50 LW |
2361 | switch (cmd) { |
2362 | case DMA_TERMINATE_ALL: | |
86eb5fb6 | 2363 | return d40_terminate_all(d40c); |
8d318a50 | 2364 | case DMA_PAUSE: |
86eb5fb6 | 2365 | return d40_pause(d40c); |
8d318a50 | 2366 | case DMA_RESUME: |
86eb5fb6 | 2367 | return d40_resume(d40c); |
95e1400f | 2368 | case DMA_SLAVE_CONFIG: |
98ca5289 | 2369 | return d40_set_runtime_config(chan, |
95e1400f | 2370 | (struct dma_slave_config *) arg); |
95e1400f LW |
2371 | default: |
2372 | break; | |
8d318a50 LW |
2373 | } |
2374 | ||
2375 | /* Other commands are unimplemented */ | |
2376 | return -ENXIO; | |
2377 | } | |
2378 | ||
2379 | /* Initialization functions */ | |
2380 | ||
2381 | static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, | |
2382 | struct d40_chan *chans, int offset, | |
2383 | int num_chans) | |
2384 | { | |
2385 | int i = 0; | |
2386 | struct d40_chan *d40c; | |
2387 | ||
2388 | INIT_LIST_HEAD(&dma->channels); | |
2389 | ||
2390 | for (i = offset; i < offset + num_chans; i++) { | |
2391 | d40c = &chans[i]; | |
2392 | d40c->base = base; | |
2393 | d40c->chan.device = dma; | |
2394 | ||
8d318a50 LW |
2395 | spin_lock_init(&d40c->lock); |
2396 | ||
2397 | d40c->log_num = D40_PHY_CHAN; | |
2398 | ||
8d318a50 LW |
2399 | INIT_LIST_HEAD(&d40c->active); |
2400 | INIT_LIST_HEAD(&d40c->queue); | |
a8f3067b | 2401 | INIT_LIST_HEAD(&d40c->pending_queue); |
8d318a50 LW |
2402 | INIT_LIST_HEAD(&d40c->client); |
2403 | ||
8d318a50 LW |
2404 | tasklet_init(&d40c->tasklet, dma_tasklet, |
2405 | (unsigned long) d40c); | |
2406 | ||
2407 | list_add_tail(&d40c->chan.device_node, | |
2408 | &dma->channels); | |
2409 | } | |
2410 | } | |
2411 | ||
7ad74a7c RV |
2412 | static void d40_ops_init(struct d40_base *base, struct dma_device *dev) |
2413 | { | |
2414 | if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) | |
2415 | dev->device_prep_slave_sg = d40_prep_slave_sg; | |
2416 | ||
2417 | if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) { | |
2418 | dev->device_prep_dma_memcpy = d40_prep_memcpy; | |
2419 | ||
2420 | /* | |
2421 | * This controller can only access address at even | |
2422 | * 32bit boundaries, i.e. 2^2 | |
2423 | */ | |
2424 | dev->copy_align = 2; | |
2425 | } | |
2426 | ||
2427 | if (dma_has_cap(DMA_SG, dev->cap_mask)) | |
2428 | dev->device_prep_dma_sg = d40_prep_memcpy_sg; | |
2429 | ||
0c842b55 RV |
2430 | if (dma_has_cap(DMA_CYCLIC, dev->cap_mask)) |
2431 | dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic; | |
2432 | ||
7ad74a7c RV |
2433 | dev->device_alloc_chan_resources = d40_alloc_chan_resources; |
2434 | dev->device_free_chan_resources = d40_free_chan_resources; | |
2435 | dev->device_issue_pending = d40_issue_pending; | |
2436 | dev->device_tx_status = d40_tx_status; | |
2437 | dev->device_control = d40_control; | |
2438 | dev->dev = base->dev; | |
2439 | } | |
2440 | ||
8d318a50 LW |
2441 | static int __init d40_dmaengine_init(struct d40_base *base, |
2442 | int num_reserved_chans) | |
2443 | { | |
2444 | int err ; | |
2445 | ||
2446 | d40_chan_init(base, &base->dma_slave, base->log_chans, | |
2447 | 0, base->num_log_chans); | |
2448 | ||
2449 | dma_cap_zero(base->dma_slave.cap_mask); | |
2450 | dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); | |
0c842b55 | 2451 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
8d318a50 | 2452 | |
7ad74a7c | 2453 | d40_ops_init(base, &base->dma_slave); |
8d318a50 LW |
2454 | |
2455 | err = dma_async_device_register(&base->dma_slave); | |
2456 | ||
2457 | if (err) { | |
6db5a8ba | 2458 | d40_err(base->dev, "Failed to register slave channels\n"); |
8d318a50 LW |
2459 | goto failure1; |
2460 | } | |
2461 | ||
2462 | d40_chan_init(base, &base->dma_memcpy, base->log_chans, | |
2463 | base->num_log_chans, base->plat_data->memcpy_len); | |
2464 | ||
2465 | dma_cap_zero(base->dma_memcpy.cap_mask); | |
2466 | dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); | |
7ad74a7c RV |
2467 | dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask); |
2468 | ||
2469 | d40_ops_init(base, &base->dma_memcpy); | |
8d318a50 LW |
2470 | |
2471 | err = dma_async_device_register(&base->dma_memcpy); | |
2472 | ||
2473 | if (err) { | |
6db5a8ba RV |
2474 | d40_err(base->dev, |
2475 | "Failed to regsiter memcpy only channels\n"); | |
8d318a50 LW |
2476 | goto failure2; |
2477 | } | |
2478 | ||
2479 | d40_chan_init(base, &base->dma_both, base->phy_chans, | |
2480 | 0, num_reserved_chans); | |
2481 | ||
2482 | dma_cap_zero(base->dma_both.cap_mask); | |
2483 | dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); | |
2484 | dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); | |
7ad74a7c | 2485 | dma_cap_set(DMA_SG, base->dma_both.cap_mask); |
0c842b55 | 2486 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
7ad74a7c RV |
2487 | |
2488 | d40_ops_init(base, &base->dma_both); | |
8d318a50 LW |
2489 | err = dma_async_device_register(&base->dma_both); |
2490 | ||
2491 | if (err) { | |
6db5a8ba RV |
2492 | d40_err(base->dev, |
2493 | "Failed to register logical and physical capable channels\n"); | |
8d318a50 LW |
2494 | goto failure3; |
2495 | } | |
2496 | return 0; | |
2497 | failure3: | |
2498 | dma_async_device_unregister(&base->dma_memcpy); | |
2499 | failure2: | |
2500 | dma_async_device_unregister(&base->dma_slave); | |
2501 | failure1: | |
2502 | return err; | |
2503 | } | |
2504 | ||
2505 | /* Initialization functions. */ | |
2506 | ||
2507 | static int __init d40_phy_res_init(struct d40_base *base) | |
2508 | { | |
2509 | int i; | |
2510 | int num_phy_chans_avail = 0; | |
2511 | u32 val[2]; | |
2512 | int odd_even_bit = -2; | |
2513 | ||
2514 | val[0] = readl(base->virtbase + D40_DREG_PRSME); | |
2515 | val[1] = readl(base->virtbase + D40_DREG_PRSMO); | |
2516 | ||
2517 | for (i = 0; i < base->num_phy_chans; i++) { | |
2518 | base->phy_res[i].num = i; | |
2519 | odd_even_bit += 2 * ((i % 2) == 0); | |
2520 | if (((val[i % 2] >> odd_even_bit) & 3) == 1) { | |
2521 | /* Mark security only channels as occupied */ | |
2522 | base->phy_res[i].allocated_src = D40_ALLOC_PHY; | |
2523 | base->phy_res[i].allocated_dst = D40_ALLOC_PHY; | |
2524 | } else { | |
2525 | base->phy_res[i].allocated_src = D40_ALLOC_FREE; | |
2526 | base->phy_res[i].allocated_dst = D40_ALLOC_FREE; | |
2527 | num_phy_chans_avail++; | |
2528 | } | |
2529 | spin_lock_init(&base->phy_res[i].lock); | |
2530 | } | |
6b7acd84 JA |
2531 | |
2532 | /* Mark disabled channels as occupied */ | |
2533 | for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { | |
f57b407c RV |
2534 | int chan = base->plat_data->disabled_channels[i]; |
2535 | ||
2536 | base->phy_res[chan].allocated_src = D40_ALLOC_PHY; | |
2537 | base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; | |
2538 | num_phy_chans_avail--; | |
6b7acd84 JA |
2539 | } |
2540 | ||
8d318a50 LW |
2541 | dev_info(base->dev, "%d of %d physical DMA channels available\n", |
2542 | num_phy_chans_avail, base->num_phy_chans); | |
2543 | ||
2544 | /* Verify settings extended vs standard */ | |
2545 | val[0] = readl(base->virtbase + D40_DREG_PRTYP); | |
2546 | ||
2547 | for (i = 0; i < base->num_phy_chans; i++) { | |
2548 | ||
2549 | if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && | |
2550 | (val[0] & 0x3) != 1) | |
2551 | dev_info(base->dev, | |
2552 | "[%s] INFO: channel %d is misconfigured (%d)\n", | |
2553 | __func__, i, val[0] & 0x3); | |
2554 | ||
2555 | val[0] = val[0] >> 2; | |
2556 | } | |
2557 | ||
2558 | return num_phy_chans_avail; | |
2559 | } | |
2560 | ||
2561 | static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) | |
2562 | { | |
8d318a50 LW |
2563 | struct stedma40_platform_data *plat_data; |
2564 | struct clk *clk = NULL; | |
2565 | void __iomem *virtbase = NULL; | |
2566 | struct resource *res = NULL; | |
2567 | struct d40_base *base = NULL; | |
2568 | int num_log_chans = 0; | |
2569 | int num_phy_chans; | |
2570 | int i; | |
f4b89764 LW |
2571 | u32 pid; |
2572 | u32 cid; | |
2573 | u8 rev; | |
8d318a50 LW |
2574 | |
2575 | clk = clk_get(&pdev->dev, NULL); | |
2576 | ||
2577 | if (IS_ERR(clk)) { | |
6db5a8ba | 2578 | d40_err(&pdev->dev, "No matching clock found\n"); |
8d318a50 LW |
2579 | goto failure; |
2580 | } | |
2581 | ||
2582 | clk_enable(clk); | |
2583 | ||
2584 | /* Get IO for DMAC base address */ | |
2585 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); | |
2586 | if (!res) | |
2587 | goto failure; | |
2588 | ||
2589 | if (request_mem_region(res->start, resource_size(res), | |
2590 | D40_NAME " I/O base") == NULL) | |
2591 | goto failure; | |
2592 | ||
2593 | virtbase = ioremap(res->start, resource_size(res)); | |
2594 | if (!virtbase) | |
2595 | goto failure; | |
2596 | ||
f4b89764 LW |
2597 | /* This is just a regular AMBA PrimeCell ID actually */ |
2598 | for (pid = 0, i = 0; i < 4; i++) | |
2599 | pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i) | |
2600 | & 255) << (i * 8); | |
2601 | for (cid = 0, i = 0; i < 4; i++) | |
2602 | cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i) | |
2603 | & 255) << (i * 8); | |
8d318a50 | 2604 | |
f4b89764 LW |
2605 | if (cid != AMBA_CID) { |
2606 | d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n"); | |
2607 | goto failure; | |
2608 | } | |
2609 | if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) { | |
6db5a8ba | 2610 | d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n", |
f4b89764 LW |
2611 | AMBA_MANF_BITS(pid), |
2612 | AMBA_VENDOR_ST); | |
8d318a50 LW |
2613 | goto failure; |
2614 | } | |
f4b89764 LW |
2615 | /* |
2616 | * HW revision: | |
2617 | * DB8500ed has revision 0 | |
2618 | * ? has revision 1 | |
2619 | * DB8500v1 has revision 2 | |
2620 | * DB8500v2 has revision 3 | |
2621 | */ | |
2622 | rev = AMBA_REV_BITS(pid); | |
3ae0267f | 2623 | |
8d318a50 LW |
2624 | /* The number of physical channels on this HW */ |
2625 | num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; | |
2626 | ||
2627 | dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n", | |
3ae0267f | 2628 | rev, res->start); |
8d318a50 LW |
2629 | |
2630 | plat_data = pdev->dev.platform_data; | |
2631 | ||
2632 | /* Count the number of logical channels in use */ | |
2633 | for (i = 0; i < plat_data->dev_len; i++) | |
2634 | if (plat_data->dev_rx[i] != 0) | |
2635 | num_log_chans++; | |
2636 | ||
2637 | for (i = 0; i < plat_data->dev_len; i++) | |
2638 | if (plat_data->dev_tx[i] != 0) | |
2639 | num_log_chans++; | |
2640 | ||
2641 | base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + | |
2642 | (num_phy_chans + num_log_chans + plat_data->memcpy_len) * | |
2643 | sizeof(struct d40_chan), GFP_KERNEL); | |
2644 | ||
2645 | if (base == NULL) { | |
6db5a8ba | 2646 | d40_err(&pdev->dev, "Out of memory\n"); |
8d318a50 LW |
2647 | goto failure; |
2648 | } | |
2649 | ||
3ae0267f | 2650 | base->rev = rev; |
8d318a50 LW |
2651 | base->clk = clk; |
2652 | base->num_phy_chans = num_phy_chans; | |
2653 | base->num_log_chans = num_log_chans; | |
2654 | base->phy_start = res->start; | |
2655 | base->phy_size = resource_size(res); | |
2656 | base->virtbase = virtbase; | |
2657 | base->plat_data = plat_data; | |
2658 | base->dev = &pdev->dev; | |
2659 | base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); | |
2660 | base->log_chans = &base->phy_chans[num_phy_chans]; | |
2661 | ||
2662 | base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res), | |
2663 | GFP_KERNEL); | |
2664 | if (!base->phy_res) | |
2665 | goto failure; | |
2666 | ||
2667 | base->lookup_phy_chans = kzalloc(num_phy_chans * | |
2668 | sizeof(struct d40_chan *), | |
2669 | GFP_KERNEL); | |
2670 | if (!base->lookup_phy_chans) | |
2671 | goto failure; | |
2672 | ||
2673 | if (num_log_chans + plat_data->memcpy_len) { | |
2674 | /* | |
2675 | * The max number of logical channels are event lines for all | |
2676 | * src devices and dst devices | |
2677 | */ | |
2678 | base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 * | |
2679 | sizeof(struct d40_chan *), | |
2680 | GFP_KERNEL); | |
2681 | if (!base->lookup_log_chans) | |
2682 | goto failure; | |
2683 | } | |
698e4732 JA |
2684 | |
2685 | base->lcla_pool.alloc_map = kzalloc(num_phy_chans * | |
2686 | sizeof(struct d40_desc *) * | |
2687 | D40_LCLA_LINK_PER_EVENT_GRP, | |
8d318a50 LW |
2688 | GFP_KERNEL); |
2689 | if (!base->lcla_pool.alloc_map) | |
2690 | goto failure; | |
2691 | ||
c675b1b4 JA |
2692 | base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), |
2693 | 0, SLAB_HWCACHE_ALIGN, | |
2694 | NULL); | |
2695 | if (base->desc_slab == NULL) | |
2696 | goto failure; | |
2697 | ||
8d318a50 LW |
2698 | return base; |
2699 | ||
2700 | failure: | |
c6134c96 | 2701 | if (!IS_ERR(clk)) { |
8d318a50 LW |
2702 | clk_disable(clk); |
2703 | clk_put(clk); | |
2704 | } | |
2705 | if (virtbase) | |
2706 | iounmap(virtbase); | |
2707 | if (res) | |
2708 | release_mem_region(res->start, | |
2709 | resource_size(res)); | |
2710 | if (virtbase) | |
2711 | iounmap(virtbase); | |
2712 | ||
2713 | if (base) { | |
2714 | kfree(base->lcla_pool.alloc_map); | |
2715 | kfree(base->lookup_log_chans); | |
2716 | kfree(base->lookup_phy_chans); | |
2717 | kfree(base->phy_res); | |
2718 | kfree(base); | |
2719 | } | |
2720 | ||
2721 | return NULL; | |
2722 | } | |
2723 | ||
2724 | static void __init d40_hw_init(struct d40_base *base) | |
2725 | { | |
2726 | ||
2727 | static const struct d40_reg_val dma_init_reg[] = { | |
2728 | /* Clock every part of the DMA block from start */ | |
2729 | { .reg = D40_DREG_GCC, .val = 0x0000ff01}, | |
2730 | ||
2731 | /* Interrupts on all logical channels */ | |
2732 | { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, | |
2733 | { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, | |
2734 | { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, | |
2735 | { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, | |
2736 | { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, | |
2737 | { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, | |
2738 | { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, | |
2739 | { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, | |
2740 | { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, | |
2741 | { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, | |
2742 | { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, | |
2743 | { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} | |
2744 | }; | |
2745 | int i; | |
2746 | u32 prmseo[2] = {0, 0}; | |
2747 | u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF}; | |
2748 | u32 pcmis = 0; | |
2749 | u32 pcicr = 0; | |
2750 | ||
2751 | for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++) | |
2752 | writel(dma_init_reg[i].val, | |
2753 | base->virtbase + dma_init_reg[i].reg); | |
2754 | ||
2755 | /* Configure all our dma channels to default settings */ | |
2756 | for (i = 0; i < base->num_phy_chans; i++) { | |
2757 | ||
2758 | activeo[i % 2] = activeo[i % 2] << 2; | |
2759 | ||
2760 | if (base->phy_res[base->num_phy_chans - i - 1].allocated_src | |
2761 | == D40_ALLOC_PHY) { | |
2762 | activeo[i % 2] |= 3; | |
2763 | continue; | |
2764 | } | |
2765 | ||
2766 | /* Enable interrupt # */ | |
2767 | pcmis = (pcmis << 1) | 1; | |
2768 | ||
2769 | /* Clear interrupt # */ | |
2770 | pcicr = (pcicr << 1) | 1; | |
2771 | ||
2772 | /* Set channel to physical mode */ | |
2773 | prmseo[i % 2] = prmseo[i % 2] << 2; | |
2774 | prmseo[i % 2] |= 1; | |
2775 | ||
2776 | } | |
2777 | ||
2778 | writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); | |
2779 | writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); | |
2780 | writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); | |
2781 | writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); | |
2782 | ||
2783 | /* Write which interrupt to enable */ | |
2784 | writel(pcmis, base->virtbase + D40_DREG_PCMIS); | |
2785 | ||
2786 | /* Write which interrupt to clear */ | |
2787 | writel(pcicr, base->virtbase + D40_DREG_PCICR); | |
2788 | ||
2789 | } | |
2790 | ||
508849ad LW |
2791 | static int __init d40_lcla_allocate(struct d40_base *base) |
2792 | { | |
026cbc42 | 2793 | struct d40_lcla_pool *pool = &base->lcla_pool; |
508849ad LW |
2794 | unsigned long *page_list; |
2795 | int i, j; | |
2796 | int ret = 0; | |
2797 | ||
2798 | /* | |
2799 | * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned, | |
2800 | * To full fill this hardware requirement without wasting 256 kb | |
2801 | * we allocate pages until we get an aligned one. | |
2802 | */ | |
2803 | page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS, | |
2804 | GFP_KERNEL); | |
2805 | ||
2806 | if (!page_list) { | |
2807 | ret = -ENOMEM; | |
2808 | goto failure; | |
2809 | } | |
2810 | ||
2811 | /* Calculating how many pages that are required */ | |
2812 | base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; | |
2813 | ||
2814 | for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) { | |
2815 | page_list[i] = __get_free_pages(GFP_KERNEL, | |
2816 | base->lcla_pool.pages); | |
2817 | if (!page_list[i]) { | |
2818 | ||
6db5a8ba RV |
2819 | d40_err(base->dev, "Failed to allocate %d pages.\n", |
2820 | base->lcla_pool.pages); | |
508849ad LW |
2821 | |
2822 | for (j = 0; j < i; j++) | |
2823 | free_pages(page_list[j], base->lcla_pool.pages); | |
2824 | goto failure; | |
2825 | } | |
2826 | ||
2827 | if ((virt_to_phys((void *)page_list[i]) & | |
2828 | (LCLA_ALIGNMENT - 1)) == 0) | |
2829 | break; | |
2830 | } | |
2831 | ||
2832 | for (j = 0; j < i; j++) | |
2833 | free_pages(page_list[j], base->lcla_pool.pages); | |
2834 | ||
2835 | if (i < MAX_LCLA_ALLOC_ATTEMPTS) { | |
2836 | base->lcla_pool.base = (void *)page_list[i]; | |
2837 | } else { | |
767a9675 JA |
2838 | /* |
2839 | * After many attempts and no succees with finding the correct | |
2840 | * alignment, try with allocating a big buffer. | |
2841 | */ | |
508849ad LW |
2842 | dev_warn(base->dev, |
2843 | "[%s] Failed to get %d pages @ 18 bit align.\n", | |
2844 | __func__, base->lcla_pool.pages); | |
2845 | base->lcla_pool.base_unaligned = kmalloc(SZ_1K * | |
2846 | base->num_phy_chans + | |
2847 | LCLA_ALIGNMENT, | |
2848 | GFP_KERNEL); | |
2849 | if (!base->lcla_pool.base_unaligned) { | |
2850 | ret = -ENOMEM; | |
2851 | goto failure; | |
2852 | } | |
2853 | ||
2854 | base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, | |
2855 | LCLA_ALIGNMENT); | |
2856 | } | |
2857 | ||
026cbc42 RV |
2858 | pool->dma_addr = dma_map_single(base->dev, pool->base, |
2859 | SZ_1K * base->num_phy_chans, | |
2860 | DMA_TO_DEVICE); | |
2861 | if (dma_mapping_error(base->dev, pool->dma_addr)) { | |
2862 | pool->dma_addr = 0; | |
2863 | ret = -ENOMEM; | |
2864 | goto failure; | |
2865 | } | |
2866 | ||
508849ad LW |
2867 | writel(virt_to_phys(base->lcla_pool.base), |
2868 | base->virtbase + D40_DREG_LCLA); | |
2869 | failure: | |
2870 | kfree(page_list); | |
2871 | return ret; | |
2872 | } | |
2873 | ||
8d318a50 LW |
2874 | static int __init d40_probe(struct platform_device *pdev) |
2875 | { | |
2876 | int err; | |
2877 | int ret = -ENOENT; | |
2878 | struct d40_base *base; | |
2879 | struct resource *res = NULL; | |
2880 | int num_reserved_chans; | |
2881 | u32 val; | |
2882 | ||
2883 | base = d40_hw_detect_init(pdev); | |
2884 | ||
2885 | if (!base) | |
2886 | goto failure; | |
2887 | ||
2888 | num_reserved_chans = d40_phy_res_init(base); | |
2889 | ||
2890 | platform_set_drvdata(pdev, base); | |
2891 | ||
2892 | spin_lock_init(&base->interrupt_lock); | |
2893 | spin_lock_init(&base->execmd_lock); | |
2894 | ||
2895 | /* Get IO for logical channel parameter address */ | |
2896 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa"); | |
2897 | if (!res) { | |
2898 | ret = -ENOENT; | |
6db5a8ba | 2899 | d40_err(&pdev->dev, "No \"lcpa\" memory resource\n"); |
8d318a50 LW |
2900 | goto failure; |
2901 | } | |
2902 | base->lcpa_size = resource_size(res); | |
2903 | base->phy_lcpa = res->start; | |
2904 | ||
2905 | if (request_mem_region(res->start, resource_size(res), | |
2906 | D40_NAME " I/O lcpa") == NULL) { | |
2907 | ret = -EBUSY; | |
6db5a8ba RV |
2908 | d40_err(&pdev->dev, |
2909 | "Failed to request LCPA region 0x%x-0x%x\n", | |
2910 | res->start, res->end); | |
8d318a50 LW |
2911 | goto failure; |
2912 | } | |
2913 | ||
2914 | /* We make use of ESRAM memory for this. */ | |
2915 | val = readl(base->virtbase + D40_DREG_LCPA); | |
2916 | if (res->start != val && val != 0) { | |
2917 | dev_warn(&pdev->dev, | |
2918 | "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n", | |
2919 | __func__, val, res->start); | |
2920 | } else | |
2921 | writel(res->start, base->virtbase + D40_DREG_LCPA); | |
2922 | ||
2923 | base->lcpa_base = ioremap(res->start, resource_size(res)); | |
2924 | if (!base->lcpa_base) { | |
2925 | ret = -ENOMEM; | |
6db5a8ba | 2926 | d40_err(&pdev->dev, "Failed to ioremap LCPA region\n"); |
8d318a50 LW |
2927 | goto failure; |
2928 | } | |
8d318a50 | 2929 | |
508849ad LW |
2930 | ret = d40_lcla_allocate(base); |
2931 | if (ret) { | |
6db5a8ba | 2932 | d40_err(&pdev->dev, "Failed to allocate LCLA area\n"); |
8d318a50 LW |
2933 | goto failure; |
2934 | } | |
2935 | ||
2936 | spin_lock_init(&base->lcla_pool.lock); | |
2937 | ||
8d318a50 LW |
2938 | base->irq = platform_get_irq(pdev, 0); |
2939 | ||
2940 | ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); | |
8d318a50 | 2941 | if (ret) { |
6db5a8ba | 2942 | d40_err(&pdev->dev, "No IRQ defined\n"); |
8d318a50 LW |
2943 | goto failure; |
2944 | } | |
2945 | ||
2946 | err = d40_dmaengine_init(base, num_reserved_chans); | |
2947 | if (err) | |
2948 | goto failure; | |
2949 | ||
2950 | d40_hw_init(base); | |
2951 | ||
2952 | dev_info(base->dev, "initialized\n"); | |
2953 | return 0; | |
2954 | ||
2955 | failure: | |
2956 | if (base) { | |
c675b1b4 JA |
2957 | if (base->desc_slab) |
2958 | kmem_cache_destroy(base->desc_slab); | |
8d318a50 LW |
2959 | if (base->virtbase) |
2960 | iounmap(base->virtbase); | |
026cbc42 RV |
2961 | |
2962 | if (base->lcla_pool.dma_addr) | |
2963 | dma_unmap_single(base->dev, base->lcla_pool.dma_addr, | |
2964 | SZ_1K * base->num_phy_chans, | |
2965 | DMA_TO_DEVICE); | |
2966 | ||
508849ad LW |
2967 | if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) |
2968 | free_pages((unsigned long)base->lcla_pool.base, | |
2969 | base->lcla_pool.pages); | |
767a9675 JA |
2970 | |
2971 | kfree(base->lcla_pool.base_unaligned); | |
2972 | ||
8d318a50 LW |
2973 | if (base->phy_lcpa) |
2974 | release_mem_region(base->phy_lcpa, | |
2975 | base->lcpa_size); | |
2976 | if (base->phy_start) | |
2977 | release_mem_region(base->phy_start, | |
2978 | base->phy_size); | |
2979 | if (base->clk) { | |
2980 | clk_disable(base->clk); | |
2981 | clk_put(base->clk); | |
2982 | } | |
2983 | ||
2984 | kfree(base->lcla_pool.alloc_map); | |
2985 | kfree(base->lookup_log_chans); | |
2986 | kfree(base->lookup_phy_chans); | |
2987 | kfree(base->phy_res); | |
2988 | kfree(base); | |
2989 | } | |
2990 | ||
6db5a8ba | 2991 | d40_err(&pdev->dev, "probe failed\n"); |
8d318a50 LW |
2992 | return ret; |
2993 | } | |
2994 | ||
2995 | static struct platform_driver d40_driver = { | |
2996 | .driver = { | |
2997 | .owner = THIS_MODULE, | |
2998 | .name = D40_NAME, | |
2999 | }, | |
3000 | }; | |
3001 | ||
cb9ab2d8 | 3002 | static int __init stedma40_init(void) |
8d318a50 LW |
3003 | { |
3004 | return platform_driver_probe(&d40_driver, d40_probe); | |
3005 | } | |
a0eb221a | 3006 | subsys_initcall(stedma40_init); |