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dmaengine: ste_dma40: minor code readability fixes
[mirror_ubuntu-artful-kernel.git] / drivers / dma / ste_dma40.c
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8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
b7f080cf 9#include <linux/dma-mapping.h>
8d318a50
LW		 10#include <linux/kernel.h>
11#include <linux/slab.h>
f492b210 12#include <linux/export.h>
8d318a50
LW		 13#include <linux/dmaengine.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
7fb3e75e
N		 17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
698e4732 19#include <linux/err.h>
f4b89764 20#include <linux/amba/bus.h>
15e4b78d 21#include <linux/regulator/consumer.h>
865fab60 22#include <linux/platform_data/dma-ste-dma40.h>
8d318a50 23
d2ebfb33 24#include "dmaengine.h"
8d318a50
LW		 25#include "ste_dma40_ll.h"
26
27#define D40_NAME "dma40"
28
29#define D40_PHY_CHAN -1
30
31/* For masking out/in 2 bit channel positions */
32#define D40_CHAN_POS(chan) (2 * (chan / 2))
33#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
34
35/* Maximum iterations taken before giving up suspending a channel */
36#define D40_SUSPEND_MAX_IT 500
37
7fb3e75e
N		 38/* Milliseconds */
39#define DMA40_AUTOSUSPEND_DELAY 100
40
508849ad
LW		 41/* Hardware requirement on LCLA alignment */
42#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 43
44/* Max number of links per event group */
45#define D40_LCLA_LINK_PER_EVENT_GRP 128
46#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
47
508849ad
LW		 48/* Attempts before giving up to trying to get pages that are aligned */
49#define MAX_LCLA_ALLOC_ATTEMPTS 256
50
51/* Bit markings for allocation map */
8d318a50
LW		 52#define D40_ALLOC_FREE (1 << 31)
53#define D40_ALLOC_PHY (1 << 30)
54#define D40_ALLOC_LOG_FREE 0
55
3cb645dc
TL		 56#define MAX(a, b) (((a) < (b)) ? (b) : (a))
57
8d318a50
LW		 58/**
59 * enum 40_command - The different commands and/or statuses.
60 *
61 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
62 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
63 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
64 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
65 */
66enum d40_command {
67 D40_DMA_STOP = 0,
68 D40_DMA_RUN = 1,
69 D40_DMA_SUSPEND_REQ = 2,
70 D40_DMA_SUSPENDED = 3
71};
72
1bdae6f4
N		 73/*
74 * enum d40_events - The different Event Enables for the event lines.
75 *
76 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
77 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
78 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
79 * @D40_ROUND_EVENTLINE: Status check for event line.
80 */
81
82enum d40_events {
83 D40_DEACTIVATE_EVENTLINE = 0,
84 D40_ACTIVATE_EVENTLINE = 1,
85 D40_SUSPEND_REQ_EVENTLINE = 2,
86 D40_ROUND_EVENTLINE = 3
87};
88
7fb3e75e
N		 89/*
90 * These are the registers that has to be saved and later restored
91 * when the DMA hw is powered off.
92 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
93 */
94static u32 d40_backup_regs[] = {
95 D40_DREG_LCPA,
96 D40_DREG_LCLA,
97 D40_DREG_PRMSE,
98 D40_DREG_PRMSO,
99 D40_DREG_PRMOE,
100 D40_DREG_PRMOO,
101};
102
103#define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
104
3cb645dc
TL		 105/*
106 * since 9540 and 8540 has the same HW revision
107 * use v4a for 9540 or ealier
108 * use v4b for 8540 or later
109 * HW revision:
110 * DB8500ed has revision 0
111 * DB8500v1 has revision 2
112 * DB8500v2 has revision 3
113 * AP9540v1 has revision 4
114 * DB8540v1 has revision 4
115 * TODO: Check if all these registers have to be saved/restored on dma40 v4a
116 */
117static u32 d40_backup_regs_v4a[] = {
7fb3e75e
N		 118 D40_DREG_PSEG1,
119 D40_DREG_PSEG2,
120 D40_DREG_PSEG3,
121 D40_DREG_PSEG4,
122 D40_DREG_PCEG1,
123 D40_DREG_PCEG2,
124 D40_DREG_PCEG3,
125 D40_DREG_PCEG4,
126 D40_DREG_RSEG1,
127 D40_DREG_RSEG2,
128 D40_DREG_RSEG3,
129 D40_DREG_RSEG4,
130 D40_DREG_RCEG1,
131 D40_DREG_RCEG2,
132 D40_DREG_RCEG3,
133 D40_DREG_RCEG4,
134};
135
3cb645dc
TL		 136#define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
137
138static u32 d40_backup_regs_v4b[] = {
139 D40_DREG_CPSEG1,
140 D40_DREG_CPSEG2,
141 D40_DREG_CPSEG3,
142 D40_DREG_CPSEG4,
143 D40_DREG_CPSEG5,
144 D40_DREG_CPCEG1,
145 D40_DREG_CPCEG2,
146 D40_DREG_CPCEG3,
147 D40_DREG_CPCEG4,
148 D40_DREG_CPCEG5,
149 D40_DREG_CRSEG1,
150 D40_DREG_CRSEG2,
151 D40_DREG_CRSEG3,
152 D40_DREG_CRSEG4,
153 D40_DREG_CRSEG5,
154 D40_DREG_CRCEG1,
155 D40_DREG_CRCEG2,
156 D40_DREG_CRCEG3,
157 D40_DREG_CRCEG4,
158 D40_DREG_CRCEG5,
159};
160
161#define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
7fb3e75e
N		 162
163static u32 d40_backup_regs_chan[] = {
164 D40_CHAN_REG_SSCFG,
165 D40_CHAN_REG_SSELT,
166 D40_CHAN_REG_SSPTR,
167 D40_CHAN_REG_SSLNK,
168 D40_CHAN_REG_SDCFG,
169 D40_CHAN_REG_SDELT,
170 D40_CHAN_REG_SDPTR,
171 D40_CHAN_REG_SDLNK,
172};
173
3cb645dc
TL		 174/**
175 * struct d40_interrupt_lookup - lookup table for interrupt handler
176 *
177 * @src: Interrupt mask register.
178 * @clr: Interrupt clear register.
179 * @is_error: true if this is an error interrupt.
180 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
181 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
182 */
183struct d40_interrupt_lookup {
184 u32 src;
185 u32 clr;
186 bool is_error;
187 int offset;
188};
189
190
191static struct d40_interrupt_lookup il_v4a[] = {
192 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
193 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
194 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
195 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
196 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
197 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
198 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
199 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
200 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
201 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
202};
203
204static struct d40_interrupt_lookup il_v4b[] = {
205 {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0},
206 {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
207 {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
208 {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
209 {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
210 {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0},
211 {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32},
212 {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64},
213 {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96},
214 {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128},
215 {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN},
216 {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN},
217};
218
219/**
220 * struct d40_reg_val - simple lookup struct
221 *
222 * @reg: The register.
223 * @val: The value that belongs to the register in reg.
224 */
225struct d40_reg_val {
226 unsigned int reg;
227 unsigned int val;
228};
229
230static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
231 /* Clock every part of the DMA block from start */
232 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
233
234 /* Interrupts on all logical channels */
235 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
236 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
237 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
238 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
239 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
240 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
241 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
242 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
243 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
244 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
245 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
246 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
247};
248static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
249 /* Clock every part of the DMA block from start */
250 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
251
252 /* Interrupts on all logical channels */
253 { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
254 { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
255 { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
256 { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
257 { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
258 { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
259 { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
260 { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
261 { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
262 { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
263 { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
264 { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
265 { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
266 { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
267 { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
268};
269
8d318a50
LW		 270/**
271 * struct d40_lli_pool - Structure for keeping LLIs in memory
272 *
273 * @base: Pointer to memory area when the pre_alloc_lli's are not large
274 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
275 * pre_alloc_lli is used.
b00f938c 276 * @dma_addr: DMA address, if mapped
8d318a50
LW		 277 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
278 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
279 * one buffer to one buffer.
280 */
281struct d40_lli_pool {
282 void *base;
508849ad 283 int size;
b00f938c 284 dma_addr_t dma_addr;
8d318a50 285 /* Space for dst and src, plus an extra for padding */
508849ad 286 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 287};
288
289/**
290 * struct d40_desc - A descriptor is one DMA job.
291 *
292 * @lli_phy: LLI settings for physical channel. Both src and dst=
293 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
294 * lli_len equals one.
295 * @lli_log: Same as above but for logical channels.
296 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 297 * @lli_len: Number of llis of current descriptor.
25985edc 298 * @lli_current: Number of transferred llis.
698e4732 299 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 300 * @txd: DMA engine struct. Used for among other things for communication
301 * during a transfer.
302 * @node: List entry.
8d318a50 303 * @is_in_client_list: true if the client owns this descriptor.
7fb3e75e 304 * @cyclic: true if this is a cyclic job
8d318a50
LW		 305 *
306 * This descriptor is used for both logical and physical transfers.
307 */
8d318a50
LW		 308struct d40_desc {
309 /* LLI physical */
310 struct d40_phy_lli_bidir lli_phy;
311 /* LLI logical */
312 struct d40_log_lli_bidir lli_log;
313
314 struct d40_lli_pool lli_pool;
941b77a3 315 int lli_len;
698e4732
JA		 316 int lli_current;
317 int lcla_alloc;
8d318a50
LW		 318
319 struct dma_async_tx_descriptor txd;
320 struct list_head node;
321
8d318a50 322 bool is_in_client_list;
0c842b55 323 bool cyclic;
8d318a50
LW		 324};
325
326/**
327 * struct d40_lcla_pool - LCLA pool settings and data.
328 *
508849ad
LW		 329 * @base: The virtual address of LCLA. 18 bit aligned.
330 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
331 * This pointer is only there for clean-up on error.
332 * @pages: The number of pages needed for all physical channels.
333 * Only used later for clean-up on error
8d318a50 334 * @lock: Lock to protect the content in this struct.
698e4732 335 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 336 */
337struct d40_lcla_pool {
338 void *base;
026cbc42 339 dma_addr_t dma_addr;
508849ad
LW		 340 void *base_unaligned;
341 int pages;
8d318a50 342 spinlock_t lock;
698e4732 343 struct d40_desc **alloc_map;
8d318a50
LW		 344};
345
346/**
347 * struct d40_phy_res - struct for handling eventlines mapped to physical
348 * channels.
349 *
350 * @lock: A lock protection this entity.
7fb3e75e 351 * @reserved: True if used by secure world or otherwise.
8d318a50
LW		 352 * @num: The physical channel number of this entity.
353 * @allocated_src: Bit mapped to show which src event line's are mapped to
354 * this physical channel. Can also be free or physically allocated.
355 * @allocated_dst: Same as for src but is dst.
356 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 357 * event line number.
8d318a50
LW		 358 */
359struct d40_phy_res {
360 spinlock_t lock;
7fb3e75e 361 bool reserved;
8d318a50
LW		 362 int num;
363 u32 allocated_src;
364 u32 allocated_dst;
365};
366
367struct d40_base;
368
369/**
370 * struct d40_chan - Struct that describes a channel.
371 *
372 * @lock: A spinlock to protect this struct.
373 * @log_num: The logical number, if any of this channel.
8d318a50
LW		 374 * @pending_tx: The number of pending transfers. Used between interrupt handler
375 * and tasklet.
376 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 377 * @phy_chan: Pointer to physical channel which this instance runs on. If this
378 * point is NULL, then the channel is not allocated.
8d318a50
LW		 379 * @chan: DMA engine handle.
380 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
381 * transfer and call client callback.
382 * @client: Cliented owned descriptor list.
da063d26 383 * @pending_queue: Submitted jobs, to be issued by issue_pending()
8d318a50 384 * @active: Active descriptor.
4226dd86 385 * @done: Completed jobs
8d318a50 386 * @queue: Queued jobs.
82babbb3 387 * @prepare_queue: Prepared jobs.
8d318a50 388 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 389 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 390 * @base: Pointer to the device instance struct.
391 * @src_def_cfg: Default cfg register setting for src.
392 * @dst_def_cfg: Default cfg register setting for dst.
393 * @log_def: Default logical channel settings.
8d318a50 394 * @lcpa: Pointer to dst and src lcpa settings.
ae752bf4 395 * @runtime_addr: runtime configured address.
396 * @runtime_direction: runtime configured direction.
8d318a50
LW		 397 *
398 * This struct can either "be" a logical or a physical channel.
399 */
400struct d40_chan {
401 spinlock_t lock;
402 int log_num;
8d318a50
LW		 403 int pending_tx;
404 bool busy;
405 struct d40_phy_res *phy_chan;
406 struct dma_chan chan;
407 struct tasklet_struct tasklet;
408 struct list_head client;
a8f3067b 409 struct list_head pending_queue;
8d318a50 410 struct list_head active;
4226dd86 411 struct list_head done;
8d318a50 412 struct list_head queue;
82babbb3 413 struct list_head prepare_queue;
8d318a50 414 struct stedma40_chan_cfg dma_cfg;
ce2ca125 415 bool configured;
8d318a50
LW		 416 struct d40_base *base;
417 /* Default register configurations */
418 u32 src_def_cfg;
419 u32 dst_def_cfg;
420 struct d40_def_lcsp log_def;
8d318a50 421 struct d40_log_lli_full *lcpa;
95e1400f
LW		 422 /* Runtime reconfiguration */
423 dma_addr_t runtime_addr;
db8196df 424 enum dma_transfer_direction runtime_direction;
8d318a50
LW		 425};
426
3cb645dc
TL		 427/**
428 * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
429 * controller
430 *
431 * @backup: the pointer to the registers address array for backup
432 * @backup_size: the size of the registers address array for backup
433 * @realtime_en: the realtime enable register
434 * @realtime_clear: the realtime clear register
435 * @high_prio_en: the high priority enable register
436 * @high_prio_clear: the high priority clear register
437 * @interrupt_en: the interrupt enable register
438 * @interrupt_clear: the interrupt clear register
439 * @il: the pointer to struct d40_interrupt_lookup
440 * @il_size: the size of d40_interrupt_lookup array
441 * @init_reg: the pointer to the struct d40_reg_val
442 * @init_reg_size: the size of d40_reg_val array
443 */
444struct d40_gen_dmac {
445 u32 *backup;
446 u32 backup_size;
447 u32 realtime_en;
448 u32 realtime_clear;
449 u32 high_prio_en;
450 u32 high_prio_clear;
451 u32 interrupt_en;
452 u32 interrupt_clear;
453 struct d40_interrupt_lookup *il;
454 u32 il_size;
455 struct d40_reg_val *init_reg;
456 u32 init_reg_size;
457};
458
8d318a50
LW		 459/**
460 * struct d40_base - The big global struct, one for each probe'd instance.
461 *
462 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
463 * @execmd_lock: Lock for execute command usage since several channels share
464 * the same physical register.
465 * @dev: The device structure.
466 * @virtbase: The virtual base address of the DMA's register.
f4185592 467 * @rev: silicon revision detected.
8d318a50
LW		 468 * @clk: Pointer to the DMA clock structure.
469 * @phy_start: Physical memory start of the DMA registers.
470 * @phy_size: Size of the DMA register map.
471 * @irq: The IRQ number.
472 * @num_phy_chans: The number of physical channels. Read from HW. This
473 * is the number of available channels for this driver, not counting "Secure
474 * mode" allocated physical channels.
475 * @num_log_chans: The number of logical channels. Calculated from
476 * num_phy_chans.
477 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
478 * @dma_slave: dma_device channels that can do only do slave transfers.
479 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
7fb3e75e 480 * @phy_chans: Room for all possible physical channels in system.
8d318a50
LW		 481 * @log_chans: Room for all possible logical channels in system.
482 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
483 * to log_chans entries.
484 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
485 * to phy_chans entries.
486 * @plat_data: Pointer to provided platform_data which is the driver
487 * configuration.
28c7a19d 488 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
8d318a50
LW		 489 * @phy_res: Vector containing all physical channels.
490 * @lcla_pool: lcla pool settings and data.
491 * @lcpa_base: The virtual mapped address of LCPA.
492 * @phy_lcpa: The physical address of the LCPA.
493 * @lcpa_size: The size of the LCPA area.
c675b1b4 494 * @desc_slab: cache for descriptors.
7fb3e75e
N		 495 * @reg_val_backup: Here the values of some hardware registers are stored
496 * before the DMA is powered off. They are restored when the power is back on.
3cb645dc
TL		 497 * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
498 * later
7fb3e75e
N		 499 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
500 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
501 * @initialized: true if the dma has been initialized
3cb645dc
TL		 502 * @gen_dmac: the struct for generic registers values to represent u8500/8540
503 * DMA controller
8d318a50
LW		 504 */
505struct d40_base {
506 spinlock_t interrupt_lock;
507 spinlock_t execmd_lock;
508 struct device *dev;
509 void __iomem *virtbase;
f4185592 510 u8 rev:4;
8d318a50
LW		 511 struct clk *clk;
512 phys_addr_t phy_start;
513 resource_size_t phy_size;
514 int irq;
515 int num_phy_chans;
516 int num_log_chans;
b96710e5 517 struct device_dma_parameters dma_parms;
8d318a50
LW		 518 struct dma_device dma_both;
519 struct dma_device dma_slave;
520 struct dma_device dma_memcpy;
521 struct d40_chan *phy_chans;
522 struct d40_chan *log_chans;
523 struct d40_chan **lookup_log_chans;
524 struct d40_chan **lookup_phy_chans;
525 struct stedma40_platform_data *plat_data;
28c7a19d 526 struct regulator *lcpa_regulator;
8d318a50
LW		 527 /* Physical half channels */
528 struct d40_phy_res *phy_res;
529 struct d40_lcla_pool lcla_pool;
530 void *lcpa_base;
531 dma_addr_t phy_lcpa;
532 resource_size_t lcpa_size;
c675b1b4 533 struct kmem_cache *desc_slab;
7fb3e75e 534 u32 reg_val_backup[BACKUP_REGS_SZ];
3cb645dc 535 u32 reg_val_backup_v4[MAX(BACKUP_REGS_SZ_V4A, BACKUP_REGS_SZ_V4B)];
7fb3e75e
N		 536 u32 *reg_val_backup_chan;
537 u16 gcc_pwr_off_mask;
538 bool initialized;
3cb645dc 539 struct d40_gen_dmac gen_dmac;
8d318a50
LW		 540};
541
262d2915
RV		 542static struct device *chan2dev(struct d40_chan *d40c)
543{
544 return &d40c->chan.dev->device;
545}
546
724a8577
RV		 547static bool chan_is_physical(struct d40_chan *chan)
548{
549 return chan->log_num == D40_PHY_CHAN;
550}
551
552static bool chan_is_logical(struct d40_chan *chan)
553{
554 return !chan_is_physical(chan);
555}
556
8ca84687
RV		 557static void __iomem *chan_base(struct d40_chan *chan)
558{
559 return chan->base->virtbase + D40_DREG_PCBASE +
560 chan->phy_chan->num * D40_DREG_PCDELTA;
561}
562
6db5a8ba
RV		 563#define d40_err(dev, format, arg...) \
564 dev_err(dev, "[%s] " format, __func__, ## arg)
565
566#define chan_err(d40c, format, arg...) \
567 d40_err(chan2dev(d40c), format, ## arg)
568
b00f938c 569static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
dbd88788 570 int lli_len)
8d318a50 571{
dbd88788 572 bool is_log = chan_is_logical(d40c);
8d318a50
LW		 573 u32 align;
574 void *base;
575
576 if (is_log)
577 align = sizeof(struct d40_log_lli);
578 else
579 align = sizeof(struct d40_phy_lli);
580
581 if (lli_len == 1) {
582 base = d40d->lli_pool.pre_alloc_lli;
583 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
584 d40d->lli_pool.base = NULL;
585 } else {
594ece4d 586 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 587
588 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
589 d40d->lli_pool.base = base;
590
591 if (d40d->lli_pool.base == NULL)
592 return -ENOMEM;
593 }
594
595 if (is_log) {
d924abad 596 d40d->lli_log.src = PTR_ALIGN(base, align);
594ece4d 597 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 598
599 d40d->lli_pool.dma_addr = 0;
8d318a50 600 } else {
d924abad 601 d40d->lli_phy.src = PTR_ALIGN(base, align);
594ece4d 602 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 603
604 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
605 d40d->lli_phy.src,
606 d40d->lli_pool.size,
607 DMA_TO_DEVICE);
608
609 if (dma_mapping_error(d40c->base->dev,
610 d40d->lli_pool.dma_addr)) {
611 kfree(d40d->lli_pool.base);
612 d40d->lli_pool.base = NULL;
613 d40d->lli_pool.dma_addr = 0;
614 return -ENOMEM;
615 }
8d318a50
LW		 616 }
617
618 return 0;
619}
620
b00f938c 621static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 622{
b00f938c
RV		 623 if (d40d->lli_pool.dma_addr)
624 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
625 d40d->lli_pool.size, DMA_TO_DEVICE);
626
8d318a50
LW		 627 kfree(d40d->lli_pool.base);
628 d40d->lli_pool.base = NULL;
629 d40d->lli_pool.size = 0;
630 d40d->lli_log.src = NULL;
631 d40d->lli_log.dst = NULL;
632 d40d->lli_phy.src = NULL;
633 d40d->lli_phy.dst = NULL;
8d318a50
LW		 634}
635
698e4732
JA		 636static int d40_lcla_alloc_one(struct d40_chan *d40c,
637 struct d40_desc *d40d)
638{
639 unsigned long flags;
640 int i;
641 int ret = -EINVAL;
698e4732
JA		 642
643 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
644
698e4732
JA		 645 /*
646 * Allocate both src and dst at the same time, therefore the half
647 * start on 1 since 0 can't be used since zero is used as end marker.
648 */
649 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
7ce529ef
FB		 650 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
651
652 if (!d40c->base->lcla_pool.alloc_map[idx]) {
653 d40c->base->lcla_pool.alloc_map[idx] = d40d;
698e4732
JA		 654 d40d->lcla_alloc++;
655 ret = i;
656 break;
657 }
658 }
659
660 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
661
662 return ret;
663}
664
665static int d40_lcla_free_all(struct d40_chan *d40c,
666 struct d40_desc *d40d)
667{
668 unsigned long flags;
669 int i;
670 int ret = -EINVAL;
671
724a8577 672 if (chan_is_physical(d40c))
698e4732
JA		 673 return 0;
674
675 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
676
677 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
7ce529ef
FB		 678 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
679
680 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
681 d40c->base->lcla_pool.alloc_map[idx] = NULL;
698e4732
JA		 682 d40d->lcla_alloc--;
683 if (d40d->lcla_alloc == 0) {
684 ret = 0;
685 break;
686 }
687 }
688 }
689
690 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
691
692 return ret;
693
694}
695
8d318a50
LW		 696static void d40_desc_remove(struct d40_desc *d40d)
697{
698 list_del(&d40d->node);
699}
700
701static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
702{
a2c15fa4 703 struct d40_desc *desc = NULL;
8d318a50
LW		 704
705 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 706 struct d40_desc *d;
707 struct d40_desc *_d;
708
7fb3e75e 709 list_for_each_entry_safe(d, _d, &d40c->client, node) {
8d318a50 710 if (async_tx_test_ack(&d->txd)) {
8d318a50 711 d40_desc_remove(d);
a2c15fa4
RV		 712 desc = d;
713 memset(desc, 0, sizeof(*desc));
c675b1b4 714 break;
8d318a50 715 }
7fb3e75e 716 }
8d318a50 717 }
a2c15fa4
RV		 718
719 if (!desc)
720 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
721
722 if (desc)
723 INIT_LIST_HEAD(&desc->node);
724
725 return desc;
8d318a50
LW		 726}
727
728static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
729{
698e4732 730
b00f938c 731 d40_pool_lli_free(d40c, d40d);
698e4732 732 d40_lcla_free_all(d40c, d40d);
c675b1b4 733 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 734}
735
736static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
737{
738 list_add_tail(&desc->node, &d40c->active);
739}
740
1c4b0927
RV		 741static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
742{
743 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
744 struct d40_phy_lli *lli_src = desc->lli_phy.src;
745 void __iomem *base = chan_base(chan);
746
747 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
748 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
749 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
750 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
751
752 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
753 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
754 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
755 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
756}
757
4226dd86
FB		 758static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
759{
760 list_add_tail(&desc->node, &d40c->done);
761}
762
e65889c7 763static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
698e4732 764{
e65889c7
RV		 765 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
766 struct d40_log_lli_bidir *lli = &desc->lli_log;
767 int lli_current = desc->lli_current;
768 int lli_len = desc->lli_len;
0c842b55 769 bool cyclic = desc->cyclic;
e65889c7 770 int curr_lcla = -EINVAL;
0c842b55 771 int first_lcla = 0;
28c7a19d 772 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
0c842b55 773 bool linkback;
e65889c7 774
0c842b55
RV		 775 /*
776 * We may have partially running cyclic transfers, in case we did't get
777 * enough LCLA entries.
778 */
779 linkback = cyclic && lli_current == 0;
780
781 /*
782 * For linkback, we need one LCLA even with only one link, because we
783 * can't link back to the one in LCPA space
784 */
785 if (linkback || (lli_len - lli_current > 1)) {
e65889c7 786 curr_lcla = d40_lcla_alloc_one(chan, desc);
0c842b55
RV		 787 first_lcla = curr_lcla;
788 }
789
790 /*
791 * For linkback, we normally load the LCPA in the loop since we need to
792 * link it to the second LCLA and not the first. However, if we
793 * couldn't even get a first LCLA, then we have to run in LCPA and
794 * reload manually.
795 */
796 if (!linkback || curr_lcla == -EINVAL) {
797 unsigned int flags = 0;
e65889c7 798
0c842b55
RV		 799 if (curr_lcla == -EINVAL)
800 flags |= LLI_TERM_INT;
e65889c7 801
0c842b55
RV		 802 d40_log_lli_lcpa_write(chan->lcpa,
803 &lli->dst[lli_current],
804 &lli->src[lli_current],
805 curr_lcla,
806 flags);
807 lli_current++;
808 }
6045f0bb
RV		 809
810 if (curr_lcla < 0)
811 goto out;
812
e65889c7
RV		 813 for (; lli_current < lli_len; lli_current++) {
814 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
815 8 * curr_lcla * 2;
816 struct d40_log_lli *lcla = pool->base + lcla_offset;
0c842b55 817 unsigned int flags = 0;
e65889c7
RV		 818 int next_lcla;
819
820 if (lli_current + 1 < lli_len)
821 next_lcla = d40_lcla_alloc_one(chan, desc);
822 else
0c842b55
RV		 823 next_lcla = linkback ? first_lcla : -EINVAL;
824
825 if (cyclic || next_lcla == -EINVAL)
826 flags |= LLI_TERM_INT;
e65889c7 827
0c842b55
RV		 828 if (linkback && curr_lcla == first_lcla) {
829 /* First link goes in both LCPA and LCLA */
830 d40_log_lli_lcpa_write(chan->lcpa,
831 &lli->dst[lli_current],
832 &lli->src[lli_current],
833 next_lcla, flags);
834 }
835
836 /*
837 * One unused LCLA in the cyclic case if the very first
838 * next_lcla fails...
839 */
e65889c7
RV		 840 d40_log_lli_lcla_write(lcla,
841 &lli->dst[lli_current],
842 &lli->src[lli_current],
0c842b55 843 next_lcla, flags);
e65889c7 844
28c7a19d
N		 845 /*
846 * Cache maintenance is not needed if lcla is
847 * mapped in esram
848 */
849 if (!use_esram_lcla) {
850 dma_sync_single_range_for_device(chan->base->dev,
851 pool->dma_addr, lcla_offset,
852 2 * sizeof(struct d40_log_lli),
853 DMA_TO_DEVICE);
854 }
e65889c7
RV		 855 curr_lcla = next_lcla;
856
0c842b55 857 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
e65889c7
RV		 858 lli_current++;
859 break;
860 }
861 }
862
6045f0bb 863out:
e65889c7
RV		 864 desc->lli_current = lli_current;
865}
698e4732 866
e65889c7
RV		 867static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
868{
724a8577 869 if (chan_is_physical(d40c)) {
1c4b0927 870 d40_phy_lli_load(d40c, d40d);
698e4732 871 d40d->lli_current = d40d->lli_len;
e65889c7
RV		 872 } else
873 d40_log_lli_to_lcxa(d40c, d40d);
698e4732
JA		 874}
875
8d318a50
LW		 876static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
877{
878 struct d40_desc *d;
879
880 if (list_empty(&d40c->active))
881 return NULL;
882
883 d = list_first_entry(&d40c->active,
884 struct d40_desc,
885 node);
886 return d;
887}
888
7404368c 889/* remove desc from current queue and add it to the pending_queue */
8d318a50
LW		 890static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
891{
7404368c
PF		 892 d40_desc_remove(desc);
893 desc->is_in_client_list = false;
a8f3067b
PF		 894 list_add_tail(&desc->node, &d40c->pending_queue);
895}
896
897static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
898{
899 struct d40_desc *d;
900
901 if (list_empty(&d40c->pending_queue))
902 return NULL;
903
904 d = list_first_entry(&d40c->pending_queue,
905 struct d40_desc,
906 node);
907 return d;
8d318a50
LW		 908}
909
910static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
911{
912 struct d40_desc *d;
913
914 if (list_empty(&d40c->queue))
915 return NULL;
916
917 d = list_first_entry(&d40c->queue,
918 struct d40_desc,
919 node);
920 return d;
921}
922
4226dd86
FB		 923static struct d40_desc *d40_first_done(struct d40_chan *d40c)
924{
925 if (list_empty(&d40c->done))
926 return NULL;
927
928 return list_first_entry(&d40c->done, struct d40_desc, node);
929}
930
d49278e3
PF		 931static int d40_psize_2_burst_size(bool is_log, int psize)
932{
933 if (is_log) {
934 if (psize == STEDMA40_PSIZE_LOG_1)
935 return 1;
936 } else {
937 if (psize == STEDMA40_PSIZE_PHY_1)
938 return 1;
939 }
940
941 return 2 << psize;
942}
943
944/*
945 * The dma only supports transmitting packages up to
946 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
947 * dma elements required to send the entire sg list
948 */
949static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
950{
951 int dmalen;
952 u32 max_w = max(data_width1, data_width2);
953 u32 min_w = min(data_width1, data_width2);
954 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
955
956 if (seg_max > STEDMA40_MAX_SEG_SIZE)
957 seg_max -= (1 << max_w);
958
959 if (!IS_ALIGNED(size, 1 << max_w))
960 return -EINVAL;
961
962 if (size <= seg_max)
963 dmalen = 1;
964 else {
965 dmalen = size / seg_max;
966 if (dmalen * seg_max < size)
967 dmalen++;
968 }
969 return dmalen;
970}
971
972static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
973 u32 data_width1, u32 data_width2)
974{
975 struct scatterlist *sg;
976 int i;
977 int len = 0;
978 int ret;
979
980 for_each_sg(sgl, sg, sg_len, i) {
981 ret = d40_size_2_dmalen(sg_dma_len(sg),
982 data_width1, data_width2);
983 if (ret < 0)
984 return ret;
985 len += ret;
986 }
987 return len;
988}
8d318a50 989
7fb3e75e
N		 990
991#ifdef CONFIG_PM
992static void dma40_backup(void __iomem *baseaddr, u32 *backup,
993 u32 *regaddr, int num, bool save)
994{
995 int i;
996
997 for (i = 0; i < num; i++) {
998 void __iomem *addr = baseaddr + regaddr[i];
999
1000 if (save)
1001 backup[i] = readl_relaxed(addr);
1002 else
1003 writel_relaxed(backup[i], addr);
1004 }
1005}
1006
1007static void d40_save_restore_registers(struct d40_base *base, bool save)
1008{
1009 int i;
1010
1011 /* Save/Restore channel specific registers */
1012 for (i = 0; i < base->num_phy_chans; i++) {
1013 void __iomem *addr;
1014 int idx;
1015
1016 if (base->phy_res[i].reserved)
1017 continue;
1018
1019 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
1020 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
1021
1022 dma40_backup(addr, &base->reg_val_backup_chan[idx],
1023 d40_backup_regs_chan,
1024 ARRAY_SIZE(d40_backup_regs_chan),
1025 save);
1026 }
1027
1028 /* Save/Restore global registers */
1029 dma40_backup(base->virtbase, base->reg_val_backup,
1030 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
1031 save);
1032
1033 /* Save/Restore registers only existing on dma40 v3 and later */
3cb645dc
TL		 1034 if (base->gen_dmac.backup)
1035 dma40_backup(base->virtbase, base->reg_val_backup_v4,
1036 base->gen_dmac.backup,
1037 base->gen_dmac.backup_size,
1038 save);
7fb3e75e
N		 1039}
1040#else
1041static void d40_save_restore_registers(struct d40_base *base, bool save)
1042{
1043}
1044#endif
8d318a50 1045
1bdae6f4
N		 1046static int __d40_execute_command_phy(struct d40_chan *d40c,
1047 enum d40_command command)
8d318a50 1048{
767a9675
JA		 1049 u32 status;
1050 int i;
8d318a50
LW		 1051 void __iomem *active_reg;
1052 int ret = 0;
1053 unsigned long flags;
1d392a7b 1054 u32 wmask;
8d318a50 1055
1bdae6f4
N		 1056 if (command == D40_DMA_STOP) {
1057 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1058 if (ret)
1059 return ret;
1060 }
1061
8d318a50
LW		 1062 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1063
1064 if (d40c->phy_chan->num % 2 == 0)
1065 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1066 else
1067 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1068
1069 if (command == D40_DMA_SUSPEND_REQ) {
1070 status = (readl(active_reg) &
1071 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1072 D40_CHAN_POS(d40c->phy_chan->num);
1073
1074 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1075 goto done;
1076 }
1077
1d392a7b
JA		 1078 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1079 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1080 active_reg);
8d318a50
LW		 1081
1082 if (command == D40_DMA_SUSPEND_REQ) {
1083
1084 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1085 status = (readl(active_reg) &
1086 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1087 D40_CHAN_POS(d40c->phy_chan->num);
1088
1089 cpu_relax();
1090 /*
1091 * Reduce the number of bus accesses while
1092 * waiting for the DMA to suspend.
1093 */
1094 udelay(3);
1095
1096 if (status == D40_DMA_STOP ||
1097 status == D40_DMA_SUSPENDED)
1098 break;
1099 }
1100
1101 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 1102 chan_err(d40c,
1103 "unable to suspend the chl %d (log: %d) status %x\n",
1104 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 1105 status);
1106 dump_stack();
1107 ret = -EBUSY;
1108 }
1109
1110 }
1111done:
1112 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1113 return ret;
1114}
1115
1116static void d40_term_all(struct d40_chan *d40c)
1117{
1118 struct d40_desc *d40d;
7404368c 1119 struct d40_desc *_d;
8d318a50 1120
4226dd86
FB		 1121 /* Release completed descriptors */
1122 while ((d40d = d40_first_done(d40c))) {
1123 d40_desc_remove(d40d);
1124 d40_desc_free(d40c, d40d);
1125 }
1126
8d318a50
LW		 1127 /* Release active descriptors */
1128 while ((d40d = d40_first_active_get(d40c))) {
1129 d40_desc_remove(d40d);
8d318a50
LW		 1130 d40_desc_free(d40c, d40d);
1131 }
1132
1133 /* Release queued descriptors waiting for transfer */
1134 while ((d40d = d40_first_queued(d40c))) {
1135 d40_desc_remove(d40d);
8d318a50
LW		 1136 d40_desc_free(d40c, d40d);
1137 }
1138
a8f3067b
PF		 1139 /* Release pending descriptors */
1140 while ((d40d = d40_first_pending(d40c))) {
1141 d40_desc_remove(d40d);
1142 d40_desc_free(d40c, d40d);
1143 }
8d318a50 1144
7404368c
PF		 1145 /* Release client owned descriptors */
1146 if (!list_empty(&d40c->client))
1147 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1148 d40_desc_remove(d40d);
1149 d40_desc_free(d40c, d40d);
1150 }
1151
82babbb3
PF		 1152 /* Release descriptors in prepare queue */
1153 if (!list_empty(&d40c->prepare_queue))
1154 list_for_each_entry_safe(d40d, _d,
1155 &d40c->prepare_queue, node) {
1156 d40_desc_remove(d40d);
1157 d40_desc_free(d40c, d40d);
1158 }
7404368c 1159
8d318a50 1160 d40c->pending_tx = 0;
8d318a50
LW		 1161}
1162
1bdae6f4
N		 1163static void __d40_config_set_event(struct d40_chan *d40c,
1164 enum d40_events event_type, u32 event,
1165 int reg)
262d2915 1166{
8ca84687 1167 void __iomem *addr = chan_base(d40c) + reg;
262d2915 1168 int tries;
1bdae6f4
N		 1169 u32 status;
1170
1171 switch (event_type) {
1172
1173 case D40_DEACTIVATE_EVENTLINE:
262d2915 1174
262d2915
RV		 1175 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1176 | ~D40_EVENTLINE_MASK(event), addr);
1bdae6f4
N		 1177 break;
1178
1179 case D40_SUSPEND_REQ_EVENTLINE:
1180 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1181 D40_EVENTLINE_POS(event);
1182
1183 if (status == D40_DEACTIVATE_EVENTLINE ||
1184 status == D40_SUSPEND_REQ_EVENTLINE)
1185 break;
262d2915 1186
1bdae6f4
N		 1187 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1188 | ~D40_EVENTLINE_MASK(event), addr);
1189
1190 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1191
1192 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1193 D40_EVENTLINE_POS(event);
1194
1195 cpu_relax();
1196 /*
1197 * Reduce the number of bus accesses while
1198 * waiting for the DMA to suspend.
1199 */
1200 udelay(3);
1201
1202 if (status == D40_DEACTIVATE_EVENTLINE)
1203 break;
1204 }
1205
1206 if (tries == D40_SUSPEND_MAX_IT) {
1207 chan_err(d40c,
1208 "unable to stop the event_line chl %d (log: %d)"
1209 "status %x\n", d40c->phy_chan->num,
1210 d40c->log_num, status);
1211 }
1212 break;
1213
1214 case D40_ACTIVATE_EVENTLINE:
262d2915
RV		 1215 /*
1216 * The hardware sometimes doesn't register the enable when src and dst
1217 * event lines are active on the same logical channel. Retry to ensure
1218 * it does. Usually only one retry is sufficient.
1219 */
1bdae6f4
N		 1220 tries = 100;
1221 while (--tries) {
1222 writel((D40_ACTIVATE_EVENTLINE <<
1223 D40_EVENTLINE_POS(event)) |
1224 ~D40_EVENTLINE_MASK(event), addr);
262d2915 1225
1bdae6f4
N		 1226 if (readl(addr) & D40_EVENTLINE_MASK(event))
1227 break;
1228 }
262d2915 1229
1bdae6f4
N		 1230 if (tries != 99)
1231 dev_dbg(chan2dev(d40c),
1232 "[%s] workaround enable S%cLNK (%d tries)\n",
1233 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1234 100 - tries);
262d2915 1235
1bdae6f4
N		 1236 WARN_ON(!tries);
1237 break;
262d2915 1238
1bdae6f4
N		 1239 case D40_ROUND_EVENTLINE:
1240 BUG();
1241 break;
8d318a50 1242
1bdae6f4
N		 1243 }
1244}
8d318a50 1245
1bdae6f4
N		 1246static void d40_config_set_event(struct d40_chan *d40c,
1247 enum d40_events event_type)
1248{
8d318a50
LW		 1249 /* Enable event line connected to device (or memcpy) */
1250 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1251 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
1252 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1253
1bdae6f4 1254 __d40_config_set_event(d40c, event_type, event,
262d2915 1255 D40_CHAN_REG_SSLNK);
8d318a50 1256 }
262d2915 1257
8d318a50
LW		 1258 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
1259 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1260
1bdae6f4 1261 __d40_config_set_event(d40c, event_type, event,
262d2915 1262 D40_CHAN_REG_SDLNK);
8d318a50 1263 }
8d318a50
LW		 1264}
1265
a5ebca47 1266static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 1267{
8ca84687 1268 void __iomem *chanbase = chan_base(d40c);
be8cb7df 1269 u32 val;
8d318a50 1270
8ca84687
RV		 1271 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1272 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 1273
a5ebca47 1274 return val;
8d318a50
LW		 1275}
1276
1bdae6f4
N		 1277static int
1278__d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1279{
1280 unsigned long flags;
1281 int ret = 0;
1282 u32 active_status;
1283 void __iomem *active_reg;
1284
1285 if (d40c->phy_chan->num % 2 == 0)
1286 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1287 else
1288 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1289
1290
1291 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1292
1293 switch (command) {
1294 case D40_DMA_STOP:
1295 case D40_DMA_SUSPEND_REQ:
1296
1297 active_status = (readl(active_reg) &
1298 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1299 D40_CHAN_POS(d40c->phy_chan->num);
1300
1301 if (active_status == D40_DMA_RUN)
1302 d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1303 else
1304 d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1305
1306 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1307 ret = __d40_execute_command_phy(d40c, command);
1308
1309 break;
1310
1311 case D40_DMA_RUN:
1312
1313 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1314 ret = __d40_execute_command_phy(d40c, command);
1315 break;
1316
1317 case D40_DMA_SUSPENDED:
1318 BUG();
1319 break;
1320 }
1321
1322 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1323 return ret;
1324}
1325
1326static int d40_channel_execute_command(struct d40_chan *d40c,
1327 enum d40_command command)
1328{
1329 if (chan_is_logical(d40c))
1330 return __d40_execute_command_log(d40c, command);
1331 else
1332 return __d40_execute_command_phy(d40c, command);
1333}
1334
20a5b6d0
RV		 1335static u32 d40_get_prmo(struct d40_chan *d40c)
1336{
1337 static const unsigned int phy_map[] = {
1338 [STEDMA40_PCHAN_BASIC_MODE]
1339 = D40_DREG_PRMO_PCHAN_BASIC,
1340 [STEDMA40_PCHAN_MODULO_MODE]
1341 = D40_DREG_PRMO_PCHAN_MODULO,
1342 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1343 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1344 };
1345 static const unsigned int log_map[] = {
1346 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1347 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1348 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1349 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1350 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1351 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1352 };
1353
724a8577 1354 if (chan_is_physical(d40c))
20a5b6d0
RV		 1355 return phy_map[d40c->dma_cfg.mode_opt];
1356 else
1357 return log_map[d40c->dma_cfg.mode_opt];
1358}
1359
b55912c6 1360static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 1361{
1362 u32 addr_base;
1363 u32 var;
8d318a50
LW		 1364
1365 /* Odd addresses are even addresses + 4 */
1366 addr_base = (d40c->phy_chan->num % 2) * 4;
1367 /* Setup channel mode to logical or physical */
724a8577 1368 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 1369 D40_CHAN_POS(d40c->phy_chan->num);
1370 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1371
1372 /* Setup operational mode option register */
20a5b6d0 1373 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 1374
1375 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1376
724a8577 1377 if (chan_is_logical(d40c)) {
8ca84687
RV		 1378 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1379 & D40_SREG_ELEM_LOG_LIDX_MASK;
1380 void __iomem *chanbase = chan_base(d40c);
1381
8d318a50 1382 /* Set default config for CFG reg */
8ca84687
RV		 1383 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1384 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 1385
b55912c6 1386 /* Set LIDX for lcla */
8ca84687
RV		 1387 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1388 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
e9f3a49c
RV		 1389
1390 /* Clear LNK which will be used by d40_chan_has_events() */
1391 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1392 writel(0, chanbase + D40_CHAN_REG_SDLNK);
8d318a50 1393 }
8d318a50
LW		 1394}
1395
aa182ae2
JA		 1396static u32 d40_residue(struct d40_chan *d40c)
1397{
1398 u32 num_elt;
1399
724a8577 1400 if (chan_is_logical(d40c))
aa182ae2
JA		 1401 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1402 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 1403 else {
1404 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1405 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1406 >> D40_SREG_ELEM_PHY_ECNT_POS;
1407 }
1408
aa182ae2
JA		 1409 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1410}
1411
1412static bool d40_tx_is_linked(struct d40_chan *d40c)
1413{
1414 bool is_link;
1415
724a8577 1416 if (chan_is_logical(d40c))
aa182ae2
JA		 1417 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1418 else
8ca84687
RV		 1419 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1420 & D40_SREG_LNK_PHYS_LNK_MASK;
1421
aa182ae2
JA		 1422 return is_link;
1423}
1424
86eb5fb6 1425static int d40_pause(struct d40_chan *d40c)
aa182ae2 1426{
aa182ae2
JA		 1427 int res = 0;
1428 unsigned long flags;
1429
3ac012af
JA		 1430 if (!d40c->busy)
1431 return 0;
1432
7fb3e75e 1433 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1434 spin_lock_irqsave(&d40c->lock, flags);
1435
1436 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1bdae6f4 1437
7fb3e75e
N		 1438 pm_runtime_mark_last_busy(d40c->base->dev);
1439 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1440 spin_unlock_irqrestore(&d40c->lock, flags);
1441 return res;
1442}
1443
86eb5fb6 1444static int d40_resume(struct d40_chan *d40c)
aa182ae2 1445{
aa182ae2
JA		 1446 int res = 0;
1447 unsigned long flags;
1448
3ac012af
JA		 1449 if (!d40c->busy)
1450 return 0;
1451
aa182ae2 1452 spin_lock_irqsave(&d40c->lock, flags);
7fb3e75e 1453 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1454
1455 /* If bytes left to transfer or linked tx resume job */
1bdae6f4 1456 if (d40_residue(d40c) || d40_tx_is_linked(d40c))
aa182ae2 1457 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
aa182ae2 1458
7fb3e75e
N		 1459 pm_runtime_mark_last_busy(d40c->base->dev);
1460 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1461 spin_unlock_irqrestore(&d40c->lock, flags);
1462 return res;
1463}
1464
8d318a50
LW		 1465static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1466{
1467 struct d40_chan *d40c = container_of(tx->chan,
1468 struct d40_chan,
1469 chan);
1470 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1471 unsigned long flags;
884485e1 1472 dma_cookie_t cookie;
8d318a50
LW		 1473
1474 spin_lock_irqsave(&d40c->lock, flags);
884485e1 1475 cookie = dma_cookie_assign(tx);
8d318a50 1476 d40_desc_queue(d40c, d40d);
8d318a50
LW		 1477 spin_unlock_irqrestore(&d40c->lock, flags);
1478
884485e1 1479 return cookie;
8d318a50
LW		 1480}
1481
1482static int d40_start(struct d40_chan *d40c)
1483{
0c32269d 1484 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 1485}
1486
1487static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1488{
1489 struct d40_desc *d40d;
1490 int err;
1491
1492 /* Start queued jobs, if any */
1493 d40d = d40_first_queued(d40c);
1494
1495 if (d40d != NULL) {
1bdae6f4 1496 if (!d40c->busy) {
7fb3e75e 1497 d40c->busy = true;
1bdae6f4
N		 1498 pm_runtime_get_sync(d40c->base->dev);
1499 }
8d318a50
LW		 1500
1501 /* Remove from queue */
1502 d40_desc_remove(d40d);
1503
1504 /* Add to active queue */
1505 d40_desc_submit(d40c, d40d);
1506
7d83a854
RV		 1507 /* Initiate DMA job */
1508 d40_desc_load(d40c, d40d);
8d318a50 1509
7d83a854
RV		 1510 /* Start dma job */
1511 err = d40_start(d40c);
8d318a50 1512
7d83a854
RV		 1513 if (err)
1514 return NULL;
8d318a50
LW		 1515 }
1516
1517 return d40d;
1518}
1519
1520/* called from interrupt context */
1521static void dma_tc_handle(struct d40_chan *d40c)
1522{
1523 struct d40_desc *d40d;
1524
8d318a50
LW		 1525 /* Get first active entry from list */
1526 d40d = d40_first_active_get(d40c);
1527
1528 if (d40d == NULL)
1529 return;
1530
0c842b55
RV		 1531 if (d40d->cyclic) {
1532 /*
1533 * If this was a paritially loaded list, we need to reloaded
1534 * it, and only when the list is completed. We need to check
1535 * for done because the interrupt will hit for every link, and
1536 * not just the last one.
1537 */
1538 if (d40d->lli_current < d40d->lli_len
1539 && !d40_tx_is_linked(d40c)
1540 && !d40_residue(d40c)) {
1541 d40_lcla_free_all(d40c, d40d);
1542 d40_desc_load(d40c, d40d);
1543 (void) d40_start(d40c);
8d318a50 1544
0c842b55
RV		 1545 if (d40d->lli_current == d40d->lli_len)
1546 d40d->lli_current = 0;
1547 }
1548 } else {
1549 d40_lcla_free_all(d40c, d40d);
8d318a50 1550
0c842b55
RV		 1551 if (d40d->lli_current < d40d->lli_len) {
1552 d40_desc_load(d40c, d40d);
1553 /* Start dma job */
1554 (void) d40_start(d40c);
1555 return;
1556 }
1557
1558 if (d40_queue_start(d40c) == NULL)
1559 d40c->busy = false;
7fb3e75e
N		 1560 pm_runtime_mark_last_busy(d40c->base->dev);
1561 pm_runtime_put_autosuspend(d40c->base->dev);
0c842b55 1562 }
8d318a50 1563
4226dd86
FB		 1564 d40_desc_remove(d40d);
1565 d40_desc_done(d40c, d40d);
1566
8d318a50
LW		 1567 d40c->pending_tx++;
1568 tasklet_schedule(&d40c->tasklet);
1569
1570}
1571
1572static void dma_tasklet(unsigned long data)
1573{
1574 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1575 struct d40_desc *d40d;
8d318a50
LW		 1576 unsigned long flags;
1577 dma_async_tx_callback callback;
1578 void *callback_param;
1579
1580 spin_lock_irqsave(&d40c->lock, flags);
1581
4226dd86
FB		 1582 /* Get first entry from the done list */
1583 d40d = d40_first_done(d40c);
1584 if (d40d == NULL) {
1585 /* Check if we have reached here for cyclic job */
1586 d40d = d40_first_active_get(d40c);
1587 if (d40d == NULL || !d40d->cyclic)
1588 goto err;
1589 }
8d318a50 1590
0c842b55 1591 if (!d40d->cyclic)
f7fbce07 1592 dma_cookie_complete(&d40d->txd);
8d318a50
LW		 1593
1594 /*
1595 * If terminating a channel pending_tx is set to zero.
1596 * This prevents any finished active jobs to return to the client.
1597 */
1598 if (d40c->pending_tx == 0) {
1599 spin_unlock_irqrestore(&d40c->lock, flags);
1600 return;
1601 }
1602
1603 /* Callback to client */
767a9675
JA		 1604 callback = d40d->txd.callback;
1605 callback_param = d40d->txd.callback_param;
1606
0c842b55
RV		 1607 if (!d40d->cyclic) {
1608 if (async_tx_test_ack(&d40d->txd)) {
767a9675 1609 d40_desc_remove(d40d);
0c842b55 1610 d40_desc_free(d40c, d40d);
f26e03ad
FB		 1611 } else if (!d40d->is_in_client_list) {
1612 d40_desc_remove(d40d);
1613 d40_lcla_free_all(d40c, d40d);
1614 list_add_tail(&d40d->node, &d40c->client);
1615 d40d->is_in_client_list = true;
8d318a50
LW		 1616 }
1617 }
1618
1619 d40c->pending_tx--;
1620
1621 if (d40c->pending_tx)
1622 tasklet_schedule(&d40c->tasklet);
1623
1624 spin_unlock_irqrestore(&d40c->lock, flags);
1625
767a9675 1626 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
8d318a50
LW		 1627 callback(callback_param);
1628
1629 return;
1630
1bdae6f4
N		 1631err:
1632 /* Rescue manouver if receiving double interrupts */
8d318a50
LW		 1633 if (d40c->pending_tx > 0)
1634 d40c->pending_tx--;
1635 spin_unlock_irqrestore(&d40c->lock, flags);
1636}
1637
1638static irqreturn_t d40_handle_interrupt(int irq, void *data)
1639{
8d318a50 1640 int i;
8d318a50
LW		 1641 u32 idx;
1642 u32 row;
1643 long chan = -1;
1644 struct d40_chan *d40c;
1645 unsigned long flags;
1646 struct d40_base *base = data;
3cb645dc
TL		 1647 u32 regs[base->gen_dmac.il_size];
1648 struct d40_interrupt_lookup *il = base->gen_dmac.il;
1649 u32 il_size = base->gen_dmac.il_size;
8d318a50
LW		 1650
1651 spin_lock_irqsave(&base->interrupt_lock, flags);
1652
1653 /* Read interrupt status of both logical and physical channels */
3cb645dc 1654 for (i = 0; i < il_size; i++)
8d318a50
LW		 1655 regs[i] = readl(base->virtbase + il[i].src);
1656
1657 for (;;) {
1658
1659 chan = find_next_bit((unsigned long *)regs,
3cb645dc 1660 BITS_PER_LONG * il_size, chan + 1);
8d318a50
LW		 1661
1662 /* No more set bits found? */
3cb645dc 1663 if (chan == BITS_PER_LONG * il_size)
8d318a50
LW		 1664 break;
1665
1666 row = chan / BITS_PER_LONG;
1667 idx = chan & (BITS_PER_LONG - 1);
1668
1669 /* ACK interrupt */
1b00348d 1670 writel(1 << idx, base->virtbase + il[row].clr);
8d318a50
LW		 1671
1672 if (il[row].offset == D40_PHY_CHAN)
1673 d40c = base->lookup_phy_chans[idx];
1674 else
1675 d40c = base->lookup_log_chans[il[row].offset + idx];
1676 spin_lock(&d40c->lock);
1677
1678 if (!il[row].is_error)
1679 dma_tc_handle(d40c);
1680 else
6db5a8ba
RV		 1681 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1682 chan, il[row].offset, idx);
8d318a50
LW		 1683
1684 spin_unlock(&d40c->lock);
1685 }
1686
1687 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1688
1689 return IRQ_HANDLED;
1690}
1691
8d318a50
LW		 1692static int d40_validate_conf(struct d40_chan *d40c,
1693 struct stedma40_chan_cfg *conf)
1694{
1695 int res = 0;
1696 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1697 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
38bdbf02 1698 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1699
0747c7ba 1700 if (!conf->dir) {
6db5a8ba 1701 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1702 res = -EINVAL;
1703 }
1704
1705 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1706 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1707 d40c->runtime_addr == 0) {
1708
6db5a8ba
RV		 1709 chan_err(d40c, "Invalid TX channel address (%d)\n",
1710 conf->dst_dev_type);
0747c7ba
LW		 1711 res = -EINVAL;
1712 }
1713
1714 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1715 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1716 d40c->runtime_addr == 0) {
6db5a8ba
RV		 1717 chan_err(d40c, "Invalid RX channel address (%d)\n",
1718 conf->src_dev_type);
0747c7ba
LW		 1719 res = -EINVAL;
1720 }
1721
1722 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
8d318a50 1723 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
6db5a8ba 1724 chan_err(d40c, "Invalid dst\n");
8d318a50
LW		 1725 res = -EINVAL;
1726 }
1727
0747c7ba 1728 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
8d318a50 1729 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
6db5a8ba 1730 chan_err(d40c, "Invalid src\n");
8d318a50
LW		 1731 res = -EINVAL;
1732 }
1733
1734 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1735 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
6db5a8ba 1736 chan_err(d40c, "No event line\n");
8d318a50
LW		 1737 res = -EINVAL;
1738 }
1739
1740 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1741 (src_event_group != dst_event_group)) {
6db5a8ba 1742 chan_err(d40c, "Invalid event group\n");
8d318a50
LW		 1743 res = -EINVAL;
1744 }
1745
1746 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1747 /*
1748 * DMAC HW supports it. Will be added to this driver,
1749 * in case any dma client requires it.
1750 */
6db5a8ba 1751 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1752 res = -EINVAL;
1753 }
1754
d49278e3
PF		 1755 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1756 (1 << conf->src_info.data_width) !=
1757 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1758 (1 << conf->dst_info.data_width)) {
1759 /*
1760 * The DMAC hardware only supports
1761 * src (burst x width) == dst (burst x width)
1762 */
1763
6db5a8ba 1764 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1765 res = -EINVAL;
1766 }
1767
8d318a50
LW		 1768 return res;
1769}
1770
5cd326fd
N		 1771static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1772 bool is_src, int log_event_line, bool is_log,
1773 bool *first_user)
8d318a50
LW		 1774{
1775 unsigned long flags;
1776 spin_lock_irqsave(&phy->lock, flags);
5cd326fd
N		 1777
1778 *first_user = ((phy->allocated_src | phy->allocated_dst)
1779 == D40_ALLOC_FREE);
1780
4aed79b2 1781 if (!is_log) {
8d318a50
LW		 1782 /* Physical interrupts are masked per physical full channel */
1783 if (phy->allocated_src == D40_ALLOC_FREE &&
1784 phy->allocated_dst == D40_ALLOC_FREE) {
1785 phy->allocated_dst = D40_ALLOC_PHY;
1786 phy->allocated_src = D40_ALLOC_PHY;
1787 goto found;
1788 } else
1789 goto not_found;
1790 }
1791
1792 /* Logical channel */
1793 if (is_src) {
1794 if (phy->allocated_src == D40_ALLOC_PHY)
1795 goto not_found;
1796
1797 if (phy->allocated_src == D40_ALLOC_FREE)
1798 phy->allocated_src = D40_ALLOC_LOG_FREE;
1799
1800 if (!(phy->allocated_src & (1 << log_event_line))) {
1801 phy->allocated_src |= 1 << log_event_line;
1802 goto found;
1803 } else
1804 goto not_found;
1805 } else {
1806 if (phy->allocated_dst == D40_ALLOC_PHY)
1807 goto not_found;
1808
1809 if (phy->allocated_dst == D40_ALLOC_FREE)
1810 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1811
1812 if (!(phy->allocated_dst & (1 << log_event_line))) {
1813 phy->allocated_dst |= 1 << log_event_line;
1814 goto found;
1815 } else
1816 goto not_found;
1817 }
1818
1819not_found:
1820 spin_unlock_irqrestore(&phy->lock, flags);
1821 return false;
1822found:
1823 spin_unlock_irqrestore(&phy->lock, flags);
1824 return true;
1825}
1826
1827static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1828 int log_event_line)
1829{
1830 unsigned long flags;
1831 bool is_free = false;
1832
1833 spin_lock_irqsave(&phy->lock, flags);
1834 if (!log_event_line) {
8d318a50
LW		 1835 phy->allocated_dst = D40_ALLOC_FREE;
1836 phy->allocated_src = D40_ALLOC_FREE;
1837 is_free = true;
1838 goto out;
1839 }
1840
1841 /* Logical channel */
1842 if (is_src) {
1843 phy->allocated_src &= ~(1 << log_event_line);
1844 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1845 phy->allocated_src = D40_ALLOC_FREE;
1846 } else {
1847 phy->allocated_dst &= ~(1 << log_event_line);
1848 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1849 phy->allocated_dst = D40_ALLOC_FREE;
1850 }
1851
1852 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1853 D40_ALLOC_FREE);
1854
1855out:
1856 spin_unlock_irqrestore(&phy->lock, flags);
1857
1858 return is_free;
1859}
1860
5cd326fd 1861static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
8d318a50
LW		 1862{
1863 int dev_type;
1864 int event_group;
1865 int event_line;
1866 struct d40_phy_res *phys;
1867 int i;
1868 int j;
1869 int log_num;
f000df8c 1870 int num_phy_chans;
8d318a50 1871 bool is_src;
38bdbf02 1872 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1873
1874 phys = d40c->base->phy_res;
f000df8c 1875 num_phy_chans = d40c->base->num_phy_chans;
8d318a50
LW		 1876
1877 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1878 dev_type = d40c->dma_cfg.src_dev_type;
1879 log_num = 2 * dev_type;
1880 is_src = true;
1881 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1882 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1883 /* dst event lines are used for logical memcpy */
1884 dev_type = d40c->dma_cfg.dst_dev_type;
1885 log_num = 2 * dev_type + 1;
1886 is_src = false;
1887 } else
1888 return -EINVAL;
1889
1890 event_group = D40_TYPE_TO_GROUP(dev_type);
1891 event_line = D40_TYPE_TO_EVENT(dev_type);
1892
1893 if (!is_log) {
1894 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1895 /* Find physical half channel */
f000df8c
GB		 1896 if (d40c->dma_cfg.use_fixed_channel) {
1897 i = d40c->dma_cfg.phy_channel;
4aed79b2 1898 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1899 0, is_log,
1900 first_phy_user))
8d318a50 1901 goto found_phy;
f000df8c
GB		 1902 } else {
1903 for (i = 0; i < num_phy_chans; i++) {
1904 if (d40_alloc_mask_set(&phys[i], is_src,
1905 0, is_log,
1906 first_phy_user))
1907 goto found_phy;
1908 }
8d318a50
LW		 1909 }
1910 } else
1911 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1912 int phy_num = j + event_group * 2;
1913 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1914 if (d40_alloc_mask_set(&phys[i],
1915 is_src,
1916 0,
5cd326fd
N		 1917 is_log,
1918 first_phy_user))
8d318a50
LW		 1919 goto found_phy;
1920 }
1921 }
1922 return -EINVAL;
1923found_phy:
1924 d40c->phy_chan = &phys[i];
1925 d40c->log_num = D40_PHY_CHAN;
1926 goto out;
1927 }
1928 if (dev_type == -1)
1929 return -EINVAL;
1930
1931 /* Find logical channel */
1932 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1933 int phy_num = j + event_group * 2;
5cd326fd
N		 1934
1935 if (d40c->dma_cfg.use_fixed_channel) {
1936 i = d40c->dma_cfg.phy_channel;
1937
1938 if ((i != phy_num) && (i != phy_num + 1)) {
1939 dev_err(chan2dev(d40c),
1940 "invalid fixed phy channel %d\n", i);
1941 return -EINVAL;
1942 }
1943
1944 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1945 is_log, first_phy_user))
1946 goto found_log;
1947
1948 dev_err(chan2dev(d40c),
1949 "could not allocate fixed phy channel %d\n", i);
1950 return -EINVAL;
1951 }
1952
8d318a50
LW		 1953 /*
1954 * Spread logical channels across all available physical rather
1955 * than pack every logical channel at the first available phy
1956 * channels.
1957 */
1958 if (is_src) {
1959 for (i = phy_num; i < phy_num + 2; i++) {
1960 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1961 event_line, is_log,
1962 first_phy_user))
8d318a50
LW		 1963 goto found_log;
1964 }
1965 } else {
1966 for (i = phy_num + 1; i >= phy_num; i--) {
1967 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1968 event_line, is_log,
1969 first_phy_user))
8d318a50
LW		 1970 goto found_log;
1971 }
1972 }
1973 }
1974 return -EINVAL;
1975
1976found_log:
1977 d40c->phy_chan = &phys[i];
1978 d40c->log_num = log_num;
1979out:
1980
1981 if (is_log)
1982 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1983 else
1984 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1985
1986 return 0;
1987
1988}
1989
8d318a50
LW		 1990static int d40_config_memcpy(struct d40_chan *d40c)
1991{
1992 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1993
1994 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1995 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1996 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1997 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1998 memcpy[d40c->chan.chan_id];
1999
2000 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
2001 dma_has_cap(DMA_SLAVE, cap)) {
2002 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
2003 } else {
6db5a8ba 2004 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 2005 return -EINVAL;
2006 }
2007
2008 return 0;
2009}
2010
8d318a50
LW		 2011static int d40_free_dma(struct d40_chan *d40c)
2012{
2013
2014 int res = 0;
d181b3a8 2015 u32 event;
8d318a50
LW		 2016 struct d40_phy_res *phy = d40c->phy_chan;
2017 bool is_src;
2018
2019 /* Terminate all queued and active transfers */
2020 d40_term_all(d40c);
2021
2022 if (phy == NULL) {
6db5a8ba 2023 chan_err(d40c, "phy == null\n");
8d318a50
LW		 2024 return -EINVAL;
2025 }
2026
2027 if (phy->allocated_src == D40_ALLOC_FREE &&
2028 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 2029 chan_err(d40c, "channel already free\n");
8d318a50
LW		 2030 return -EINVAL;
2031 }
2032
8d318a50
LW		 2033 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
2034 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
2035 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8d318a50
LW		 2036 is_src = false;
2037 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
2038 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8d318a50
LW		 2039 is_src = true;
2040 } else {
6db5a8ba 2041 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 2042 return -EINVAL;
2043 }
2044
7fb3e75e 2045 pm_runtime_get_sync(d40c->base->dev);
1bdae6f4 2046 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
d181b3a8 2047 if (res) {
1bdae6f4 2048 chan_err(d40c, "stop failed\n");
7fb3e75e 2049 goto out;
d181b3a8
JA		 2050 }
2051
1bdae6f4 2052 d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
8d318a50 2053
1bdae6f4 2054 if (chan_is_logical(d40c))
8d318a50 2055 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1bdae6f4
N		 2056 else
2057 d40c->base->lookup_phy_chans[phy->num] = NULL;
7fb3e75e
N		 2058
2059 if (d40c->busy) {
2060 pm_runtime_mark_last_busy(d40c->base->dev);
2061 pm_runtime_put_autosuspend(d40c->base->dev);
2062 }
2063
2064 d40c->busy = false;
8d318a50 2065 d40c->phy_chan = NULL;
ce2ca125 2066 d40c->configured = false;
7fb3e75e 2067out:
8d318a50 2068
7fb3e75e
N		 2069 pm_runtime_mark_last_busy(d40c->base->dev);
2070 pm_runtime_put_autosuspend(d40c->base->dev);
2071 return res;
8d318a50
LW		 2072}
2073
a5ebca47
JA		 2074static bool d40_is_paused(struct d40_chan *d40c)
2075{
8ca84687 2076 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 2077 bool is_paused = false;
2078 unsigned long flags;
2079 void __iomem *active_reg;
2080 u32 status;
2081 u32 event;
a5ebca47
JA		 2082
2083 spin_lock_irqsave(&d40c->lock, flags);
2084
724a8577 2085 if (chan_is_physical(d40c)) {
a5ebca47
JA		 2086 if (d40c->phy_chan->num % 2 == 0)
2087 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2088 else
2089 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2090
2091 status = (readl(active_reg) &
2092 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
2093 D40_CHAN_POS(d40c->phy_chan->num);
2094 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
2095 is_paused = true;
2096
2097 goto _exit;
2098 }
2099
a5ebca47 2100 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
9dbfbd35 2101 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
a5ebca47 2102 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8ca84687 2103 status = readl(chanbase + D40_CHAN_REG_SDLNK);
9dbfbd35 2104 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
a5ebca47 2105 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8ca84687 2106 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 2107 } else {
6db5a8ba 2108 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 2109 goto _exit;
2110 }
9dbfbd35 2111
a5ebca47
JA		 2112 status = (status & D40_EVENTLINE_MASK(event)) >>
2113 D40_EVENTLINE_POS(event);
2114
2115 if (status != D40_DMA_RUN)
2116 is_paused = true;
a5ebca47
JA		 2117_exit:
2118 spin_unlock_irqrestore(&d40c->lock, flags);
2119 return is_paused;
2120
2121}
2122
8d318a50
LW		 2123static u32 stedma40_residue(struct dma_chan *chan)
2124{
2125 struct d40_chan *d40c =
2126 container_of(chan, struct d40_chan, chan);
2127 u32 bytes_left;
2128 unsigned long flags;
2129
2130 spin_lock_irqsave(&d40c->lock, flags);
2131 bytes_left = d40_residue(d40c);
2132 spin_unlock_irqrestore(&d40c->lock, flags);
2133
2134 return bytes_left;
2135}
2136
3e3a0763
RV		 2137static int
2138d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
2139 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 2140 unsigned int sg_len, dma_addr_t src_dev_addr,
2141 dma_addr_t dst_dev_addr)
3e3a0763
RV		 2142{
2143 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2144 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2145 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
5ed04b85 2146 int ret;
3e3a0763 2147
5ed04b85
RV		 2148 ret = d40_log_sg_to_lli(sg_src, sg_len,
2149 src_dev_addr,
2150 desc->lli_log.src,
2151 chan->log_def.lcsp1,
2152 src_info->data_width,
2153 dst_info->data_width);
2154
2155 ret = d40_log_sg_to_lli(sg_dst, sg_len,
2156 dst_dev_addr,
2157 desc->lli_log.dst,
2158 chan->log_def.lcsp3,
2159 dst_info->data_width,
2160 src_info->data_width);
2161
2162 return ret < 0 ? ret : 0;
3e3a0763
RV		 2163}
2164
2165static int
2166d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2167 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 2168 unsigned int sg_len, dma_addr_t src_dev_addr,
2169 dma_addr_t dst_dev_addr)
3e3a0763 2170{
3e3a0763
RV		 2171 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2172 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2173 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
0c842b55 2174 unsigned long flags = 0;
3e3a0763
RV		 2175 int ret;
2176
0c842b55
RV		 2177 if (desc->cyclic)
2178 flags |= LLI_CYCLIC | LLI_TERM_INT;
2179
3e3a0763
RV		 2180 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2181 desc->lli_phy.src,
2182 virt_to_phys(desc->lli_phy.src),
2183 chan->src_def_cfg,
0c842b55 2184 src_info, dst_info, flags);
3e3a0763
RV		 2185
2186 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2187 desc->lli_phy.dst,
2188 virt_to_phys(desc->lli_phy.dst),
2189 chan->dst_def_cfg,
0c842b55 2190 dst_info, src_info, flags);
3e3a0763
RV		 2191
2192 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2193 desc->lli_pool.size, DMA_TO_DEVICE);
2194
2195 return ret < 0 ? ret : 0;
2196}
2197
5f81158f
RV		 2198static struct d40_desc *
2199d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2200 unsigned int sg_len, unsigned long dma_flags)
2201{
2202 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2203 struct d40_desc *desc;
dbd88788 2204 int ret;
5f81158f
RV		 2205
2206 desc = d40_desc_get(chan);
2207 if (!desc)
2208 return NULL;
2209
2210 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2211 cfg->dst_info.data_width);
2212 if (desc->lli_len < 0) {
2213 chan_err(chan, "Unaligned size\n");
dbd88788
RV		 2214 goto err;
2215 }
5f81158f 2216
dbd88788
RV		 2217 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2218 if (ret < 0) {
2219 chan_err(chan, "Could not allocate lli\n");
2220 goto err;
5f81158f
RV		 2221 }
2222
2223 desc->lli_current = 0;
2224 desc->txd.flags = dma_flags;
2225 desc->txd.tx_submit = d40_tx_submit;
2226
2227 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2228
2229 return desc;
dbd88788
RV		 2230
2231err:
2232 d40_desc_free(chan, desc);
2233 return NULL;
5f81158f
RV		 2234}
2235
cade1d30 2236static dma_addr_t
db8196df 2237d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
8d318a50 2238{
cade1d30
RV		 2239 struct stedma40_platform_data *plat = chan->base->plat_data;
2240 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
711b9cea 2241 dma_addr_t addr = 0;
cade1d30
RV		 2242
2243 if (chan->runtime_addr)
2244 return chan->runtime_addr;
2245
db8196df 2246 if (direction == DMA_DEV_TO_MEM)
cade1d30 2247 addr = plat->dev_rx[cfg->src_dev_type];
db8196df 2248 else if (direction == DMA_MEM_TO_DEV)
cade1d30
RV		 2249 addr = plat->dev_tx[cfg->dst_dev_type];
2250
2251 return addr;
2252}
2253
2254static struct dma_async_tx_descriptor *
2255d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2256 struct scatterlist *sg_dst, unsigned int sg_len,
db8196df 2257 enum dma_transfer_direction direction, unsigned long dma_flags)
cade1d30
RV		 2258{
2259 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
822c5676
RV		 2260 dma_addr_t src_dev_addr = 0;
2261 dma_addr_t dst_dev_addr = 0;
cade1d30 2262 struct d40_desc *desc;
2a614340 2263 unsigned long flags;
cade1d30 2264 int ret;
8d318a50 2265
cade1d30
RV		 2266 if (!chan->phy_chan) {
2267 chan_err(chan, "Cannot prepare unallocated channel\n");
2268 return NULL;
0d0f6b8b
JA		 2269 }
2270
cade1d30 2271 spin_lock_irqsave(&chan->lock, flags);
8d318a50 2272
cade1d30
RV		 2273 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2274 if (desc == NULL)
8d318a50
LW		 2275 goto err;
2276
0c842b55
RV		 2277 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2278 desc->cyclic = true;
2279
7e426da8 2280 if (direction != DMA_TRANS_NONE) {
822c5676
RV		 2281 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
2282
db8196df 2283 if (direction == DMA_DEV_TO_MEM)
822c5676 2284 src_dev_addr = dev_addr;
db8196df 2285 else if (direction == DMA_MEM_TO_DEV)
822c5676
RV		 2286 dst_dev_addr = dev_addr;
2287 }
cade1d30
RV		 2288
2289 if (chan_is_logical(chan))
2290 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
822c5676 2291 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2292 else
2293 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
822c5676 2294 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2295
2296 if (ret) {
2297 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2298 chan_is_logical(chan) ? "log" : "phy", ret);
2299 goto err;
8d318a50
LW		 2300 }
2301
82babbb3
PF		 2302 /*
2303 * add descriptor to the prepare queue in order to be able
2304 * to free them later in terminate_all
2305 */
2306 list_add_tail(&desc->node, &chan->prepare_queue);
2307
cade1d30
RV		 2308 spin_unlock_irqrestore(&chan->lock, flags);
2309
2310 return &desc->txd;
8d318a50 2311
8d318a50 2312err:
cade1d30
RV		 2313 if (desc)
2314 d40_desc_free(chan, desc);
2315 spin_unlock_irqrestore(&chan->lock, flags);
8d318a50
LW		 2316 return NULL;
2317}
8d318a50
LW		 2318
2319bool stedma40_filter(struct dma_chan *chan, void *data)
2320{
2321 struct stedma40_chan_cfg *info = data;
2322 struct d40_chan *d40c =
2323 container_of(chan, struct d40_chan, chan);
2324 int err;
2325
2326 if (data) {
2327 err = d40_validate_conf(d40c, info);
2328 if (!err)
2329 d40c->dma_cfg = *info;
2330 } else
2331 err = d40_config_memcpy(d40c);
2332
ce2ca125
RV		 2333 if (!err)
2334 d40c->configured = true;
2335
8d318a50
LW		 2336 return err == 0;
2337}
2338EXPORT_SYMBOL(stedma40_filter);
2339
ac2c0a38
RV		 2340static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2341{
2342 bool realtime = d40c->dma_cfg.realtime;
2343 bool highprio = d40c->dma_cfg.high_priority;
3cb645dc 2344 u32 rtreg;
ac2c0a38
RV		 2345 u32 event = D40_TYPE_TO_EVENT(dev_type);
2346 u32 group = D40_TYPE_TO_GROUP(dev_type);
2347 u32 bit = 1 << event;
ccc3d697 2348 u32 prioreg;
3cb645dc 2349 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
ccc3d697 2350
3cb645dc 2351 rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
ccc3d697
RV		 2352 /*
2353 * Due to a hardware bug, in some cases a logical channel triggered by
2354 * a high priority destination event line can generate extra packet
2355 * transactions.
2356 *
2357 * The workaround is to not set the high priority level for the
2358 * destination event lines that trigger logical channels.
2359 */
2360 if (!src && chan_is_logical(d40c))
2361 highprio = false;
2362
3cb645dc 2363 prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
ac2c0a38
RV		 2364
2365 /* Destination event lines are stored in the upper halfword */
2366 if (!src)
2367 bit <<= 16;
2368
2369 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2370 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2371}
2372
2373static void d40_set_prio_realtime(struct d40_chan *d40c)
2374{
2375 if (d40c->base->rev < 3)
2376 return;
2377
2378 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
2379 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2380 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
2381
2382 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
2383 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2384 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
2385}
2386
8d318a50
LW		 2387/* DMA ENGINE functions */
2388static int d40_alloc_chan_resources(struct dma_chan *chan)
2389{
2390 int err;
2391 unsigned long flags;
2392 struct d40_chan *d40c =
2393 container_of(chan, struct d40_chan, chan);
ef1872ec 2394 bool is_free_phy;
8d318a50
LW		 2395 spin_lock_irqsave(&d40c->lock, flags);
2396
d3ee98cd 2397 dma_cookie_init(chan);
8d318a50 2398
ce2ca125
RV		 2399 /* If no dma configuration is set use default configuration (memcpy) */
2400 if (!d40c->configured) {
8d318a50 2401 err = d40_config_memcpy(d40c);
ff0b12ba 2402 if (err) {
6db5a8ba 2403 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 2404 goto fail;
2405 }
8d318a50
LW		 2406 }
2407
5cd326fd 2408 err = d40_allocate_channel(d40c, &is_free_phy);
8d318a50 2409 if (err) {
6db5a8ba 2410 chan_err(d40c, "Failed to allocate channel\n");
7fb3e75e 2411 d40c->configured = false;
ff0b12ba 2412 goto fail;
8d318a50
LW		 2413 }
2414
7fb3e75e 2415 pm_runtime_get_sync(d40c->base->dev);
ef1872ec
LW		 2416 /* Fill in basic CFG register values */
2417 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
724a8577 2418 &d40c->dst_def_cfg, chan_is_logical(d40c));
ef1872ec 2419
ac2c0a38
RV		 2420 d40_set_prio_realtime(d40c);
2421
724a8577 2422 if (chan_is_logical(d40c)) {
ef1872ec
LW		 2423 d40_log_cfg(&d40c->dma_cfg,
2424 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2425
2426 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
2427 d40c->lcpa = d40c->base->lcpa_base +
f26e03ad 2428 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
ef1872ec
LW		 2429 else
2430 d40c->lcpa = d40c->base->lcpa_base +
f26e03ad
FB		 2431 d40c->dma_cfg.dst_dev_type *
2432 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
ef1872ec
LW		 2433 }
2434
5cd326fd
N		 2435 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2436 chan_is_logical(d40c) ? "logical" : "physical",
2437 d40c->phy_chan->num,
2438 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2439
2440
ef1872ec
LW		 2441 /*
2442 * Only write channel configuration to the DMA if the physical
2443 * resource is free. In case of multiple logical channels
2444 * on the same physical resource, only the first write is necessary.
2445 */
b55912c6
JA		 2446 if (is_free_phy)
2447 d40_config_write(d40c);
ff0b12ba 2448fail:
7fb3e75e
N		 2449 pm_runtime_mark_last_busy(d40c->base->dev);
2450 pm_runtime_put_autosuspend(d40c->base->dev);
8d318a50 2451 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 2452 return err;
8d318a50
LW		 2453}
2454
2455static void d40_free_chan_resources(struct dma_chan *chan)
2456{
2457 struct d40_chan *d40c =
2458 container_of(chan, struct d40_chan, chan);
2459 int err;
2460 unsigned long flags;
2461
0d0f6b8b 2462 if (d40c->phy_chan == NULL) {
6db5a8ba 2463 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 2464 return;
2465 }
2466
8d318a50
LW		 2467 spin_lock_irqsave(&d40c->lock, flags);
2468
2469 err = d40_free_dma(d40c);
2470
2471 if (err)
6db5a8ba 2472 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 2473 spin_unlock_irqrestore(&d40c->lock, flags);
2474}
2475
2476static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2477 dma_addr_t dst,
2478 dma_addr_t src,
2479 size_t size,
2a614340 2480 unsigned long dma_flags)
8d318a50 2481{
95944c6e
RV		 2482 struct scatterlist dst_sg;
2483 struct scatterlist src_sg;
8d318a50 2484
95944c6e
RV		 2485 sg_init_table(&dst_sg, 1);
2486 sg_init_table(&src_sg, 1);
8d318a50 2487
95944c6e
RV		 2488 sg_dma_address(&dst_sg) = dst;
2489 sg_dma_address(&src_sg) = src;
8d318a50 2490
95944c6e
RV		 2491 sg_dma_len(&dst_sg) = size;
2492 sg_dma_len(&src_sg) = size;
8d318a50 2493
cade1d30 2494 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
8d318a50
LW		 2495}
2496
0d688662 2497static struct dma_async_tx_descriptor *
cade1d30
RV		 2498d40_prep_memcpy_sg(struct dma_chan *chan,
2499 struct scatterlist *dst_sg, unsigned int dst_nents,
2500 struct scatterlist *src_sg, unsigned int src_nents,
2501 unsigned long dma_flags)
0d688662
IS		 2502{
2503 if (dst_nents != src_nents)
2504 return NULL;
2505
cade1d30 2506 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
00ac0341
RV		 2507}
2508
f26e03ad
FB		 2509static struct dma_async_tx_descriptor *
2510d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2511 unsigned int sg_len, enum dma_transfer_direction direction,
2512 unsigned long dma_flags, void *context)
8d318a50 2513{
db8196df 2514 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV)
00ac0341
RV		 2515 return NULL;
2516
cade1d30 2517 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
8d318a50
LW		 2518}
2519
0c842b55
RV		 2520static struct dma_async_tx_descriptor *
2521dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2522 size_t buf_len, size_t period_len,
ec8b5e48
PU		 2523 enum dma_transfer_direction direction, unsigned long flags,
2524 void *context)
0c842b55
RV		 2525{
2526 unsigned int periods = buf_len / period_len;
2527 struct dma_async_tx_descriptor *txd;
2528 struct scatterlist *sg;
2529 int i;
2530
79ca7ec3 2531 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
0c842b55
RV		 2532 for (i = 0; i < periods; i++) {
2533 sg_dma_address(&sg[i]) = dma_addr;
2534 sg_dma_len(&sg[i]) = period_len;
2535 dma_addr += period_len;
2536 }
2537
2538 sg[periods].offset = 0;
fdaf9c4b 2539 sg_dma_len(&sg[periods]) = 0;
0c842b55
RV		 2540 sg[periods].page_link =
2541 ((unsigned long)sg | 0x01) & ~0x02;
2542
2543 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2544 DMA_PREP_INTERRUPT);
2545
2546 kfree(sg);
2547
2548 return txd;
2549}
2550
8d318a50
LW		 2551static enum dma_status d40_tx_status(struct dma_chan *chan,
2552 dma_cookie_t cookie,
2553 struct dma_tx_state *txstate)
2554{
2555 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
96a2af41 2556 enum dma_status ret;
8d318a50 2557
0d0f6b8b 2558 if (d40c->phy_chan == NULL) {
6db5a8ba 2559 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2560 return -EINVAL;
2561 }
2562
96a2af41
RKAL		 2563 ret = dma_cookie_status(chan, cookie, txstate);
2564 if (ret != DMA_SUCCESS)
2565 dma_set_residue(txstate, stedma40_residue(chan));
8d318a50 2566
a5ebca47
JA		 2567 if (d40_is_paused(d40c))
2568 ret = DMA_PAUSED;
8d318a50
LW		 2569
2570 return ret;
2571}
2572
2573static void d40_issue_pending(struct dma_chan *chan)
2574{
2575 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2576 unsigned long flags;
2577
0d0f6b8b 2578 if (d40c->phy_chan == NULL) {
6db5a8ba 2579 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2580 return;
2581 }
2582
8d318a50
LW		 2583 spin_lock_irqsave(&d40c->lock, flags);
2584
a8f3067b
PF		 2585 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2586
2587 /* Busy means that queued jobs are already being processed */
8d318a50
LW		 2588 if (!d40c->busy)
2589 (void) d40_queue_start(d40c);
2590
2591 spin_unlock_irqrestore(&d40c->lock, flags);
2592}
2593
1bdae6f4
N		 2594static void d40_terminate_all(struct dma_chan *chan)
2595{
2596 unsigned long flags;
2597 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2598 int ret;
2599
2600 spin_lock_irqsave(&d40c->lock, flags);
2601
2602 pm_runtime_get_sync(d40c->base->dev);
2603 ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2604 if (ret)
2605 chan_err(d40c, "Failed to stop channel\n");
2606
2607 d40_term_all(d40c);
2608 pm_runtime_mark_last_busy(d40c->base->dev);
2609 pm_runtime_put_autosuspend(d40c->base->dev);
2610 if (d40c->busy) {
2611 pm_runtime_mark_last_busy(d40c->base->dev);
2612 pm_runtime_put_autosuspend(d40c->base->dev);
2613 }
2614 d40c->busy = false;
2615
2616 spin_unlock_irqrestore(&d40c->lock, flags);
2617}
2618
98ca5289
RV		 2619static int
2620dma40_config_to_halfchannel(struct d40_chan *d40c,
2621 struct stedma40_half_channel_info *info,
2622 enum dma_slave_buswidth width,
2623 u32 maxburst)
2624{
2625 enum stedma40_periph_data_width addr_width;
2626 int psize;
2627
2628 switch (width) {
2629 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2630 addr_width = STEDMA40_BYTE_WIDTH;
2631 break;
2632 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2633 addr_width = STEDMA40_HALFWORD_WIDTH;
2634 break;
2635 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2636 addr_width = STEDMA40_WORD_WIDTH;
2637 break;
2638 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2639 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2640 break;
2641 default:
2642 dev_err(d40c->base->dev,
2643 "illegal peripheral address width "
2644 "requested (%d)\n",
2645 width);
2646 return -EINVAL;
2647 }
2648
2649 if (chan_is_logical(d40c)) {
2650 if (maxburst >= 16)
2651 psize = STEDMA40_PSIZE_LOG_16;
2652 else if (maxburst >= 8)
2653 psize = STEDMA40_PSIZE_LOG_8;
2654 else if (maxburst >= 4)
2655 psize = STEDMA40_PSIZE_LOG_4;
2656 else
2657 psize = STEDMA40_PSIZE_LOG_1;
2658 } else {
2659 if (maxburst >= 16)
2660 psize = STEDMA40_PSIZE_PHY_16;
2661 else if (maxburst >= 8)
2662 psize = STEDMA40_PSIZE_PHY_8;
2663 else if (maxburst >= 4)
2664 psize = STEDMA40_PSIZE_PHY_4;
2665 else
2666 psize = STEDMA40_PSIZE_PHY_1;
2667 }
2668
2669 info->data_width = addr_width;
2670 info->psize = psize;
2671 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2672
2673 return 0;
2674}
2675
95e1400f 2676/* Runtime reconfiguration extension */
98ca5289
RV		 2677static int d40_set_runtime_config(struct dma_chan *chan,
2678 struct dma_slave_config *config)
95e1400f
LW		 2679{
2680 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2681 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
98ca5289 2682 enum dma_slave_buswidth src_addr_width, dst_addr_width;
95e1400f 2683 dma_addr_t config_addr;
98ca5289
RV		 2684 u32 src_maxburst, dst_maxburst;
2685 int ret;
2686
2687 src_addr_width = config->src_addr_width;
2688 src_maxburst = config->src_maxburst;
2689 dst_addr_width = config->dst_addr_width;
2690 dst_maxburst = config->dst_maxburst;
95e1400f 2691
db8196df 2692 if (config->direction == DMA_DEV_TO_MEM) {
95e1400f
LW		 2693 dma_addr_t dev_addr_rx =
2694 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2695
2696 config_addr = config->src_addr;
2697 if (dev_addr_rx)
2698 dev_dbg(d40c->base->dev,
2699 "channel has a pre-wired RX address %08x "
2700 "overriding with %08x\n",
2701 dev_addr_rx, config_addr);
2702 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2703 dev_dbg(d40c->base->dev,
2704 "channel was not configured for peripheral "
2705 "to memory transfer (%d) overriding\n",
2706 cfg->dir);
2707 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2708
98ca5289
RV		 2709 /* Configure the memory side */
2710 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2711 dst_addr_width = src_addr_width;
2712 if (dst_maxburst == 0)
2713 dst_maxburst = src_maxburst;
95e1400f 2714
db8196df 2715 } else if (config->direction == DMA_MEM_TO_DEV) {
95e1400f
LW		 2716 dma_addr_t dev_addr_tx =
2717 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2718
2719 config_addr = config->dst_addr;
2720 if (dev_addr_tx)
2721 dev_dbg(d40c->base->dev,
2722 "channel has a pre-wired TX address %08x "
2723 "overriding with %08x\n",
2724 dev_addr_tx, config_addr);
2725 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2726 dev_dbg(d40c->base->dev,
2727 "channel was not configured for memory "
2728 "to peripheral transfer (%d) overriding\n",
2729 cfg->dir);
2730 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2731
98ca5289
RV		 2732 /* Configure the memory side */
2733 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2734 src_addr_width = dst_addr_width;
2735 if (src_maxburst == 0)
2736 src_maxburst = dst_maxburst;
95e1400f
LW		 2737 } else {
2738 dev_err(d40c->base->dev,
2739 "unrecognized channel direction %d\n",
2740 config->direction);
98ca5289 2741 return -EINVAL;
95e1400f
LW		 2742 }
2743
98ca5289 2744 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
95e1400f 2745 dev_err(d40c->base->dev,
98ca5289
RV		 2746 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2747 src_maxburst,
2748 src_addr_width,
2749 dst_maxburst,
2750 dst_addr_width);
2751 return -EINVAL;
95e1400f
LW		 2752 }
2753
92bb6cdb
PF		 2754 if (src_maxburst > 16) {
2755 src_maxburst = 16;
2756 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2757 } else if (dst_maxburst > 16) {
2758 dst_maxburst = 16;
2759 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2760 }
2761
98ca5289
RV		 2762 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2763 src_addr_width,
2764 src_maxburst);
2765 if (ret)
2766 return ret;
95e1400f 2767
98ca5289
RV		 2768 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2769 dst_addr_width,
2770 dst_maxburst);
2771 if (ret)
2772 return ret;
95e1400f 2773
a59670a4 2774 /* Fill in register values */
724a8577 2775 if (chan_is_logical(d40c))
a59670a4
PF		 2776 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2777 else
2778 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2779 &d40c->dst_def_cfg, false);
2780
95e1400f
LW		 2781 /* These settings will take precedence later */
2782 d40c->runtime_addr = config_addr;
2783 d40c->runtime_direction = config->direction;
2784 dev_dbg(d40c->base->dev,
98ca5289
RV		 2785 "configured channel %s for %s, data width %d/%d, "
2786 "maxburst %d/%d elements, LE, no flow control\n",
95e1400f 2787 dma_chan_name(chan),
db8196df 2788 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
98ca5289
RV		 2789 src_addr_width, dst_addr_width,
2790 src_maxburst, dst_maxburst);
2791
2792 return 0;
95e1400f
LW		 2793}
2794
05827630
LW		 2795static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2796 unsigned long arg)
8d318a50 2797{
8d318a50
LW		 2798 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2799
0d0f6b8b 2800 if (d40c->phy_chan == NULL) {
6db5a8ba 2801 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2802 return -EINVAL;
2803 }
2804
8d318a50
LW		 2805 switch (cmd) {
2806 case DMA_TERMINATE_ALL:
1bdae6f4
N		 2807 d40_terminate_all(chan);
2808 return 0;
8d318a50 2809 case DMA_PAUSE:
86eb5fb6 2810 return d40_pause(d40c);
8d318a50 2811 case DMA_RESUME:
86eb5fb6 2812 return d40_resume(d40c);
95e1400f 2813 case DMA_SLAVE_CONFIG:
98ca5289 2814 return d40_set_runtime_config(chan,
95e1400f 2815 (struct dma_slave_config *) arg);
95e1400f
LW		 2816 default:
2817 break;
8d318a50
LW		 2818 }
2819
2820 /* Other commands are unimplemented */
2821 return -ENXIO;
2822}
2823
2824/* Initialization functions */
2825
2826static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2827 struct d40_chan *chans, int offset,
2828 int num_chans)
2829{
2830 int i = 0;
2831 struct d40_chan *d40c;
2832
2833 INIT_LIST_HEAD(&dma->channels);
2834
2835 for (i = offset; i < offset + num_chans; i++) {
2836 d40c = &chans[i];
2837 d40c->base = base;
2838 d40c->chan.device = dma;
2839
8d318a50
LW		 2840 spin_lock_init(&d40c->lock);
2841
2842 d40c->log_num = D40_PHY_CHAN;
2843
4226dd86 2844 INIT_LIST_HEAD(&d40c->done);
8d318a50
LW		 2845 INIT_LIST_HEAD(&d40c->active);
2846 INIT_LIST_HEAD(&d40c->queue);
a8f3067b 2847 INIT_LIST_HEAD(&d40c->pending_queue);
8d318a50 2848 INIT_LIST_HEAD(&d40c->client);
82babbb3 2849 INIT_LIST_HEAD(&d40c->prepare_queue);
8d318a50 2850
8d318a50
LW		 2851 tasklet_init(&d40c->tasklet, dma_tasklet,
2852 (unsigned long) d40c);
2853
2854 list_add_tail(&d40c->chan.device_node,
2855 &dma->channels);
2856 }
2857}
2858
7ad74a7c
RV		 2859static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2860{
2861 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2862 dev->device_prep_slave_sg = d40_prep_slave_sg;
2863
2864 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2865 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2866
2867 /*
2868 * This controller can only access address at even
2869 * 32bit boundaries, i.e. 2^2
2870 */
2871 dev->copy_align = 2;
2872 }
2873
2874 if (dma_has_cap(DMA_SG, dev->cap_mask))
2875 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2876
0c842b55
RV		 2877 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2878 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2879
7ad74a7c
RV		 2880 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2881 dev->device_free_chan_resources = d40_free_chan_resources;
2882 dev->device_issue_pending = d40_issue_pending;
2883 dev->device_tx_status = d40_tx_status;
2884 dev->device_control = d40_control;
2885 dev->dev = base->dev;
2886}
2887
8d318a50
LW		 2888static int __init d40_dmaengine_init(struct d40_base *base,
2889 int num_reserved_chans)
2890{
2891 int err ;
2892
2893 d40_chan_init(base, &base->dma_slave, base->log_chans,
2894 0, base->num_log_chans);
2895
2896 dma_cap_zero(base->dma_slave.cap_mask);
2897 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
0c842b55 2898 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
8d318a50 2899
7ad74a7c 2900 d40_ops_init(base, &base->dma_slave);
8d318a50
LW		 2901
2902 err = dma_async_device_register(&base->dma_slave);
2903
2904 if (err) {
6db5a8ba 2905 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2906 goto failure1;
2907 }
2908
2909 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2910 base->num_log_chans, base->plat_data->memcpy_len);
2911
2912 dma_cap_zero(base->dma_memcpy.cap_mask);
2913 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
7ad74a7c
RV		 2914 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2915
2916 d40_ops_init(base, &base->dma_memcpy);
8d318a50
LW		 2917
2918 err = dma_async_device_register(&base->dma_memcpy);
2919
2920 if (err) {
6db5a8ba
RV		 2921 d40_err(base->dev,
2922 "Failed to regsiter memcpy only channels\n");
8d318a50
LW		 2923 goto failure2;
2924 }
2925
2926 d40_chan_init(base, &base->dma_both, base->phy_chans,
2927 0, num_reserved_chans);
2928
2929 dma_cap_zero(base->dma_both.cap_mask);
2930 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2931 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
7ad74a7c 2932 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
0c842b55 2933 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
7ad74a7c
RV		 2934
2935 d40_ops_init(base, &base->dma_both);
8d318a50
LW		 2936 err = dma_async_device_register(&base->dma_both);
2937
2938 if (err) {
6db5a8ba
RV		 2939 d40_err(base->dev,
2940 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2941 goto failure3;
2942 }
2943 return 0;
2944failure3:
2945 dma_async_device_unregister(&base->dma_memcpy);
2946failure2:
2947 dma_async_device_unregister(&base->dma_slave);
2948failure1:
2949 return err;
2950}
2951
7fb3e75e
N		 2952/* Suspend resume functionality */
2953#ifdef CONFIG_PM
2954static int dma40_pm_suspend(struct device *dev)
2955{
28c7a19d
N		 2956 struct platform_device *pdev = to_platform_device(dev);
2957 struct d40_base *base = platform_get_drvdata(pdev);
2958 int ret = 0;
7fb3e75e 2959
28c7a19d
N		 2960 if (base->lcpa_regulator)
2961 ret = regulator_disable(base->lcpa_regulator);
2962 return ret;
7fb3e75e
N		 2963}
2964
2965static int dma40_runtime_suspend(struct device *dev)
2966{
2967 struct platform_device *pdev = to_platform_device(dev);
2968 struct d40_base *base = platform_get_drvdata(pdev);
2969
2970 d40_save_restore_registers(base, true);
2971
2972 /* Don't disable/enable clocks for v1 due to HW bugs */
2973 if (base->rev != 1)
2974 writel_relaxed(base->gcc_pwr_off_mask,
2975 base->virtbase + D40_DREG_GCC);
2976
2977 return 0;
2978}
2979
2980static int dma40_runtime_resume(struct device *dev)
2981{
2982 struct platform_device *pdev = to_platform_device(dev);
2983 struct d40_base *base = platform_get_drvdata(pdev);
2984
2985 if (base->initialized)
2986 d40_save_restore_registers(base, false);
2987
2988 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
2989 base->virtbase + D40_DREG_GCC);
2990 return 0;
2991}
2992
28c7a19d
N		 2993static int dma40_resume(struct device *dev)
2994{
2995 struct platform_device *pdev = to_platform_device(dev);
2996 struct d40_base *base = platform_get_drvdata(pdev);
2997 int ret = 0;
2998
2999 if (base->lcpa_regulator)
3000 ret = regulator_enable(base->lcpa_regulator);
3001
3002 return ret;
3003}
7fb3e75e
N		 3004
3005static const struct dev_pm_ops dma40_pm_ops = {
3006 .suspend = dma40_pm_suspend,
3007 .runtime_suspend = dma40_runtime_suspend,
3008 .runtime_resume = dma40_runtime_resume,
28c7a19d 3009 .resume = dma40_resume,
7fb3e75e
N		 3010};
3011#define DMA40_PM_OPS (&dma40_pm_ops)
3012#else
3013#define DMA40_PM_OPS NULL
3014#endif
3015
8d318a50
LW		 3016/* Initialization functions. */
3017
3018static int __init d40_phy_res_init(struct d40_base *base)
3019{
3020 int i;
3021 int num_phy_chans_avail = 0;
3022 u32 val[2];
3023 int odd_even_bit = -2;
7fb3e75e 3024 int gcc = D40_DREG_GCC_ENA;
8d318a50
LW		 3025
3026 val[0] = readl(base->virtbase + D40_DREG_PRSME);
3027 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3028
3029 for (i = 0; i < base->num_phy_chans; i++) {
3030 base->phy_res[i].num = i;
3031 odd_even_bit += 2 * ((i % 2) == 0);
3032 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
3033 /* Mark security only channels as occupied */
3034 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
3035 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 3036 base->phy_res[i].reserved = true;
3037 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3038 D40_DREG_GCC_SRC);
3039 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3040 D40_DREG_GCC_DST);
3041
3042
8d318a50
LW		 3043 } else {
3044 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
3045 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
7fb3e75e 3046 base->phy_res[i].reserved = false;
8d318a50
LW		 3047 num_phy_chans_avail++;
3048 }
3049 spin_lock_init(&base->phy_res[i].lock);
3050 }
6b7acd84
JA		 3051
3052 /* Mark disabled channels as occupied */
3053 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 3054 int chan = base->plat_data->disabled_channels[i];
3055
3056 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
3057 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 3058 base->phy_res[chan].reserved = true;
3059 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3060 D40_DREG_GCC_SRC);
3061 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3062 D40_DREG_GCC_DST);
f57b407c 3063 num_phy_chans_avail--;
6b7acd84
JA		 3064 }
3065
8d318a50
LW		 3066 dev_info(base->dev, "%d of %d physical DMA channels available\n",
3067 num_phy_chans_avail, base->num_phy_chans);
3068
3069 /* Verify settings extended vs standard */
3070 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3071
3072 for (i = 0; i < base->num_phy_chans; i++) {
3073
3074 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
3075 (val[0] & 0x3) != 1)
3076 dev_info(base->dev,
3077 "[%s] INFO: channel %d is misconfigured (%d)\n",
3078 __func__, i, val[0] & 0x3);
3079
3080 val[0] = val[0] >> 2;
3081 }
3082
7fb3e75e
N		 3083 /*
3084 * To keep things simple, Enable all clocks initially.
3085 * The clocks will get managed later post channel allocation.
3086 * The clocks for the event lines on which reserved channels exists
3087 * are not managed here.
3088 */
3089 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3090 base->gcc_pwr_off_mask = gcc;
3091
8d318a50
LW		 3092 return num_phy_chans_avail;
3093}
3094
3095static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3096{
8d318a50
LW		 3097 struct stedma40_platform_data *plat_data;
3098 struct clk *clk = NULL;
3099 void __iomem *virtbase = NULL;
3100 struct resource *res = NULL;
3101 struct d40_base *base = NULL;
3102 int num_log_chans = 0;
3103 int num_phy_chans;
b707c658 3104 int clk_ret = -EINVAL;
8d318a50 3105 int i;
f4b89764
LW		 3106 u32 pid;
3107 u32 cid;
3108 u8 rev;
8d318a50
LW		 3109
3110 clk = clk_get(&pdev->dev, NULL);
8d318a50 3111 if (IS_ERR(clk)) {
6db5a8ba 3112 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 3113 goto failure;
3114 }
3115
b707c658
UH		 3116 clk_ret = clk_prepare_enable(clk);
3117 if (clk_ret) {
3118 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
3119 goto failure;
3120 }
8d318a50
LW		 3121
3122 /* Get IO for DMAC base address */
3123 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3124 if (!res)
3125 goto failure;
3126
3127 if (request_mem_region(res->start, resource_size(res),
3128 D40_NAME " I/O base") == NULL)
3129 goto failure;
3130
3131 virtbase = ioremap(res->start, resource_size(res));
3132 if (!virtbase)
3133 goto failure;
3134
f4b89764
LW		 3135 /* This is just a regular AMBA PrimeCell ID actually */
3136 for (pid = 0, i = 0; i < 4; i++)
3137 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3138 & 255) << (i * 8);
3139 for (cid = 0, i = 0; i < 4; i++)
3140 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3141 & 255) << (i * 8);
8d318a50 3142
f4b89764
LW		 3143 if (cid != AMBA_CID) {
3144 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
3145 goto failure;
3146 }
3147 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
6db5a8ba 3148 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
f4b89764
LW		 3149 AMBA_MANF_BITS(pid),
3150 AMBA_VENDOR_ST);
8d318a50
LW		 3151 goto failure;
3152 }
f4b89764
LW		 3153 /*
3154 * HW revision:
3155 * DB8500ed has revision 0
3156 * ? has revision 1
3157 * DB8500v1 has revision 2
3158 * DB8500v2 has revision 3
47db92f4
GB		 3159 * AP9540v1 has revision 4
3160 * DB8540v1 has revision 4
f4b89764
LW		 3161 */
3162 rev = AMBA_REV_BITS(pid);
3ae0267f 3163
47db92f4
GB		 3164 plat_data = pdev->dev.platform_data;
3165
8d318a50 3166 /* The number of physical channels on this HW */
47db92f4
GB		 3167 if (plat_data->num_of_phy_chans)
3168 num_phy_chans = plat_data->num_of_phy_chans;
3169 else
3170 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
8d318a50 3171
47db92f4
GB		 3172 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x with %d physical channels\n",
3173 rev, res->start, num_phy_chans);
8d318a50 3174
1bdae6f4
N		 3175 if (rev < 2) {
3176 d40_err(&pdev->dev, "hardware revision: %d is not supported",
3177 rev);
3178 goto failure;
3179 }
3180
8d318a50
LW		 3181 /* Count the number of logical channels in use */
3182 for (i = 0; i < plat_data->dev_len; i++)
3183 if (plat_data->dev_rx[i] != 0)
3184 num_log_chans++;
3185
3186 for (i = 0; i < plat_data->dev_len; i++)
3187 if (plat_data->dev_tx[i] != 0)
3188 num_log_chans++;
3189
3190 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3191 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
3192 sizeof(struct d40_chan), GFP_KERNEL);
3193
3194 if (base == NULL) {
6db5a8ba 3195 d40_err(&pdev->dev, "Out of memory\n");
8d318a50
LW		 3196 goto failure;
3197 }
3198
3ae0267f 3199 base->rev = rev;
8d318a50
LW		 3200 base->clk = clk;
3201 base->num_phy_chans = num_phy_chans;
3202 base->num_log_chans = num_log_chans;
3203 base->phy_start = res->start;
3204 base->phy_size = resource_size(res);
3205 base->virtbase = virtbase;
3206 base->plat_data = plat_data;
3207 base->dev = &pdev->dev;
3208 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3209 base->log_chans = &base->phy_chans[num_phy_chans];
3210
3cb645dc
TL		 3211 if (base->plat_data->num_of_phy_chans == 14) {
3212 base->gen_dmac.backup = d40_backup_regs_v4b;
3213 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3214 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3215 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3216 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3217 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3218 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3219 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3220 base->gen_dmac.il = il_v4b;
3221 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3222 base->gen_dmac.init_reg = dma_init_reg_v4b;
3223 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3224 } else {
3225 if (base->rev >= 3) {
3226 base->gen_dmac.backup = d40_backup_regs_v4a;
3227 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3228 }
3229 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3230 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3231 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3232 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3233 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3234 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3235 base->gen_dmac.il = il_v4a;
3236 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3237 base->gen_dmac.init_reg = dma_init_reg_v4a;
3238 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3239 }
3240
8d318a50
LW		 3241 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
3242 GFP_KERNEL);
3243 if (!base->phy_res)
3244 goto failure;
3245
3246 base->lookup_phy_chans = kzalloc(num_phy_chans *
3247 sizeof(struct d40_chan *),
3248 GFP_KERNEL);
3249 if (!base->lookup_phy_chans)
3250 goto failure;
3251
3252 if (num_log_chans + plat_data->memcpy_len) {
3253 /*
3254 * The max number of logical channels are event lines for all
3255 * src devices and dst devices
3256 */
3257 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
3258 sizeof(struct d40_chan *),
3259 GFP_KERNEL);
3260 if (!base->lookup_log_chans)
3261 goto failure;
3262 }
698e4732 3263
7fb3e75e
N		 3264 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3265 sizeof(d40_backup_regs_chan),
8d318a50 3266 GFP_KERNEL);
7fb3e75e
N		 3267 if (!base->reg_val_backup_chan)
3268 goto failure;
3269
3270 base->lcla_pool.alloc_map =
3271 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
3272 * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
8d318a50
LW		 3273 if (!base->lcla_pool.alloc_map)
3274 goto failure;
3275
c675b1b4
JA		 3276 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3277 0, SLAB_HWCACHE_ALIGN,
3278 NULL);
3279 if (base->desc_slab == NULL)
3280 goto failure;
3281
8d318a50
LW		 3282 return base;
3283
3284failure:
b707c658
UH		 3285 if (!clk_ret)
3286 clk_disable_unprepare(clk);
3287 if (!IS_ERR(clk))
8d318a50 3288 clk_put(clk);
8d318a50
LW		 3289 if (virtbase)
3290 iounmap(virtbase);
3291 if (res)
3292 release_mem_region(res->start,
3293 resource_size(res));
3294 if (virtbase)
3295 iounmap(virtbase);
3296
3297 if (base) {
3298 kfree(base->lcla_pool.alloc_map);
1bdae6f4 3299 kfree(base->reg_val_backup_chan);
8d318a50
LW		 3300 kfree(base->lookup_log_chans);
3301 kfree(base->lookup_phy_chans);
3302 kfree(base->phy_res);
3303 kfree(base);
3304 }
3305
3306 return NULL;
3307}
3308
3309static void __init d40_hw_init(struct d40_base *base)
3310{
3311
8d318a50
LW		 3312 int i;
3313 u32 prmseo[2] = {0, 0};
3314 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3315 u32 pcmis = 0;
3316 u32 pcicr = 0;
3cb645dc
TL		 3317 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3318 u32 reg_size = base->gen_dmac.init_reg_size;
8d318a50 3319
3cb645dc 3320 for (i = 0; i < reg_size; i++)
8d318a50
LW		 3321 writel(dma_init_reg[i].val,
3322 base->virtbase + dma_init_reg[i].reg);
3323
3324 /* Configure all our dma channels to default settings */
3325 for (i = 0; i < base->num_phy_chans; i++) {
3326
3327 activeo[i % 2] = activeo[i % 2] << 2;
3328
3329 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3330 == D40_ALLOC_PHY) {
3331 activeo[i % 2] |= 3;
3332 continue;
3333 }
3334
3335 /* Enable interrupt # */
3336 pcmis = (pcmis << 1) | 1;
3337
3338 /* Clear interrupt # */
3339 pcicr = (pcicr << 1) | 1;
3340
3341 /* Set channel to physical mode */
3342 prmseo[i % 2] = prmseo[i % 2] << 2;
3343 prmseo[i % 2] |= 1;
3344
3345 }
3346
3347 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3348 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3349 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3350 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3351
3352 /* Write which interrupt to enable */
3cb645dc 3353 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
8d318a50
LW		 3354
3355 /* Write which interrupt to clear */
3cb645dc 3356 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
8d318a50 3357
3cb645dc
TL		 3358 /* These are __initdata and cannot be accessed after init */
3359 base->gen_dmac.init_reg = NULL;
3360 base->gen_dmac.init_reg_size = 0;
8d318a50
LW		 3361}
3362
508849ad
LW		 3363static int __init d40_lcla_allocate(struct d40_base *base)
3364{
026cbc42 3365 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 3366 unsigned long *page_list;
3367 int i, j;
3368 int ret = 0;
3369
3370 /*
3371 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3372 * To full fill this hardware requirement without wasting 256 kb
3373 * we allocate pages until we get an aligned one.
3374 */
3375 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3376 GFP_KERNEL);
3377
3378 if (!page_list) {
3379 ret = -ENOMEM;
3380 goto failure;
3381 }
3382
3383 /* Calculating how many pages that are required */
3384 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3385
3386 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3387 page_list[i] = __get_free_pages(GFP_KERNEL,
3388 base->lcla_pool.pages);
3389 if (!page_list[i]) {
3390
6db5a8ba
RV		 3391 d40_err(base->dev, "Failed to allocate %d pages.\n",
3392 base->lcla_pool.pages);
508849ad
LW		 3393
3394 for (j = 0; j < i; j++)
3395 free_pages(page_list[j], base->lcla_pool.pages);
3396 goto failure;
3397 }
3398
3399 if ((virt_to_phys((void *)page_list[i]) &
3400 (LCLA_ALIGNMENT - 1)) == 0)
3401 break;
3402 }
3403
3404 for (j = 0; j < i; j++)
3405 free_pages(page_list[j], base->lcla_pool.pages);
3406
3407 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3408 base->lcla_pool.base = (void *)page_list[i];
3409 } else {
767a9675
JA		 3410 /*
3411 * After many attempts and no succees with finding the correct
3412 * alignment, try with allocating a big buffer.
3413 */
508849ad
LW		 3414 dev_warn(base->dev,
3415 "[%s] Failed to get %d pages @ 18 bit align.\n",
3416 __func__, base->lcla_pool.pages);
3417 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3418 base->num_phy_chans +
3419 LCLA_ALIGNMENT,
3420 GFP_KERNEL);
3421 if (!base->lcla_pool.base_unaligned) {
3422 ret = -ENOMEM;
3423 goto failure;
3424 }
3425
3426 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3427 LCLA_ALIGNMENT);
3428 }
3429
026cbc42
RV		 3430 pool->dma_addr = dma_map_single(base->dev, pool->base,
3431 SZ_1K * base->num_phy_chans,
3432 DMA_TO_DEVICE);
3433 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3434 pool->dma_addr = 0;
3435 ret = -ENOMEM;
3436 goto failure;
3437 }
3438
508849ad
LW		 3439 writel(virt_to_phys(base->lcla_pool.base),
3440 base->virtbase + D40_DREG_LCLA);
3441failure:
3442 kfree(page_list);
3443 return ret;
3444}
3445
8d318a50
LW		 3446static int __init d40_probe(struct platform_device *pdev)
3447{
3448 int err;
3449 int ret = -ENOENT;
3450 struct d40_base *base;
3451 struct resource *res = NULL;
3452 int num_reserved_chans;
3453 u32 val;
3454
3455 base = d40_hw_detect_init(pdev);
3456
3457 if (!base)
3458 goto failure;
3459
3460 num_reserved_chans = d40_phy_res_init(base);
3461
3462 platform_set_drvdata(pdev, base);
3463
3464 spin_lock_init(&base->interrupt_lock);
3465 spin_lock_init(&base->execmd_lock);
3466
3467 /* Get IO for logical channel parameter address */
3468 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3469 if (!res) {
3470 ret = -ENOENT;
6db5a8ba 3471 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 3472 goto failure;
3473 }
3474 base->lcpa_size = resource_size(res);
3475 base->phy_lcpa = res->start;
3476
3477 if (request_mem_region(res->start, resource_size(res),
3478 D40_NAME " I/O lcpa") == NULL) {
3479 ret = -EBUSY;
6db5a8ba
RV		 3480 d40_err(&pdev->dev,
3481 "Failed to request LCPA region 0x%x-0x%x\n",
3482 res->start, res->end);
8d318a50
LW		 3483 goto failure;
3484 }
3485
3486 /* We make use of ESRAM memory for this. */
3487 val = readl(base->virtbase + D40_DREG_LCPA);
3488 if (res->start != val && val != 0) {
3489 dev_warn(&pdev->dev,
3490 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
3491 __func__, val, res->start);
3492 } else
3493 writel(res->start, base->virtbase + D40_DREG_LCPA);
3494
3495 base->lcpa_base = ioremap(res->start, resource_size(res));
3496 if (!base->lcpa_base) {
3497 ret = -ENOMEM;
6db5a8ba 3498 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 3499 goto failure;
3500 }
28c7a19d
N		 3501 /* If lcla has to be located in ESRAM we don't need to allocate */
3502 if (base->plat_data->use_esram_lcla) {
3503 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3504 "lcla_esram");
3505 if (!res) {
3506 ret = -ENOENT;
3507 d40_err(&pdev->dev,
3508 "No \"lcla_esram\" memory resource\n");
3509 goto failure;
3510 }
3511 base->lcla_pool.base = ioremap(res->start,
3512 resource_size(res));
3513 if (!base->lcla_pool.base) {
3514 ret = -ENOMEM;
3515 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3516 goto failure;
3517 }
3518 writel(res->start, base->virtbase + D40_DREG_LCLA);
8d318a50 3519
28c7a19d
N		 3520 } else {
3521 ret = d40_lcla_allocate(base);
3522 if (ret) {
3523 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3524 goto failure;
3525 }
8d318a50
LW		 3526 }
3527
3528 spin_lock_init(&base->lcla_pool.lock);
3529
8d318a50
LW		 3530 base->irq = platform_get_irq(pdev, 0);
3531
3532 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 3533 if (ret) {
6db5a8ba 3534 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 3535 goto failure;
3536 }
3537
7fb3e75e
N		 3538 pm_runtime_irq_safe(base->dev);
3539 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3540 pm_runtime_use_autosuspend(base->dev);
3541 pm_runtime_enable(base->dev);
3542 pm_runtime_resume(base->dev);
28c7a19d
N		 3543
3544 if (base->plat_data->use_esram_lcla) {
3545
3546 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3547 if (IS_ERR(base->lcpa_regulator)) {
3548 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3549 base->lcpa_regulator = NULL;
3550 goto failure;
3551 }
3552
3553 ret = regulator_enable(base->lcpa_regulator);
3554 if (ret) {
3555 d40_err(&pdev->dev,
3556 "Failed to enable lcpa_regulator\n");
3557 regulator_put(base->lcpa_regulator);
3558 base->lcpa_regulator = NULL;
3559 goto failure;
3560 }
3561 }
3562
7fb3e75e 3563 base->initialized = true;
8d318a50
LW		 3564 err = d40_dmaengine_init(base, num_reserved_chans);
3565 if (err)
3566 goto failure;
3567
b96710e5
PF		 3568 base->dev->dma_parms = &base->dma_parms;
3569 err = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3570 if (err) {
3571 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3572 goto failure;
3573 }
3574
8d318a50
LW		 3575 d40_hw_init(base);
3576
3577 dev_info(base->dev, "initialized\n");
3578 return 0;
3579
3580failure:
3581 if (base) {
c675b1b4
JA		 3582 if (base->desc_slab)
3583 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 3584 if (base->virtbase)
3585 iounmap(base->virtbase);
026cbc42 3586
28c7a19d
N		 3587 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3588 iounmap(base->lcla_pool.base);
3589 base->lcla_pool.base = NULL;
3590 }
3591
026cbc42
RV		 3592 if (base->lcla_pool.dma_addr)
3593 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3594 SZ_1K * base->num_phy_chans,
3595 DMA_TO_DEVICE);
3596
508849ad
LW		 3597 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3598 free_pages((unsigned long)base->lcla_pool.base,
3599 base->lcla_pool.pages);
767a9675
JA		 3600
3601 kfree(base->lcla_pool.base_unaligned);
3602
8d318a50
LW		 3603 if (base->phy_lcpa)
3604 release_mem_region(base->phy_lcpa,
3605 base->lcpa_size);
3606 if (base->phy_start)
3607 release_mem_region(base->phy_start,
3608 base->phy_size);
3609 if (base->clk) {
3610 clk_disable(base->clk);
3611 clk_put(base->clk);
3612 }
3613
28c7a19d
N		 3614 if (base->lcpa_regulator) {
3615 regulator_disable(base->lcpa_regulator);
3616 regulator_put(base->lcpa_regulator);
3617 }
3618
8d318a50
LW		 3619 kfree(base->lcla_pool.alloc_map);
3620 kfree(base->lookup_log_chans);
3621 kfree(base->lookup_phy_chans);
3622 kfree(base->phy_res);
3623 kfree(base);
3624 }
3625
6db5a8ba 3626 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 3627 return ret;
3628}
3629
3630static struct platform_driver d40_driver = {
3631 .driver = {
3632 .owner = THIS_MODULE,
3633 .name = D40_NAME,
7fb3e75e 3634 .pm = DMA40_PM_OPS,
8d318a50
LW		 3635 },
3636};
3637
cb9ab2d8 3638static int __init stedma40_init(void)
8d318a50
LW		 3639{
3640 return platform_driver_probe(&d40_driver, d40_probe);
3641}
a0eb221a 3642subsys_initcall(stedma40_init);
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