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dma40: remove "hardware link with previous jobs" code
[mirror_ubuntu-bionic-kernel.git] / drivers / dma / ste_dma40.c
CommitLineData
8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
9#include <linux/kernel.h>
10#include <linux/slab.h>
11#include <linux/dmaengine.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
698e4732 15#include <linux/err.h>
8d318a50
LW		 16
17#include <plat/ste_dma40.h>
18
19#include "ste_dma40_ll.h"
20
21#define D40_NAME "dma40"
22
23#define D40_PHY_CHAN -1
24
25/* For masking out/in 2 bit channel positions */
26#define D40_CHAN_POS(chan) (2 * (chan / 2))
27#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
28
29/* Maximum iterations taken before giving up suspending a channel */
30#define D40_SUSPEND_MAX_IT 500
31
508849ad
LW		 32/* Hardware requirement on LCLA alignment */
33#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 34
35/* Max number of links per event group */
36#define D40_LCLA_LINK_PER_EVENT_GRP 128
37#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
38
508849ad
LW		 39/* Attempts before giving up to trying to get pages that are aligned */
40#define MAX_LCLA_ALLOC_ATTEMPTS 256
41
42/* Bit markings for allocation map */
8d318a50
LW		 43#define D40_ALLOC_FREE (1 << 31)
44#define D40_ALLOC_PHY (1 << 30)
45#define D40_ALLOC_LOG_FREE 0
46
8d318a50 47/* Hardware designer of the block */
3ae0267f 48#define D40_HW_DESIGNER 0x8
8d318a50
LW		 49
50/**
51 * enum 40_command - The different commands and/or statuses.
52 *
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 */
58enum d40_command {
59 D40_DMA_STOP = 0,
60 D40_DMA_RUN = 1,
61 D40_DMA_SUSPEND_REQ = 2,
62 D40_DMA_SUSPENDED = 3
63};
64
65/**
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
67 *
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
71 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
72 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
73 * one buffer to one buffer.
74 */
75struct d40_lli_pool {
76 void *base;
508849ad 77 int size;
8d318a50 78 /* Space for dst and src, plus an extra for padding */
508849ad 79 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 80};
81
82/**
83 * struct d40_desc - A descriptor is one DMA job.
84 *
85 * @lli_phy: LLI settings for physical channel. Both src and dst=
86 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
87 * lli_len equals one.
88 * @lli_log: Same as above but for logical channels.
89 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 90 * @lli_len: Number of llis of current descriptor.
698e4732
JA		 91 * @lli_current: Number of transfered llis.
92 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 93 * @txd: DMA engine struct. Used for among other things for communication
94 * during a transfer.
95 * @node: List entry.
8d318a50 96 * @is_in_client_list: true if the client owns this descriptor.
aa182ae2 97 * the previous one.
8d318a50
LW		 98 *
99 * This descriptor is used for both logical and physical transfers.
100 */
8d318a50
LW		 101struct d40_desc {
102 /* LLI physical */
103 struct d40_phy_lli_bidir lli_phy;
104 /* LLI logical */
105 struct d40_log_lli_bidir lli_log;
106
107 struct d40_lli_pool lli_pool;
941b77a3 108 int lli_len;
698e4732
JA		 109 int lli_current;
110 int lcla_alloc;
8d318a50
LW		 111
112 struct dma_async_tx_descriptor txd;
113 struct list_head node;
114
8d318a50
LW		 115 bool is_in_client_list;
116};
117
118/**
119 * struct d40_lcla_pool - LCLA pool settings and data.
120 *
508849ad
LW		 121 * @base: The virtual address of LCLA. 18 bit aligned.
122 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
123 * This pointer is only there for clean-up on error.
124 * @pages: The number of pages needed for all physical channels.
125 * Only used later for clean-up on error
8d318a50 126 * @lock: Lock to protect the content in this struct.
698e4732 127 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 128 */
129struct d40_lcla_pool {
130 void *base;
508849ad
LW		 131 void *base_unaligned;
132 int pages;
8d318a50 133 spinlock_t lock;
698e4732 134 struct d40_desc **alloc_map;
8d318a50
LW		 135};
136
137/**
138 * struct d40_phy_res - struct for handling eventlines mapped to physical
139 * channels.
140 *
141 * @lock: A lock protection this entity.
142 * @num: The physical channel number of this entity.
143 * @allocated_src: Bit mapped to show which src event line's are mapped to
144 * this physical channel. Can also be free or physically allocated.
145 * @allocated_dst: Same as for src but is dst.
146 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 147 * event line number.
8d318a50
LW		 148 */
149struct d40_phy_res {
150 spinlock_t lock;
151 int num;
152 u32 allocated_src;
153 u32 allocated_dst;
154};
155
156struct d40_base;
157
158/**
159 * struct d40_chan - Struct that describes a channel.
160 *
161 * @lock: A spinlock to protect this struct.
162 * @log_num: The logical number, if any of this channel.
163 * @completed: Starts with 1, after first interrupt it is set to dma engine's
164 * current cookie.
165 * @pending_tx: The number of pending transfers. Used between interrupt handler
166 * and tasklet.
167 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 168 * @phy_chan: Pointer to physical channel which this instance runs on. If this
169 * point is NULL, then the channel is not allocated.
8d318a50
LW		 170 * @chan: DMA engine handle.
171 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
172 * transfer and call client callback.
173 * @client: Cliented owned descriptor list.
174 * @active: Active descriptor.
175 * @queue: Queued jobs.
8d318a50 176 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 177 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 178 * @base: Pointer to the device instance struct.
179 * @src_def_cfg: Default cfg register setting for src.
180 * @dst_def_cfg: Default cfg register setting for dst.
181 * @log_def: Default logical channel settings.
182 * @lcla: Space for one dst src pair for logical channel transfers.
183 * @lcpa: Pointer to dst and src lcpa settings.
184 *
185 * This struct can either "be" a logical or a physical channel.
186 */
187struct d40_chan {
188 spinlock_t lock;
189 int log_num;
190 /* ID of the most recent completed transfer */
191 int completed;
192 int pending_tx;
193 bool busy;
194 struct d40_phy_res *phy_chan;
195 struct dma_chan chan;
196 struct tasklet_struct tasklet;
197 struct list_head client;
198 struct list_head active;
199 struct list_head queue;
8d318a50 200 struct stedma40_chan_cfg dma_cfg;
ce2ca125 201 bool configured;
8d318a50
LW		 202 struct d40_base *base;
203 /* Default register configurations */
204 u32 src_def_cfg;
205 u32 dst_def_cfg;
206 struct d40_def_lcsp log_def;
8d318a50 207 struct d40_log_lli_full *lcpa;
95e1400f
LW		 208 /* Runtime reconfiguration */
209 dma_addr_t runtime_addr;
210 enum dma_data_direction runtime_direction;
8d318a50
LW		 211};
212
213/**
214 * struct d40_base - The big global struct, one for each probe'd instance.
215 *
216 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
217 * @execmd_lock: Lock for execute command usage since several channels share
218 * the same physical register.
219 * @dev: The device structure.
220 * @virtbase: The virtual base address of the DMA's register.
f4185592 221 * @rev: silicon revision detected.
8d318a50
LW		 222 * @clk: Pointer to the DMA clock structure.
223 * @phy_start: Physical memory start of the DMA registers.
224 * @phy_size: Size of the DMA register map.
225 * @irq: The IRQ number.
226 * @num_phy_chans: The number of physical channels. Read from HW. This
227 * is the number of available channels for this driver, not counting "Secure
228 * mode" allocated physical channels.
229 * @num_log_chans: The number of logical channels. Calculated from
230 * num_phy_chans.
231 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
232 * @dma_slave: dma_device channels that can do only do slave transfers.
233 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
8d318a50
LW		 234 * @log_chans: Room for all possible logical channels in system.
235 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
236 * to log_chans entries.
237 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
238 * to phy_chans entries.
239 * @plat_data: Pointer to provided platform_data which is the driver
240 * configuration.
241 * @phy_res: Vector containing all physical channels.
242 * @lcla_pool: lcla pool settings and data.
243 * @lcpa_base: The virtual mapped address of LCPA.
244 * @phy_lcpa: The physical address of the LCPA.
245 * @lcpa_size: The size of the LCPA area.
c675b1b4 246 * @desc_slab: cache for descriptors.
8d318a50
LW		 247 */
248struct d40_base {
249 spinlock_t interrupt_lock;
250 spinlock_t execmd_lock;
251 struct device *dev;
252 void __iomem *virtbase;
f4185592 253 u8 rev:4;
8d318a50
LW		 254 struct clk *clk;
255 phys_addr_t phy_start;
256 resource_size_t phy_size;
257 int irq;
258 int num_phy_chans;
259 int num_log_chans;
260 struct dma_device dma_both;
261 struct dma_device dma_slave;
262 struct dma_device dma_memcpy;
263 struct d40_chan *phy_chans;
264 struct d40_chan *log_chans;
265 struct d40_chan **lookup_log_chans;
266 struct d40_chan **lookup_phy_chans;
267 struct stedma40_platform_data *plat_data;
268 /* Physical half channels */
269 struct d40_phy_res *phy_res;
270 struct d40_lcla_pool lcla_pool;
271 void *lcpa_base;
272 dma_addr_t phy_lcpa;
273 resource_size_t lcpa_size;
c675b1b4 274 struct kmem_cache *desc_slab;
8d318a50
LW		 275};
276
277/**
278 * struct d40_interrupt_lookup - lookup table for interrupt handler
279 *
280 * @src: Interrupt mask register.
281 * @clr: Interrupt clear register.
282 * @is_error: true if this is an error interrupt.
283 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
284 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
285 */
286struct d40_interrupt_lookup {
287 u32 src;
288 u32 clr;
289 bool is_error;
290 int offset;
291};
292
293/**
294 * struct d40_reg_val - simple lookup struct
295 *
296 * @reg: The register.
297 * @val: The value that belongs to the register in reg.
298 */
299struct d40_reg_val {
300 unsigned int reg;
301 unsigned int val;
302};
303
262d2915
RV		 304static struct device *chan2dev(struct d40_chan *d40c)
305{
306 return &d40c->chan.dev->device;
307}
308
8d318a50
LW		 309static int d40_pool_lli_alloc(struct d40_desc *d40d,
310 int lli_len, bool is_log)
311{
312 u32 align;
313 void *base;
314
315 if (is_log)
316 align = sizeof(struct d40_log_lli);
317 else
318 align = sizeof(struct d40_phy_lli);
319
320 if (lli_len == 1) {
321 base = d40d->lli_pool.pre_alloc_lli;
322 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
323 d40d->lli_pool.base = NULL;
324 } else {
325 d40d->lli_pool.size = ALIGN(lli_len * 2 * align, align);
326
327 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
328 d40d->lli_pool.base = base;
329
330 if (d40d->lli_pool.base == NULL)
331 return -ENOMEM;
332 }
333
334 if (is_log) {
335 d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base,
336 align);
337 d40d->lli_log.dst = PTR_ALIGN(d40d->lli_log.src + lli_len,
338 align);
339 } else {
340 d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base,
341 align);
342 d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len,
343 align);
8d318a50
LW		 344 }
345
346 return 0;
347}
348
349static void d40_pool_lli_free(struct d40_desc *d40d)
350{
351 kfree(d40d->lli_pool.base);
352 d40d->lli_pool.base = NULL;
353 d40d->lli_pool.size = 0;
354 d40d->lli_log.src = NULL;
355 d40d->lli_log.dst = NULL;
356 d40d->lli_phy.src = NULL;
357 d40d->lli_phy.dst = NULL;
8d318a50
LW		 358}
359
698e4732
JA		 360static int d40_lcla_alloc_one(struct d40_chan *d40c,
361 struct d40_desc *d40d)
362{
363 unsigned long flags;
364 int i;
365 int ret = -EINVAL;
366 int p;
367
368 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
369
370 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
371
372 /*
373 * Allocate both src and dst at the same time, therefore the half
374 * start on 1 since 0 can't be used since zero is used as end marker.
375 */
376 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
377 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
378 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
379 d40d->lcla_alloc++;
380 ret = i;
381 break;
382 }
383 }
384
385 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
386
387 return ret;
388}
389
390static int d40_lcla_free_all(struct d40_chan *d40c,
391 struct d40_desc *d40d)
392{
393 unsigned long flags;
394 int i;
395 int ret = -EINVAL;
396
397 if (d40c->log_num == D40_PHY_CHAN)
398 return 0;
399
400 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
401
402 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
403 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
404 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
405 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
406 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
407 d40d->lcla_alloc--;
408 if (d40d->lcla_alloc == 0) {
409 ret = 0;
410 break;
411 }
412 }
413 }
414
415 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
416
417 return ret;
418
419}
420
8d318a50
LW		 421static void d40_desc_remove(struct d40_desc *d40d)
422{
423 list_del(&d40d->node);
424}
425
426static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
427{
a2c15fa4 428 struct d40_desc *desc = NULL;
8d318a50
LW		 429
430 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 431 struct d40_desc *d;
432 struct d40_desc *_d;
433
8d318a50
LW		 434 list_for_each_entry_safe(d, _d, &d40c->client, node)
435 if (async_tx_test_ack(&d->txd)) {
436 d40_pool_lli_free(d);
437 d40_desc_remove(d);
a2c15fa4
RV		 438 desc = d;
439 memset(desc, 0, sizeof(*desc));
c675b1b4 440 break;
8d318a50 441 }
8d318a50 442 }
a2c15fa4
RV		 443
444 if (!desc)
445 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
446
447 if (desc)
448 INIT_LIST_HEAD(&desc->node);
449
450 return desc;
8d318a50
LW		 451}
452
453static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
454{
698e4732
JA		 455
456 d40_lcla_free_all(d40c, d40d);
c675b1b4 457 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 458}
459
460static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
461{
462 list_add_tail(&desc->node, &d40c->active);
463}
464
698e4732
JA		 465static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
466{
467 int curr_lcla = -EINVAL, next_lcla;
468
469 if (d40c->log_num == D40_PHY_CHAN) {
470 d40_phy_lli_write(d40c->base->virtbase,
471 d40c->phy_chan->num,
472 d40d->lli_phy.dst,
473 d40d->lli_phy.src);
474 d40d->lli_current = d40d->lli_len;
475 } else {
476
477 if ((d40d->lli_len - d40d->lli_current) > 1)
478 curr_lcla = d40_lcla_alloc_one(d40c, d40d);
479
480 d40_log_lli_lcpa_write(d40c->lcpa,
481 &d40d->lli_log.dst[d40d->lli_current],
482 &d40d->lli_log.src[d40d->lli_current],
483 curr_lcla);
484
485 d40d->lli_current++;
486 for (; d40d->lli_current < d40d->lli_len; d40d->lli_current++) {
487 struct d40_log_lli *lcla;
488
489 if (d40d->lli_current + 1 < d40d->lli_len)
490 next_lcla = d40_lcla_alloc_one(d40c, d40d);
491 else
492 next_lcla = -EINVAL;
493
494 lcla = d40c->base->lcla_pool.base +
495 d40c->phy_chan->num * 1024 +
496 8 * curr_lcla * 2;
497
498 d40_log_lli_lcla_write(lcla,
499 &d40d->lli_log.dst[d40d->lli_current],
500 &d40d->lli_log.src[d40d->lli_current],
501 next_lcla);
502
503 (void) dma_map_single(d40c->base->dev, lcla,
504 2 * sizeof(struct d40_log_lli),
505 DMA_TO_DEVICE);
506
507 curr_lcla = next_lcla;
508
509 if (curr_lcla == -EINVAL) {
510 d40d->lli_current++;
511 break;
512 }
513
514 }
515 }
516}
517
8d318a50
LW		 518static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
519{
520 struct d40_desc *d;
521
522 if (list_empty(&d40c->active))
523 return NULL;
524
525 d = list_first_entry(&d40c->active,
526 struct d40_desc,
527 node);
528 return d;
529}
530
531static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
532{
533 list_add_tail(&desc->node, &d40c->queue);
534}
535
536static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
537{
538 struct d40_desc *d;
539
540 if (list_empty(&d40c->queue))
541 return NULL;
542
543 d = list_first_entry(&d40c->queue,
544 struct d40_desc,
545 node);
546 return d;
547}
548
d49278e3
PF		 549static int d40_psize_2_burst_size(bool is_log, int psize)
550{
551 if (is_log) {
552 if (psize == STEDMA40_PSIZE_LOG_1)
553 return 1;
554 } else {
555 if (psize == STEDMA40_PSIZE_PHY_1)
556 return 1;
557 }
558
559 return 2 << psize;
560}
561
562/*
563 * The dma only supports transmitting packages up to
564 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
565 * dma elements required to send the entire sg list
566 */
567static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
568{
569 int dmalen;
570 u32 max_w = max(data_width1, data_width2);
571 u32 min_w = min(data_width1, data_width2);
572 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
573
574 if (seg_max > STEDMA40_MAX_SEG_SIZE)
575 seg_max -= (1 << max_w);
576
577 if (!IS_ALIGNED(size, 1 << max_w))
578 return -EINVAL;
579
580 if (size <= seg_max)
581 dmalen = 1;
582 else {
583 dmalen = size / seg_max;
584 if (dmalen * seg_max < size)
585 dmalen++;
586 }
587 return dmalen;
588}
589
590static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
591 u32 data_width1, u32 data_width2)
592{
593 struct scatterlist *sg;
594 int i;
595 int len = 0;
596 int ret;
597
598 for_each_sg(sgl, sg, sg_len, i) {
599 ret = d40_size_2_dmalen(sg_dma_len(sg),
600 data_width1, data_width2);
601 if (ret < 0)
602 return ret;
603 len += ret;
604 }
605 return len;
606}
8d318a50 607
d49278e3 608/* Support functions for logical channels */
8d318a50
LW		 609
610static int d40_channel_execute_command(struct d40_chan *d40c,
611 enum d40_command command)
612{
767a9675
JA		 613 u32 status;
614 int i;
8d318a50
LW		 615 void __iomem *active_reg;
616 int ret = 0;
617 unsigned long flags;
1d392a7b 618 u32 wmask;
8d318a50
LW		 619
620 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
621
622 if (d40c->phy_chan->num % 2 == 0)
623 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
624 else
625 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
626
627 if (command == D40_DMA_SUSPEND_REQ) {
628 status = (readl(active_reg) &
629 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
630 D40_CHAN_POS(d40c->phy_chan->num);
631
632 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
633 goto done;
634 }
635
1d392a7b
JA		 636 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
637 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
638 active_reg);
8d318a50
LW		 639
640 if (command == D40_DMA_SUSPEND_REQ) {
641
642 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
643 status = (readl(active_reg) &
644 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
645 D40_CHAN_POS(d40c->phy_chan->num);
646
647 cpu_relax();
648 /*
649 * Reduce the number of bus accesses while
650 * waiting for the DMA to suspend.
651 */
652 udelay(3);
653
654 if (status == D40_DMA_STOP ||
655 status == D40_DMA_SUSPENDED)
656 break;
657 }
658
659 if (i == D40_SUSPEND_MAX_IT) {
660 dev_err(&d40c->chan.dev->device,
661 "[%s]: unable to suspend the chl %d (log: %d) status %x\n",
662 __func__, d40c->phy_chan->num, d40c->log_num,
663 status);
664 dump_stack();
665 ret = -EBUSY;
666 }
667
668 }
669done:
670 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
671 return ret;
672}
673
674static void d40_term_all(struct d40_chan *d40c)
675{
676 struct d40_desc *d40d;
8d318a50
LW		 677
678 /* Release active descriptors */
679 while ((d40d = d40_first_active_get(d40c))) {
680 d40_desc_remove(d40d);
8d318a50
LW		 681 d40_desc_free(d40c, d40d);
682 }
683
684 /* Release queued descriptors waiting for transfer */
685 while ((d40d = d40_first_queued(d40c))) {
686 d40_desc_remove(d40d);
8d318a50
LW		 687 d40_desc_free(d40c, d40d);
688 }
689
8d318a50
LW		 690
691 d40c->pending_tx = 0;
692 d40c->busy = false;
693}
694
262d2915
RV		 695static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
696 u32 event, int reg)
697{
698 void __iomem *addr = d40c->base->virtbase + D40_DREG_PCBASE
699 + d40c->phy_chan->num * D40_DREG_PCDELTA + reg;
700 int tries;
701
702 if (!enable) {
703 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
704 | ~D40_EVENTLINE_MASK(event), addr);
705 return;
706 }
707
708 /*
709 * The hardware sometimes doesn't register the enable when src and dst
710 * event lines are active on the same logical channel. Retry to ensure
711 * it does. Usually only one retry is sufficient.
712 */
713 tries = 100;
714 while (--tries) {
715 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
716 | ~D40_EVENTLINE_MASK(event), addr);
717
718 if (readl(addr) & D40_EVENTLINE_MASK(event))
719 break;
720 }
721
722 if (tries != 99)
723 dev_dbg(chan2dev(d40c),
724 "[%s] workaround enable S%cLNK (%d tries)\n",
725 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
726 100 - tries);
727
728 WARN_ON(!tries);
729}
730
8d318a50
LW		 731static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
732{
8d318a50
LW		 733 unsigned long flags;
734
8d318a50
LW		 735 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
736
737 /* Enable event line connected to device (or memcpy) */
738 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
739 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
740 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
741
262d2915
RV		 742 __d40_config_set_event(d40c, do_enable, event,
743 D40_CHAN_REG_SSLNK);
8d318a50 744 }
262d2915 745
8d318a50
LW		 746 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
747 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
748
262d2915
RV		 749 __d40_config_set_event(d40c, do_enable, event,
750 D40_CHAN_REG_SDLNK);
8d318a50
LW		 751 }
752
753 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
754}
755
a5ebca47 756static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 757{
be8cb7df 758 u32 val;
8d318a50 759
be8cb7df
JA		 760 val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
761 d40c->phy_chan->num * D40_DREG_PCDELTA +
762 D40_CHAN_REG_SSLNK);
763
764 val |= readl(d40c->base->virtbase + D40_DREG_PCBASE +
765 d40c->phy_chan->num * D40_DREG_PCDELTA +
766 D40_CHAN_REG_SDLNK);
a5ebca47 767 return val;
8d318a50
LW		 768}
769
20a5b6d0
RV		 770static u32 d40_get_prmo(struct d40_chan *d40c)
771{
772 static const unsigned int phy_map[] = {
773 [STEDMA40_PCHAN_BASIC_MODE]
774 = D40_DREG_PRMO_PCHAN_BASIC,
775 [STEDMA40_PCHAN_MODULO_MODE]
776 = D40_DREG_PRMO_PCHAN_MODULO,
777 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
778 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
779 };
780 static const unsigned int log_map[] = {
781 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
782 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
783 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
784 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
785 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
786 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
787 };
788
789 if (d40c->log_num == D40_PHY_CHAN)
790 return phy_map[d40c->dma_cfg.mode_opt];
791 else
792 return log_map[d40c->dma_cfg.mode_opt];
793}
794
b55912c6 795static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 796{
797 u32 addr_base;
798 u32 var;
8d318a50
LW		 799
800 /* Odd addresses are even addresses + 4 */
801 addr_base = (d40c->phy_chan->num % 2) * 4;
802 /* Setup channel mode to logical or physical */
803 var = ((u32)(d40c->log_num != D40_PHY_CHAN) + 1) <<
804 D40_CHAN_POS(d40c->phy_chan->num);
805 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
806
807 /* Setup operational mode option register */
20a5b6d0 808 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 809
810 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
811
812 if (d40c->log_num != D40_PHY_CHAN) {
813 /* Set default config for CFG reg */
814 writel(d40c->src_def_cfg,
815 d40c->base->virtbase + D40_DREG_PCBASE +
816 d40c->phy_chan->num * D40_DREG_PCDELTA +
817 D40_CHAN_REG_SSCFG);
818 writel(d40c->dst_def_cfg,
819 d40c->base->virtbase + D40_DREG_PCBASE +
820 d40c->phy_chan->num * D40_DREG_PCDELTA +
821 D40_CHAN_REG_SDCFG);
822
b55912c6
JA		 823 /* Set LIDX for lcla */
824 writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
825 D40_SREG_ELEM_LOG_LIDX_MASK,
826 d40c->base->virtbase + D40_DREG_PCBASE +
827 d40c->phy_chan->num * D40_DREG_PCDELTA +
828 D40_CHAN_REG_SDELT);
829
830 writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
831 D40_SREG_ELEM_LOG_LIDX_MASK,
832 d40c->base->virtbase + D40_DREG_PCBASE +
833 d40c->phy_chan->num * D40_DREG_PCDELTA +
834 D40_CHAN_REG_SSELT);
835
8d318a50 836 }
8d318a50
LW		 837}
838
aa182ae2
JA		 839static u32 d40_residue(struct d40_chan *d40c)
840{
841 u32 num_elt;
842
843 if (d40c->log_num != D40_PHY_CHAN)
844 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
845 >> D40_MEM_LCSP2_ECNT_POS;
846 else
847 num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE +
848 d40c->phy_chan->num * D40_DREG_PCDELTA +
849 D40_CHAN_REG_SDELT) &
850 D40_SREG_ELEM_PHY_ECNT_MASK) >>
851 D40_SREG_ELEM_PHY_ECNT_POS;
852 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
853}
854
855static bool d40_tx_is_linked(struct d40_chan *d40c)
856{
857 bool is_link;
858
859 if (d40c->log_num != D40_PHY_CHAN)
860 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
861 else
862 is_link = readl(d40c->base->virtbase + D40_DREG_PCBASE +
863 d40c->phy_chan->num * D40_DREG_PCDELTA +
864 D40_CHAN_REG_SDLNK) &
865 D40_SREG_LNK_PHYS_LNK_MASK;
866 return is_link;
867}
868
869static int d40_pause(struct dma_chan *chan)
870{
871 struct d40_chan *d40c =
872 container_of(chan, struct d40_chan, chan);
873 int res = 0;
874 unsigned long flags;
875
3ac012af
JA		 876 if (!d40c->busy)
877 return 0;
878
aa182ae2
JA		 879 spin_lock_irqsave(&d40c->lock, flags);
880
881 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
882 if (res == 0) {
883 if (d40c->log_num != D40_PHY_CHAN) {
884 d40_config_set_event(d40c, false);
885 /* Resume the other logical channels if any */
886 if (d40_chan_has_events(d40c))
887 res = d40_channel_execute_command(d40c,
888 D40_DMA_RUN);
889 }
890 }
891
892 spin_unlock_irqrestore(&d40c->lock, flags);
893 return res;
894}
895
896static int d40_resume(struct dma_chan *chan)
897{
898 struct d40_chan *d40c =
899 container_of(chan, struct d40_chan, chan);
900 int res = 0;
901 unsigned long flags;
902
3ac012af
JA		 903 if (!d40c->busy)
904 return 0;
905
aa182ae2
JA		 906 spin_lock_irqsave(&d40c->lock, flags);
907
908 if (d40c->base->rev == 0)
909 if (d40c->log_num != D40_PHY_CHAN) {
910 res = d40_channel_execute_command(d40c,
911 D40_DMA_SUSPEND_REQ);
912 goto no_suspend;
913 }
914
915 /* If bytes left to transfer or linked tx resume job */
916 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
917
918 if (d40c->log_num != D40_PHY_CHAN)
919 d40_config_set_event(d40c, true);
920
921 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
922 }
923
924no_suspend:
925 spin_unlock_irqrestore(&d40c->lock, flags);
926 return res;
927}
928
8d318a50
LW		 929static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
930{
931 struct d40_chan *d40c = container_of(tx->chan,
932 struct d40_chan,
933 chan);
934 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
935 unsigned long flags;
936
937 spin_lock_irqsave(&d40c->lock, flags);
938
aa182ae2
JA		 939 d40c->chan.cookie++;
940
941 if (d40c->chan.cookie < 0)
942 d40c->chan.cookie = 1;
943
944 d40d->txd.cookie = d40c->chan.cookie;
945
8d318a50
LW		 946 d40_desc_queue(d40c, d40d);
947
948 spin_unlock_irqrestore(&d40c->lock, flags);
949
950 return tx->cookie;
951}
952
953static int d40_start(struct d40_chan *d40c)
954{
f4185592
LW		 955 if (d40c->base->rev == 0) {
956 int err;
957
958 if (d40c->log_num != D40_PHY_CHAN) {
959 err = d40_channel_execute_command(d40c,
960 D40_DMA_SUSPEND_REQ);
961 if (err)
962 return err;
963 }
964 }
965
0c32269d 966 if (d40c->log_num != D40_PHY_CHAN)
8d318a50 967 d40_config_set_event(d40c, true);
8d318a50 968
0c32269d 969 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 970}
971
972static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
973{
974 struct d40_desc *d40d;
975 int err;
976
977 /* Start queued jobs, if any */
978 d40d = d40_first_queued(d40c);
979
980 if (d40d != NULL) {
981 d40c->busy = true;
982
983 /* Remove from queue */
984 d40_desc_remove(d40d);
985
986 /* Add to active queue */
987 d40_desc_submit(d40c, d40d);
988
7d83a854
RV		 989 /* Initiate DMA job */
990 d40_desc_load(d40c, d40d);
8d318a50 991
7d83a854
RV		 992 /* Start dma job */
993 err = d40_start(d40c);
8d318a50 994
7d83a854
RV		 995 if (err)
996 return NULL;
8d318a50
LW		 997 }
998
999 return d40d;
1000}
1001
1002/* called from interrupt context */
1003static void dma_tc_handle(struct d40_chan *d40c)
1004{
1005 struct d40_desc *d40d;
1006
8d318a50
LW		 1007 /* Get first active entry from list */
1008 d40d = d40_first_active_get(d40c);
1009
1010 if (d40d == NULL)
1011 return;
1012
698e4732 1013 d40_lcla_free_all(d40c, d40d);
8d318a50 1014
698e4732 1015 if (d40d->lli_current < d40d->lli_len) {
8d318a50
LW		 1016 d40_desc_load(d40c, d40d);
1017 /* Start dma job */
1018 (void) d40_start(d40c);
1019 return;
1020 }
1021
1022 if (d40_queue_start(d40c) == NULL)
1023 d40c->busy = false;
1024
1025 d40c->pending_tx++;
1026 tasklet_schedule(&d40c->tasklet);
1027
1028}
1029
1030static void dma_tasklet(unsigned long data)
1031{
1032 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1033 struct d40_desc *d40d;
8d318a50
LW		 1034 unsigned long flags;
1035 dma_async_tx_callback callback;
1036 void *callback_param;
1037
1038 spin_lock_irqsave(&d40c->lock, flags);
1039
1040 /* Get first active entry from list */
767a9675 1041 d40d = d40_first_active_get(d40c);
8d318a50 1042
767a9675 1043 if (d40d == NULL)
8d318a50
LW		 1044 goto err;
1045
767a9675 1046 d40c->completed = d40d->txd.cookie;
8d318a50
LW		 1047
1048 /*
1049 * If terminating a channel pending_tx is set to zero.
1050 * This prevents any finished active jobs to return to the client.
1051 */
1052 if (d40c->pending_tx == 0) {
1053 spin_unlock_irqrestore(&d40c->lock, flags);
1054 return;
1055 }
1056
1057 /* Callback to client */
767a9675
JA		 1058 callback = d40d->txd.callback;
1059 callback_param = d40d->txd.callback_param;
1060
1061 if (async_tx_test_ack(&d40d->txd)) {
1062 d40_pool_lli_free(d40d);
1063 d40_desc_remove(d40d);
1064 d40_desc_free(d40c, d40d);
8d318a50 1065 } else {
767a9675
JA		 1066 if (!d40d->is_in_client_list) {
1067 d40_desc_remove(d40d);
698e4732 1068 d40_lcla_free_all(d40c, d40d);
767a9675
JA		 1069 list_add_tail(&d40d->node, &d40c->client);
1070 d40d->is_in_client_list = true;
8d318a50
LW		 1071 }
1072 }
1073
1074 d40c->pending_tx--;
1075
1076 if (d40c->pending_tx)
1077 tasklet_schedule(&d40c->tasklet);
1078
1079 spin_unlock_irqrestore(&d40c->lock, flags);
1080
767a9675 1081 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
8d318a50
LW		 1082 callback(callback_param);
1083
1084 return;
1085
1086 err:
1087 /* Rescue manouver if receiving double interrupts */
1088 if (d40c->pending_tx > 0)
1089 d40c->pending_tx--;
1090 spin_unlock_irqrestore(&d40c->lock, flags);
1091}
1092
1093static irqreturn_t d40_handle_interrupt(int irq, void *data)
1094{
1095 static const struct d40_interrupt_lookup il[] = {
1096 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1097 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1098 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1099 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1100 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1101 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1102 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1103 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1104 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1105 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1106 };
1107
1108 int i;
1109 u32 regs[ARRAY_SIZE(il)];
8d318a50
LW		 1110 u32 idx;
1111 u32 row;
1112 long chan = -1;
1113 struct d40_chan *d40c;
1114 unsigned long flags;
1115 struct d40_base *base = data;
1116
1117 spin_lock_irqsave(&base->interrupt_lock, flags);
1118
1119 /* Read interrupt status of both logical and physical channels */
1120 for (i = 0; i < ARRAY_SIZE(il); i++)
1121 regs[i] = readl(base->virtbase + il[i].src);
1122
1123 for (;;) {
1124
1125 chan = find_next_bit((unsigned long *)regs,
1126 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1127
1128 /* No more set bits found? */
1129 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1130 break;
1131
1132 row = chan / BITS_PER_LONG;
1133 idx = chan & (BITS_PER_LONG - 1);
1134
1135 /* ACK interrupt */
1b00348d 1136 writel(1 << idx, base->virtbase + il[row].clr);
8d318a50
LW		 1137
1138 if (il[row].offset == D40_PHY_CHAN)
1139 d40c = base->lookup_phy_chans[idx];
1140 else
1141 d40c = base->lookup_log_chans[il[row].offset + idx];
1142 spin_lock(&d40c->lock);
1143
1144 if (!il[row].is_error)
1145 dma_tc_handle(d40c);
1146 else
508849ad
LW		 1147 dev_err(base->dev,
1148 "[%s] IRQ chan: %ld offset %d idx %d\n",
8d318a50
LW		 1149 __func__, chan, il[row].offset, idx);
1150
1151 spin_unlock(&d40c->lock);
1152 }
1153
1154 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1155
1156 return IRQ_HANDLED;
1157}
1158
8d318a50
LW		 1159static int d40_validate_conf(struct d40_chan *d40c,
1160 struct stedma40_chan_cfg *conf)
1161{
1162 int res = 0;
1163 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1164 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
38bdbf02 1165 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1166
0747c7ba
LW		 1167 if (!conf->dir) {
1168 dev_err(&d40c->chan.dev->device, "[%s] Invalid direction.\n",
1169 __func__);
1170 res = -EINVAL;
1171 }
1172
1173 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1174 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1175 d40c->runtime_addr == 0) {
1176
1177 dev_err(&d40c->chan.dev->device,
1178 "[%s] Invalid TX channel address (%d)\n",
1179 __func__, conf->dst_dev_type);
1180 res = -EINVAL;
1181 }
1182
1183 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1184 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1185 d40c->runtime_addr == 0) {
1186 dev_err(&d40c->chan.dev->device,
1187 "[%s] Invalid RX channel address (%d)\n",
1188 __func__, conf->src_dev_type);
1189 res = -EINVAL;
1190 }
1191
1192 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
8d318a50
LW		 1193 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
1194 dev_err(&d40c->chan.dev->device, "[%s] Invalid dst\n",
1195 __func__);
1196 res = -EINVAL;
1197 }
1198
0747c7ba 1199 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
8d318a50
LW		 1200 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1201 dev_err(&d40c->chan.dev->device, "[%s] Invalid src\n",
1202 __func__);
1203 res = -EINVAL;
1204 }
1205
1206 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1207 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1208 dev_err(&d40c->chan.dev->device,
1209 "[%s] No event line\n", __func__);
1210 res = -EINVAL;
1211 }
1212
1213 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1214 (src_event_group != dst_event_group)) {
1215 dev_err(&d40c->chan.dev->device,
1216 "[%s] Invalid event group\n", __func__);
1217 res = -EINVAL;
1218 }
1219
1220 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1221 /*
1222 * DMAC HW supports it. Will be added to this driver,
1223 * in case any dma client requires it.
1224 */
1225 dev_err(&d40c->chan.dev->device,
1226 "[%s] periph to periph not supported\n",
1227 __func__);
1228 res = -EINVAL;
1229 }
1230
d49278e3
PF		 1231 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1232 (1 << conf->src_info.data_width) !=
1233 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1234 (1 << conf->dst_info.data_width)) {
1235 /*
1236 * The DMAC hardware only supports
1237 * src (burst x width) == dst (burst x width)
1238 */
1239
1240 dev_err(&d40c->chan.dev->device,
1241 "[%s] src (burst x width) != dst (burst x width)\n",
1242 __func__);
1243 res = -EINVAL;
1244 }
1245
8d318a50
LW		 1246 return res;
1247}
1248
1249static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
4aed79b2 1250 int log_event_line, bool is_log)
8d318a50
LW		 1251{
1252 unsigned long flags;
1253 spin_lock_irqsave(&phy->lock, flags);
4aed79b2 1254 if (!is_log) {
8d318a50
LW		 1255 /* Physical interrupts are masked per physical full channel */
1256 if (phy->allocated_src == D40_ALLOC_FREE &&
1257 phy->allocated_dst == D40_ALLOC_FREE) {
1258 phy->allocated_dst = D40_ALLOC_PHY;
1259 phy->allocated_src = D40_ALLOC_PHY;
1260 goto found;
1261 } else
1262 goto not_found;
1263 }
1264
1265 /* Logical channel */
1266 if (is_src) {
1267 if (phy->allocated_src == D40_ALLOC_PHY)
1268 goto not_found;
1269
1270 if (phy->allocated_src == D40_ALLOC_FREE)
1271 phy->allocated_src = D40_ALLOC_LOG_FREE;
1272
1273 if (!(phy->allocated_src & (1 << log_event_line))) {
1274 phy->allocated_src |= 1 << log_event_line;
1275 goto found;
1276 } else
1277 goto not_found;
1278 } else {
1279 if (phy->allocated_dst == D40_ALLOC_PHY)
1280 goto not_found;
1281
1282 if (phy->allocated_dst == D40_ALLOC_FREE)
1283 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1284
1285 if (!(phy->allocated_dst & (1 << log_event_line))) {
1286 phy->allocated_dst |= 1 << log_event_line;
1287 goto found;
1288 } else
1289 goto not_found;
1290 }
1291
1292not_found:
1293 spin_unlock_irqrestore(&phy->lock, flags);
1294 return false;
1295found:
1296 spin_unlock_irqrestore(&phy->lock, flags);
1297 return true;
1298}
1299
1300static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1301 int log_event_line)
1302{
1303 unsigned long flags;
1304 bool is_free = false;
1305
1306 spin_lock_irqsave(&phy->lock, flags);
1307 if (!log_event_line) {
8d318a50
LW		 1308 phy->allocated_dst = D40_ALLOC_FREE;
1309 phy->allocated_src = D40_ALLOC_FREE;
1310 is_free = true;
1311 goto out;
1312 }
1313
1314 /* Logical channel */
1315 if (is_src) {
1316 phy->allocated_src &= ~(1 << log_event_line);
1317 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1318 phy->allocated_src = D40_ALLOC_FREE;
1319 } else {
1320 phy->allocated_dst &= ~(1 << log_event_line);
1321 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1322 phy->allocated_dst = D40_ALLOC_FREE;
1323 }
1324
1325 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1326 D40_ALLOC_FREE);
1327
1328out:
1329 spin_unlock_irqrestore(&phy->lock, flags);
1330
1331 return is_free;
1332}
1333
1334static int d40_allocate_channel(struct d40_chan *d40c)
1335{
1336 int dev_type;
1337 int event_group;
1338 int event_line;
1339 struct d40_phy_res *phys;
1340 int i;
1341 int j;
1342 int log_num;
1343 bool is_src;
38bdbf02 1344 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1345
1346 phys = d40c->base->phy_res;
1347
1348 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1349 dev_type = d40c->dma_cfg.src_dev_type;
1350 log_num = 2 * dev_type;
1351 is_src = true;
1352 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1353 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1354 /* dst event lines are used for logical memcpy */
1355 dev_type = d40c->dma_cfg.dst_dev_type;
1356 log_num = 2 * dev_type + 1;
1357 is_src = false;
1358 } else
1359 return -EINVAL;
1360
1361 event_group = D40_TYPE_TO_GROUP(dev_type);
1362 event_line = D40_TYPE_TO_EVENT(dev_type);
1363
1364 if (!is_log) {
1365 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1366 /* Find physical half channel */
1367 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1368
4aed79b2
MM		 1369 if (d40_alloc_mask_set(&phys[i], is_src,
1370 0, is_log))
8d318a50
LW		 1371 goto found_phy;
1372 }
1373 } else
1374 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1375 int phy_num = j + event_group * 2;
1376 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1377 if (d40_alloc_mask_set(&phys[i],
1378 is_src,
1379 0,
1380 is_log))
8d318a50
LW		 1381 goto found_phy;
1382 }
1383 }
1384 return -EINVAL;
1385found_phy:
1386 d40c->phy_chan = &phys[i];
1387 d40c->log_num = D40_PHY_CHAN;
1388 goto out;
1389 }
1390 if (dev_type == -1)
1391 return -EINVAL;
1392
1393 /* Find logical channel */
1394 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1395 int phy_num = j + event_group * 2;
1396 /*
1397 * Spread logical channels across all available physical rather
1398 * than pack every logical channel at the first available phy
1399 * channels.
1400 */
1401 if (is_src) {
1402 for (i = phy_num; i < phy_num + 2; i++) {
1403 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1404 event_line, is_log))
8d318a50
LW		 1405 goto found_log;
1406 }
1407 } else {
1408 for (i = phy_num + 1; i >= phy_num; i--) {
1409 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1410 event_line, is_log))
8d318a50
LW		 1411 goto found_log;
1412 }
1413 }
1414 }
1415 return -EINVAL;
1416
1417found_log:
1418 d40c->phy_chan = &phys[i];
1419 d40c->log_num = log_num;
1420out:
1421
1422 if (is_log)
1423 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1424 else
1425 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1426
1427 return 0;
1428
1429}
1430
8d318a50
LW		 1431static int d40_config_memcpy(struct d40_chan *d40c)
1432{
1433 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1434
1435 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1436 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1437 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1438 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1439 memcpy[d40c->chan.chan_id];
1440
1441 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1442 dma_has_cap(DMA_SLAVE, cap)) {
1443 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1444 } else {
1445 dev_err(&d40c->chan.dev->device, "[%s] No memcpy\n",
1446 __func__);
1447 return -EINVAL;
1448 }
1449
1450 return 0;
1451}
1452
1453
1454static int d40_free_dma(struct d40_chan *d40c)
1455{
1456
1457 int res = 0;
d181b3a8 1458 u32 event;
8d318a50
LW		 1459 struct d40_phy_res *phy = d40c->phy_chan;
1460 bool is_src;
a8be8627
PF		 1461 struct d40_desc *d;
1462 struct d40_desc *_d;
1463
8d318a50
LW		 1464
1465 /* Terminate all queued and active transfers */
1466 d40_term_all(d40c);
1467
a8be8627
PF		 1468 /* Release client owned descriptors */
1469 if (!list_empty(&d40c->client))
1470 list_for_each_entry_safe(d, _d, &d40c->client, node) {
1471 d40_pool_lli_free(d);
1472 d40_desc_remove(d);
a8be8627
PF		 1473 d40_desc_free(d40c, d);
1474 }
1475
8d318a50
LW		 1476 if (phy == NULL) {
1477 dev_err(&d40c->chan.dev->device, "[%s] phy == null\n",
1478 __func__);
1479 return -EINVAL;
1480 }
1481
1482 if (phy->allocated_src == D40_ALLOC_FREE &&
1483 phy->allocated_dst == D40_ALLOC_FREE) {
1484 dev_err(&d40c->chan.dev->device, "[%s] channel already free\n",
1485 __func__);
1486 return -EINVAL;
1487 }
1488
8d318a50
LW		 1489 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1490 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1491 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8d318a50
LW		 1492 is_src = false;
1493 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1494 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8d318a50
LW		 1495 is_src = true;
1496 } else {
1497 dev_err(&d40c->chan.dev->device,
1498 "[%s] Unknown direction\n", __func__);
1499 return -EINVAL;
1500 }
1501
d181b3a8
JA		 1502 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1503 if (res) {
1504 dev_err(&d40c->chan.dev->device, "[%s] suspend failed\n",
1505 __func__);
1506 return res;
1507 }
1508
8d318a50 1509 if (d40c->log_num != D40_PHY_CHAN) {
d181b3a8 1510 /* Release logical channel, deactivate the event line */
8d318a50 1511
d181b3a8 1512 d40_config_set_event(d40c, false);
8d318a50
LW		 1513 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1514
1515 /*
1516 * Check if there are more logical allocation
1517 * on this phy channel.
1518 */
1519 if (!d40_alloc_mask_free(phy, is_src, event)) {
1520 /* Resume the other logical channels if any */
1521 if (d40_chan_has_events(d40c)) {
1522 res = d40_channel_execute_command(d40c,
1523 D40_DMA_RUN);
1524 if (res) {
1525 dev_err(&d40c->chan.dev->device,
1526 "[%s] Executing RUN command\n",
1527 __func__);
1528 return res;
1529 }
1530 }
1531 return 0;
1532 }
d181b3a8
JA		 1533 } else {
1534 (void) d40_alloc_mask_free(phy, is_src, 0);
1535 }
8d318a50
LW		 1536
1537 /* Release physical channel */
1538 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1539 if (res) {
1540 dev_err(&d40c->chan.dev->device,
1541 "[%s] Failed to stop channel\n", __func__);
1542 return res;
1543 }
1544 d40c->phy_chan = NULL;
ce2ca125 1545 d40c->configured = false;
8d318a50
LW		 1546 d40c->base->lookup_phy_chans[phy->num] = NULL;
1547
1548 return 0;
8d318a50
LW		 1549}
1550
a5ebca47
JA		 1551static bool d40_is_paused(struct d40_chan *d40c)
1552{
1553 bool is_paused = false;
1554 unsigned long flags;
1555 void __iomem *active_reg;
1556 u32 status;
1557 u32 event;
a5ebca47
JA		 1558
1559 spin_lock_irqsave(&d40c->lock, flags);
1560
1561 if (d40c->log_num == D40_PHY_CHAN) {
1562 if (d40c->phy_chan->num % 2 == 0)
1563 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1564 else
1565 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1566
1567 status = (readl(active_reg) &
1568 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1569 D40_CHAN_POS(d40c->phy_chan->num);
1570 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1571 is_paused = true;
1572
1573 goto _exit;
1574 }
1575
a5ebca47 1576 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
9dbfbd35 1577 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
a5ebca47 1578 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
9dbfbd35
JA		 1579 status = readl(d40c->base->virtbase + D40_DREG_PCBASE +
1580 d40c->phy_chan->num * D40_DREG_PCDELTA +
1581 D40_CHAN_REG_SDLNK);
1582 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
a5ebca47 1583 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
9dbfbd35
JA		 1584 status = readl(d40c->base->virtbase + D40_DREG_PCBASE +
1585 d40c->phy_chan->num * D40_DREG_PCDELTA +
1586 D40_CHAN_REG_SSLNK);
1587 } else {
a5ebca47
JA		 1588 dev_err(&d40c->chan.dev->device,
1589 "[%s] Unknown direction\n", __func__);
1590 goto _exit;
1591 }
9dbfbd35 1592
a5ebca47
JA		 1593 status = (status & D40_EVENTLINE_MASK(event)) >>
1594 D40_EVENTLINE_POS(event);
1595
1596 if (status != D40_DMA_RUN)
1597 is_paused = true;
a5ebca47
JA		 1598_exit:
1599 spin_unlock_irqrestore(&d40c->lock, flags);
1600 return is_paused;
1601
1602}
1603
1604
8d318a50
LW		 1605static u32 stedma40_residue(struct dma_chan *chan)
1606{
1607 struct d40_chan *d40c =
1608 container_of(chan, struct d40_chan, chan);
1609 u32 bytes_left;
1610 unsigned long flags;
1611
1612 spin_lock_irqsave(&d40c->lock, flags);
1613 bytes_left = d40_residue(d40c);
1614 spin_unlock_irqrestore(&d40c->lock, flags);
1615
1616 return bytes_left;
1617}
1618
8d318a50
LW		 1619struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
1620 struct scatterlist *sgl_dst,
1621 struct scatterlist *sgl_src,
1622 unsigned int sgl_len,
2a614340 1623 unsigned long dma_flags)
8d318a50
LW		 1624{
1625 int res;
1626 struct d40_desc *d40d;
1627 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1628 chan);
2a614340 1629 unsigned long flags;
8d318a50 1630
0d0f6b8b
JA		 1631 if (d40c->phy_chan == NULL) {
1632 dev_err(&d40c->chan.dev->device,
1633 "[%s] Unallocated channel.\n", __func__);
1634 return ERR_PTR(-EINVAL);
1635 }
1636
2a614340 1637 spin_lock_irqsave(&d40c->lock, flags);
8d318a50
LW		 1638 d40d = d40_desc_get(d40c);
1639
1640 if (d40d == NULL)
1641 goto err;
1642
d49278e3
PF		 1643 d40d->lli_len = d40_sg_2_dmalen(sgl_dst, sgl_len,
1644 d40c->dma_cfg.src_info.data_width,
1645 d40c->dma_cfg.dst_info.data_width);
1646 if (d40d->lli_len < 0) {
1647 dev_err(&d40c->chan.dev->device,
1648 "[%s] Unaligned size\n", __func__);
1649 goto err;
1650 }
1651
698e4732 1652 d40d->lli_current = 0;
2a614340 1653 d40d->txd.flags = dma_flags;
8d318a50
LW		 1654
1655 if (d40c->log_num != D40_PHY_CHAN) {
8d318a50 1656
d49278e3 1657 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
8d318a50
LW		 1658 dev_err(&d40c->chan.dev->device,
1659 "[%s] Out of memory\n", __func__);
1660 goto err;
1661 }
1662
698e4732 1663 (void) d40_log_sg_to_lli(sgl_src,
8d318a50
LW		 1664 sgl_len,
1665 d40d->lli_log.src,
1666 d40c->log_def.lcsp1,
d49278e3
PF		 1667 d40c->dma_cfg.src_info.data_width,
1668 d40c->dma_cfg.dst_info.data_width);
8d318a50 1669
698e4732 1670 (void) d40_log_sg_to_lli(sgl_dst,
8d318a50
LW		 1671 sgl_len,
1672 d40d->lli_log.dst,
1673 d40c->log_def.lcsp3,
d49278e3
PF		 1674 d40c->dma_cfg.dst_info.data_width,
1675 d40c->dma_cfg.src_info.data_width);
8d318a50 1676 } else {
d49278e3 1677 if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
8d318a50
LW		 1678 dev_err(&d40c->chan.dev->device,
1679 "[%s] Out of memory\n", __func__);
1680 goto err;
1681 }
1682
1683 res = d40_phy_sg_to_lli(sgl_src,
1684 sgl_len,
1685 0,
1686 d40d->lli_phy.src,
aa182ae2 1687 virt_to_phys(d40d->lli_phy.src),
8d318a50
LW		 1688 d40c->src_def_cfg,
1689 d40c->dma_cfg.src_info.data_width,
d49278e3 1690 d40c->dma_cfg.dst_info.data_width,
0246e77b 1691 d40c->dma_cfg.src_info.psize);
8d318a50
LW		 1692
1693 if (res < 0)
1694 goto err;
1695
1696 res = d40_phy_sg_to_lli(sgl_dst,
1697 sgl_len,
1698 0,
1699 d40d->lli_phy.dst,
aa182ae2 1700 virt_to_phys(d40d->lli_phy.dst),
8d318a50
LW		 1701 d40c->dst_def_cfg,
1702 d40c->dma_cfg.dst_info.data_width,
d49278e3 1703 d40c->dma_cfg.src_info.data_width,
0246e77b 1704 d40c->dma_cfg.dst_info.psize);
8d318a50
LW		 1705
1706 if (res < 0)
1707 goto err;
1708
1709 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1710 d40d->lli_pool.size, DMA_TO_DEVICE);
1711 }
1712
1713 dma_async_tx_descriptor_init(&d40d->txd, chan);
1714
1715 d40d->txd.tx_submit = d40_tx_submit;
1716
2a614340 1717 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1718
1719 return &d40d->txd;
1720err:
819504f4
RV		 1721 if (d40d)
1722 d40_desc_free(d40c, d40d);
2a614340 1723 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1724 return NULL;
1725}
1726EXPORT_SYMBOL(stedma40_memcpy_sg);
1727
1728bool stedma40_filter(struct dma_chan *chan, void *data)
1729{
1730 struct stedma40_chan_cfg *info = data;
1731 struct d40_chan *d40c =
1732 container_of(chan, struct d40_chan, chan);
1733 int err;
1734
1735 if (data) {
1736 err = d40_validate_conf(d40c, info);
1737 if (!err)
1738 d40c->dma_cfg = *info;
1739 } else
1740 err = d40_config_memcpy(d40c);
1741
ce2ca125
RV		 1742 if (!err)
1743 d40c->configured = true;
1744
8d318a50
LW		 1745 return err == 0;
1746}
1747EXPORT_SYMBOL(stedma40_filter);
1748
1749/* DMA ENGINE functions */
1750static int d40_alloc_chan_resources(struct dma_chan *chan)
1751{
1752 int err;
1753 unsigned long flags;
1754 struct d40_chan *d40c =
1755 container_of(chan, struct d40_chan, chan);
ef1872ec 1756 bool is_free_phy;
8d318a50
LW		 1757 spin_lock_irqsave(&d40c->lock, flags);
1758
1759 d40c->completed = chan->cookie = 1;
1760
ce2ca125
RV		 1761 /* If no dma configuration is set use default configuration (memcpy) */
1762 if (!d40c->configured) {
8d318a50 1763 err = d40_config_memcpy(d40c);
ff0b12ba
JA		 1764 if (err) {
1765 dev_err(&d40c->chan.dev->device,
1766 "[%s] Failed to configure memcpy channel\n",
1767 __func__);
1768 goto fail;
1769 }
8d318a50 1770 }
ef1872ec 1771 is_free_phy = (d40c->phy_chan == NULL);
8d318a50
LW		 1772
1773 err = d40_allocate_channel(d40c);
1774 if (err) {
1775 dev_err(&d40c->chan.dev->device,
1776 "[%s] Failed to allocate channel\n", __func__);
ff0b12ba 1777 goto fail;
8d318a50
LW		 1778 }
1779
ef1872ec
LW		 1780 /* Fill in basic CFG register values */
1781 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1782 &d40c->dst_def_cfg, d40c->log_num != D40_PHY_CHAN);
1783
1784 if (d40c->log_num != D40_PHY_CHAN) {
1785 d40_log_cfg(&d40c->dma_cfg,
1786 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1787
1788 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1789 d40c->lcpa = d40c->base->lcpa_base +
1790 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1791 else
1792 d40c->lcpa = d40c->base->lcpa_base +
1793 d40c->dma_cfg.dst_dev_type *
1794 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1795 }
1796
1797 /*
1798 * Only write channel configuration to the DMA if the physical
1799 * resource is free. In case of multiple logical channels
1800 * on the same physical resource, only the first write is necessary.
1801 */
b55912c6
JA		 1802 if (is_free_phy)
1803 d40_config_write(d40c);
ff0b12ba 1804fail:
8d318a50 1805 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 1806 return err;
8d318a50
LW		 1807}
1808
1809static void d40_free_chan_resources(struct dma_chan *chan)
1810{
1811 struct d40_chan *d40c =
1812 container_of(chan, struct d40_chan, chan);
1813 int err;
1814 unsigned long flags;
1815
0d0f6b8b
JA		 1816 if (d40c->phy_chan == NULL) {
1817 dev_err(&d40c->chan.dev->device,
1818 "[%s] Cannot free unallocated channel\n", __func__);
1819 return;
1820 }
1821
1822
8d318a50
LW		 1823 spin_lock_irqsave(&d40c->lock, flags);
1824
1825 err = d40_free_dma(d40c);
1826
1827 if (err)
1828 dev_err(&d40c->chan.dev->device,
1829 "[%s] Failed to free channel\n", __func__);
1830 spin_unlock_irqrestore(&d40c->lock, flags);
1831}
1832
1833static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1834 dma_addr_t dst,
1835 dma_addr_t src,
1836 size_t size,
2a614340 1837 unsigned long dma_flags)
8d318a50
LW		 1838{
1839 struct d40_desc *d40d;
1840 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1841 chan);
2a614340 1842 unsigned long flags;
8d318a50 1843
0d0f6b8b
JA		 1844 if (d40c->phy_chan == NULL) {
1845 dev_err(&d40c->chan.dev->device,
1846 "[%s] Channel is not allocated.\n", __func__);
1847 return ERR_PTR(-EINVAL);
1848 }
1849
2a614340 1850 spin_lock_irqsave(&d40c->lock, flags);
8d318a50
LW		 1851 d40d = d40_desc_get(d40c);
1852
1853 if (d40d == NULL) {
1854 dev_err(&d40c->chan.dev->device,
1855 "[%s] Descriptor is NULL\n", __func__);
1856 goto err;
1857 }
1858
2a614340 1859 d40d->txd.flags = dma_flags;
d49278e3
PF		 1860 d40d->lli_len = d40_size_2_dmalen(size,
1861 d40c->dma_cfg.src_info.data_width,
1862 d40c->dma_cfg.dst_info.data_width);
1863 if (d40d->lli_len < 0) {
1864 dev_err(&d40c->chan.dev->device,
1865 "[%s] Unaligned size\n", __func__);
1866 goto err;
1867 }
1868
8d318a50
LW		 1869
1870 dma_async_tx_descriptor_init(&d40d->txd, chan);
1871
1872 d40d->txd.tx_submit = d40_tx_submit;
1873
1874 if (d40c->log_num != D40_PHY_CHAN) {
1875
d49278e3 1876 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
8d318a50
LW		 1877 dev_err(&d40c->chan.dev->device,
1878 "[%s] Out of memory\n", __func__);
1879 goto err;
1880 }
698e4732 1881 d40d->lli_current = 0;
8d318a50 1882
d49278e3
PF		 1883 if (d40_log_buf_to_lli(d40d->lli_log.src,
1884 src,
1885 size,
1886 d40c->log_def.lcsp1,
1887 d40c->dma_cfg.src_info.data_width,
1888 d40c->dma_cfg.dst_info.data_width,
1889 true) == NULL)
1890 goto err;
8d318a50 1891
d49278e3
PF		 1892 if (d40_log_buf_to_lli(d40d->lli_log.dst,
1893 dst,
1894 size,
1895 d40c->log_def.lcsp3,
1896 d40c->dma_cfg.dst_info.data_width,
1897 d40c->dma_cfg.src_info.data_width,
1898 true) == NULL)
1899 goto err;
8d318a50
LW		 1900
1901 } else {
1902
d49278e3 1903 if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
8d318a50
LW		 1904 dev_err(&d40c->chan.dev->device,
1905 "[%s] Out of memory\n", __func__);
1906 goto err;
1907 }
1908
d49278e3 1909 if (d40_phy_buf_to_lli(d40d->lli_phy.src,
8d318a50
LW		 1910 src,
1911 size,
1912 d40c->dma_cfg.src_info.psize,
1913 0,
1914 d40c->src_def_cfg,
1915 true,
1916 d40c->dma_cfg.src_info.data_width,
d49278e3
PF		 1917 d40c->dma_cfg.dst_info.data_width,
1918 false) == NULL)
1919 goto err;
8d318a50 1920
d49278e3 1921 if (d40_phy_buf_to_lli(d40d->lli_phy.dst,
8d318a50
LW		 1922 dst,
1923 size,
1924 d40c->dma_cfg.dst_info.psize,
1925 0,
1926 d40c->dst_def_cfg,
1927 true,
1928 d40c->dma_cfg.dst_info.data_width,
d49278e3
PF		 1929 d40c->dma_cfg.src_info.data_width,
1930 false) == NULL)
1931 goto err;
8d318a50
LW		 1932
1933 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1934 d40d->lli_pool.size, DMA_TO_DEVICE);
1935 }
1936
2a614340 1937 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1938 return &d40d->txd;
1939
8d318a50 1940err:
819504f4
RV		 1941 if (d40d)
1942 d40_desc_free(d40c, d40d);
2a614340 1943 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1944 return NULL;
1945}
1946
0d688662
IS		 1947static struct dma_async_tx_descriptor *
1948d40_prep_sg(struct dma_chan *chan,
1949 struct scatterlist *dst_sg, unsigned int dst_nents,
1950 struct scatterlist *src_sg, unsigned int src_nents,
1951 unsigned long dma_flags)
1952{
1953 if (dst_nents != src_nents)
1954 return NULL;
1955
1956 return stedma40_memcpy_sg(chan, dst_sg, src_sg, dst_nents, dma_flags);
1957}
1958
8d318a50
LW		 1959static int d40_prep_slave_sg_log(struct d40_desc *d40d,
1960 struct d40_chan *d40c,
1961 struct scatterlist *sgl,
1962 unsigned int sg_len,
1963 enum dma_data_direction direction,
2a614340 1964 unsigned long dma_flags)
8d318a50
LW		 1965{
1966 dma_addr_t dev_addr = 0;
1967 int total_size;
8d318a50 1968
d49278e3
PF		 1969 d40d->lli_len = d40_sg_2_dmalen(sgl, sg_len,
1970 d40c->dma_cfg.src_info.data_width,
1971 d40c->dma_cfg.dst_info.data_width);
1972 if (d40d->lli_len < 0) {
1973 dev_err(&d40c->chan.dev->device,
1974 "[%s] Unaligned size\n", __func__);
1975 return -EINVAL;
1976 }
1977
1978 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
8d318a50
LW		 1979 dev_err(&d40c->chan.dev->device,
1980 "[%s] Out of memory\n", __func__);
1981 return -ENOMEM;
1982 }
1983
698e4732 1984 d40d->lli_current = 0;
8d318a50 1985
2a614340 1986 if (direction == DMA_FROM_DEVICE)
95e1400f
LW		 1987 if (d40c->runtime_addr)
1988 dev_addr = d40c->runtime_addr;
1989 else
1990 dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
2a614340 1991 else if (direction == DMA_TO_DEVICE)
95e1400f
LW		 1992 if (d40c->runtime_addr)
1993 dev_addr = d40c->runtime_addr;
1994 else
1995 dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1996
2a614340 1997 else
8d318a50 1998 return -EINVAL;
2a614340 1999
698e4732 2000 total_size = d40_log_sg_to_dev(sgl, sg_len,
2a614340
JA		 2001 &d40d->lli_log,
2002 &d40c->log_def,
2003 d40c->dma_cfg.src_info.data_width,
2004 d40c->dma_cfg.dst_info.data_width,
2005 direction,
698e4732 2006 dev_addr);
2a614340 2007
8d318a50
LW		 2008 if (total_size < 0)
2009 return -EINVAL;
2010
2011 return 0;
2012}
2013
2014static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
2015 struct d40_chan *d40c,
2016 struct scatterlist *sgl,
2017 unsigned int sgl_len,
2018 enum dma_data_direction direction,
2a614340 2019 unsigned long dma_flags)
8d318a50
LW		 2020{
2021 dma_addr_t src_dev_addr;
2022 dma_addr_t dst_dev_addr;
2023 int res;
2024
d49278e3
PF		 2025 d40d->lli_len = d40_sg_2_dmalen(sgl, sgl_len,
2026 d40c->dma_cfg.src_info.data_width,
2027 d40c->dma_cfg.dst_info.data_width);
2028 if (d40d->lli_len < 0) {
2029 dev_err(&d40c->chan.dev->device,
2030 "[%s] Unaligned size\n", __func__);
2031 return -EINVAL;
2032 }
2033
2034 if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
8d318a50
LW		 2035 dev_err(&d40c->chan.dev->device,
2036 "[%s] Out of memory\n", __func__);
2037 return -ENOMEM;
2038 }
2039
698e4732 2040 d40d->lli_current = 0;
8d318a50
LW		 2041
2042 if (direction == DMA_FROM_DEVICE) {
2043 dst_dev_addr = 0;
95e1400f
LW		 2044 if (d40c->runtime_addr)
2045 src_dev_addr = d40c->runtime_addr;
2046 else
2047 src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
8d318a50 2048 } else if (direction == DMA_TO_DEVICE) {
95e1400f
LW		 2049 if (d40c->runtime_addr)
2050 dst_dev_addr = d40c->runtime_addr;
2051 else
2052 dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
8d318a50
LW		 2053 src_dev_addr = 0;
2054 } else
2055 return -EINVAL;
2056
2057 res = d40_phy_sg_to_lli(sgl,
2058 sgl_len,
2059 src_dev_addr,
2060 d40d->lli_phy.src,
aa182ae2 2061 virt_to_phys(d40d->lli_phy.src),
8d318a50
LW		 2062 d40c->src_def_cfg,
2063 d40c->dma_cfg.src_info.data_width,
d49278e3 2064 d40c->dma_cfg.dst_info.data_width,
0246e77b 2065 d40c->dma_cfg.src_info.psize);
8d318a50
LW		 2066 if (res < 0)
2067 return res;
2068
2069 res = d40_phy_sg_to_lli(sgl,
2070 sgl_len,
2071 dst_dev_addr,
2072 d40d->lli_phy.dst,
aa182ae2 2073 virt_to_phys(d40d->lli_phy.dst),
8d318a50
LW		 2074 d40c->dst_def_cfg,
2075 d40c->dma_cfg.dst_info.data_width,
d49278e3 2076 d40c->dma_cfg.src_info.data_width,
0246e77b 2077 d40c->dma_cfg.dst_info.psize);
8d318a50
LW		 2078 if (res < 0)
2079 return res;
2080
2081 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
2082 d40d->lli_pool.size, DMA_TO_DEVICE);
2083 return 0;
2084}
2085
2086static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2087 struct scatterlist *sgl,
2088 unsigned int sg_len,
2089 enum dma_data_direction direction,
2a614340 2090 unsigned long dma_flags)
8d318a50
LW		 2091{
2092 struct d40_desc *d40d;
2093 struct d40_chan *d40c = container_of(chan, struct d40_chan,
2094 chan);
2a614340 2095 unsigned long flags;
8d318a50
LW		 2096 int err;
2097
0d0f6b8b
JA		 2098 if (d40c->phy_chan == NULL) {
2099 dev_err(&d40c->chan.dev->device,
2100 "[%s] Cannot prepare unallocated channel\n", __func__);
2101 return ERR_PTR(-EINVAL);
2102 }
2103
2a614340 2104 spin_lock_irqsave(&d40c->lock, flags);
8d318a50 2105 d40d = d40_desc_get(d40c);
8d318a50
LW		 2106
2107 if (d40d == NULL)
819504f4 2108 goto err;
8d318a50 2109
8d318a50
LW		 2110 if (d40c->log_num != D40_PHY_CHAN)
2111 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2a614340 2112 direction, dma_flags);
8d318a50
LW		 2113 else
2114 err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
2a614340 2115 direction, dma_flags);
8d318a50
LW		 2116 if (err) {
2117 dev_err(&d40c->chan.dev->device,
2118 "[%s] Failed to prepare %s slave sg job: %d\n",
2119 __func__,
2120 d40c->log_num != D40_PHY_CHAN ? "log" : "phy", err);
819504f4 2121 goto err;
8d318a50
LW		 2122 }
2123
2a614340 2124 d40d->txd.flags = dma_flags;
8d318a50
LW		 2125
2126 dma_async_tx_descriptor_init(&d40d->txd, chan);
2127
2128 d40d->txd.tx_submit = d40_tx_submit;
2129
819504f4 2130 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50 2131 return &d40d->txd;
819504f4
RV		 2132
2133err:
2134 if (d40d)
2135 d40_desc_free(d40c, d40d);
2136 spin_unlock_irqrestore(&d40c->lock, flags);
2137 return NULL;
8d318a50
LW		 2138}
2139
2140static enum dma_status d40_tx_status(struct dma_chan *chan,
2141 dma_cookie_t cookie,
2142 struct dma_tx_state *txstate)
2143{
2144 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2145 dma_cookie_t last_used;
2146 dma_cookie_t last_complete;
2147 int ret;
2148
0d0f6b8b
JA		 2149 if (d40c->phy_chan == NULL) {
2150 dev_err(&d40c->chan.dev->device,
2151 "[%s] Cannot read status of unallocated channel\n",
2152 __func__);
2153 return -EINVAL;
2154 }
2155
8d318a50
LW		 2156 last_complete = d40c->completed;
2157 last_used = chan->cookie;
2158
a5ebca47
JA		 2159 if (d40_is_paused(d40c))
2160 ret = DMA_PAUSED;
2161 else
2162 ret = dma_async_is_complete(cookie, last_complete, last_used);
8d318a50 2163
a5ebca47
JA		 2164 dma_set_tx_state(txstate, last_complete, last_used,
2165 stedma40_residue(chan));
8d318a50
LW		 2166
2167 return ret;
2168}
2169
2170static void d40_issue_pending(struct dma_chan *chan)
2171{
2172 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2173 unsigned long flags;
2174
0d0f6b8b
JA		 2175 if (d40c->phy_chan == NULL) {
2176 dev_err(&d40c->chan.dev->device,
2177 "[%s] Channel is not allocated!\n", __func__);
2178 return;
2179 }
2180
8d318a50
LW		 2181 spin_lock_irqsave(&d40c->lock, flags);
2182
2183 /* Busy means that pending jobs are already being processed */
2184 if (!d40c->busy)
2185 (void) d40_queue_start(d40c);
2186
2187 spin_unlock_irqrestore(&d40c->lock, flags);
2188}
2189
95e1400f
LW		 2190/* Runtime reconfiguration extension */
2191static void d40_set_runtime_config(struct dma_chan *chan,
2192 struct dma_slave_config *config)
2193{
2194 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2195 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2196 enum dma_slave_buswidth config_addr_width;
2197 dma_addr_t config_addr;
2198 u32 config_maxburst;
2199 enum stedma40_periph_data_width addr_width;
2200 int psize;
2201
2202 if (config->direction == DMA_FROM_DEVICE) {
2203 dma_addr_t dev_addr_rx =
2204 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2205
2206 config_addr = config->src_addr;
2207 if (dev_addr_rx)
2208 dev_dbg(d40c->base->dev,
2209 "channel has a pre-wired RX address %08x "
2210 "overriding with %08x\n",
2211 dev_addr_rx, config_addr);
2212 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2213 dev_dbg(d40c->base->dev,
2214 "channel was not configured for peripheral "
2215 "to memory transfer (%d) overriding\n",
2216 cfg->dir);
2217 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2218
2219 config_addr_width = config->src_addr_width;
2220 config_maxburst = config->src_maxburst;
2221
2222 } else if (config->direction == DMA_TO_DEVICE) {
2223 dma_addr_t dev_addr_tx =
2224 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2225
2226 config_addr = config->dst_addr;
2227 if (dev_addr_tx)
2228 dev_dbg(d40c->base->dev,
2229 "channel has a pre-wired TX address %08x "
2230 "overriding with %08x\n",
2231 dev_addr_tx, config_addr);
2232 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2233 dev_dbg(d40c->base->dev,
2234 "channel was not configured for memory "
2235 "to peripheral transfer (%d) overriding\n",
2236 cfg->dir);
2237 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2238
2239 config_addr_width = config->dst_addr_width;
2240 config_maxburst = config->dst_maxburst;
2241
2242 } else {
2243 dev_err(d40c->base->dev,
2244 "unrecognized channel direction %d\n",
2245 config->direction);
2246 return;
2247 }
2248
2249 switch (config_addr_width) {
2250 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2251 addr_width = STEDMA40_BYTE_WIDTH;
2252 break;
2253 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2254 addr_width = STEDMA40_HALFWORD_WIDTH;
2255 break;
2256 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2257 addr_width = STEDMA40_WORD_WIDTH;
2258 break;
2259 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2260 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2261 break;
2262 default:
2263 dev_err(d40c->base->dev,
2264 "illegal peripheral address width "
2265 "requested (%d)\n",
2266 config->src_addr_width);
2267 return;
2268 }
2269
a59670a4
PF		 2270 if (d40c->log_num != D40_PHY_CHAN) {
2271 if (config_maxburst >= 16)
2272 psize = STEDMA40_PSIZE_LOG_16;
2273 else if (config_maxburst >= 8)
2274 psize = STEDMA40_PSIZE_LOG_8;
2275 else if (config_maxburst >= 4)
2276 psize = STEDMA40_PSIZE_LOG_4;
2277 else
2278 psize = STEDMA40_PSIZE_LOG_1;
2279 } else {
2280 if (config_maxburst >= 16)
2281 psize = STEDMA40_PSIZE_PHY_16;
2282 else if (config_maxburst >= 8)
2283 psize = STEDMA40_PSIZE_PHY_8;
2284 else if (config_maxburst >= 4)
2285 psize = STEDMA40_PSIZE_PHY_4;
d49278e3
PF		 2286 else if (config_maxburst >= 2)
2287 psize = STEDMA40_PSIZE_PHY_2;
a59670a4
PF		 2288 else
2289 psize = STEDMA40_PSIZE_PHY_1;
2290 }
95e1400f
LW		 2291
2292 /* Set up all the endpoint configs */
2293 cfg->src_info.data_width = addr_width;
2294 cfg->src_info.psize = psize;
51f5d744 2295 cfg->src_info.big_endian = false;
95e1400f
LW		 2296 cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2297 cfg->dst_info.data_width = addr_width;
2298 cfg->dst_info.psize = psize;
51f5d744 2299 cfg->dst_info.big_endian = false;
95e1400f
LW		 2300 cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2301
a59670a4
PF		 2302 /* Fill in register values */
2303 if (d40c->log_num != D40_PHY_CHAN)
2304 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2305 else
2306 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2307 &d40c->dst_def_cfg, false);
2308
95e1400f
LW		 2309 /* These settings will take precedence later */
2310 d40c->runtime_addr = config_addr;
2311 d40c->runtime_direction = config->direction;
2312 dev_dbg(d40c->base->dev,
2313 "configured channel %s for %s, data width %d, "
2314 "maxburst %d bytes, LE, no flow control\n",
2315 dma_chan_name(chan),
2316 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2317 config_addr_width,
2318 config_maxburst);
2319}
2320
05827630
LW		 2321static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2322 unsigned long arg)
8d318a50
LW		 2323{
2324 unsigned long flags;
2325 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2326
0d0f6b8b
JA		 2327 if (d40c->phy_chan == NULL) {
2328 dev_err(&d40c->chan.dev->device,
2329 "[%s] Channel is not allocated!\n", __func__);
2330 return -EINVAL;
2331 }
2332
8d318a50
LW		 2333 switch (cmd) {
2334 case DMA_TERMINATE_ALL:
2335 spin_lock_irqsave(&d40c->lock, flags);
2336 d40_term_all(d40c);
2337 spin_unlock_irqrestore(&d40c->lock, flags);
2338 return 0;
2339 case DMA_PAUSE:
2340 return d40_pause(chan);
2341 case DMA_RESUME:
2342 return d40_resume(chan);
95e1400f
LW		 2343 case DMA_SLAVE_CONFIG:
2344 d40_set_runtime_config(chan,
2345 (struct dma_slave_config *) arg);
2346 return 0;
2347 default:
2348 break;
8d318a50
LW		 2349 }
2350
2351 /* Other commands are unimplemented */
2352 return -ENXIO;
2353}
2354
2355/* Initialization functions */
2356
2357static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2358 struct d40_chan *chans, int offset,
2359 int num_chans)
2360{
2361 int i = 0;
2362 struct d40_chan *d40c;
2363
2364 INIT_LIST_HEAD(&dma->channels);
2365
2366 for (i = offset; i < offset + num_chans; i++) {
2367 d40c = &chans[i];
2368 d40c->base = base;
2369 d40c->chan.device = dma;
2370
8d318a50
LW		 2371 spin_lock_init(&d40c->lock);
2372
2373 d40c->log_num = D40_PHY_CHAN;
2374
8d318a50
LW		 2375 INIT_LIST_HEAD(&d40c->active);
2376 INIT_LIST_HEAD(&d40c->queue);
2377 INIT_LIST_HEAD(&d40c->client);
2378
8d318a50
LW		 2379 tasklet_init(&d40c->tasklet, dma_tasklet,
2380 (unsigned long) d40c);
2381
2382 list_add_tail(&d40c->chan.device_node,
2383 &dma->channels);
2384 }
2385}
2386
2387static int __init d40_dmaengine_init(struct d40_base *base,
2388 int num_reserved_chans)
2389{
2390 int err ;
2391
2392 d40_chan_init(base, &base->dma_slave, base->log_chans,
2393 0, base->num_log_chans);
2394
2395 dma_cap_zero(base->dma_slave.cap_mask);
2396 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2397
2398 base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2399 base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2400 base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
0d688662 2401 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
8d318a50
LW		 2402 base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2403 base->dma_slave.device_tx_status = d40_tx_status;
2404 base->dma_slave.device_issue_pending = d40_issue_pending;
2405 base->dma_slave.device_control = d40_control;
2406 base->dma_slave.dev = base->dev;
2407
2408 err = dma_async_device_register(&base->dma_slave);
2409
2410 if (err) {
2411 dev_err(base->dev,
2412 "[%s] Failed to register slave channels\n",
2413 __func__);
2414 goto failure1;
2415 }
2416
2417 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2418 base->num_log_chans, base->plat_data->memcpy_len);
2419
2420 dma_cap_zero(base->dma_memcpy.cap_mask);
2421 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
0d688662 2422 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
8d318a50
LW		 2423
2424 base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2425 base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2426 base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
0d688662 2427 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
8d318a50
LW		 2428 base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2429 base->dma_memcpy.device_tx_status = d40_tx_status;
2430 base->dma_memcpy.device_issue_pending = d40_issue_pending;
2431 base->dma_memcpy.device_control = d40_control;
2432 base->dma_memcpy.dev = base->dev;
2433 /*
2434 * This controller can only access address at even
2435 * 32bit boundaries, i.e. 2^2
2436 */
2437 base->dma_memcpy.copy_align = 2;
2438
2439 err = dma_async_device_register(&base->dma_memcpy);
2440
2441 if (err) {
2442 dev_err(base->dev,
2443 "[%s] Failed to regsiter memcpy only channels\n",
2444 __func__);
2445 goto failure2;
2446 }
2447
2448 d40_chan_init(base, &base->dma_both, base->phy_chans,
2449 0, num_reserved_chans);
2450
2451 dma_cap_zero(base->dma_both.cap_mask);
2452 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2453 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
0d688662 2454 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
8d318a50
LW		 2455
2456 base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2457 base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2458 base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
0d688662 2459 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
8d318a50
LW		 2460 base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2461 base->dma_both.device_tx_status = d40_tx_status;
2462 base->dma_both.device_issue_pending = d40_issue_pending;
2463 base->dma_both.device_control = d40_control;
2464 base->dma_both.dev = base->dev;
2465 base->dma_both.copy_align = 2;
2466 err = dma_async_device_register(&base->dma_both);
2467
2468 if (err) {
2469 dev_err(base->dev,
2470 "[%s] Failed to register logical and physical capable channels\n",
2471 __func__);
2472 goto failure3;
2473 }
2474 return 0;
2475failure3:
2476 dma_async_device_unregister(&base->dma_memcpy);
2477failure2:
2478 dma_async_device_unregister(&base->dma_slave);
2479failure1:
2480 return err;
2481}
2482
2483/* Initialization functions. */
2484
2485static int __init d40_phy_res_init(struct d40_base *base)
2486{
2487 int i;
2488 int num_phy_chans_avail = 0;
2489 u32 val[2];
2490 int odd_even_bit = -2;
2491
2492 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2493 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2494
2495 for (i = 0; i < base->num_phy_chans; i++) {
2496 base->phy_res[i].num = i;
2497 odd_even_bit += 2 * ((i % 2) == 0);
2498 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2499 /* Mark security only channels as occupied */
2500 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2501 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2502 } else {
2503 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2504 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2505 num_phy_chans_avail++;
2506 }
2507 spin_lock_init(&base->phy_res[i].lock);
2508 }
6b7acd84
JA		 2509
2510 /* Mark disabled channels as occupied */
2511 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 2512 int chan = base->plat_data->disabled_channels[i];
2513
2514 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2515 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2516 num_phy_chans_avail--;
6b7acd84
JA		 2517 }
2518
8d318a50
LW		 2519 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2520 num_phy_chans_avail, base->num_phy_chans);
2521
2522 /* Verify settings extended vs standard */
2523 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2524
2525 for (i = 0; i < base->num_phy_chans; i++) {
2526
2527 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2528 (val[0] & 0x3) != 1)
2529 dev_info(base->dev,
2530 "[%s] INFO: channel %d is misconfigured (%d)\n",
2531 __func__, i, val[0] & 0x3);
2532
2533 val[0] = val[0] >> 2;
2534 }
2535
2536 return num_phy_chans_avail;
2537}
2538
2539static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2540{
2541 static const struct d40_reg_val dma_id_regs[] = {
2542 /* Peripheral Id */
2543 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2544 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2545 /*
2546 * D40_DREG_PERIPHID2 Depends on HW revision:
2547 * MOP500/HREF ED has 0x0008,
2548 * ? has 0x0018,
2549 * HREF V1 has 0x0028
2550 */
2551 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2552
2553 /* PCell Id */
2554 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2555 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2556 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2557 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2558 };
2559 struct stedma40_platform_data *plat_data;
2560 struct clk *clk = NULL;
2561 void __iomem *virtbase = NULL;
2562 struct resource *res = NULL;
2563 struct d40_base *base = NULL;
2564 int num_log_chans = 0;
2565 int num_phy_chans;
2566 int i;
f4185592 2567 u32 val;
3ae0267f 2568 u32 rev;
8d318a50
LW		 2569
2570 clk = clk_get(&pdev->dev, NULL);
2571
2572 if (IS_ERR(clk)) {
2573 dev_err(&pdev->dev, "[%s] No matching clock found\n",
2574 __func__);
2575 goto failure;
2576 }
2577
2578 clk_enable(clk);
2579
2580 /* Get IO for DMAC base address */
2581 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2582 if (!res)
2583 goto failure;
2584
2585 if (request_mem_region(res->start, resource_size(res),
2586 D40_NAME " I/O base") == NULL)
2587 goto failure;
2588
2589 virtbase = ioremap(res->start, resource_size(res));
2590 if (!virtbase)
2591 goto failure;
2592
2593 /* HW version check */
2594 for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2595 if (dma_id_regs[i].val !=
2596 readl(virtbase + dma_id_regs[i].reg)) {
2597 dev_err(&pdev->dev,
2598 "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2599 __func__,
2600 dma_id_regs[i].val,
2601 dma_id_regs[i].reg,
2602 readl(virtbase + dma_id_regs[i].reg));
2603 goto failure;
2604 }
2605 }
2606
3ae0267f 2607 /* Get silicon revision and designer */
f4185592 2608 val = readl(virtbase + D40_DREG_PERIPHID2);
8d318a50 2609
3ae0267f
JA		 2610 if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2611 D40_HW_DESIGNER) {
8d318a50
LW		 2612 dev_err(&pdev->dev,
2613 "[%s] Unknown designer! Got %x wanted %x\n",
3ae0267f
JA		 2614 __func__, val & D40_DREG_PERIPHID2_DESIGNER_MASK,
2615 D40_HW_DESIGNER);
8d318a50
LW		 2616 goto failure;
2617 }
2618
3ae0267f
JA		 2619 rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2620 D40_DREG_PERIPHID2_REV_POS;
2621
8d318a50
LW		 2622 /* The number of physical channels on this HW */
2623 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2624
2625 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
3ae0267f 2626 rev, res->start);
8d318a50
LW		 2627
2628 plat_data = pdev->dev.platform_data;
2629
2630 /* Count the number of logical channels in use */
2631 for (i = 0; i < plat_data->dev_len; i++)
2632 if (plat_data->dev_rx[i] != 0)
2633 num_log_chans++;
2634
2635 for (i = 0; i < plat_data->dev_len; i++)
2636 if (plat_data->dev_tx[i] != 0)
2637 num_log_chans++;
2638
2639 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2640 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2641 sizeof(struct d40_chan), GFP_KERNEL);
2642
2643 if (base == NULL) {
2644 dev_err(&pdev->dev, "[%s] Out of memory\n", __func__);
2645 goto failure;
2646 }
2647
3ae0267f 2648 base->rev = rev;
8d318a50
LW		 2649 base->clk = clk;
2650 base->num_phy_chans = num_phy_chans;
2651 base->num_log_chans = num_log_chans;
2652 base->phy_start = res->start;
2653 base->phy_size = resource_size(res);
2654 base->virtbase = virtbase;
2655 base->plat_data = plat_data;
2656 base->dev = &pdev->dev;
2657 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2658 base->log_chans = &base->phy_chans[num_phy_chans];
2659
2660 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2661 GFP_KERNEL);
2662 if (!base->phy_res)
2663 goto failure;
2664
2665 base->lookup_phy_chans = kzalloc(num_phy_chans *
2666 sizeof(struct d40_chan *),
2667 GFP_KERNEL);
2668 if (!base->lookup_phy_chans)
2669 goto failure;
2670
2671 if (num_log_chans + plat_data->memcpy_len) {
2672 /*
2673 * The max number of logical channels are event lines for all
2674 * src devices and dst devices
2675 */
2676 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2677 sizeof(struct d40_chan *),
2678 GFP_KERNEL);
2679 if (!base->lookup_log_chans)
2680 goto failure;
2681 }
698e4732
JA		 2682
2683 base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
2684 sizeof(struct d40_desc *) *
2685 D40_LCLA_LINK_PER_EVENT_GRP,
8d318a50
LW		 2686 GFP_KERNEL);
2687 if (!base->lcla_pool.alloc_map)
2688 goto failure;
2689
c675b1b4
JA		 2690 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2691 0, SLAB_HWCACHE_ALIGN,
2692 NULL);
2693 if (base->desc_slab == NULL)
2694 goto failure;
2695
8d318a50
LW		 2696 return base;
2697
2698failure:
c6134c96 2699 if (!IS_ERR(clk)) {
8d318a50
LW		 2700 clk_disable(clk);
2701 clk_put(clk);
2702 }
2703 if (virtbase)
2704 iounmap(virtbase);
2705 if (res)
2706 release_mem_region(res->start,
2707 resource_size(res));
2708 if (virtbase)
2709 iounmap(virtbase);
2710
2711 if (base) {
2712 kfree(base->lcla_pool.alloc_map);
2713 kfree(base->lookup_log_chans);
2714 kfree(base->lookup_phy_chans);
2715 kfree(base->phy_res);
2716 kfree(base);
2717 }
2718
2719 return NULL;
2720}
2721
2722static void __init d40_hw_init(struct d40_base *base)
2723{
2724
2725 static const struct d40_reg_val dma_init_reg[] = {
2726 /* Clock every part of the DMA block from start */
2727 { .reg = D40_DREG_GCC, .val = 0x0000ff01},
2728
2729 /* Interrupts on all logical channels */
2730 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2731 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2732 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2733 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2734 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2735 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2736 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2737 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2738 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2739 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2740 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2741 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2742 };
2743 int i;
2744 u32 prmseo[2] = {0, 0};
2745 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2746 u32 pcmis = 0;
2747 u32 pcicr = 0;
2748
2749 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2750 writel(dma_init_reg[i].val,
2751 base->virtbase + dma_init_reg[i].reg);
2752
2753 /* Configure all our dma channels to default settings */
2754 for (i = 0; i < base->num_phy_chans; i++) {
2755
2756 activeo[i % 2] = activeo[i % 2] << 2;
2757
2758 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2759 == D40_ALLOC_PHY) {
2760 activeo[i % 2] |= 3;
2761 continue;
2762 }
2763
2764 /* Enable interrupt # */
2765 pcmis = (pcmis << 1) | 1;
2766
2767 /* Clear interrupt # */
2768 pcicr = (pcicr << 1) | 1;
2769
2770 /* Set channel to physical mode */
2771 prmseo[i % 2] = prmseo[i % 2] << 2;
2772 prmseo[i % 2] |= 1;
2773
2774 }
2775
2776 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2777 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2778 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2779 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2780
2781 /* Write which interrupt to enable */
2782 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2783
2784 /* Write which interrupt to clear */
2785 writel(pcicr, base->virtbase + D40_DREG_PCICR);
2786
2787}
2788
508849ad
LW		 2789static int __init d40_lcla_allocate(struct d40_base *base)
2790{
2791 unsigned long *page_list;
2792 int i, j;
2793 int ret = 0;
2794
2795 /*
2796 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2797 * To full fill this hardware requirement without wasting 256 kb
2798 * we allocate pages until we get an aligned one.
2799 */
2800 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2801 GFP_KERNEL);
2802
2803 if (!page_list) {
2804 ret = -ENOMEM;
2805 goto failure;
2806 }
2807
2808 /* Calculating how many pages that are required */
2809 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2810
2811 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2812 page_list[i] = __get_free_pages(GFP_KERNEL,
2813 base->lcla_pool.pages);
2814 if (!page_list[i]) {
2815
2816 dev_err(base->dev,
2817 "[%s] Failed to allocate %d pages.\n",
2818 __func__, base->lcla_pool.pages);
2819
2820 for (j = 0; j < i; j++)
2821 free_pages(page_list[j], base->lcla_pool.pages);
2822 goto failure;
2823 }
2824
2825 if ((virt_to_phys((void *)page_list[i]) &
2826 (LCLA_ALIGNMENT - 1)) == 0)
2827 break;
2828 }
2829
2830 for (j = 0; j < i; j++)
2831 free_pages(page_list[j], base->lcla_pool.pages);
2832
2833 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2834 base->lcla_pool.base = (void *)page_list[i];
2835 } else {
767a9675
JA		 2836 /*
2837 * After many attempts and no succees with finding the correct
2838 * alignment, try with allocating a big buffer.
2839 */
508849ad
LW		 2840 dev_warn(base->dev,
2841 "[%s] Failed to get %d pages @ 18 bit align.\n",
2842 __func__, base->lcla_pool.pages);
2843 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2844 base->num_phy_chans +
2845 LCLA_ALIGNMENT,
2846 GFP_KERNEL);
2847 if (!base->lcla_pool.base_unaligned) {
2848 ret = -ENOMEM;
2849 goto failure;
2850 }
2851
2852 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2853 LCLA_ALIGNMENT);
2854 }
2855
2856 writel(virt_to_phys(base->lcla_pool.base),
2857 base->virtbase + D40_DREG_LCLA);
2858failure:
2859 kfree(page_list);
2860 return ret;
2861}
2862
8d318a50
LW		 2863static int __init d40_probe(struct platform_device *pdev)
2864{
2865 int err;
2866 int ret = -ENOENT;
2867 struct d40_base *base;
2868 struct resource *res = NULL;
2869 int num_reserved_chans;
2870 u32 val;
2871
2872 base = d40_hw_detect_init(pdev);
2873
2874 if (!base)
2875 goto failure;
2876
2877 num_reserved_chans = d40_phy_res_init(base);
2878
2879 platform_set_drvdata(pdev, base);
2880
2881 spin_lock_init(&base->interrupt_lock);
2882 spin_lock_init(&base->execmd_lock);
2883
2884 /* Get IO for logical channel parameter address */
2885 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2886 if (!res) {
2887 ret = -ENOENT;
2888 dev_err(&pdev->dev,
2889 "[%s] No \"lcpa\" memory resource\n",
2890 __func__);
2891 goto failure;
2892 }
2893 base->lcpa_size = resource_size(res);
2894 base->phy_lcpa = res->start;
2895
2896 if (request_mem_region(res->start, resource_size(res),
2897 D40_NAME " I/O lcpa") == NULL) {
2898 ret = -EBUSY;
2899 dev_err(&pdev->dev,
2900 "[%s] Failed to request LCPA region 0x%x-0x%x\n",
2901 __func__, res->start, res->end);
2902 goto failure;
2903 }
2904
2905 /* We make use of ESRAM memory for this. */
2906 val = readl(base->virtbase + D40_DREG_LCPA);
2907 if (res->start != val && val != 0) {
2908 dev_warn(&pdev->dev,
2909 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2910 __func__, val, res->start);
2911 } else
2912 writel(res->start, base->virtbase + D40_DREG_LCPA);
2913
2914 base->lcpa_base = ioremap(res->start, resource_size(res));
2915 if (!base->lcpa_base) {
2916 ret = -ENOMEM;
2917 dev_err(&pdev->dev,
2918 "[%s] Failed to ioremap LCPA region\n",
2919 __func__);
2920 goto failure;
2921 }
8d318a50 2922
508849ad
LW		 2923 ret = d40_lcla_allocate(base);
2924 if (ret) {
2925 dev_err(&pdev->dev, "[%s] Failed to allocate LCLA area\n",
2926 __func__);
8d318a50
LW		 2927 goto failure;
2928 }
2929
2930 spin_lock_init(&base->lcla_pool.lock);
2931
8d318a50
LW		 2932 base->irq = platform_get_irq(pdev, 0);
2933
2934 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
2935
2936 if (ret) {
2937 dev_err(&pdev->dev, "[%s] No IRQ defined\n", __func__);
2938 goto failure;
2939 }
2940
2941 err = d40_dmaengine_init(base, num_reserved_chans);
2942 if (err)
2943 goto failure;
2944
2945 d40_hw_init(base);
2946
2947 dev_info(base->dev, "initialized\n");
2948 return 0;
2949
2950failure:
2951 if (base) {
c675b1b4
JA		 2952 if (base->desc_slab)
2953 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 2954 if (base->virtbase)
2955 iounmap(base->virtbase);
508849ad
LW		 2956 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2957 free_pages((unsigned long)base->lcla_pool.base,
2958 base->lcla_pool.pages);
767a9675
JA		 2959
2960 kfree(base->lcla_pool.base_unaligned);
2961
8d318a50
LW		 2962 if (base->phy_lcpa)
2963 release_mem_region(base->phy_lcpa,
2964 base->lcpa_size);
2965 if (base->phy_start)
2966 release_mem_region(base->phy_start,
2967 base->phy_size);
2968 if (base->clk) {
2969 clk_disable(base->clk);
2970 clk_put(base->clk);
2971 }
2972
2973 kfree(base->lcla_pool.alloc_map);
2974 kfree(base->lookup_log_chans);
2975 kfree(base->lookup_phy_chans);
2976 kfree(base->phy_res);
2977 kfree(base);
2978 }
2979
2980 dev_err(&pdev->dev, "[%s] probe failed\n", __func__);
2981 return ret;
2982}
2983
2984static struct platform_driver d40_driver = {
2985 .driver = {
2986 .owner = THIS_MODULE,
2987 .name = D40_NAME,
2988 },
2989};
2990
cb9ab2d8 2991static int __init stedma40_init(void)
8d318a50
LW		 2992{
2993 return platform_driver_probe(&d40_driver, d40_probe);
2994}
2995arch_initcall(stedma40_init);
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