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8d318a50 | 1 | /* |
d49278e3 PF |
2 | * Copyright (C) Ericsson AB 2007-2008 |
3 | * Copyright (C) ST-Ericsson SA 2008-2010 | |
661385f9 | 4 | * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson |
767a9675 | 5 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson |
8d318a50 | 6 | * License terms: GNU General Public License (GPL) version 2 |
8d318a50 LW |
7 | */ |
8 | ||
b7f080cf | 9 | #include <linux/dma-mapping.h> |
8d318a50 LW |
10 | #include <linux/kernel.h> |
11 | #include <linux/slab.h> | |
f492b210 | 12 | #include <linux/export.h> |
8d318a50 LW |
13 | #include <linux/dmaengine.h> |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/delay.h> | |
7fb3e75e N |
17 | #include <linux/pm.h> |
18 | #include <linux/pm_runtime.h> | |
698e4732 | 19 | #include <linux/err.h> |
f4b89764 | 20 | #include <linux/amba/bus.h> |
8d318a50 LW |
21 | |
22 | #include <plat/ste_dma40.h> | |
23 | ||
24 | #include "ste_dma40_ll.h" | |
25 | ||
26 | #define D40_NAME "dma40" | |
27 | ||
28 | #define D40_PHY_CHAN -1 | |
29 | ||
30 | /* For masking out/in 2 bit channel positions */ | |
31 | #define D40_CHAN_POS(chan) (2 * (chan / 2)) | |
32 | #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan)) | |
33 | ||
34 | /* Maximum iterations taken before giving up suspending a channel */ | |
35 | #define D40_SUSPEND_MAX_IT 500 | |
36 | ||
7fb3e75e N |
37 | /* Milliseconds */ |
38 | #define DMA40_AUTOSUSPEND_DELAY 100 | |
39 | ||
508849ad LW |
40 | /* Hardware requirement on LCLA alignment */ |
41 | #define LCLA_ALIGNMENT 0x40000 | |
698e4732 JA |
42 | |
43 | /* Max number of links per event group */ | |
44 | #define D40_LCLA_LINK_PER_EVENT_GRP 128 | |
45 | #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP | |
46 | ||
508849ad LW |
47 | /* Attempts before giving up to trying to get pages that are aligned */ |
48 | #define MAX_LCLA_ALLOC_ATTEMPTS 256 | |
49 | ||
50 | /* Bit markings for allocation map */ | |
8d318a50 LW |
51 | #define D40_ALLOC_FREE (1 << 31) |
52 | #define D40_ALLOC_PHY (1 << 30) | |
53 | #define D40_ALLOC_LOG_FREE 0 | |
54 | ||
8d318a50 LW |
55 | /** |
56 | * enum 40_command - The different commands and/or statuses. | |
57 | * | |
58 | * @D40_DMA_STOP: DMA channel command STOP or status STOPPED, | |
59 | * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN. | |
60 | * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible. | |
61 | * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED. | |
62 | */ | |
63 | enum d40_command { | |
64 | D40_DMA_STOP = 0, | |
65 | D40_DMA_RUN = 1, | |
66 | D40_DMA_SUSPEND_REQ = 2, | |
67 | D40_DMA_SUSPENDED = 3 | |
68 | }; | |
69 | ||
7fb3e75e N |
70 | /* |
71 | * These are the registers that has to be saved and later restored | |
72 | * when the DMA hw is powered off. | |
73 | * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works. | |
74 | */ | |
75 | static u32 d40_backup_regs[] = { | |
76 | D40_DREG_LCPA, | |
77 | D40_DREG_LCLA, | |
78 | D40_DREG_PRMSE, | |
79 | D40_DREG_PRMSO, | |
80 | D40_DREG_PRMOE, | |
81 | D40_DREG_PRMOO, | |
82 | }; | |
83 | ||
84 | #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs) | |
85 | ||
86 | /* TODO: Check if all these registers have to be saved/restored on dma40 v3 */ | |
87 | static u32 d40_backup_regs_v3[] = { | |
88 | D40_DREG_PSEG1, | |
89 | D40_DREG_PSEG2, | |
90 | D40_DREG_PSEG3, | |
91 | D40_DREG_PSEG4, | |
92 | D40_DREG_PCEG1, | |
93 | D40_DREG_PCEG2, | |
94 | D40_DREG_PCEG3, | |
95 | D40_DREG_PCEG4, | |
96 | D40_DREG_RSEG1, | |
97 | D40_DREG_RSEG2, | |
98 | D40_DREG_RSEG3, | |
99 | D40_DREG_RSEG4, | |
100 | D40_DREG_RCEG1, | |
101 | D40_DREG_RCEG2, | |
102 | D40_DREG_RCEG3, | |
103 | D40_DREG_RCEG4, | |
104 | }; | |
105 | ||
106 | #define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3) | |
107 | ||
108 | static u32 d40_backup_regs_chan[] = { | |
109 | D40_CHAN_REG_SSCFG, | |
110 | D40_CHAN_REG_SSELT, | |
111 | D40_CHAN_REG_SSPTR, | |
112 | D40_CHAN_REG_SSLNK, | |
113 | D40_CHAN_REG_SDCFG, | |
114 | D40_CHAN_REG_SDELT, | |
115 | D40_CHAN_REG_SDPTR, | |
116 | D40_CHAN_REG_SDLNK, | |
117 | }; | |
118 | ||
8d318a50 LW |
119 | /** |
120 | * struct d40_lli_pool - Structure for keeping LLIs in memory | |
121 | * | |
122 | * @base: Pointer to memory area when the pre_alloc_lli's are not large | |
123 | * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if | |
124 | * pre_alloc_lli is used. | |
b00f938c | 125 | * @dma_addr: DMA address, if mapped |
8d318a50 LW |
126 | * @size: The size in bytes of the memory at base or the size of pre_alloc_lli. |
127 | * @pre_alloc_lli: Pre allocated area for the most common case of transfers, | |
128 | * one buffer to one buffer. | |
129 | */ | |
130 | struct d40_lli_pool { | |
131 | void *base; | |
508849ad | 132 | int size; |
b00f938c | 133 | dma_addr_t dma_addr; |
8d318a50 | 134 | /* Space for dst and src, plus an extra for padding */ |
508849ad | 135 | u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)]; |
8d318a50 LW |
136 | }; |
137 | ||
138 | /** | |
139 | * struct d40_desc - A descriptor is one DMA job. | |
140 | * | |
141 | * @lli_phy: LLI settings for physical channel. Both src and dst= | |
142 | * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if | |
143 | * lli_len equals one. | |
144 | * @lli_log: Same as above but for logical channels. | |
145 | * @lli_pool: The pool with two entries pre-allocated. | |
941b77a3 | 146 | * @lli_len: Number of llis of current descriptor. |
25985edc | 147 | * @lli_current: Number of transferred llis. |
698e4732 | 148 | * @lcla_alloc: Number of LCLA entries allocated. |
8d318a50 LW |
149 | * @txd: DMA engine struct. Used for among other things for communication |
150 | * during a transfer. | |
151 | * @node: List entry. | |
8d318a50 | 152 | * @is_in_client_list: true if the client owns this descriptor. |
7fb3e75e | 153 | * @cyclic: true if this is a cyclic job |
8d318a50 LW |
154 | * |
155 | * This descriptor is used for both logical and physical transfers. | |
156 | */ | |
8d318a50 LW |
157 | struct d40_desc { |
158 | /* LLI physical */ | |
159 | struct d40_phy_lli_bidir lli_phy; | |
160 | /* LLI logical */ | |
161 | struct d40_log_lli_bidir lli_log; | |
162 | ||
163 | struct d40_lli_pool lli_pool; | |
941b77a3 | 164 | int lli_len; |
698e4732 JA |
165 | int lli_current; |
166 | int lcla_alloc; | |
8d318a50 LW |
167 | |
168 | struct dma_async_tx_descriptor txd; | |
169 | struct list_head node; | |
170 | ||
8d318a50 | 171 | bool is_in_client_list; |
0c842b55 | 172 | bool cyclic; |
8d318a50 LW |
173 | }; |
174 | ||
175 | /** | |
176 | * struct d40_lcla_pool - LCLA pool settings and data. | |
177 | * | |
508849ad LW |
178 | * @base: The virtual address of LCLA. 18 bit aligned. |
179 | * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used. | |
180 | * This pointer is only there for clean-up on error. | |
181 | * @pages: The number of pages needed for all physical channels. | |
182 | * Only used later for clean-up on error | |
8d318a50 | 183 | * @lock: Lock to protect the content in this struct. |
698e4732 | 184 | * @alloc_map: big map over which LCLA entry is own by which job. |
8d318a50 LW |
185 | */ |
186 | struct d40_lcla_pool { | |
187 | void *base; | |
026cbc42 | 188 | dma_addr_t dma_addr; |
508849ad LW |
189 | void *base_unaligned; |
190 | int pages; | |
8d318a50 | 191 | spinlock_t lock; |
698e4732 | 192 | struct d40_desc **alloc_map; |
8d318a50 LW |
193 | }; |
194 | ||
195 | /** | |
196 | * struct d40_phy_res - struct for handling eventlines mapped to physical | |
197 | * channels. | |
198 | * | |
199 | * @lock: A lock protection this entity. | |
7fb3e75e | 200 | * @reserved: True if used by secure world or otherwise. |
8d318a50 LW |
201 | * @num: The physical channel number of this entity. |
202 | * @allocated_src: Bit mapped to show which src event line's are mapped to | |
203 | * this physical channel. Can also be free or physically allocated. | |
204 | * @allocated_dst: Same as for src but is dst. | |
205 | * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as | |
767a9675 | 206 | * event line number. |
8d318a50 LW |
207 | */ |
208 | struct d40_phy_res { | |
209 | spinlock_t lock; | |
7fb3e75e | 210 | bool reserved; |
8d318a50 LW |
211 | int num; |
212 | u32 allocated_src; | |
213 | u32 allocated_dst; | |
214 | }; | |
215 | ||
216 | struct d40_base; | |
217 | ||
218 | /** | |
219 | * struct d40_chan - Struct that describes a channel. | |
220 | * | |
221 | * @lock: A spinlock to protect this struct. | |
222 | * @log_num: The logical number, if any of this channel. | |
223 | * @completed: Starts with 1, after first interrupt it is set to dma engine's | |
224 | * current cookie. | |
225 | * @pending_tx: The number of pending transfers. Used between interrupt handler | |
226 | * and tasklet. | |
227 | * @busy: Set to true when transfer is ongoing on this channel. | |
2a614340 JA |
228 | * @phy_chan: Pointer to physical channel which this instance runs on. If this |
229 | * point is NULL, then the channel is not allocated. | |
8d318a50 LW |
230 | * @chan: DMA engine handle. |
231 | * @tasklet: Tasklet that gets scheduled from interrupt context to complete a | |
232 | * transfer and call client callback. | |
233 | * @client: Cliented owned descriptor list. | |
da063d26 | 234 | * @pending_queue: Submitted jobs, to be issued by issue_pending() |
8d318a50 LW |
235 | * @active: Active descriptor. |
236 | * @queue: Queued jobs. | |
82babbb3 | 237 | * @prepare_queue: Prepared jobs. |
8d318a50 | 238 | * @dma_cfg: The client configuration of this dma channel. |
ce2ca125 | 239 | * @configured: whether the dma_cfg configuration is valid |
8d318a50 LW |
240 | * @base: Pointer to the device instance struct. |
241 | * @src_def_cfg: Default cfg register setting for src. | |
242 | * @dst_def_cfg: Default cfg register setting for dst. | |
243 | * @log_def: Default logical channel settings. | |
8d318a50 | 244 | * @lcpa: Pointer to dst and src lcpa settings. |
ae752bf4 | 245 | * @runtime_addr: runtime configured address. |
246 | * @runtime_direction: runtime configured direction. | |
8d318a50 LW |
247 | * |
248 | * This struct can either "be" a logical or a physical channel. | |
249 | */ | |
250 | struct d40_chan { | |
251 | spinlock_t lock; | |
252 | int log_num; | |
253 | /* ID of the most recent completed transfer */ | |
254 | int completed; | |
255 | int pending_tx; | |
256 | bool busy; | |
257 | struct d40_phy_res *phy_chan; | |
258 | struct dma_chan chan; | |
259 | struct tasklet_struct tasklet; | |
260 | struct list_head client; | |
a8f3067b | 261 | struct list_head pending_queue; |
8d318a50 LW |
262 | struct list_head active; |
263 | struct list_head queue; | |
82babbb3 | 264 | struct list_head prepare_queue; |
8d318a50 | 265 | struct stedma40_chan_cfg dma_cfg; |
ce2ca125 | 266 | bool configured; |
8d318a50 LW |
267 | struct d40_base *base; |
268 | /* Default register configurations */ | |
269 | u32 src_def_cfg; | |
270 | u32 dst_def_cfg; | |
271 | struct d40_def_lcsp log_def; | |
8d318a50 | 272 | struct d40_log_lli_full *lcpa; |
95e1400f LW |
273 | /* Runtime reconfiguration */ |
274 | dma_addr_t runtime_addr; | |
db8196df | 275 | enum dma_transfer_direction runtime_direction; |
8d318a50 LW |
276 | }; |
277 | ||
278 | /** | |
279 | * struct d40_base - The big global struct, one for each probe'd instance. | |
280 | * | |
281 | * @interrupt_lock: Lock used to make sure one interrupt is handle a time. | |
282 | * @execmd_lock: Lock for execute command usage since several channels share | |
283 | * the same physical register. | |
284 | * @dev: The device structure. | |
285 | * @virtbase: The virtual base address of the DMA's register. | |
f4185592 | 286 | * @rev: silicon revision detected. |
8d318a50 LW |
287 | * @clk: Pointer to the DMA clock structure. |
288 | * @phy_start: Physical memory start of the DMA registers. | |
289 | * @phy_size: Size of the DMA register map. | |
290 | * @irq: The IRQ number. | |
291 | * @num_phy_chans: The number of physical channels. Read from HW. This | |
292 | * is the number of available channels for this driver, not counting "Secure | |
293 | * mode" allocated physical channels. | |
294 | * @num_log_chans: The number of logical channels. Calculated from | |
295 | * num_phy_chans. | |
296 | * @dma_both: dma_device channels that can do both memcpy and slave transfers. | |
297 | * @dma_slave: dma_device channels that can do only do slave transfers. | |
298 | * @dma_memcpy: dma_device channels that can do only do memcpy transfers. | |
7fb3e75e | 299 | * @phy_chans: Room for all possible physical channels in system. |
8d318a50 LW |
300 | * @log_chans: Room for all possible logical channels in system. |
301 | * @lookup_log_chans: Used to map interrupt number to logical channel. Points | |
302 | * to log_chans entries. | |
303 | * @lookup_phy_chans: Used to map interrupt number to physical channel. Points | |
304 | * to phy_chans entries. | |
305 | * @plat_data: Pointer to provided platform_data which is the driver | |
306 | * configuration. | |
28c7a19d | 307 | * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla. |
8d318a50 LW |
308 | * @phy_res: Vector containing all physical channels. |
309 | * @lcla_pool: lcla pool settings and data. | |
310 | * @lcpa_base: The virtual mapped address of LCPA. | |
311 | * @phy_lcpa: The physical address of the LCPA. | |
312 | * @lcpa_size: The size of the LCPA area. | |
c675b1b4 | 313 | * @desc_slab: cache for descriptors. |
7fb3e75e N |
314 | * @reg_val_backup: Here the values of some hardware registers are stored |
315 | * before the DMA is powered off. They are restored when the power is back on. | |
316 | * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and | |
317 | * later. | |
318 | * @reg_val_backup_chan: Backup data for standard channel parameter registers. | |
319 | * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off. | |
320 | * @initialized: true if the dma has been initialized | |
8d318a50 LW |
321 | */ |
322 | struct d40_base { | |
323 | spinlock_t interrupt_lock; | |
324 | spinlock_t execmd_lock; | |
325 | struct device *dev; | |
326 | void __iomem *virtbase; | |
f4185592 | 327 | u8 rev:4; |
8d318a50 LW |
328 | struct clk *clk; |
329 | phys_addr_t phy_start; | |
330 | resource_size_t phy_size; | |
331 | int irq; | |
332 | int num_phy_chans; | |
333 | int num_log_chans; | |
334 | struct dma_device dma_both; | |
335 | struct dma_device dma_slave; | |
336 | struct dma_device dma_memcpy; | |
337 | struct d40_chan *phy_chans; | |
338 | struct d40_chan *log_chans; | |
339 | struct d40_chan **lookup_log_chans; | |
340 | struct d40_chan **lookup_phy_chans; | |
341 | struct stedma40_platform_data *plat_data; | |
28c7a19d | 342 | struct regulator *lcpa_regulator; |
8d318a50 LW |
343 | /* Physical half channels */ |
344 | struct d40_phy_res *phy_res; | |
345 | struct d40_lcla_pool lcla_pool; | |
346 | void *lcpa_base; | |
347 | dma_addr_t phy_lcpa; | |
348 | resource_size_t lcpa_size; | |
c675b1b4 | 349 | struct kmem_cache *desc_slab; |
7fb3e75e N |
350 | u32 reg_val_backup[BACKUP_REGS_SZ]; |
351 | u32 reg_val_backup_v3[BACKUP_REGS_SZ_V3]; | |
352 | u32 *reg_val_backup_chan; | |
353 | u16 gcc_pwr_off_mask; | |
354 | bool initialized; | |
8d318a50 LW |
355 | }; |
356 | ||
357 | /** | |
358 | * struct d40_interrupt_lookup - lookup table for interrupt handler | |
359 | * | |
360 | * @src: Interrupt mask register. | |
361 | * @clr: Interrupt clear register. | |
362 | * @is_error: true if this is an error interrupt. | |
363 | * @offset: start delta in the lookup_log_chans in d40_base. If equals to | |
364 | * D40_PHY_CHAN, the lookup_phy_chans shall be used instead. | |
365 | */ | |
366 | struct d40_interrupt_lookup { | |
367 | u32 src; | |
368 | u32 clr; | |
369 | bool is_error; | |
370 | int offset; | |
371 | }; | |
372 | ||
373 | /** | |
374 | * struct d40_reg_val - simple lookup struct | |
375 | * | |
376 | * @reg: The register. | |
377 | * @val: The value that belongs to the register in reg. | |
378 | */ | |
379 | struct d40_reg_val { | |
380 | unsigned int reg; | |
381 | unsigned int val; | |
382 | }; | |
383 | ||
262d2915 RV |
384 | static struct device *chan2dev(struct d40_chan *d40c) |
385 | { | |
386 | return &d40c->chan.dev->device; | |
387 | } | |
388 | ||
724a8577 RV |
389 | static bool chan_is_physical(struct d40_chan *chan) |
390 | { | |
391 | return chan->log_num == D40_PHY_CHAN; | |
392 | } | |
393 | ||
394 | static bool chan_is_logical(struct d40_chan *chan) | |
395 | { | |
396 | return !chan_is_physical(chan); | |
397 | } | |
398 | ||
8ca84687 RV |
399 | static void __iomem *chan_base(struct d40_chan *chan) |
400 | { | |
401 | return chan->base->virtbase + D40_DREG_PCBASE + | |
402 | chan->phy_chan->num * D40_DREG_PCDELTA; | |
403 | } | |
404 | ||
6db5a8ba RV |
405 | #define d40_err(dev, format, arg...) \ |
406 | dev_err(dev, "[%s] " format, __func__, ## arg) | |
407 | ||
408 | #define chan_err(d40c, format, arg...) \ | |
409 | d40_err(chan2dev(d40c), format, ## arg) | |
410 | ||
b00f938c | 411 | static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d, |
dbd88788 | 412 | int lli_len) |
8d318a50 | 413 | { |
dbd88788 | 414 | bool is_log = chan_is_logical(d40c); |
8d318a50 LW |
415 | u32 align; |
416 | void *base; | |
417 | ||
418 | if (is_log) | |
419 | align = sizeof(struct d40_log_lli); | |
420 | else | |
421 | align = sizeof(struct d40_phy_lli); | |
422 | ||
423 | if (lli_len == 1) { | |
424 | base = d40d->lli_pool.pre_alloc_lli; | |
425 | d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli); | |
426 | d40d->lli_pool.base = NULL; | |
427 | } else { | |
594ece4d | 428 | d40d->lli_pool.size = lli_len * 2 * align; |
8d318a50 LW |
429 | |
430 | base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); | |
431 | d40d->lli_pool.base = base; | |
432 | ||
433 | if (d40d->lli_pool.base == NULL) | |
434 | return -ENOMEM; | |
435 | } | |
436 | ||
437 | if (is_log) { | |
d924abad | 438 | d40d->lli_log.src = PTR_ALIGN(base, align); |
594ece4d | 439 | d40d->lli_log.dst = d40d->lli_log.src + lli_len; |
b00f938c RV |
440 | |
441 | d40d->lli_pool.dma_addr = 0; | |
8d318a50 | 442 | } else { |
d924abad | 443 | d40d->lli_phy.src = PTR_ALIGN(base, align); |
594ece4d | 444 | d40d->lli_phy.dst = d40d->lli_phy.src + lli_len; |
b00f938c RV |
445 | |
446 | d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev, | |
447 | d40d->lli_phy.src, | |
448 | d40d->lli_pool.size, | |
449 | DMA_TO_DEVICE); | |
450 | ||
451 | if (dma_mapping_error(d40c->base->dev, | |
452 | d40d->lli_pool.dma_addr)) { | |
453 | kfree(d40d->lli_pool.base); | |
454 | d40d->lli_pool.base = NULL; | |
455 | d40d->lli_pool.dma_addr = 0; | |
456 | return -ENOMEM; | |
457 | } | |
8d318a50 LW |
458 | } |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
b00f938c | 463 | static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d) |
8d318a50 | 464 | { |
b00f938c RV |
465 | if (d40d->lli_pool.dma_addr) |
466 | dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr, | |
467 | d40d->lli_pool.size, DMA_TO_DEVICE); | |
468 | ||
8d318a50 LW |
469 | kfree(d40d->lli_pool.base); |
470 | d40d->lli_pool.base = NULL; | |
471 | d40d->lli_pool.size = 0; | |
472 | d40d->lli_log.src = NULL; | |
473 | d40d->lli_log.dst = NULL; | |
474 | d40d->lli_phy.src = NULL; | |
475 | d40d->lli_phy.dst = NULL; | |
8d318a50 LW |
476 | } |
477 | ||
698e4732 JA |
478 | static int d40_lcla_alloc_one(struct d40_chan *d40c, |
479 | struct d40_desc *d40d) | |
480 | { | |
481 | unsigned long flags; | |
482 | int i; | |
483 | int ret = -EINVAL; | |
484 | int p; | |
485 | ||
486 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); | |
487 | ||
488 | p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP; | |
489 | ||
490 | /* | |
491 | * Allocate both src and dst at the same time, therefore the half | |
492 | * start on 1 since 0 can't be used since zero is used as end marker. | |
493 | */ | |
494 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { | |
495 | if (!d40c->base->lcla_pool.alloc_map[p + i]) { | |
496 | d40c->base->lcla_pool.alloc_map[p + i] = d40d; | |
497 | d40d->lcla_alloc++; | |
498 | ret = i; | |
499 | break; | |
500 | } | |
501 | } | |
502 | ||
503 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); | |
504 | ||
505 | return ret; | |
506 | } | |
507 | ||
508 | static int d40_lcla_free_all(struct d40_chan *d40c, | |
509 | struct d40_desc *d40d) | |
510 | { | |
511 | unsigned long flags; | |
512 | int i; | |
513 | int ret = -EINVAL; | |
514 | ||
724a8577 | 515 | if (chan_is_physical(d40c)) |
698e4732 JA |
516 | return 0; |
517 | ||
518 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); | |
519 | ||
520 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { | |
521 | if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * | |
522 | D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) { | |
523 | d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * | |
524 | D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL; | |
525 | d40d->lcla_alloc--; | |
526 | if (d40d->lcla_alloc == 0) { | |
527 | ret = 0; | |
528 | break; | |
529 | } | |
530 | } | |
531 | } | |
532 | ||
533 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); | |
534 | ||
535 | return ret; | |
536 | ||
537 | } | |
538 | ||
8d318a50 LW |
539 | static void d40_desc_remove(struct d40_desc *d40d) |
540 | { | |
541 | list_del(&d40d->node); | |
542 | } | |
543 | ||
544 | static struct d40_desc *d40_desc_get(struct d40_chan *d40c) | |
545 | { | |
a2c15fa4 | 546 | struct d40_desc *desc = NULL; |
8d318a50 LW |
547 | |
548 | if (!list_empty(&d40c->client)) { | |
a2c15fa4 RV |
549 | struct d40_desc *d; |
550 | struct d40_desc *_d; | |
551 | ||
7fb3e75e | 552 | list_for_each_entry_safe(d, _d, &d40c->client, node) { |
8d318a50 | 553 | if (async_tx_test_ack(&d->txd)) { |
8d318a50 | 554 | d40_desc_remove(d); |
a2c15fa4 RV |
555 | desc = d; |
556 | memset(desc, 0, sizeof(*desc)); | |
c675b1b4 | 557 | break; |
8d318a50 | 558 | } |
7fb3e75e | 559 | } |
8d318a50 | 560 | } |
a2c15fa4 RV |
561 | |
562 | if (!desc) | |
563 | desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT); | |
564 | ||
565 | if (desc) | |
566 | INIT_LIST_HEAD(&desc->node); | |
567 | ||
568 | return desc; | |
8d318a50 LW |
569 | } |
570 | ||
571 | static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d) | |
572 | { | |
698e4732 | 573 | |
b00f938c | 574 | d40_pool_lli_free(d40c, d40d); |
698e4732 | 575 | d40_lcla_free_all(d40c, d40d); |
c675b1b4 | 576 | kmem_cache_free(d40c->base->desc_slab, d40d); |
8d318a50 LW |
577 | } |
578 | ||
579 | static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc) | |
580 | { | |
581 | list_add_tail(&desc->node, &d40c->active); | |
582 | } | |
583 | ||
1c4b0927 RV |
584 | static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc) |
585 | { | |
586 | struct d40_phy_lli *lli_dst = desc->lli_phy.dst; | |
587 | struct d40_phy_lli *lli_src = desc->lli_phy.src; | |
588 | void __iomem *base = chan_base(chan); | |
589 | ||
590 | writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); | |
591 | writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT); | |
592 | writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR); | |
593 | writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK); | |
594 | ||
595 | writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); | |
596 | writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT); | |
597 | writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR); | |
598 | writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK); | |
599 | } | |
600 | ||
e65889c7 | 601 | static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc) |
698e4732 | 602 | { |
e65889c7 RV |
603 | struct d40_lcla_pool *pool = &chan->base->lcla_pool; |
604 | struct d40_log_lli_bidir *lli = &desc->lli_log; | |
605 | int lli_current = desc->lli_current; | |
606 | int lli_len = desc->lli_len; | |
0c842b55 | 607 | bool cyclic = desc->cyclic; |
e65889c7 | 608 | int curr_lcla = -EINVAL; |
0c842b55 | 609 | int first_lcla = 0; |
28c7a19d | 610 | bool use_esram_lcla = chan->base->plat_data->use_esram_lcla; |
0c842b55 | 611 | bool linkback; |
e65889c7 | 612 | |
0c842b55 RV |
613 | /* |
614 | * We may have partially running cyclic transfers, in case we did't get | |
615 | * enough LCLA entries. | |
616 | */ | |
617 | linkback = cyclic && lli_current == 0; | |
618 | ||
619 | /* | |
620 | * For linkback, we need one LCLA even with only one link, because we | |
621 | * can't link back to the one in LCPA space | |
622 | */ | |
623 | if (linkback || (lli_len - lli_current > 1)) { | |
e65889c7 | 624 | curr_lcla = d40_lcla_alloc_one(chan, desc); |
0c842b55 RV |
625 | first_lcla = curr_lcla; |
626 | } | |
627 | ||
628 | /* | |
629 | * For linkback, we normally load the LCPA in the loop since we need to | |
630 | * link it to the second LCLA and not the first. However, if we | |
631 | * couldn't even get a first LCLA, then we have to run in LCPA and | |
632 | * reload manually. | |
633 | */ | |
634 | if (!linkback || curr_lcla == -EINVAL) { | |
635 | unsigned int flags = 0; | |
e65889c7 | 636 | |
0c842b55 RV |
637 | if (curr_lcla == -EINVAL) |
638 | flags |= LLI_TERM_INT; | |
e65889c7 | 639 | |
0c842b55 RV |
640 | d40_log_lli_lcpa_write(chan->lcpa, |
641 | &lli->dst[lli_current], | |
642 | &lli->src[lli_current], | |
643 | curr_lcla, | |
644 | flags); | |
645 | lli_current++; | |
646 | } | |
6045f0bb RV |
647 | |
648 | if (curr_lcla < 0) | |
649 | goto out; | |
650 | ||
e65889c7 RV |
651 | for (; lli_current < lli_len; lli_current++) { |
652 | unsigned int lcla_offset = chan->phy_chan->num * 1024 + | |
653 | 8 * curr_lcla * 2; | |
654 | struct d40_log_lli *lcla = pool->base + lcla_offset; | |
0c842b55 | 655 | unsigned int flags = 0; |
e65889c7 RV |
656 | int next_lcla; |
657 | ||
658 | if (lli_current + 1 < lli_len) | |
659 | next_lcla = d40_lcla_alloc_one(chan, desc); | |
660 | else | |
0c842b55 RV |
661 | next_lcla = linkback ? first_lcla : -EINVAL; |
662 | ||
663 | if (cyclic || next_lcla == -EINVAL) | |
664 | flags |= LLI_TERM_INT; | |
e65889c7 | 665 | |
0c842b55 RV |
666 | if (linkback && curr_lcla == first_lcla) { |
667 | /* First link goes in both LCPA and LCLA */ | |
668 | d40_log_lli_lcpa_write(chan->lcpa, | |
669 | &lli->dst[lli_current], | |
670 | &lli->src[lli_current], | |
671 | next_lcla, flags); | |
672 | } | |
673 | ||
674 | /* | |
675 | * One unused LCLA in the cyclic case if the very first | |
676 | * next_lcla fails... | |
677 | */ | |
e65889c7 RV |
678 | d40_log_lli_lcla_write(lcla, |
679 | &lli->dst[lli_current], | |
680 | &lli->src[lli_current], | |
0c842b55 | 681 | next_lcla, flags); |
e65889c7 | 682 | |
28c7a19d N |
683 | /* |
684 | * Cache maintenance is not needed if lcla is | |
685 | * mapped in esram | |
686 | */ | |
687 | if (!use_esram_lcla) { | |
688 | dma_sync_single_range_for_device(chan->base->dev, | |
689 | pool->dma_addr, lcla_offset, | |
690 | 2 * sizeof(struct d40_log_lli), | |
691 | DMA_TO_DEVICE); | |
692 | } | |
e65889c7 RV |
693 | curr_lcla = next_lcla; |
694 | ||
0c842b55 | 695 | if (curr_lcla == -EINVAL || curr_lcla == first_lcla) { |
e65889c7 RV |
696 | lli_current++; |
697 | break; | |
698 | } | |
699 | } | |
700 | ||
6045f0bb | 701 | out: |
e65889c7 RV |
702 | desc->lli_current = lli_current; |
703 | } | |
698e4732 | 704 | |
e65889c7 RV |
705 | static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d) |
706 | { | |
724a8577 | 707 | if (chan_is_physical(d40c)) { |
1c4b0927 | 708 | d40_phy_lli_load(d40c, d40d); |
698e4732 | 709 | d40d->lli_current = d40d->lli_len; |
e65889c7 RV |
710 | } else |
711 | d40_log_lli_to_lcxa(d40c, d40d); | |
698e4732 JA |
712 | } |
713 | ||
8d318a50 LW |
714 | static struct d40_desc *d40_first_active_get(struct d40_chan *d40c) |
715 | { | |
716 | struct d40_desc *d; | |
717 | ||
718 | if (list_empty(&d40c->active)) | |
719 | return NULL; | |
720 | ||
721 | d = list_first_entry(&d40c->active, | |
722 | struct d40_desc, | |
723 | node); | |
724 | return d; | |
725 | } | |
726 | ||
7404368c | 727 | /* remove desc from current queue and add it to the pending_queue */ |
8d318a50 LW |
728 | static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc) |
729 | { | |
7404368c PF |
730 | d40_desc_remove(desc); |
731 | desc->is_in_client_list = false; | |
a8f3067b PF |
732 | list_add_tail(&desc->node, &d40c->pending_queue); |
733 | } | |
734 | ||
735 | static struct d40_desc *d40_first_pending(struct d40_chan *d40c) | |
736 | { | |
737 | struct d40_desc *d; | |
738 | ||
739 | if (list_empty(&d40c->pending_queue)) | |
740 | return NULL; | |
741 | ||
742 | d = list_first_entry(&d40c->pending_queue, | |
743 | struct d40_desc, | |
744 | node); | |
745 | return d; | |
8d318a50 LW |
746 | } |
747 | ||
748 | static struct d40_desc *d40_first_queued(struct d40_chan *d40c) | |
749 | { | |
750 | struct d40_desc *d; | |
751 | ||
752 | if (list_empty(&d40c->queue)) | |
753 | return NULL; | |
754 | ||
755 | d = list_first_entry(&d40c->queue, | |
756 | struct d40_desc, | |
757 | node); | |
758 | return d; | |
759 | } | |
760 | ||
d49278e3 PF |
761 | static int d40_psize_2_burst_size(bool is_log, int psize) |
762 | { | |
763 | if (is_log) { | |
764 | if (psize == STEDMA40_PSIZE_LOG_1) | |
765 | return 1; | |
766 | } else { | |
767 | if (psize == STEDMA40_PSIZE_PHY_1) | |
768 | return 1; | |
769 | } | |
770 | ||
771 | return 2 << psize; | |
772 | } | |
773 | ||
774 | /* | |
775 | * The dma only supports transmitting packages up to | |
776 | * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of | |
777 | * dma elements required to send the entire sg list | |
778 | */ | |
779 | static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2) | |
780 | { | |
781 | int dmalen; | |
782 | u32 max_w = max(data_width1, data_width2); | |
783 | u32 min_w = min(data_width1, data_width2); | |
784 | u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w); | |
785 | ||
786 | if (seg_max > STEDMA40_MAX_SEG_SIZE) | |
787 | seg_max -= (1 << max_w); | |
788 | ||
789 | if (!IS_ALIGNED(size, 1 << max_w)) | |
790 | return -EINVAL; | |
791 | ||
792 | if (size <= seg_max) | |
793 | dmalen = 1; | |
794 | else { | |
795 | dmalen = size / seg_max; | |
796 | if (dmalen * seg_max < size) | |
797 | dmalen++; | |
798 | } | |
799 | return dmalen; | |
800 | } | |
801 | ||
802 | static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len, | |
803 | u32 data_width1, u32 data_width2) | |
804 | { | |
805 | struct scatterlist *sg; | |
806 | int i; | |
807 | int len = 0; | |
808 | int ret; | |
809 | ||
810 | for_each_sg(sgl, sg, sg_len, i) { | |
811 | ret = d40_size_2_dmalen(sg_dma_len(sg), | |
812 | data_width1, data_width2); | |
813 | if (ret < 0) | |
814 | return ret; | |
815 | len += ret; | |
816 | } | |
817 | return len; | |
818 | } | |
8d318a50 | 819 | |
7fb3e75e N |
820 | |
821 | #ifdef CONFIG_PM | |
822 | static void dma40_backup(void __iomem *baseaddr, u32 *backup, | |
823 | u32 *regaddr, int num, bool save) | |
824 | { | |
825 | int i; | |
826 | ||
827 | for (i = 0; i < num; i++) { | |
828 | void __iomem *addr = baseaddr + regaddr[i]; | |
829 | ||
830 | if (save) | |
831 | backup[i] = readl_relaxed(addr); | |
832 | else | |
833 | writel_relaxed(backup[i], addr); | |
834 | } | |
835 | } | |
836 | ||
837 | static void d40_save_restore_registers(struct d40_base *base, bool save) | |
838 | { | |
839 | int i; | |
840 | ||
841 | /* Save/Restore channel specific registers */ | |
842 | for (i = 0; i < base->num_phy_chans; i++) { | |
843 | void __iomem *addr; | |
844 | int idx; | |
845 | ||
846 | if (base->phy_res[i].reserved) | |
847 | continue; | |
848 | ||
849 | addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA; | |
850 | idx = i * ARRAY_SIZE(d40_backup_regs_chan); | |
851 | ||
852 | dma40_backup(addr, &base->reg_val_backup_chan[idx], | |
853 | d40_backup_regs_chan, | |
854 | ARRAY_SIZE(d40_backup_regs_chan), | |
855 | save); | |
856 | } | |
857 | ||
858 | /* Save/Restore global registers */ | |
859 | dma40_backup(base->virtbase, base->reg_val_backup, | |
860 | d40_backup_regs, ARRAY_SIZE(d40_backup_regs), | |
861 | save); | |
862 | ||
863 | /* Save/Restore registers only existing on dma40 v3 and later */ | |
864 | if (base->rev >= 3) | |
865 | dma40_backup(base->virtbase, base->reg_val_backup_v3, | |
866 | d40_backup_regs_v3, | |
867 | ARRAY_SIZE(d40_backup_regs_v3), | |
868 | save); | |
869 | } | |
870 | #else | |
871 | static void d40_save_restore_registers(struct d40_base *base, bool save) | |
872 | { | |
873 | } | |
874 | #endif | |
8d318a50 LW |
875 | |
876 | static int d40_channel_execute_command(struct d40_chan *d40c, | |
877 | enum d40_command command) | |
878 | { | |
767a9675 JA |
879 | u32 status; |
880 | int i; | |
8d318a50 LW |
881 | void __iomem *active_reg; |
882 | int ret = 0; | |
883 | unsigned long flags; | |
1d392a7b | 884 | u32 wmask; |
8d318a50 LW |
885 | |
886 | spin_lock_irqsave(&d40c->base->execmd_lock, flags); | |
887 | ||
888 | if (d40c->phy_chan->num % 2 == 0) | |
889 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; | |
890 | else | |
891 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; | |
892 | ||
893 | if (command == D40_DMA_SUSPEND_REQ) { | |
894 | status = (readl(active_reg) & | |
895 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
896 | D40_CHAN_POS(d40c->phy_chan->num); | |
897 | ||
898 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) | |
899 | goto done; | |
900 | } | |
901 | ||
1d392a7b JA |
902 | wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num)); |
903 | writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)), | |
904 | active_reg); | |
8d318a50 LW |
905 | |
906 | if (command == D40_DMA_SUSPEND_REQ) { | |
907 | ||
908 | for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) { | |
909 | status = (readl(active_reg) & | |
910 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
911 | D40_CHAN_POS(d40c->phy_chan->num); | |
912 | ||
913 | cpu_relax(); | |
914 | /* | |
915 | * Reduce the number of bus accesses while | |
916 | * waiting for the DMA to suspend. | |
917 | */ | |
918 | udelay(3); | |
919 | ||
920 | if (status == D40_DMA_STOP || | |
921 | status == D40_DMA_SUSPENDED) | |
922 | break; | |
923 | } | |
924 | ||
925 | if (i == D40_SUSPEND_MAX_IT) { | |
6db5a8ba RV |
926 | chan_err(d40c, |
927 | "unable to suspend the chl %d (log: %d) status %x\n", | |
928 | d40c->phy_chan->num, d40c->log_num, | |
8d318a50 LW |
929 | status); |
930 | dump_stack(); | |
931 | ret = -EBUSY; | |
932 | } | |
933 | ||
934 | } | |
935 | done: | |
936 | spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); | |
937 | return ret; | |
938 | } | |
939 | ||
940 | static void d40_term_all(struct d40_chan *d40c) | |
941 | { | |
942 | struct d40_desc *d40d; | |
7404368c | 943 | struct d40_desc *_d; |
8d318a50 LW |
944 | |
945 | /* Release active descriptors */ | |
946 | while ((d40d = d40_first_active_get(d40c))) { | |
947 | d40_desc_remove(d40d); | |
8d318a50 LW |
948 | d40_desc_free(d40c, d40d); |
949 | } | |
950 | ||
951 | /* Release queued descriptors waiting for transfer */ | |
952 | while ((d40d = d40_first_queued(d40c))) { | |
953 | d40_desc_remove(d40d); | |
8d318a50 LW |
954 | d40_desc_free(d40c, d40d); |
955 | } | |
956 | ||
a8f3067b PF |
957 | /* Release pending descriptors */ |
958 | while ((d40d = d40_first_pending(d40c))) { | |
959 | d40_desc_remove(d40d); | |
960 | d40_desc_free(d40c, d40d); | |
961 | } | |
8d318a50 | 962 | |
7404368c PF |
963 | /* Release client owned descriptors */ |
964 | if (!list_empty(&d40c->client)) | |
965 | list_for_each_entry_safe(d40d, _d, &d40c->client, node) { | |
966 | d40_desc_remove(d40d); | |
967 | d40_desc_free(d40c, d40d); | |
968 | } | |
969 | ||
82babbb3 PF |
970 | /* Release descriptors in prepare queue */ |
971 | if (!list_empty(&d40c->prepare_queue)) | |
972 | list_for_each_entry_safe(d40d, _d, | |
973 | &d40c->prepare_queue, node) { | |
974 | d40_desc_remove(d40d); | |
975 | d40_desc_free(d40c, d40d); | |
976 | } | |
7404368c | 977 | |
8d318a50 LW |
978 | d40c->pending_tx = 0; |
979 | d40c->busy = false; | |
980 | } | |
981 | ||
262d2915 RV |
982 | static void __d40_config_set_event(struct d40_chan *d40c, bool enable, |
983 | u32 event, int reg) | |
984 | { | |
8ca84687 | 985 | void __iomem *addr = chan_base(d40c) + reg; |
262d2915 RV |
986 | int tries; |
987 | ||
988 | if (!enable) { | |
989 | writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) | |
990 | | ~D40_EVENTLINE_MASK(event), addr); | |
991 | return; | |
992 | } | |
993 | ||
994 | /* | |
995 | * The hardware sometimes doesn't register the enable when src and dst | |
996 | * event lines are active on the same logical channel. Retry to ensure | |
997 | * it does. Usually only one retry is sufficient. | |
998 | */ | |
999 | tries = 100; | |
1000 | while (--tries) { | |
1001 | writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) | |
1002 | | ~D40_EVENTLINE_MASK(event), addr); | |
1003 | ||
1004 | if (readl(addr) & D40_EVENTLINE_MASK(event)) | |
1005 | break; | |
1006 | } | |
1007 | ||
1008 | if (tries != 99) | |
1009 | dev_dbg(chan2dev(d40c), | |
1010 | "[%s] workaround enable S%cLNK (%d tries)\n", | |
1011 | __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D', | |
1012 | 100 - tries); | |
1013 | ||
1014 | WARN_ON(!tries); | |
1015 | } | |
1016 | ||
8d318a50 LW |
1017 | static void d40_config_set_event(struct d40_chan *d40c, bool do_enable) |
1018 | { | |
8d318a50 LW |
1019 | unsigned long flags; |
1020 | ||
8d318a50 LW |
1021 | spin_lock_irqsave(&d40c->phy_chan->lock, flags); |
1022 | ||
1023 | /* Enable event line connected to device (or memcpy) */ | |
1024 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || | |
1025 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) { | |
1026 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
1027 | ||
262d2915 RV |
1028 | __d40_config_set_event(d40c, do_enable, event, |
1029 | D40_CHAN_REG_SSLNK); | |
8d318a50 | 1030 | } |
262d2915 | 1031 | |
8d318a50 LW |
1032 | if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) { |
1033 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
1034 | ||
262d2915 RV |
1035 | __d40_config_set_event(d40c, do_enable, event, |
1036 | D40_CHAN_REG_SDLNK); | |
8d318a50 LW |
1037 | } |
1038 | ||
1039 | spin_unlock_irqrestore(&d40c->phy_chan->lock, flags); | |
1040 | } | |
1041 | ||
a5ebca47 | 1042 | static u32 d40_chan_has_events(struct d40_chan *d40c) |
8d318a50 | 1043 | { |
8ca84687 | 1044 | void __iomem *chanbase = chan_base(d40c); |
be8cb7df | 1045 | u32 val; |
8d318a50 | 1046 | |
8ca84687 RV |
1047 | val = readl(chanbase + D40_CHAN_REG_SSLNK); |
1048 | val |= readl(chanbase + D40_CHAN_REG_SDLNK); | |
be8cb7df | 1049 | |
a5ebca47 | 1050 | return val; |
8d318a50 LW |
1051 | } |
1052 | ||
20a5b6d0 RV |
1053 | static u32 d40_get_prmo(struct d40_chan *d40c) |
1054 | { | |
1055 | static const unsigned int phy_map[] = { | |
1056 | [STEDMA40_PCHAN_BASIC_MODE] | |
1057 | = D40_DREG_PRMO_PCHAN_BASIC, | |
1058 | [STEDMA40_PCHAN_MODULO_MODE] | |
1059 | = D40_DREG_PRMO_PCHAN_MODULO, | |
1060 | [STEDMA40_PCHAN_DOUBLE_DST_MODE] | |
1061 | = D40_DREG_PRMO_PCHAN_DOUBLE_DST, | |
1062 | }; | |
1063 | static const unsigned int log_map[] = { | |
1064 | [STEDMA40_LCHAN_SRC_PHY_DST_LOG] | |
1065 | = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG, | |
1066 | [STEDMA40_LCHAN_SRC_LOG_DST_PHY] | |
1067 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY, | |
1068 | [STEDMA40_LCHAN_SRC_LOG_DST_LOG] | |
1069 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG, | |
1070 | }; | |
1071 | ||
724a8577 | 1072 | if (chan_is_physical(d40c)) |
20a5b6d0 RV |
1073 | return phy_map[d40c->dma_cfg.mode_opt]; |
1074 | else | |
1075 | return log_map[d40c->dma_cfg.mode_opt]; | |
1076 | } | |
1077 | ||
b55912c6 | 1078 | static void d40_config_write(struct d40_chan *d40c) |
8d318a50 LW |
1079 | { |
1080 | u32 addr_base; | |
1081 | u32 var; | |
8d318a50 LW |
1082 | |
1083 | /* Odd addresses are even addresses + 4 */ | |
1084 | addr_base = (d40c->phy_chan->num % 2) * 4; | |
1085 | /* Setup channel mode to logical or physical */ | |
724a8577 | 1086 | var = ((u32)(chan_is_logical(d40c)) + 1) << |
8d318a50 LW |
1087 | D40_CHAN_POS(d40c->phy_chan->num); |
1088 | writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); | |
1089 | ||
1090 | /* Setup operational mode option register */ | |
20a5b6d0 | 1091 | var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num); |
8d318a50 LW |
1092 | |
1093 | writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); | |
1094 | ||
724a8577 | 1095 | if (chan_is_logical(d40c)) { |
8ca84687 RV |
1096 | int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) |
1097 | & D40_SREG_ELEM_LOG_LIDX_MASK; | |
1098 | void __iomem *chanbase = chan_base(d40c); | |
1099 | ||
8d318a50 | 1100 | /* Set default config for CFG reg */ |
8ca84687 RV |
1101 | writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG); |
1102 | writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG); | |
8d318a50 | 1103 | |
b55912c6 | 1104 | /* Set LIDX for lcla */ |
8ca84687 RV |
1105 | writel(lidx, chanbase + D40_CHAN_REG_SSELT); |
1106 | writel(lidx, chanbase + D40_CHAN_REG_SDELT); | |
8d318a50 | 1107 | } |
8d318a50 LW |
1108 | } |
1109 | ||
aa182ae2 JA |
1110 | static u32 d40_residue(struct d40_chan *d40c) |
1111 | { | |
1112 | u32 num_elt; | |
1113 | ||
724a8577 | 1114 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
1115 | num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK) |
1116 | >> D40_MEM_LCSP2_ECNT_POS; | |
8ca84687 RV |
1117 | else { |
1118 | u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT); | |
1119 | num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK) | |
1120 | >> D40_SREG_ELEM_PHY_ECNT_POS; | |
1121 | } | |
1122 | ||
aa182ae2 JA |
1123 | return num_elt * (1 << d40c->dma_cfg.dst_info.data_width); |
1124 | } | |
1125 | ||
1126 | static bool d40_tx_is_linked(struct d40_chan *d40c) | |
1127 | { | |
1128 | bool is_link; | |
1129 | ||
724a8577 | 1130 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
1131 | is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK; |
1132 | else | |
8ca84687 RV |
1133 | is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK) |
1134 | & D40_SREG_LNK_PHYS_LNK_MASK; | |
1135 | ||
aa182ae2 JA |
1136 | return is_link; |
1137 | } | |
1138 | ||
86eb5fb6 | 1139 | static int d40_pause(struct d40_chan *d40c) |
aa182ae2 | 1140 | { |
aa182ae2 JA |
1141 | int res = 0; |
1142 | unsigned long flags; | |
1143 | ||
3ac012af JA |
1144 | if (!d40c->busy) |
1145 | return 0; | |
1146 | ||
7fb3e75e | 1147 | pm_runtime_get_sync(d40c->base->dev); |
aa182ae2 JA |
1148 | spin_lock_irqsave(&d40c->lock, flags); |
1149 | ||
1150 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); | |
1151 | if (res == 0) { | |
724a8577 | 1152 | if (chan_is_logical(d40c)) { |
aa182ae2 JA |
1153 | d40_config_set_event(d40c, false); |
1154 | /* Resume the other logical channels if any */ | |
1155 | if (d40_chan_has_events(d40c)) | |
1156 | res = d40_channel_execute_command(d40c, | |
1157 | D40_DMA_RUN); | |
1158 | } | |
1159 | } | |
7fb3e75e N |
1160 | pm_runtime_mark_last_busy(d40c->base->dev); |
1161 | pm_runtime_put_autosuspend(d40c->base->dev); | |
aa182ae2 JA |
1162 | spin_unlock_irqrestore(&d40c->lock, flags); |
1163 | return res; | |
1164 | } | |
1165 | ||
86eb5fb6 | 1166 | static int d40_resume(struct d40_chan *d40c) |
aa182ae2 | 1167 | { |
aa182ae2 JA |
1168 | int res = 0; |
1169 | unsigned long flags; | |
1170 | ||
3ac012af JA |
1171 | if (!d40c->busy) |
1172 | return 0; | |
1173 | ||
aa182ae2 | 1174 | spin_lock_irqsave(&d40c->lock, flags); |
7fb3e75e | 1175 | pm_runtime_get_sync(d40c->base->dev); |
aa182ae2 | 1176 | if (d40c->base->rev == 0) |
724a8577 | 1177 | if (chan_is_logical(d40c)) { |
aa182ae2 JA |
1178 | res = d40_channel_execute_command(d40c, |
1179 | D40_DMA_SUSPEND_REQ); | |
1180 | goto no_suspend; | |
1181 | } | |
1182 | ||
1183 | /* If bytes left to transfer or linked tx resume job */ | |
1184 | if (d40_residue(d40c) || d40_tx_is_linked(d40c)) { | |
1185 | ||
724a8577 | 1186 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
1187 | d40_config_set_event(d40c, true); |
1188 | ||
1189 | res = d40_channel_execute_command(d40c, D40_DMA_RUN); | |
1190 | } | |
1191 | ||
1192 | no_suspend: | |
7fb3e75e N |
1193 | pm_runtime_mark_last_busy(d40c->base->dev); |
1194 | pm_runtime_put_autosuspend(d40c->base->dev); | |
aa182ae2 JA |
1195 | spin_unlock_irqrestore(&d40c->lock, flags); |
1196 | return res; | |
1197 | } | |
1198 | ||
86eb5fb6 RV |
1199 | static int d40_terminate_all(struct d40_chan *chan) |
1200 | { | |
1201 | unsigned long flags; | |
1202 | int ret = 0; | |
1203 | ||
1204 | ret = d40_pause(chan); | |
1205 | if (!ret && chan_is_physical(chan)) | |
1206 | ret = d40_channel_execute_command(chan, D40_DMA_STOP); | |
1207 | ||
1208 | spin_lock_irqsave(&chan->lock, flags); | |
1209 | d40_term_all(chan); | |
1210 | spin_unlock_irqrestore(&chan->lock, flags); | |
1211 | ||
1212 | return ret; | |
1213 | } | |
1214 | ||
8d318a50 LW |
1215 | static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx) |
1216 | { | |
1217 | struct d40_chan *d40c = container_of(tx->chan, | |
1218 | struct d40_chan, | |
1219 | chan); | |
1220 | struct d40_desc *d40d = container_of(tx, struct d40_desc, txd); | |
1221 | unsigned long flags; | |
1222 | ||
1223 | spin_lock_irqsave(&d40c->lock, flags); | |
1224 | ||
aa182ae2 JA |
1225 | d40c->chan.cookie++; |
1226 | ||
1227 | if (d40c->chan.cookie < 0) | |
1228 | d40c->chan.cookie = 1; | |
1229 | ||
1230 | d40d->txd.cookie = d40c->chan.cookie; | |
1231 | ||
8d318a50 LW |
1232 | d40_desc_queue(d40c, d40d); |
1233 | ||
1234 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1235 | ||
1236 | return tx->cookie; | |
1237 | } | |
1238 | ||
1239 | static int d40_start(struct d40_chan *d40c) | |
1240 | { | |
f4185592 LW |
1241 | if (d40c->base->rev == 0) { |
1242 | int err; | |
1243 | ||
724a8577 | 1244 | if (chan_is_logical(d40c)) { |
f4185592 LW |
1245 | err = d40_channel_execute_command(d40c, |
1246 | D40_DMA_SUSPEND_REQ); | |
1247 | if (err) | |
1248 | return err; | |
1249 | } | |
1250 | } | |
1251 | ||
724a8577 | 1252 | if (chan_is_logical(d40c)) |
8d318a50 | 1253 | d40_config_set_event(d40c, true); |
8d318a50 | 1254 | |
0c32269d | 1255 | return d40_channel_execute_command(d40c, D40_DMA_RUN); |
8d318a50 LW |
1256 | } |
1257 | ||
1258 | static struct d40_desc *d40_queue_start(struct d40_chan *d40c) | |
1259 | { | |
1260 | struct d40_desc *d40d; | |
1261 | int err; | |
1262 | ||
1263 | /* Start queued jobs, if any */ | |
1264 | d40d = d40_first_queued(d40c); | |
1265 | ||
1266 | if (d40d != NULL) { | |
7fb3e75e N |
1267 | if (!d40c->busy) |
1268 | d40c->busy = true; | |
1269 | ||
1270 | pm_runtime_get_sync(d40c->base->dev); | |
8d318a50 LW |
1271 | |
1272 | /* Remove from queue */ | |
1273 | d40_desc_remove(d40d); | |
1274 | ||
1275 | /* Add to active queue */ | |
1276 | d40_desc_submit(d40c, d40d); | |
1277 | ||
7d83a854 RV |
1278 | /* Initiate DMA job */ |
1279 | d40_desc_load(d40c, d40d); | |
8d318a50 | 1280 | |
7d83a854 RV |
1281 | /* Start dma job */ |
1282 | err = d40_start(d40c); | |
8d318a50 | 1283 | |
7d83a854 RV |
1284 | if (err) |
1285 | return NULL; | |
8d318a50 LW |
1286 | } |
1287 | ||
1288 | return d40d; | |
1289 | } | |
1290 | ||
1291 | /* called from interrupt context */ | |
1292 | static void dma_tc_handle(struct d40_chan *d40c) | |
1293 | { | |
1294 | struct d40_desc *d40d; | |
1295 | ||
8d318a50 LW |
1296 | /* Get first active entry from list */ |
1297 | d40d = d40_first_active_get(d40c); | |
1298 | ||
1299 | if (d40d == NULL) | |
1300 | return; | |
1301 | ||
0c842b55 RV |
1302 | if (d40d->cyclic) { |
1303 | /* | |
1304 | * If this was a paritially loaded list, we need to reloaded | |
1305 | * it, and only when the list is completed. We need to check | |
1306 | * for done because the interrupt will hit for every link, and | |
1307 | * not just the last one. | |
1308 | */ | |
1309 | if (d40d->lli_current < d40d->lli_len | |
1310 | && !d40_tx_is_linked(d40c) | |
1311 | && !d40_residue(d40c)) { | |
1312 | d40_lcla_free_all(d40c, d40d); | |
1313 | d40_desc_load(d40c, d40d); | |
1314 | (void) d40_start(d40c); | |
8d318a50 | 1315 | |
0c842b55 RV |
1316 | if (d40d->lli_current == d40d->lli_len) |
1317 | d40d->lli_current = 0; | |
1318 | } | |
1319 | } else { | |
1320 | d40_lcla_free_all(d40c, d40d); | |
8d318a50 | 1321 | |
0c842b55 RV |
1322 | if (d40d->lli_current < d40d->lli_len) { |
1323 | d40_desc_load(d40c, d40d); | |
1324 | /* Start dma job */ | |
1325 | (void) d40_start(d40c); | |
1326 | return; | |
1327 | } | |
1328 | ||
1329 | if (d40_queue_start(d40c) == NULL) | |
1330 | d40c->busy = false; | |
7fb3e75e N |
1331 | pm_runtime_mark_last_busy(d40c->base->dev); |
1332 | pm_runtime_put_autosuspend(d40c->base->dev); | |
0c842b55 | 1333 | } |
8d318a50 LW |
1334 | |
1335 | d40c->pending_tx++; | |
1336 | tasklet_schedule(&d40c->tasklet); | |
1337 | ||
1338 | } | |
1339 | ||
1340 | static void dma_tasklet(unsigned long data) | |
1341 | { | |
1342 | struct d40_chan *d40c = (struct d40_chan *) data; | |
767a9675 | 1343 | struct d40_desc *d40d; |
8d318a50 LW |
1344 | unsigned long flags; |
1345 | dma_async_tx_callback callback; | |
1346 | void *callback_param; | |
1347 | ||
1348 | spin_lock_irqsave(&d40c->lock, flags); | |
1349 | ||
1350 | /* Get first active entry from list */ | |
767a9675 | 1351 | d40d = d40_first_active_get(d40c); |
767a9675 | 1352 | if (d40d == NULL) |
8d318a50 LW |
1353 | goto err; |
1354 | ||
0c842b55 RV |
1355 | if (!d40d->cyclic) |
1356 | d40c->completed = d40d->txd.cookie; | |
8d318a50 LW |
1357 | |
1358 | /* | |
1359 | * If terminating a channel pending_tx is set to zero. | |
1360 | * This prevents any finished active jobs to return to the client. | |
1361 | */ | |
1362 | if (d40c->pending_tx == 0) { | |
1363 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1364 | return; | |
1365 | } | |
1366 | ||
1367 | /* Callback to client */ | |
767a9675 JA |
1368 | callback = d40d->txd.callback; |
1369 | callback_param = d40d->txd.callback_param; | |
1370 | ||
0c842b55 RV |
1371 | if (!d40d->cyclic) { |
1372 | if (async_tx_test_ack(&d40d->txd)) { | |
767a9675 | 1373 | d40_desc_remove(d40d); |
0c842b55 RV |
1374 | d40_desc_free(d40c, d40d); |
1375 | } else { | |
1376 | if (!d40d->is_in_client_list) { | |
1377 | d40_desc_remove(d40d); | |
1378 | d40_lcla_free_all(d40c, d40d); | |
1379 | list_add_tail(&d40d->node, &d40c->client); | |
1380 | d40d->is_in_client_list = true; | |
1381 | } | |
8d318a50 LW |
1382 | } |
1383 | } | |
1384 | ||
1385 | d40c->pending_tx--; | |
1386 | ||
1387 | if (d40c->pending_tx) | |
1388 | tasklet_schedule(&d40c->tasklet); | |
1389 | ||
1390 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1391 | ||
767a9675 | 1392 | if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT)) |
8d318a50 LW |
1393 | callback(callback_param); |
1394 | ||
1395 | return; | |
1396 | ||
1397 | err: | |
25985edc | 1398 | /* Rescue manoeuvre if receiving double interrupts */ |
8d318a50 LW |
1399 | if (d40c->pending_tx > 0) |
1400 | d40c->pending_tx--; | |
1401 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1402 | } | |
1403 | ||
1404 | static irqreturn_t d40_handle_interrupt(int irq, void *data) | |
1405 | { | |
1406 | static const struct d40_interrupt_lookup il[] = { | |
1407 | {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0}, | |
1408 | {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32}, | |
1409 | {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64}, | |
1410 | {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96}, | |
1411 | {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0}, | |
1412 | {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32}, | |
1413 | {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64}, | |
1414 | {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96}, | |
1415 | {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN}, | |
1416 | {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN}, | |
1417 | }; | |
1418 | ||
1419 | int i; | |
1420 | u32 regs[ARRAY_SIZE(il)]; | |
8d318a50 LW |
1421 | u32 idx; |
1422 | u32 row; | |
1423 | long chan = -1; | |
1424 | struct d40_chan *d40c; | |
1425 | unsigned long flags; | |
1426 | struct d40_base *base = data; | |
1427 | ||
1428 | spin_lock_irqsave(&base->interrupt_lock, flags); | |
1429 | ||
1430 | /* Read interrupt status of both logical and physical channels */ | |
1431 | for (i = 0; i < ARRAY_SIZE(il); i++) | |
1432 | regs[i] = readl(base->virtbase + il[i].src); | |
1433 | ||
1434 | for (;;) { | |
1435 | ||
1436 | chan = find_next_bit((unsigned long *)regs, | |
1437 | BITS_PER_LONG * ARRAY_SIZE(il), chan + 1); | |
1438 | ||
1439 | /* No more set bits found? */ | |
1440 | if (chan == BITS_PER_LONG * ARRAY_SIZE(il)) | |
1441 | break; | |
1442 | ||
1443 | row = chan / BITS_PER_LONG; | |
1444 | idx = chan & (BITS_PER_LONG - 1); | |
1445 | ||
1446 | /* ACK interrupt */ | |
1b00348d | 1447 | writel(1 << idx, base->virtbase + il[row].clr); |
8d318a50 LW |
1448 | |
1449 | if (il[row].offset == D40_PHY_CHAN) | |
1450 | d40c = base->lookup_phy_chans[idx]; | |
1451 | else | |
1452 | d40c = base->lookup_log_chans[il[row].offset + idx]; | |
1453 | spin_lock(&d40c->lock); | |
1454 | ||
1455 | if (!il[row].is_error) | |
1456 | dma_tc_handle(d40c); | |
1457 | else | |
6db5a8ba RV |
1458 | d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n", |
1459 | chan, il[row].offset, idx); | |
8d318a50 LW |
1460 | |
1461 | spin_unlock(&d40c->lock); | |
1462 | } | |
1463 | ||
1464 | spin_unlock_irqrestore(&base->interrupt_lock, flags); | |
1465 | ||
1466 | return IRQ_HANDLED; | |
1467 | } | |
1468 | ||
8d318a50 LW |
1469 | static int d40_validate_conf(struct d40_chan *d40c, |
1470 | struct stedma40_chan_cfg *conf) | |
1471 | { | |
1472 | int res = 0; | |
1473 | u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type); | |
1474 | u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type); | |
38bdbf02 | 1475 | bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; |
8d318a50 | 1476 | |
0747c7ba | 1477 | if (!conf->dir) { |
6db5a8ba | 1478 | chan_err(d40c, "Invalid direction.\n"); |
0747c7ba LW |
1479 | res = -EINVAL; |
1480 | } | |
1481 | ||
1482 | if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY && | |
1483 | d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 && | |
1484 | d40c->runtime_addr == 0) { | |
1485 | ||
6db5a8ba RV |
1486 | chan_err(d40c, "Invalid TX channel address (%d)\n", |
1487 | conf->dst_dev_type); | |
0747c7ba LW |
1488 | res = -EINVAL; |
1489 | } | |
1490 | ||
1491 | if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY && | |
1492 | d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 && | |
1493 | d40c->runtime_addr == 0) { | |
6db5a8ba RV |
1494 | chan_err(d40c, "Invalid RX channel address (%d)\n", |
1495 | conf->src_dev_type); | |
0747c7ba LW |
1496 | res = -EINVAL; |
1497 | } | |
1498 | ||
1499 | if (conf->dir == STEDMA40_MEM_TO_PERIPH && | |
8d318a50 | 1500 | dst_event_group == STEDMA40_DEV_DST_MEMORY) { |
6db5a8ba | 1501 | chan_err(d40c, "Invalid dst\n"); |
8d318a50 LW |
1502 | res = -EINVAL; |
1503 | } | |
1504 | ||
0747c7ba | 1505 | if (conf->dir == STEDMA40_PERIPH_TO_MEM && |
8d318a50 | 1506 | src_event_group == STEDMA40_DEV_SRC_MEMORY) { |
6db5a8ba | 1507 | chan_err(d40c, "Invalid src\n"); |
8d318a50 LW |
1508 | res = -EINVAL; |
1509 | } | |
1510 | ||
1511 | if (src_event_group == STEDMA40_DEV_SRC_MEMORY && | |
1512 | dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) { | |
6db5a8ba | 1513 | chan_err(d40c, "No event line\n"); |
8d318a50 LW |
1514 | res = -EINVAL; |
1515 | } | |
1516 | ||
1517 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH && | |
1518 | (src_event_group != dst_event_group)) { | |
6db5a8ba | 1519 | chan_err(d40c, "Invalid event group\n"); |
8d318a50 LW |
1520 | res = -EINVAL; |
1521 | } | |
1522 | ||
1523 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) { | |
1524 | /* | |
1525 | * DMAC HW supports it. Will be added to this driver, | |
1526 | * in case any dma client requires it. | |
1527 | */ | |
6db5a8ba | 1528 | chan_err(d40c, "periph to periph not supported\n"); |
8d318a50 LW |
1529 | res = -EINVAL; |
1530 | } | |
1531 | ||
d49278e3 PF |
1532 | if (d40_psize_2_burst_size(is_log, conf->src_info.psize) * |
1533 | (1 << conf->src_info.data_width) != | |
1534 | d40_psize_2_burst_size(is_log, conf->dst_info.psize) * | |
1535 | (1 << conf->dst_info.data_width)) { | |
1536 | /* | |
1537 | * The DMAC hardware only supports | |
1538 | * src (burst x width) == dst (burst x width) | |
1539 | */ | |
1540 | ||
6db5a8ba | 1541 | chan_err(d40c, "src (burst x width) != dst (burst x width)\n"); |
d49278e3 PF |
1542 | res = -EINVAL; |
1543 | } | |
1544 | ||
8d318a50 LW |
1545 | return res; |
1546 | } | |
1547 | ||
1548 | static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src, | |
4aed79b2 | 1549 | int log_event_line, bool is_log) |
8d318a50 LW |
1550 | { |
1551 | unsigned long flags; | |
1552 | spin_lock_irqsave(&phy->lock, flags); | |
4aed79b2 | 1553 | if (!is_log) { |
8d318a50 LW |
1554 | /* Physical interrupts are masked per physical full channel */ |
1555 | if (phy->allocated_src == D40_ALLOC_FREE && | |
1556 | phy->allocated_dst == D40_ALLOC_FREE) { | |
1557 | phy->allocated_dst = D40_ALLOC_PHY; | |
1558 | phy->allocated_src = D40_ALLOC_PHY; | |
1559 | goto found; | |
1560 | } else | |
1561 | goto not_found; | |
1562 | } | |
1563 | ||
1564 | /* Logical channel */ | |
1565 | if (is_src) { | |
1566 | if (phy->allocated_src == D40_ALLOC_PHY) | |
1567 | goto not_found; | |
1568 | ||
1569 | if (phy->allocated_src == D40_ALLOC_FREE) | |
1570 | phy->allocated_src = D40_ALLOC_LOG_FREE; | |
1571 | ||
1572 | if (!(phy->allocated_src & (1 << log_event_line))) { | |
1573 | phy->allocated_src |= 1 << log_event_line; | |
1574 | goto found; | |
1575 | } else | |
1576 | goto not_found; | |
1577 | } else { | |
1578 | if (phy->allocated_dst == D40_ALLOC_PHY) | |
1579 | goto not_found; | |
1580 | ||
1581 | if (phy->allocated_dst == D40_ALLOC_FREE) | |
1582 | phy->allocated_dst = D40_ALLOC_LOG_FREE; | |
1583 | ||
1584 | if (!(phy->allocated_dst & (1 << log_event_line))) { | |
1585 | phy->allocated_dst |= 1 << log_event_line; | |
1586 | goto found; | |
1587 | } else | |
1588 | goto not_found; | |
1589 | } | |
1590 | ||
1591 | not_found: | |
1592 | spin_unlock_irqrestore(&phy->lock, flags); | |
1593 | return false; | |
1594 | found: | |
1595 | spin_unlock_irqrestore(&phy->lock, flags); | |
1596 | return true; | |
1597 | } | |
1598 | ||
1599 | static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, | |
1600 | int log_event_line) | |
1601 | { | |
1602 | unsigned long flags; | |
1603 | bool is_free = false; | |
1604 | ||
1605 | spin_lock_irqsave(&phy->lock, flags); | |
1606 | if (!log_event_line) { | |
8d318a50 LW |
1607 | phy->allocated_dst = D40_ALLOC_FREE; |
1608 | phy->allocated_src = D40_ALLOC_FREE; | |
1609 | is_free = true; | |
1610 | goto out; | |
1611 | } | |
1612 | ||
1613 | /* Logical channel */ | |
1614 | if (is_src) { | |
1615 | phy->allocated_src &= ~(1 << log_event_line); | |
1616 | if (phy->allocated_src == D40_ALLOC_LOG_FREE) | |
1617 | phy->allocated_src = D40_ALLOC_FREE; | |
1618 | } else { | |
1619 | phy->allocated_dst &= ~(1 << log_event_line); | |
1620 | if (phy->allocated_dst == D40_ALLOC_LOG_FREE) | |
1621 | phy->allocated_dst = D40_ALLOC_FREE; | |
1622 | } | |
1623 | ||
1624 | is_free = ((phy->allocated_src | phy->allocated_dst) == | |
1625 | D40_ALLOC_FREE); | |
1626 | ||
1627 | out: | |
1628 | spin_unlock_irqrestore(&phy->lock, flags); | |
1629 | ||
1630 | return is_free; | |
1631 | } | |
1632 | ||
1633 | static int d40_allocate_channel(struct d40_chan *d40c) | |
1634 | { | |
1635 | int dev_type; | |
1636 | int event_group; | |
1637 | int event_line; | |
1638 | struct d40_phy_res *phys; | |
1639 | int i; | |
1640 | int j; | |
1641 | int log_num; | |
1642 | bool is_src; | |
38bdbf02 | 1643 | bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL; |
8d318a50 LW |
1644 | |
1645 | phys = d40c->base->phy_res; | |
1646 | ||
1647 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { | |
1648 | dev_type = d40c->dma_cfg.src_dev_type; | |
1649 | log_num = 2 * dev_type; | |
1650 | is_src = true; | |
1651 | } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || | |
1652 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1653 | /* dst event lines are used for logical memcpy */ | |
1654 | dev_type = d40c->dma_cfg.dst_dev_type; | |
1655 | log_num = 2 * dev_type + 1; | |
1656 | is_src = false; | |
1657 | } else | |
1658 | return -EINVAL; | |
1659 | ||
1660 | event_group = D40_TYPE_TO_GROUP(dev_type); | |
1661 | event_line = D40_TYPE_TO_EVENT(dev_type); | |
1662 | ||
1663 | if (!is_log) { | |
1664 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1665 | /* Find physical half channel */ | |
1666 | for (i = 0; i < d40c->base->num_phy_chans; i++) { | |
1667 | ||
4aed79b2 MM |
1668 | if (d40_alloc_mask_set(&phys[i], is_src, |
1669 | 0, is_log)) | |
8d318a50 LW |
1670 | goto found_phy; |
1671 | } | |
1672 | } else | |
1673 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { | |
1674 | int phy_num = j + event_group * 2; | |
1675 | for (i = phy_num; i < phy_num + 2; i++) { | |
508849ad LW |
1676 | if (d40_alloc_mask_set(&phys[i], |
1677 | is_src, | |
1678 | 0, | |
1679 | is_log)) | |
8d318a50 LW |
1680 | goto found_phy; |
1681 | } | |
1682 | } | |
1683 | return -EINVAL; | |
1684 | found_phy: | |
1685 | d40c->phy_chan = &phys[i]; | |
1686 | d40c->log_num = D40_PHY_CHAN; | |
1687 | goto out; | |
1688 | } | |
1689 | if (dev_type == -1) | |
1690 | return -EINVAL; | |
1691 | ||
1692 | /* Find logical channel */ | |
1693 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { | |
1694 | int phy_num = j + event_group * 2; | |
1695 | /* | |
1696 | * Spread logical channels across all available physical rather | |
1697 | * than pack every logical channel at the first available phy | |
1698 | * channels. | |
1699 | */ | |
1700 | if (is_src) { | |
1701 | for (i = phy_num; i < phy_num + 2; i++) { | |
1702 | if (d40_alloc_mask_set(&phys[i], is_src, | |
4aed79b2 | 1703 | event_line, is_log)) |
8d318a50 LW |
1704 | goto found_log; |
1705 | } | |
1706 | } else { | |
1707 | for (i = phy_num + 1; i >= phy_num; i--) { | |
1708 | if (d40_alloc_mask_set(&phys[i], is_src, | |
4aed79b2 | 1709 | event_line, is_log)) |
8d318a50 LW |
1710 | goto found_log; |
1711 | } | |
1712 | } | |
1713 | } | |
1714 | return -EINVAL; | |
1715 | ||
1716 | found_log: | |
1717 | d40c->phy_chan = &phys[i]; | |
1718 | d40c->log_num = log_num; | |
1719 | out: | |
1720 | ||
1721 | if (is_log) | |
1722 | d40c->base->lookup_log_chans[d40c->log_num] = d40c; | |
1723 | else | |
1724 | d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; | |
1725 | ||
1726 | return 0; | |
1727 | ||
1728 | } | |
1729 | ||
8d318a50 LW |
1730 | static int d40_config_memcpy(struct d40_chan *d40c) |
1731 | { | |
1732 | dma_cap_mask_t cap = d40c->chan.device->cap_mask; | |
1733 | ||
1734 | if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { | |
1735 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log; | |
1736 | d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY; | |
1737 | d40c->dma_cfg.dst_dev_type = d40c->base->plat_data-> | |
1738 | memcpy[d40c->chan.chan_id]; | |
1739 | ||
1740 | } else if (dma_has_cap(DMA_MEMCPY, cap) && | |
1741 | dma_has_cap(DMA_SLAVE, cap)) { | |
1742 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy; | |
1743 | } else { | |
6db5a8ba | 1744 | chan_err(d40c, "No memcpy\n"); |
8d318a50 LW |
1745 | return -EINVAL; |
1746 | } | |
1747 | ||
1748 | return 0; | |
1749 | } | |
1750 | ||
1751 | ||
1752 | static int d40_free_dma(struct d40_chan *d40c) | |
1753 | { | |
1754 | ||
1755 | int res = 0; | |
d181b3a8 | 1756 | u32 event; |
8d318a50 LW |
1757 | struct d40_phy_res *phy = d40c->phy_chan; |
1758 | bool is_src; | |
1759 | ||
1760 | /* Terminate all queued and active transfers */ | |
1761 | d40_term_all(d40c); | |
1762 | ||
1763 | if (phy == NULL) { | |
6db5a8ba | 1764 | chan_err(d40c, "phy == null\n"); |
8d318a50 LW |
1765 | return -EINVAL; |
1766 | } | |
1767 | ||
1768 | if (phy->allocated_src == D40_ALLOC_FREE && | |
1769 | phy->allocated_dst == D40_ALLOC_FREE) { | |
6db5a8ba | 1770 | chan_err(d40c, "channel already free\n"); |
8d318a50 LW |
1771 | return -EINVAL; |
1772 | } | |
1773 | ||
8d318a50 LW |
1774 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
1775 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1776 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
8d318a50 LW |
1777 | is_src = false; |
1778 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { | |
1779 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
8d318a50 LW |
1780 | is_src = true; |
1781 | } else { | |
6db5a8ba | 1782 | chan_err(d40c, "Unknown direction\n"); |
8d318a50 LW |
1783 | return -EINVAL; |
1784 | } | |
1785 | ||
7fb3e75e | 1786 | pm_runtime_get_sync(d40c->base->dev); |
d181b3a8 JA |
1787 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); |
1788 | if (res) { | |
6db5a8ba | 1789 | chan_err(d40c, "suspend failed\n"); |
7fb3e75e | 1790 | goto out; |
d181b3a8 JA |
1791 | } |
1792 | ||
724a8577 | 1793 | if (chan_is_logical(d40c)) { |
d181b3a8 | 1794 | /* Release logical channel, deactivate the event line */ |
8d318a50 | 1795 | |
d181b3a8 | 1796 | d40_config_set_event(d40c, false); |
8d318a50 LW |
1797 | d40c->base->lookup_log_chans[d40c->log_num] = NULL; |
1798 | ||
1799 | /* | |
1800 | * Check if there are more logical allocation | |
1801 | * on this phy channel. | |
1802 | */ | |
1803 | if (!d40_alloc_mask_free(phy, is_src, event)) { | |
1804 | /* Resume the other logical channels if any */ | |
1805 | if (d40_chan_has_events(d40c)) { | |
1806 | res = d40_channel_execute_command(d40c, | |
1807 | D40_DMA_RUN); | |
7fb3e75e | 1808 | if (res) |
6db5a8ba RV |
1809 | chan_err(d40c, |
1810 | "Executing RUN command\n"); | |
8d318a50 | 1811 | } |
7fb3e75e | 1812 | goto out; |
8d318a50 | 1813 | } |
d181b3a8 JA |
1814 | } else { |
1815 | (void) d40_alloc_mask_free(phy, is_src, 0); | |
1816 | } | |
8d318a50 LW |
1817 | |
1818 | /* Release physical channel */ | |
1819 | res = d40_channel_execute_command(d40c, D40_DMA_STOP); | |
1820 | if (res) { | |
6db5a8ba | 1821 | chan_err(d40c, "Failed to stop channel\n"); |
7fb3e75e | 1822 | goto out; |
8d318a50 | 1823 | } |
7fb3e75e N |
1824 | |
1825 | if (d40c->busy) { | |
1826 | pm_runtime_mark_last_busy(d40c->base->dev); | |
1827 | pm_runtime_put_autosuspend(d40c->base->dev); | |
1828 | } | |
1829 | ||
1830 | d40c->busy = false; | |
8d318a50 | 1831 | d40c->phy_chan = NULL; |
ce2ca125 | 1832 | d40c->configured = false; |
8d318a50 | 1833 | d40c->base->lookup_phy_chans[phy->num] = NULL; |
7fb3e75e | 1834 | out: |
8d318a50 | 1835 | |
7fb3e75e N |
1836 | pm_runtime_mark_last_busy(d40c->base->dev); |
1837 | pm_runtime_put_autosuspend(d40c->base->dev); | |
1838 | return res; | |
8d318a50 LW |
1839 | } |
1840 | ||
a5ebca47 JA |
1841 | static bool d40_is_paused(struct d40_chan *d40c) |
1842 | { | |
8ca84687 | 1843 | void __iomem *chanbase = chan_base(d40c); |
a5ebca47 JA |
1844 | bool is_paused = false; |
1845 | unsigned long flags; | |
1846 | void __iomem *active_reg; | |
1847 | u32 status; | |
1848 | u32 event; | |
a5ebca47 JA |
1849 | |
1850 | spin_lock_irqsave(&d40c->lock, flags); | |
1851 | ||
724a8577 | 1852 | if (chan_is_physical(d40c)) { |
a5ebca47 JA |
1853 | if (d40c->phy_chan->num % 2 == 0) |
1854 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; | |
1855 | else | |
1856 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; | |
1857 | ||
1858 | status = (readl(active_reg) & | |
1859 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
1860 | D40_CHAN_POS(d40c->phy_chan->num); | |
1861 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) | |
1862 | is_paused = true; | |
1863 | ||
1864 | goto _exit; | |
1865 | } | |
1866 | ||
a5ebca47 | 1867 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
9dbfbd35 | 1868 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
a5ebca47 | 1869 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); |
8ca84687 | 1870 | status = readl(chanbase + D40_CHAN_REG_SDLNK); |
9dbfbd35 | 1871 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
a5ebca47 | 1872 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); |
8ca84687 | 1873 | status = readl(chanbase + D40_CHAN_REG_SSLNK); |
9dbfbd35 | 1874 | } else { |
6db5a8ba | 1875 | chan_err(d40c, "Unknown direction\n"); |
a5ebca47 JA |
1876 | goto _exit; |
1877 | } | |
9dbfbd35 | 1878 | |
a5ebca47 JA |
1879 | status = (status & D40_EVENTLINE_MASK(event)) >> |
1880 | D40_EVENTLINE_POS(event); | |
1881 | ||
1882 | if (status != D40_DMA_RUN) | |
1883 | is_paused = true; | |
a5ebca47 JA |
1884 | _exit: |
1885 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1886 | return is_paused; | |
1887 | ||
1888 | } | |
1889 | ||
1890 | ||
8d318a50 LW |
1891 | static u32 stedma40_residue(struct dma_chan *chan) |
1892 | { | |
1893 | struct d40_chan *d40c = | |
1894 | container_of(chan, struct d40_chan, chan); | |
1895 | u32 bytes_left; | |
1896 | unsigned long flags; | |
1897 | ||
1898 | spin_lock_irqsave(&d40c->lock, flags); | |
1899 | bytes_left = d40_residue(d40c); | |
1900 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1901 | ||
1902 | return bytes_left; | |
1903 | } | |
1904 | ||
3e3a0763 RV |
1905 | static int |
1906 | d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc, | |
1907 | struct scatterlist *sg_src, struct scatterlist *sg_dst, | |
822c5676 RV |
1908 | unsigned int sg_len, dma_addr_t src_dev_addr, |
1909 | dma_addr_t dst_dev_addr) | |
3e3a0763 RV |
1910 | { |
1911 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
1912 | struct stedma40_half_channel_info *src_info = &cfg->src_info; | |
1913 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; | |
5ed04b85 | 1914 | int ret; |
3e3a0763 | 1915 | |
5ed04b85 RV |
1916 | ret = d40_log_sg_to_lli(sg_src, sg_len, |
1917 | src_dev_addr, | |
1918 | desc->lli_log.src, | |
1919 | chan->log_def.lcsp1, | |
1920 | src_info->data_width, | |
1921 | dst_info->data_width); | |
1922 | ||
1923 | ret = d40_log_sg_to_lli(sg_dst, sg_len, | |
1924 | dst_dev_addr, | |
1925 | desc->lli_log.dst, | |
1926 | chan->log_def.lcsp3, | |
1927 | dst_info->data_width, | |
1928 | src_info->data_width); | |
1929 | ||
1930 | return ret < 0 ? ret : 0; | |
3e3a0763 RV |
1931 | } |
1932 | ||
1933 | static int | |
1934 | d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc, | |
1935 | struct scatterlist *sg_src, struct scatterlist *sg_dst, | |
822c5676 RV |
1936 | unsigned int sg_len, dma_addr_t src_dev_addr, |
1937 | dma_addr_t dst_dev_addr) | |
3e3a0763 | 1938 | { |
3e3a0763 RV |
1939 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
1940 | struct stedma40_half_channel_info *src_info = &cfg->src_info; | |
1941 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; | |
0c842b55 | 1942 | unsigned long flags = 0; |
3e3a0763 RV |
1943 | int ret; |
1944 | ||
0c842b55 RV |
1945 | if (desc->cyclic) |
1946 | flags |= LLI_CYCLIC | LLI_TERM_INT; | |
1947 | ||
3e3a0763 RV |
1948 | ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr, |
1949 | desc->lli_phy.src, | |
1950 | virt_to_phys(desc->lli_phy.src), | |
1951 | chan->src_def_cfg, | |
0c842b55 | 1952 | src_info, dst_info, flags); |
3e3a0763 RV |
1953 | |
1954 | ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr, | |
1955 | desc->lli_phy.dst, | |
1956 | virt_to_phys(desc->lli_phy.dst), | |
1957 | chan->dst_def_cfg, | |
0c842b55 | 1958 | dst_info, src_info, flags); |
3e3a0763 RV |
1959 | |
1960 | dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr, | |
1961 | desc->lli_pool.size, DMA_TO_DEVICE); | |
1962 | ||
1963 | return ret < 0 ? ret : 0; | |
1964 | } | |
1965 | ||
1966 | ||
5f81158f RV |
1967 | static struct d40_desc * |
1968 | d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg, | |
1969 | unsigned int sg_len, unsigned long dma_flags) | |
1970 | { | |
1971 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
1972 | struct d40_desc *desc; | |
dbd88788 | 1973 | int ret; |
5f81158f RV |
1974 | |
1975 | desc = d40_desc_get(chan); | |
1976 | if (!desc) | |
1977 | return NULL; | |
1978 | ||
1979 | desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width, | |
1980 | cfg->dst_info.data_width); | |
1981 | if (desc->lli_len < 0) { | |
1982 | chan_err(chan, "Unaligned size\n"); | |
dbd88788 RV |
1983 | goto err; |
1984 | } | |
5f81158f | 1985 | |
dbd88788 RV |
1986 | ret = d40_pool_lli_alloc(chan, desc, desc->lli_len); |
1987 | if (ret < 0) { | |
1988 | chan_err(chan, "Could not allocate lli\n"); | |
1989 | goto err; | |
5f81158f RV |
1990 | } |
1991 | ||
dbd88788 | 1992 | |
5f81158f RV |
1993 | desc->lli_current = 0; |
1994 | desc->txd.flags = dma_flags; | |
1995 | desc->txd.tx_submit = d40_tx_submit; | |
1996 | ||
1997 | dma_async_tx_descriptor_init(&desc->txd, &chan->chan); | |
1998 | ||
1999 | return desc; | |
dbd88788 RV |
2000 | |
2001 | err: | |
2002 | d40_desc_free(chan, desc); | |
2003 | return NULL; | |
5f81158f RV |
2004 | } |
2005 | ||
cade1d30 | 2006 | static dma_addr_t |
db8196df | 2007 | d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction) |
8d318a50 | 2008 | { |
cade1d30 RV |
2009 | struct stedma40_platform_data *plat = chan->base->plat_data; |
2010 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
711b9cea | 2011 | dma_addr_t addr = 0; |
cade1d30 RV |
2012 | |
2013 | if (chan->runtime_addr) | |
2014 | return chan->runtime_addr; | |
2015 | ||
db8196df | 2016 | if (direction == DMA_DEV_TO_MEM) |
cade1d30 | 2017 | addr = plat->dev_rx[cfg->src_dev_type]; |
db8196df | 2018 | else if (direction == DMA_MEM_TO_DEV) |
cade1d30 RV |
2019 | addr = plat->dev_tx[cfg->dst_dev_type]; |
2020 | ||
2021 | return addr; | |
2022 | } | |
2023 | ||
2024 | static struct dma_async_tx_descriptor * | |
2025 | d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, | |
2026 | struct scatterlist *sg_dst, unsigned int sg_len, | |
db8196df | 2027 | enum dma_transfer_direction direction, unsigned long dma_flags) |
cade1d30 RV |
2028 | { |
2029 | struct d40_chan *chan = container_of(dchan, struct d40_chan, chan); | |
822c5676 RV |
2030 | dma_addr_t src_dev_addr = 0; |
2031 | dma_addr_t dst_dev_addr = 0; | |
cade1d30 | 2032 | struct d40_desc *desc; |
2a614340 | 2033 | unsigned long flags; |
cade1d30 | 2034 | int ret; |
8d318a50 | 2035 | |
cade1d30 RV |
2036 | if (!chan->phy_chan) { |
2037 | chan_err(chan, "Cannot prepare unallocated channel\n"); | |
2038 | return NULL; | |
0d0f6b8b JA |
2039 | } |
2040 | ||
0c842b55 | 2041 | |
cade1d30 | 2042 | spin_lock_irqsave(&chan->lock, flags); |
8d318a50 | 2043 | |
cade1d30 RV |
2044 | desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags); |
2045 | if (desc == NULL) | |
8d318a50 LW |
2046 | goto err; |
2047 | ||
0c842b55 RV |
2048 | if (sg_next(&sg_src[sg_len - 1]) == sg_src) |
2049 | desc->cyclic = true; | |
2050 | ||
822c5676 RV |
2051 | if (direction != DMA_NONE) { |
2052 | dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); | |
2053 | ||
db8196df | 2054 | if (direction == DMA_DEV_TO_MEM) |
822c5676 | 2055 | src_dev_addr = dev_addr; |
db8196df | 2056 | else if (direction == DMA_MEM_TO_DEV) |
822c5676 RV |
2057 | dst_dev_addr = dev_addr; |
2058 | } | |
cade1d30 RV |
2059 | |
2060 | if (chan_is_logical(chan)) | |
2061 | ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst, | |
822c5676 | 2062 | sg_len, src_dev_addr, dst_dev_addr); |
cade1d30 RV |
2063 | else |
2064 | ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst, | |
822c5676 | 2065 | sg_len, src_dev_addr, dst_dev_addr); |
cade1d30 RV |
2066 | |
2067 | if (ret) { | |
2068 | chan_err(chan, "Failed to prepare %s sg job: %d\n", | |
2069 | chan_is_logical(chan) ? "log" : "phy", ret); | |
2070 | goto err; | |
8d318a50 LW |
2071 | } |
2072 | ||
82babbb3 PF |
2073 | /* |
2074 | * add descriptor to the prepare queue in order to be able | |
2075 | * to free them later in terminate_all | |
2076 | */ | |
2077 | list_add_tail(&desc->node, &chan->prepare_queue); | |
2078 | ||
cade1d30 RV |
2079 | spin_unlock_irqrestore(&chan->lock, flags); |
2080 | ||
2081 | return &desc->txd; | |
8d318a50 | 2082 | |
8d318a50 | 2083 | err: |
cade1d30 RV |
2084 | if (desc) |
2085 | d40_desc_free(chan, desc); | |
2086 | spin_unlock_irqrestore(&chan->lock, flags); | |
8d318a50 LW |
2087 | return NULL; |
2088 | } | |
8d318a50 LW |
2089 | |
2090 | bool stedma40_filter(struct dma_chan *chan, void *data) | |
2091 | { | |
2092 | struct stedma40_chan_cfg *info = data; | |
2093 | struct d40_chan *d40c = | |
2094 | container_of(chan, struct d40_chan, chan); | |
2095 | int err; | |
2096 | ||
2097 | if (data) { | |
2098 | err = d40_validate_conf(d40c, info); | |
2099 | if (!err) | |
2100 | d40c->dma_cfg = *info; | |
2101 | } else | |
2102 | err = d40_config_memcpy(d40c); | |
2103 | ||
ce2ca125 RV |
2104 | if (!err) |
2105 | d40c->configured = true; | |
2106 | ||
8d318a50 LW |
2107 | return err == 0; |
2108 | } | |
2109 | EXPORT_SYMBOL(stedma40_filter); | |
2110 | ||
ac2c0a38 RV |
2111 | static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src) |
2112 | { | |
2113 | bool realtime = d40c->dma_cfg.realtime; | |
2114 | bool highprio = d40c->dma_cfg.high_priority; | |
2115 | u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1; | |
2116 | u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1; | |
2117 | u32 event = D40_TYPE_TO_EVENT(dev_type); | |
2118 | u32 group = D40_TYPE_TO_GROUP(dev_type); | |
2119 | u32 bit = 1 << event; | |
2120 | ||
2121 | /* Destination event lines are stored in the upper halfword */ | |
2122 | if (!src) | |
2123 | bit <<= 16; | |
2124 | ||
2125 | writel(bit, d40c->base->virtbase + prioreg + group * 4); | |
2126 | writel(bit, d40c->base->virtbase + rtreg + group * 4); | |
2127 | } | |
2128 | ||
2129 | static void d40_set_prio_realtime(struct d40_chan *d40c) | |
2130 | { | |
2131 | if (d40c->base->rev < 3) | |
2132 | return; | |
2133 | ||
2134 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || | |
2135 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) | |
2136 | __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true); | |
2137 | ||
2138 | if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) || | |
2139 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) | |
2140 | __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false); | |
2141 | } | |
2142 | ||
8d318a50 LW |
2143 | /* DMA ENGINE functions */ |
2144 | static int d40_alloc_chan_resources(struct dma_chan *chan) | |
2145 | { | |
2146 | int err; | |
2147 | unsigned long flags; | |
2148 | struct d40_chan *d40c = | |
2149 | container_of(chan, struct d40_chan, chan); | |
ef1872ec | 2150 | bool is_free_phy; |
8d318a50 LW |
2151 | spin_lock_irqsave(&d40c->lock, flags); |
2152 | ||
2153 | d40c->completed = chan->cookie = 1; | |
2154 | ||
ce2ca125 RV |
2155 | /* If no dma configuration is set use default configuration (memcpy) */ |
2156 | if (!d40c->configured) { | |
8d318a50 | 2157 | err = d40_config_memcpy(d40c); |
ff0b12ba | 2158 | if (err) { |
6db5a8ba | 2159 | chan_err(d40c, "Failed to configure memcpy channel\n"); |
ff0b12ba JA |
2160 | goto fail; |
2161 | } | |
8d318a50 | 2162 | } |
ef1872ec | 2163 | is_free_phy = (d40c->phy_chan == NULL); |
8d318a50 LW |
2164 | |
2165 | err = d40_allocate_channel(d40c); | |
2166 | if (err) { | |
6db5a8ba | 2167 | chan_err(d40c, "Failed to allocate channel\n"); |
7fb3e75e | 2168 | d40c->configured = false; |
ff0b12ba | 2169 | goto fail; |
8d318a50 LW |
2170 | } |
2171 | ||
7fb3e75e | 2172 | pm_runtime_get_sync(d40c->base->dev); |
ef1872ec LW |
2173 | /* Fill in basic CFG register values */ |
2174 | d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, | |
724a8577 | 2175 | &d40c->dst_def_cfg, chan_is_logical(d40c)); |
ef1872ec | 2176 | |
ac2c0a38 RV |
2177 | d40_set_prio_realtime(d40c); |
2178 | ||
724a8577 | 2179 | if (chan_is_logical(d40c)) { |
ef1872ec LW |
2180 | d40_log_cfg(&d40c->dma_cfg, |
2181 | &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); | |
2182 | ||
2183 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) | |
2184 | d40c->lcpa = d40c->base->lcpa_base + | |
2185 | d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE; | |
2186 | else | |
2187 | d40c->lcpa = d40c->base->lcpa_base + | |
2188 | d40c->dma_cfg.dst_dev_type * | |
2189 | D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; | |
2190 | } | |
2191 | ||
2192 | /* | |
2193 | * Only write channel configuration to the DMA if the physical | |
2194 | * resource is free. In case of multiple logical channels | |
2195 | * on the same physical resource, only the first write is necessary. | |
2196 | */ | |
b55912c6 JA |
2197 | if (is_free_phy) |
2198 | d40_config_write(d40c); | |
ff0b12ba | 2199 | fail: |
7fb3e75e N |
2200 | pm_runtime_mark_last_busy(d40c->base->dev); |
2201 | pm_runtime_put_autosuspend(d40c->base->dev); | |
8d318a50 | 2202 | spin_unlock_irqrestore(&d40c->lock, flags); |
ff0b12ba | 2203 | return err; |
8d318a50 LW |
2204 | } |
2205 | ||
2206 | static void d40_free_chan_resources(struct dma_chan *chan) | |
2207 | { | |
2208 | struct d40_chan *d40c = | |
2209 | container_of(chan, struct d40_chan, chan); | |
2210 | int err; | |
2211 | unsigned long flags; | |
2212 | ||
0d0f6b8b | 2213 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2214 | chan_err(d40c, "Cannot free unallocated channel\n"); |
0d0f6b8b JA |
2215 | return; |
2216 | } | |
2217 | ||
2218 | ||
8d318a50 LW |
2219 | spin_lock_irqsave(&d40c->lock, flags); |
2220 | ||
2221 | err = d40_free_dma(d40c); | |
2222 | ||
2223 | if (err) | |
6db5a8ba | 2224 | chan_err(d40c, "Failed to free channel\n"); |
8d318a50 LW |
2225 | spin_unlock_irqrestore(&d40c->lock, flags); |
2226 | } | |
2227 | ||
2228 | static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan, | |
2229 | dma_addr_t dst, | |
2230 | dma_addr_t src, | |
2231 | size_t size, | |
2a614340 | 2232 | unsigned long dma_flags) |
8d318a50 | 2233 | { |
95944c6e RV |
2234 | struct scatterlist dst_sg; |
2235 | struct scatterlist src_sg; | |
8d318a50 | 2236 | |
95944c6e RV |
2237 | sg_init_table(&dst_sg, 1); |
2238 | sg_init_table(&src_sg, 1); | |
8d318a50 | 2239 | |
95944c6e RV |
2240 | sg_dma_address(&dst_sg) = dst; |
2241 | sg_dma_address(&src_sg) = src; | |
8d318a50 | 2242 | |
95944c6e RV |
2243 | sg_dma_len(&dst_sg) = size; |
2244 | sg_dma_len(&src_sg) = size; | |
8d318a50 | 2245 | |
cade1d30 | 2246 | return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags); |
8d318a50 LW |
2247 | } |
2248 | ||
0d688662 | 2249 | static struct dma_async_tx_descriptor * |
cade1d30 RV |
2250 | d40_prep_memcpy_sg(struct dma_chan *chan, |
2251 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
2252 | struct scatterlist *src_sg, unsigned int src_nents, | |
2253 | unsigned long dma_flags) | |
0d688662 IS |
2254 | { |
2255 | if (dst_nents != src_nents) | |
2256 | return NULL; | |
2257 | ||
cade1d30 | 2258 | return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags); |
00ac0341 RV |
2259 | } |
2260 | ||
8d318a50 LW |
2261 | static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan, |
2262 | struct scatterlist *sgl, | |
2263 | unsigned int sg_len, | |
db8196df | 2264 | enum dma_transfer_direction direction, |
2a614340 | 2265 | unsigned long dma_flags) |
8d318a50 | 2266 | { |
db8196df | 2267 | if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) |
00ac0341 RV |
2268 | return NULL; |
2269 | ||
cade1d30 | 2270 | return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags); |
8d318a50 LW |
2271 | } |
2272 | ||
0c842b55 RV |
2273 | static struct dma_async_tx_descriptor * |
2274 | dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, | |
2275 | size_t buf_len, size_t period_len, | |
db8196df | 2276 | enum dma_transfer_direction direction) |
0c842b55 RV |
2277 | { |
2278 | unsigned int periods = buf_len / period_len; | |
2279 | struct dma_async_tx_descriptor *txd; | |
2280 | struct scatterlist *sg; | |
2281 | int i; | |
2282 | ||
79ca7ec3 | 2283 | sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT); |
0c842b55 RV |
2284 | for (i = 0; i < periods; i++) { |
2285 | sg_dma_address(&sg[i]) = dma_addr; | |
2286 | sg_dma_len(&sg[i]) = period_len; | |
2287 | dma_addr += period_len; | |
2288 | } | |
2289 | ||
2290 | sg[periods].offset = 0; | |
2291 | sg[periods].length = 0; | |
2292 | sg[periods].page_link = | |
2293 | ((unsigned long)sg | 0x01) & ~0x02; | |
2294 | ||
2295 | txd = d40_prep_sg(chan, sg, sg, periods, direction, | |
2296 | DMA_PREP_INTERRUPT); | |
2297 | ||
2298 | kfree(sg); | |
2299 | ||
2300 | return txd; | |
2301 | } | |
2302 | ||
8d318a50 LW |
2303 | static enum dma_status d40_tx_status(struct dma_chan *chan, |
2304 | dma_cookie_t cookie, | |
2305 | struct dma_tx_state *txstate) | |
2306 | { | |
2307 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2308 | dma_cookie_t last_used; | |
2309 | dma_cookie_t last_complete; | |
2310 | int ret; | |
2311 | ||
0d0f6b8b | 2312 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2313 | chan_err(d40c, "Cannot read status of unallocated channel\n"); |
0d0f6b8b JA |
2314 | return -EINVAL; |
2315 | } | |
2316 | ||
8d318a50 LW |
2317 | last_complete = d40c->completed; |
2318 | last_used = chan->cookie; | |
2319 | ||
a5ebca47 JA |
2320 | if (d40_is_paused(d40c)) |
2321 | ret = DMA_PAUSED; | |
2322 | else | |
2323 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
8d318a50 | 2324 | |
a5ebca47 JA |
2325 | dma_set_tx_state(txstate, last_complete, last_used, |
2326 | stedma40_residue(chan)); | |
8d318a50 LW |
2327 | |
2328 | return ret; | |
2329 | } | |
2330 | ||
2331 | static void d40_issue_pending(struct dma_chan *chan) | |
2332 | { | |
2333 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2334 | unsigned long flags; | |
2335 | ||
0d0f6b8b | 2336 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2337 | chan_err(d40c, "Channel is not allocated!\n"); |
0d0f6b8b JA |
2338 | return; |
2339 | } | |
2340 | ||
8d318a50 LW |
2341 | spin_lock_irqsave(&d40c->lock, flags); |
2342 | ||
a8f3067b PF |
2343 | list_splice_tail_init(&d40c->pending_queue, &d40c->queue); |
2344 | ||
2345 | /* Busy means that queued jobs are already being processed */ | |
8d318a50 LW |
2346 | if (!d40c->busy) |
2347 | (void) d40_queue_start(d40c); | |
2348 | ||
2349 | spin_unlock_irqrestore(&d40c->lock, flags); | |
2350 | } | |
2351 | ||
98ca5289 RV |
2352 | static int |
2353 | dma40_config_to_halfchannel(struct d40_chan *d40c, | |
2354 | struct stedma40_half_channel_info *info, | |
2355 | enum dma_slave_buswidth width, | |
2356 | u32 maxburst) | |
2357 | { | |
2358 | enum stedma40_periph_data_width addr_width; | |
2359 | int psize; | |
2360 | ||
2361 | switch (width) { | |
2362 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
2363 | addr_width = STEDMA40_BYTE_WIDTH; | |
2364 | break; | |
2365 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
2366 | addr_width = STEDMA40_HALFWORD_WIDTH; | |
2367 | break; | |
2368 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
2369 | addr_width = STEDMA40_WORD_WIDTH; | |
2370 | break; | |
2371 | case DMA_SLAVE_BUSWIDTH_8_BYTES: | |
2372 | addr_width = STEDMA40_DOUBLEWORD_WIDTH; | |
2373 | break; | |
2374 | default: | |
2375 | dev_err(d40c->base->dev, | |
2376 | "illegal peripheral address width " | |
2377 | "requested (%d)\n", | |
2378 | width); | |
2379 | return -EINVAL; | |
2380 | } | |
2381 | ||
2382 | if (chan_is_logical(d40c)) { | |
2383 | if (maxburst >= 16) | |
2384 | psize = STEDMA40_PSIZE_LOG_16; | |
2385 | else if (maxburst >= 8) | |
2386 | psize = STEDMA40_PSIZE_LOG_8; | |
2387 | else if (maxburst >= 4) | |
2388 | psize = STEDMA40_PSIZE_LOG_4; | |
2389 | else | |
2390 | psize = STEDMA40_PSIZE_LOG_1; | |
2391 | } else { | |
2392 | if (maxburst >= 16) | |
2393 | psize = STEDMA40_PSIZE_PHY_16; | |
2394 | else if (maxburst >= 8) | |
2395 | psize = STEDMA40_PSIZE_PHY_8; | |
2396 | else if (maxburst >= 4) | |
2397 | psize = STEDMA40_PSIZE_PHY_4; | |
2398 | else | |
2399 | psize = STEDMA40_PSIZE_PHY_1; | |
2400 | } | |
2401 | ||
2402 | info->data_width = addr_width; | |
2403 | info->psize = psize; | |
2404 | info->flow_ctrl = STEDMA40_NO_FLOW_CTRL; | |
2405 | ||
2406 | return 0; | |
2407 | } | |
2408 | ||
95e1400f | 2409 | /* Runtime reconfiguration extension */ |
98ca5289 RV |
2410 | static int d40_set_runtime_config(struct dma_chan *chan, |
2411 | struct dma_slave_config *config) | |
95e1400f LW |
2412 | { |
2413 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2414 | struct stedma40_chan_cfg *cfg = &d40c->dma_cfg; | |
98ca5289 | 2415 | enum dma_slave_buswidth src_addr_width, dst_addr_width; |
95e1400f | 2416 | dma_addr_t config_addr; |
98ca5289 RV |
2417 | u32 src_maxburst, dst_maxburst; |
2418 | int ret; | |
2419 | ||
2420 | src_addr_width = config->src_addr_width; | |
2421 | src_maxburst = config->src_maxburst; | |
2422 | dst_addr_width = config->dst_addr_width; | |
2423 | dst_maxburst = config->dst_maxburst; | |
95e1400f | 2424 | |
db8196df | 2425 | if (config->direction == DMA_DEV_TO_MEM) { |
95e1400f LW |
2426 | dma_addr_t dev_addr_rx = |
2427 | d40c->base->plat_data->dev_rx[cfg->src_dev_type]; | |
2428 | ||
2429 | config_addr = config->src_addr; | |
2430 | if (dev_addr_rx) | |
2431 | dev_dbg(d40c->base->dev, | |
2432 | "channel has a pre-wired RX address %08x " | |
2433 | "overriding with %08x\n", | |
2434 | dev_addr_rx, config_addr); | |
2435 | if (cfg->dir != STEDMA40_PERIPH_TO_MEM) | |
2436 | dev_dbg(d40c->base->dev, | |
2437 | "channel was not configured for peripheral " | |
2438 | "to memory transfer (%d) overriding\n", | |
2439 | cfg->dir); | |
2440 | cfg->dir = STEDMA40_PERIPH_TO_MEM; | |
2441 | ||
98ca5289 RV |
2442 | /* Configure the memory side */ |
2443 | if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
2444 | dst_addr_width = src_addr_width; | |
2445 | if (dst_maxburst == 0) | |
2446 | dst_maxburst = src_maxburst; | |
95e1400f | 2447 | |
db8196df | 2448 | } else if (config->direction == DMA_MEM_TO_DEV) { |
95e1400f LW |
2449 | dma_addr_t dev_addr_tx = |
2450 | d40c->base->plat_data->dev_tx[cfg->dst_dev_type]; | |
2451 | ||
2452 | config_addr = config->dst_addr; | |
2453 | if (dev_addr_tx) | |
2454 | dev_dbg(d40c->base->dev, | |
2455 | "channel has a pre-wired TX address %08x " | |
2456 | "overriding with %08x\n", | |
2457 | dev_addr_tx, config_addr); | |
2458 | if (cfg->dir != STEDMA40_MEM_TO_PERIPH) | |
2459 | dev_dbg(d40c->base->dev, | |
2460 | "channel was not configured for memory " | |
2461 | "to peripheral transfer (%d) overriding\n", | |
2462 | cfg->dir); | |
2463 | cfg->dir = STEDMA40_MEM_TO_PERIPH; | |
2464 | ||
98ca5289 RV |
2465 | /* Configure the memory side */ |
2466 | if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
2467 | src_addr_width = dst_addr_width; | |
2468 | if (src_maxburst == 0) | |
2469 | src_maxburst = dst_maxburst; | |
95e1400f LW |
2470 | } else { |
2471 | dev_err(d40c->base->dev, | |
2472 | "unrecognized channel direction %d\n", | |
2473 | config->direction); | |
98ca5289 | 2474 | return -EINVAL; |
95e1400f LW |
2475 | } |
2476 | ||
98ca5289 | 2477 | if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) { |
95e1400f | 2478 | dev_err(d40c->base->dev, |
98ca5289 RV |
2479 | "src/dst width/maxburst mismatch: %d*%d != %d*%d\n", |
2480 | src_maxburst, | |
2481 | src_addr_width, | |
2482 | dst_maxburst, | |
2483 | dst_addr_width); | |
2484 | return -EINVAL; | |
95e1400f LW |
2485 | } |
2486 | ||
98ca5289 RV |
2487 | ret = dma40_config_to_halfchannel(d40c, &cfg->src_info, |
2488 | src_addr_width, | |
2489 | src_maxburst); | |
2490 | if (ret) | |
2491 | return ret; | |
95e1400f | 2492 | |
98ca5289 RV |
2493 | ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info, |
2494 | dst_addr_width, | |
2495 | dst_maxburst); | |
2496 | if (ret) | |
2497 | return ret; | |
95e1400f | 2498 | |
a59670a4 | 2499 | /* Fill in register values */ |
724a8577 | 2500 | if (chan_is_logical(d40c)) |
a59670a4 PF |
2501 | d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); |
2502 | else | |
2503 | d40_phy_cfg(cfg, &d40c->src_def_cfg, | |
2504 | &d40c->dst_def_cfg, false); | |
2505 | ||
95e1400f LW |
2506 | /* These settings will take precedence later */ |
2507 | d40c->runtime_addr = config_addr; | |
2508 | d40c->runtime_direction = config->direction; | |
2509 | dev_dbg(d40c->base->dev, | |
98ca5289 RV |
2510 | "configured channel %s for %s, data width %d/%d, " |
2511 | "maxburst %d/%d elements, LE, no flow control\n", | |
95e1400f | 2512 | dma_chan_name(chan), |
db8196df | 2513 | (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX", |
98ca5289 RV |
2514 | src_addr_width, dst_addr_width, |
2515 | src_maxburst, dst_maxburst); | |
2516 | ||
2517 | return 0; | |
95e1400f LW |
2518 | } |
2519 | ||
05827630 LW |
2520 | static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
2521 | unsigned long arg) | |
8d318a50 | 2522 | { |
8d318a50 LW |
2523 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
2524 | ||
0d0f6b8b | 2525 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2526 | chan_err(d40c, "Channel is not allocated!\n"); |
0d0f6b8b JA |
2527 | return -EINVAL; |
2528 | } | |
2529 | ||
8d318a50 LW |
2530 | switch (cmd) { |
2531 | case DMA_TERMINATE_ALL: | |
86eb5fb6 | 2532 | return d40_terminate_all(d40c); |
8d318a50 | 2533 | case DMA_PAUSE: |
86eb5fb6 | 2534 | return d40_pause(d40c); |
8d318a50 | 2535 | case DMA_RESUME: |
86eb5fb6 | 2536 | return d40_resume(d40c); |
95e1400f | 2537 | case DMA_SLAVE_CONFIG: |
98ca5289 | 2538 | return d40_set_runtime_config(chan, |
95e1400f | 2539 | (struct dma_slave_config *) arg); |
95e1400f LW |
2540 | default: |
2541 | break; | |
8d318a50 LW |
2542 | } |
2543 | ||
2544 | /* Other commands are unimplemented */ | |
2545 | return -ENXIO; | |
2546 | } | |
2547 | ||
2548 | /* Initialization functions */ | |
2549 | ||
2550 | static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, | |
2551 | struct d40_chan *chans, int offset, | |
2552 | int num_chans) | |
2553 | { | |
2554 | int i = 0; | |
2555 | struct d40_chan *d40c; | |
2556 | ||
2557 | INIT_LIST_HEAD(&dma->channels); | |
2558 | ||
2559 | for (i = offset; i < offset + num_chans; i++) { | |
2560 | d40c = &chans[i]; | |
2561 | d40c->base = base; | |
2562 | d40c->chan.device = dma; | |
2563 | ||
8d318a50 LW |
2564 | spin_lock_init(&d40c->lock); |
2565 | ||
2566 | d40c->log_num = D40_PHY_CHAN; | |
2567 | ||
8d318a50 LW |
2568 | INIT_LIST_HEAD(&d40c->active); |
2569 | INIT_LIST_HEAD(&d40c->queue); | |
a8f3067b | 2570 | INIT_LIST_HEAD(&d40c->pending_queue); |
8d318a50 | 2571 | INIT_LIST_HEAD(&d40c->client); |
82babbb3 | 2572 | INIT_LIST_HEAD(&d40c->prepare_queue); |
8d318a50 | 2573 | |
8d318a50 LW |
2574 | tasklet_init(&d40c->tasklet, dma_tasklet, |
2575 | (unsigned long) d40c); | |
2576 | ||
2577 | list_add_tail(&d40c->chan.device_node, | |
2578 | &dma->channels); | |
2579 | } | |
2580 | } | |
2581 | ||
7ad74a7c RV |
2582 | static void d40_ops_init(struct d40_base *base, struct dma_device *dev) |
2583 | { | |
2584 | if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) | |
2585 | dev->device_prep_slave_sg = d40_prep_slave_sg; | |
2586 | ||
2587 | if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) { | |
2588 | dev->device_prep_dma_memcpy = d40_prep_memcpy; | |
2589 | ||
2590 | /* | |
2591 | * This controller can only access address at even | |
2592 | * 32bit boundaries, i.e. 2^2 | |
2593 | */ | |
2594 | dev->copy_align = 2; | |
2595 | } | |
2596 | ||
2597 | if (dma_has_cap(DMA_SG, dev->cap_mask)) | |
2598 | dev->device_prep_dma_sg = d40_prep_memcpy_sg; | |
2599 | ||
0c842b55 RV |
2600 | if (dma_has_cap(DMA_CYCLIC, dev->cap_mask)) |
2601 | dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic; | |
2602 | ||
7ad74a7c RV |
2603 | dev->device_alloc_chan_resources = d40_alloc_chan_resources; |
2604 | dev->device_free_chan_resources = d40_free_chan_resources; | |
2605 | dev->device_issue_pending = d40_issue_pending; | |
2606 | dev->device_tx_status = d40_tx_status; | |
2607 | dev->device_control = d40_control; | |
2608 | dev->dev = base->dev; | |
2609 | } | |
2610 | ||
8d318a50 LW |
2611 | static int __init d40_dmaengine_init(struct d40_base *base, |
2612 | int num_reserved_chans) | |
2613 | { | |
2614 | int err ; | |
2615 | ||
2616 | d40_chan_init(base, &base->dma_slave, base->log_chans, | |
2617 | 0, base->num_log_chans); | |
2618 | ||
2619 | dma_cap_zero(base->dma_slave.cap_mask); | |
2620 | dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); | |
0c842b55 | 2621 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
8d318a50 | 2622 | |
7ad74a7c | 2623 | d40_ops_init(base, &base->dma_slave); |
8d318a50 LW |
2624 | |
2625 | err = dma_async_device_register(&base->dma_slave); | |
2626 | ||
2627 | if (err) { | |
6db5a8ba | 2628 | d40_err(base->dev, "Failed to register slave channels\n"); |
8d318a50 LW |
2629 | goto failure1; |
2630 | } | |
2631 | ||
2632 | d40_chan_init(base, &base->dma_memcpy, base->log_chans, | |
2633 | base->num_log_chans, base->plat_data->memcpy_len); | |
2634 | ||
2635 | dma_cap_zero(base->dma_memcpy.cap_mask); | |
2636 | dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); | |
7ad74a7c RV |
2637 | dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask); |
2638 | ||
2639 | d40_ops_init(base, &base->dma_memcpy); | |
8d318a50 LW |
2640 | |
2641 | err = dma_async_device_register(&base->dma_memcpy); | |
2642 | ||
2643 | if (err) { | |
6db5a8ba RV |
2644 | d40_err(base->dev, |
2645 | "Failed to regsiter memcpy only channels\n"); | |
8d318a50 LW |
2646 | goto failure2; |
2647 | } | |
2648 | ||
2649 | d40_chan_init(base, &base->dma_both, base->phy_chans, | |
2650 | 0, num_reserved_chans); | |
2651 | ||
2652 | dma_cap_zero(base->dma_both.cap_mask); | |
2653 | dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); | |
2654 | dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); | |
7ad74a7c | 2655 | dma_cap_set(DMA_SG, base->dma_both.cap_mask); |
0c842b55 | 2656 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
7ad74a7c RV |
2657 | |
2658 | d40_ops_init(base, &base->dma_both); | |
8d318a50 LW |
2659 | err = dma_async_device_register(&base->dma_both); |
2660 | ||
2661 | if (err) { | |
6db5a8ba RV |
2662 | d40_err(base->dev, |
2663 | "Failed to register logical and physical capable channels\n"); | |
8d318a50 LW |
2664 | goto failure3; |
2665 | } | |
2666 | return 0; | |
2667 | failure3: | |
2668 | dma_async_device_unregister(&base->dma_memcpy); | |
2669 | failure2: | |
2670 | dma_async_device_unregister(&base->dma_slave); | |
2671 | failure1: | |
2672 | return err; | |
2673 | } | |
2674 | ||
7fb3e75e N |
2675 | /* Suspend resume functionality */ |
2676 | #ifdef CONFIG_PM | |
2677 | static int dma40_pm_suspend(struct device *dev) | |
2678 | { | |
28c7a19d N |
2679 | struct platform_device *pdev = to_platform_device(dev); |
2680 | struct d40_base *base = platform_get_drvdata(pdev); | |
2681 | int ret = 0; | |
7fb3e75e N |
2682 | if (!pm_runtime_suspended(dev)) |
2683 | return -EBUSY; | |
2684 | ||
28c7a19d N |
2685 | if (base->lcpa_regulator) |
2686 | ret = regulator_disable(base->lcpa_regulator); | |
2687 | return ret; | |
7fb3e75e N |
2688 | } |
2689 | ||
2690 | static int dma40_runtime_suspend(struct device *dev) | |
2691 | { | |
2692 | struct platform_device *pdev = to_platform_device(dev); | |
2693 | struct d40_base *base = platform_get_drvdata(pdev); | |
2694 | ||
2695 | d40_save_restore_registers(base, true); | |
2696 | ||
2697 | /* Don't disable/enable clocks for v1 due to HW bugs */ | |
2698 | if (base->rev != 1) | |
2699 | writel_relaxed(base->gcc_pwr_off_mask, | |
2700 | base->virtbase + D40_DREG_GCC); | |
2701 | ||
2702 | return 0; | |
2703 | } | |
2704 | ||
2705 | static int dma40_runtime_resume(struct device *dev) | |
2706 | { | |
2707 | struct platform_device *pdev = to_platform_device(dev); | |
2708 | struct d40_base *base = platform_get_drvdata(pdev); | |
2709 | ||
2710 | if (base->initialized) | |
2711 | d40_save_restore_registers(base, false); | |
2712 | ||
2713 | writel_relaxed(D40_DREG_GCC_ENABLE_ALL, | |
2714 | base->virtbase + D40_DREG_GCC); | |
2715 | return 0; | |
2716 | } | |
2717 | ||
28c7a19d N |
2718 | static int dma40_resume(struct device *dev) |
2719 | { | |
2720 | struct platform_device *pdev = to_platform_device(dev); | |
2721 | struct d40_base *base = platform_get_drvdata(pdev); | |
2722 | int ret = 0; | |
2723 | ||
2724 | if (base->lcpa_regulator) | |
2725 | ret = regulator_enable(base->lcpa_regulator); | |
2726 | ||
2727 | return ret; | |
2728 | } | |
7fb3e75e N |
2729 | |
2730 | static const struct dev_pm_ops dma40_pm_ops = { | |
2731 | .suspend = dma40_pm_suspend, | |
2732 | .runtime_suspend = dma40_runtime_suspend, | |
2733 | .runtime_resume = dma40_runtime_resume, | |
28c7a19d | 2734 | .resume = dma40_resume, |
7fb3e75e N |
2735 | }; |
2736 | #define DMA40_PM_OPS (&dma40_pm_ops) | |
2737 | #else | |
2738 | #define DMA40_PM_OPS NULL | |
2739 | #endif | |
2740 | ||
8d318a50 LW |
2741 | /* Initialization functions. */ |
2742 | ||
2743 | static int __init d40_phy_res_init(struct d40_base *base) | |
2744 | { | |
2745 | int i; | |
2746 | int num_phy_chans_avail = 0; | |
2747 | u32 val[2]; | |
2748 | int odd_even_bit = -2; | |
7fb3e75e | 2749 | int gcc = D40_DREG_GCC_ENA; |
8d318a50 LW |
2750 | |
2751 | val[0] = readl(base->virtbase + D40_DREG_PRSME); | |
2752 | val[1] = readl(base->virtbase + D40_DREG_PRSMO); | |
2753 | ||
2754 | for (i = 0; i < base->num_phy_chans; i++) { | |
2755 | base->phy_res[i].num = i; | |
2756 | odd_even_bit += 2 * ((i % 2) == 0); | |
2757 | if (((val[i % 2] >> odd_even_bit) & 3) == 1) { | |
2758 | /* Mark security only channels as occupied */ | |
2759 | base->phy_res[i].allocated_src = D40_ALLOC_PHY; | |
2760 | base->phy_res[i].allocated_dst = D40_ALLOC_PHY; | |
7fb3e75e N |
2761 | base->phy_res[i].reserved = true; |
2762 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), | |
2763 | D40_DREG_GCC_SRC); | |
2764 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), | |
2765 | D40_DREG_GCC_DST); | |
2766 | ||
2767 | ||
8d318a50 LW |
2768 | } else { |
2769 | base->phy_res[i].allocated_src = D40_ALLOC_FREE; | |
2770 | base->phy_res[i].allocated_dst = D40_ALLOC_FREE; | |
7fb3e75e | 2771 | base->phy_res[i].reserved = false; |
8d318a50 LW |
2772 | num_phy_chans_avail++; |
2773 | } | |
2774 | spin_lock_init(&base->phy_res[i].lock); | |
2775 | } | |
6b7acd84 JA |
2776 | |
2777 | /* Mark disabled channels as occupied */ | |
2778 | for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { | |
f57b407c RV |
2779 | int chan = base->plat_data->disabled_channels[i]; |
2780 | ||
2781 | base->phy_res[chan].allocated_src = D40_ALLOC_PHY; | |
2782 | base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; | |
7fb3e75e N |
2783 | base->phy_res[chan].reserved = true; |
2784 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), | |
2785 | D40_DREG_GCC_SRC); | |
2786 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), | |
2787 | D40_DREG_GCC_DST); | |
f57b407c | 2788 | num_phy_chans_avail--; |
6b7acd84 JA |
2789 | } |
2790 | ||
8d318a50 LW |
2791 | dev_info(base->dev, "%d of %d physical DMA channels available\n", |
2792 | num_phy_chans_avail, base->num_phy_chans); | |
2793 | ||
2794 | /* Verify settings extended vs standard */ | |
2795 | val[0] = readl(base->virtbase + D40_DREG_PRTYP); | |
2796 | ||
2797 | for (i = 0; i < base->num_phy_chans; i++) { | |
2798 | ||
2799 | if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && | |
2800 | (val[0] & 0x3) != 1) | |
2801 | dev_info(base->dev, | |
2802 | "[%s] INFO: channel %d is misconfigured (%d)\n", | |
2803 | __func__, i, val[0] & 0x3); | |
2804 | ||
2805 | val[0] = val[0] >> 2; | |
2806 | } | |
2807 | ||
7fb3e75e N |
2808 | /* |
2809 | * To keep things simple, Enable all clocks initially. | |
2810 | * The clocks will get managed later post channel allocation. | |
2811 | * The clocks for the event lines on which reserved channels exists | |
2812 | * are not managed here. | |
2813 | */ | |
2814 | writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); | |
2815 | base->gcc_pwr_off_mask = gcc; | |
2816 | ||
8d318a50 LW |
2817 | return num_phy_chans_avail; |
2818 | } | |
2819 | ||
2820 | static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) | |
2821 | { | |
8d318a50 LW |
2822 | struct stedma40_platform_data *plat_data; |
2823 | struct clk *clk = NULL; | |
2824 | void __iomem *virtbase = NULL; | |
2825 | struct resource *res = NULL; | |
2826 | struct d40_base *base = NULL; | |
2827 | int num_log_chans = 0; | |
2828 | int num_phy_chans; | |
2829 | int i; | |
f4b89764 LW |
2830 | u32 pid; |
2831 | u32 cid; | |
2832 | u8 rev; | |
8d318a50 LW |
2833 | |
2834 | clk = clk_get(&pdev->dev, NULL); | |
2835 | ||
2836 | if (IS_ERR(clk)) { | |
6db5a8ba | 2837 | d40_err(&pdev->dev, "No matching clock found\n"); |
8d318a50 LW |
2838 | goto failure; |
2839 | } | |
2840 | ||
2841 | clk_enable(clk); | |
2842 | ||
2843 | /* Get IO for DMAC base address */ | |
2844 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); | |
2845 | if (!res) | |
2846 | goto failure; | |
2847 | ||
2848 | if (request_mem_region(res->start, resource_size(res), | |
2849 | D40_NAME " I/O base") == NULL) | |
2850 | goto failure; | |
2851 | ||
2852 | virtbase = ioremap(res->start, resource_size(res)); | |
2853 | if (!virtbase) | |
2854 | goto failure; | |
2855 | ||
f4b89764 LW |
2856 | /* This is just a regular AMBA PrimeCell ID actually */ |
2857 | for (pid = 0, i = 0; i < 4; i++) | |
2858 | pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i) | |
2859 | & 255) << (i * 8); | |
2860 | for (cid = 0, i = 0; i < 4; i++) | |
2861 | cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i) | |
2862 | & 255) << (i * 8); | |
8d318a50 | 2863 | |
f4b89764 LW |
2864 | if (cid != AMBA_CID) { |
2865 | d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n"); | |
2866 | goto failure; | |
2867 | } | |
2868 | if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) { | |
6db5a8ba | 2869 | d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n", |
f4b89764 LW |
2870 | AMBA_MANF_BITS(pid), |
2871 | AMBA_VENDOR_ST); | |
8d318a50 LW |
2872 | goto failure; |
2873 | } | |
f4b89764 LW |
2874 | /* |
2875 | * HW revision: | |
2876 | * DB8500ed has revision 0 | |
2877 | * ? has revision 1 | |
2878 | * DB8500v1 has revision 2 | |
2879 | * DB8500v2 has revision 3 | |
2880 | */ | |
2881 | rev = AMBA_REV_BITS(pid); | |
3ae0267f | 2882 | |
8d318a50 LW |
2883 | /* The number of physical channels on this HW */ |
2884 | num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; | |
2885 | ||
2886 | dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n", | |
3ae0267f | 2887 | rev, res->start); |
8d318a50 LW |
2888 | |
2889 | plat_data = pdev->dev.platform_data; | |
2890 | ||
2891 | /* Count the number of logical channels in use */ | |
2892 | for (i = 0; i < plat_data->dev_len; i++) | |
2893 | if (plat_data->dev_rx[i] != 0) | |
2894 | num_log_chans++; | |
2895 | ||
2896 | for (i = 0; i < plat_data->dev_len; i++) | |
2897 | if (plat_data->dev_tx[i] != 0) | |
2898 | num_log_chans++; | |
2899 | ||
2900 | base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + | |
2901 | (num_phy_chans + num_log_chans + plat_data->memcpy_len) * | |
2902 | sizeof(struct d40_chan), GFP_KERNEL); | |
2903 | ||
2904 | if (base == NULL) { | |
6db5a8ba | 2905 | d40_err(&pdev->dev, "Out of memory\n"); |
8d318a50 LW |
2906 | goto failure; |
2907 | } | |
2908 | ||
3ae0267f | 2909 | base->rev = rev; |
8d318a50 LW |
2910 | base->clk = clk; |
2911 | base->num_phy_chans = num_phy_chans; | |
2912 | base->num_log_chans = num_log_chans; | |
2913 | base->phy_start = res->start; | |
2914 | base->phy_size = resource_size(res); | |
2915 | base->virtbase = virtbase; | |
2916 | base->plat_data = plat_data; | |
2917 | base->dev = &pdev->dev; | |
2918 | base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); | |
2919 | base->log_chans = &base->phy_chans[num_phy_chans]; | |
2920 | ||
2921 | base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res), | |
2922 | GFP_KERNEL); | |
2923 | if (!base->phy_res) | |
2924 | goto failure; | |
2925 | ||
2926 | base->lookup_phy_chans = kzalloc(num_phy_chans * | |
2927 | sizeof(struct d40_chan *), | |
2928 | GFP_KERNEL); | |
2929 | if (!base->lookup_phy_chans) | |
2930 | goto failure; | |
2931 | ||
2932 | if (num_log_chans + plat_data->memcpy_len) { | |
2933 | /* | |
2934 | * The max number of logical channels are event lines for all | |
2935 | * src devices and dst devices | |
2936 | */ | |
2937 | base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 * | |
2938 | sizeof(struct d40_chan *), | |
2939 | GFP_KERNEL); | |
2940 | if (!base->lookup_log_chans) | |
2941 | goto failure; | |
2942 | } | |
698e4732 | 2943 | |
7fb3e75e N |
2944 | base->reg_val_backup_chan = kmalloc(base->num_phy_chans * |
2945 | sizeof(d40_backup_regs_chan), | |
8d318a50 | 2946 | GFP_KERNEL); |
7fb3e75e N |
2947 | if (!base->reg_val_backup_chan) |
2948 | goto failure; | |
2949 | ||
2950 | base->lcla_pool.alloc_map = | |
2951 | kzalloc(num_phy_chans * sizeof(struct d40_desc *) | |
2952 | * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL); | |
8d318a50 LW |
2953 | if (!base->lcla_pool.alloc_map) |
2954 | goto failure; | |
2955 | ||
c675b1b4 JA |
2956 | base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), |
2957 | 0, SLAB_HWCACHE_ALIGN, | |
2958 | NULL); | |
2959 | if (base->desc_slab == NULL) | |
2960 | goto failure; | |
2961 | ||
8d318a50 LW |
2962 | return base; |
2963 | ||
2964 | failure: | |
c6134c96 | 2965 | if (!IS_ERR(clk)) { |
8d318a50 LW |
2966 | clk_disable(clk); |
2967 | clk_put(clk); | |
2968 | } | |
2969 | if (virtbase) | |
2970 | iounmap(virtbase); | |
2971 | if (res) | |
2972 | release_mem_region(res->start, | |
2973 | resource_size(res)); | |
2974 | if (virtbase) | |
2975 | iounmap(virtbase); | |
2976 | ||
2977 | if (base) { | |
2978 | kfree(base->lcla_pool.alloc_map); | |
2979 | kfree(base->lookup_log_chans); | |
2980 | kfree(base->lookup_phy_chans); | |
2981 | kfree(base->phy_res); | |
2982 | kfree(base); | |
2983 | } | |
2984 | ||
2985 | return NULL; | |
2986 | } | |
2987 | ||
2988 | static void __init d40_hw_init(struct d40_base *base) | |
2989 | { | |
2990 | ||
7fb3e75e | 2991 | static struct d40_reg_val dma_init_reg[] = { |
8d318a50 | 2992 | /* Clock every part of the DMA block from start */ |
7fb3e75e | 2993 | { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, |
8d318a50 LW |
2994 | |
2995 | /* Interrupts on all logical channels */ | |
2996 | { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, | |
2997 | { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, | |
2998 | { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, | |
2999 | { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, | |
3000 | { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, | |
3001 | { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, | |
3002 | { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, | |
3003 | { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, | |
3004 | { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, | |
3005 | { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, | |
3006 | { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, | |
3007 | { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} | |
3008 | }; | |
3009 | int i; | |
3010 | u32 prmseo[2] = {0, 0}; | |
3011 | u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF}; | |
3012 | u32 pcmis = 0; | |
3013 | u32 pcicr = 0; | |
3014 | ||
3015 | for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++) | |
3016 | writel(dma_init_reg[i].val, | |
3017 | base->virtbase + dma_init_reg[i].reg); | |
3018 | ||
3019 | /* Configure all our dma channels to default settings */ | |
3020 | for (i = 0; i < base->num_phy_chans; i++) { | |
3021 | ||
3022 | activeo[i % 2] = activeo[i % 2] << 2; | |
3023 | ||
3024 | if (base->phy_res[base->num_phy_chans - i - 1].allocated_src | |
3025 | == D40_ALLOC_PHY) { | |
3026 | activeo[i % 2] |= 3; | |
3027 | continue; | |
3028 | } | |
3029 | ||
3030 | /* Enable interrupt # */ | |
3031 | pcmis = (pcmis << 1) | 1; | |
3032 | ||
3033 | /* Clear interrupt # */ | |
3034 | pcicr = (pcicr << 1) | 1; | |
3035 | ||
3036 | /* Set channel to physical mode */ | |
3037 | prmseo[i % 2] = prmseo[i % 2] << 2; | |
3038 | prmseo[i % 2] |= 1; | |
3039 | ||
3040 | } | |
3041 | ||
3042 | writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); | |
3043 | writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); | |
3044 | writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); | |
3045 | writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); | |
3046 | ||
3047 | /* Write which interrupt to enable */ | |
3048 | writel(pcmis, base->virtbase + D40_DREG_PCMIS); | |
3049 | ||
3050 | /* Write which interrupt to clear */ | |
3051 | writel(pcicr, base->virtbase + D40_DREG_PCICR); | |
3052 | ||
3053 | } | |
3054 | ||
508849ad LW |
3055 | static int __init d40_lcla_allocate(struct d40_base *base) |
3056 | { | |
026cbc42 | 3057 | struct d40_lcla_pool *pool = &base->lcla_pool; |
508849ad LW |
3058 | unsigned long *page_list; |
3059 | int i, j; | |
3060 | int ret = 0; | |
3061 | ||
3062 | /* | |
3063 | * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned, | |
3064 | * To full fill this hardware requirement without wasting 256 kb | |
3065 | * we allocate pages until we get an aligned one. | |
3066 | */ | |
3067 | page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS, | |
3068 | GFP_KERNEL); | |
3069 | ||
3070 | if (!page_list) { | |
3071 | ret = -ENOMEM; | |
3072 | goto failure; | |
3073 | } | |
3074 | ||
3075 | /* Calculating how many pages that are required */ | |
3076 | base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; | |
3077 | ||
3078 | for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) { | |
3079 | page_list[i] = __get_free_pages(GFP_KERNEL, | |
3080 | base->lcla_pool.pages); | |
3081 | if (!page_list[i]) { | |
3082 | ||
6db5a8ba RV |
3083 | d40_err(base->dev, "Failed to allocate %d pages.\n", |
3084 | base->lcla_pool.pages); | |
508849ad LW |
3085 | |
3086 | for (j = 0; j < i; j++) | |
3087 | free_pages(page_list[j], base->lcla_pool.pages); | |
3088 | goto failure; | |
3089 | } | |
3090 | ||
3091 | if ((virt_to_phys((void *)page_list[i]) & | |
3092 | (LCLA_ALIGNMENT - 1)) == 0) | |
3093 | break; | |
3094 | } | |
3095 | ||
3096 | for (j = 0; j < i; j++) | |
3097 | free_pages(page_list[j], base->lcla_pool.pages); | |
3098 | ||
3099 | if (i < MAX_LCLA_ALLOC_ATTEMPTS) { | |
3100 | base->lcla_pool.base = (void *)page_list[i]; | |
3101 | } else { | |
767a9675 JA |
3102 | /* |
3103 | * After many attempts and no succees with finding the correct | |
3104 | * alignment, try with allocating a big buffer. | |
3105 | */ | |
508849ad LW |
3106 | dev_warn(base->dev, |
3107 | "[%s] Failed to get %d pages @ 18 bit align.\n", | |
3108 | __func__, base->lcla_pool.pages); | |
3109 | base->lcla_pool.base_unaligned = kmalloc(SZ_1K * | |
3110 | base->num_phy_chans + | |
3111 | LCLA_ALIGNMENT, | |
3112 | GFP_KERNEL); | |
3113 | if (!base->lcla_pool.base_unaligned) { | |
3114 | ret = -ENOMEM; | |
3115 | goto failure; | |
3116 | } | |
3117 | ||
3118 | base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, | |
3119 | LCLA_ALIGNMENT); | |
3120 | } | |
3121 | ||
026cbc42 RV |
3122 | pool->dma_addr = dma_map_single(base->dev, pool->base, |
3123 | SZ_1K * base->num_phy_chans, | |
3124 | DMA_TO_DEVICE); | |
3125 | if (dma_mapping_error(base->dev, pool->dma_addr)) { | |
3126 | pool->dma_addr = 0; | |
3127 | ret = -ENOMEM; | |
3128 | goto failure; | |
3129 | } | |
3130 | ||
508849ad LW |
3131 | writel(virt_to_phys(base->lcla_pool.base), |
3132 | base->virtbase + D40_DREG_LCLA); | |
3133 | failure: | |
3134 | kfree(page_list); | |
3135 | return ret; | |
3136 | } | |
3137 | ||
8d318a50 LW |
3138 | static int __init d40_probe(struct platform_device *pdev) |
3139 | { | |
3140 | int err; | |
3141 | int ret = -ENOENT; | |
3142 | struct d40_base *base; | |
3143 | struct resource *res = NULL; | |
3144 | int num_reserved_chans; | |
3145 | u32 val; | |
3146 | ||
3147 | base = d40_hw_detect_init(pdev); | |
3148 | ||
3149 | if (!base) | |
3150 | goto failure; | |
3151 | ||
3152 | num_reserved_chans = d40_phy_res_init(base); | |
3153 | ||
3154 | platform_set_drvdata(pdev, base); | |
3155 | ||
3156 | spin_lock_init(&base->interrupt_lock); | |
3157 | spin_lock_init(&base->execmd_lock); | |
3158 | ||
3159 | /* Get IO for logical channel parameter address */ | |
3160 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa"); | |
3161 | if (!res) { | |
3162 | ret = -ENOENT; | |
6db5a8ba | 3163 | d40_err(&pdev->dev, "No \"lcpa\" memory resource\n"); |
8d318a50 LW |
3164 | goto failure; |
3165 | } | |
3166 | base->lcpa_size = resource_size(res); | |
3167 | base->phy_lcpa = res->start; | |
3168 | ||
3169 | if (request_mem_region(res->start, resource_size(res), | |
3170 | D40_NAME " I/O lcpa") == NULL) { | |
3171 | ret = -EBUSY; | |
6db5a8ba RV |
3172 | d40_err(&pdev->dev, |
3173 | "Failed to request LCPA region 0x%x-0x%x\n", | |
3174 | res->start, res->end); | |
8d318a50 LW |
3175 | goto failure; |
3176 | } | |
3177 | ||
3178 | /* We make use of ESRAM memory for this. */ | |
3179 | val = readl(base->virtbase + D40_DREG_LCPA); | |
3180 | if (res->start != val && val != 0) { | |
3181 | dev_warn(&pdev->dev, | |
3182 | "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n", | |
3183 | __func__, val, res->start); | |
3184 | } else | |
3185 | writel(res->start, base->virtbase + D40_DREG_LCPA); | |
3186 | ||
3187 | base->lcpa_base = ioremap(res->start, resource_size(res)); | |
3188 | if (!base->lcpa_base) { | |
3189 | ret = -ENOMEM; | |
6db5a8ba | 3190 | d40_err(&pdev->dev, "Failed to ioremap LCPA region\n"); |
8d318a50 LW |
3191 | goto failure; |
3192 | } | |
28c7a19d N |
3193 | /* If lcla has to be located in ESRAM we don't need to allocate */ |
3194 | if (base->plat_data->use_esram_lcla) { | |
3195 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
3196 | "lcla_esram"); | |
3197 | if (!res) { | |
3198 | ret = -ENOENT; | |
3199 | d40_err(&pdev->dev, | |
3200 | "No \"lcla_esram\" memory resource\n"); | |
3201 | goto failure; | |
3202 | } | |
3203 | base->lcla_pool.base = ioremap(res->start, | |
3204 | resource_size(res)); | |
3205 | if (!base->lcla_pool.base) { | |
3206 | ret = -ENOMEM; | |
3207 | d40_err(&pdev->dev, "Failed to ioremap LCLA region\n"); | |
3208 | goto failure; | |
3209 | } | |
3210 | writel(res->start, base->virtbase + D40_DREG_LCLA); | |
8d318a50 | 3211 | |
28c7a19d N |
3212 | } else { |
3213 | ret = d40_lcla_allocate(base); | |
3214 | if (ret) { | |
3215 | d40_err(&pdev->dev, "Failed to allocate LCLA area\n"); | |
3216 | goto failure; | |
3217 | } | |
8d318a50 LW |
3218 | } |
3219 | ||
3220 | spin_lock_init(&base->lcla_pool.lock); | |
3221 | ||
8d318a50 LW |
3222 | base->irq = platform_get_irq(pdev, 0); |
3223 | ||
3224 | ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); | |
8d318a50 | 3225 | if (ret) { |
6db5a8ba | 3226 | d40_err(&pdev->dev, "No IRQ defined\n"); |
8d318a50 LW |
3227 | goto failure; |
3228 | } | |
3229 | ||
7fb3e75e N |
3230 | pm_runtime_irq_safe(base->dev); |
3231 | pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY); | |
3232 | pm_runtime_use_autosuspend(base->dev); | |
3233 | pm_runtime_enable(base->dev); | |
3234 | pm_runtime_resume(base->dev); | |
28c7a19d N |
3235 | |
3236 | if (base->plat_data->use_esram_lcla) { | |
3237 | ||
3238 | base->lcpa_regulator = regulator_get(base->dev, "lcla_esram"); | |
3239 | if (IS_ERR(base->lcpa_regulator)) { | |
3240 | d40_err(&pdev->dev, "Failed to get lcpa_regulator\n"); | |
3241 | base->lcpa_regulator = NULL; | |
3242 | goto failure; | |
3243 | } | |
3244 | ||
3245 | ret = regulator_enable(base->lcpa_regulator); | |
3246 | if (ret) { | |
3247 | d40_err(&pdev->dev, | |
3248 | "Failed to enable lcpa_regulator\n"); | |
3249 | regulator_put(base->lcpa_regulator); | |
3250 | base->lcpa_regulator = NULL; | |
3251 | goto failure; | |
3252 | } | |
3253 | } | |
3254 | ||
7fb3e75e | 3255 | base->initialized = true; |
8d318a50 LW |
3256 | err = d40_dmaengine_init(base, num_reserved_chans); |
3257 | if (err) | |
3258 | goto failure; | |
3259 | ||
3260 | d40_hw_init(base); | |
3261 | ||
3262 | dev_info(base->dev, "initialized\n"); | |
3263 | return 0; | |
3264 | ||
3265 | failure: | |
3266 | if (base) { | |
c675b1b4 JA |
3267 | if (base->desc_slab) |
3268 | kmem_cache_destroy(base->desc_slab); | |
8d318a50 LW |
3269 | if (base->virtbase) |
3270 | iounmap(base->virtbase); | |
026cbc42 | 3271 | |
28c7a19d N |
3272 | if (base->lcla_pool.base && base->plat_data->use_esram_lcla) { |
3273 | iounmap(base->lcla_pool.base); | |
3274 | base->lcla_pool.base = NULL; | |
3275 | } | |
3276 | ||
026cbc42 RV |
3277 | if (base->lcla_pool.dma_addr) |
3278 | dma_unmap_single(base->dev, base->lcla_pool.dma_addr, | |
3279 | SZ_1K * base->num_phy_chans, | |
3280 | DMA_TO_DEVICE); | |
3281 | ||
508849ad LW |
3282 | if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) |
3283 | free_pages((unsigned long)base->lcla_pool.base, | |
3284 | base->lcla_pool.pages); | |
767a9675 JA |
3285 | |
3286 | kfree(base->lcla_pool.base_unaligned); | |
3287 | ||
8d318a50 LW |
3288 | if (base->phy_lcpa) |
3289 | release_mem_region(base->phy_lcpa, | |
3290 | base->lcpa_size); | |
3291 | if (base->phy_start) | |
3292 | release_mem_region(base->phy_start, | |
3293 | base->phy_size); | |
3294 | if (base->clk) { | |
3295 | clk_disable(base->clk); | |
3296 | clk_put(base->clk); | |
3297 | } | |
3298 | ||
28c7a19d N |
3299 | if (base->lcpa_regulator) { |
3300 | regulator_disable(base->lcpa_regulator); | |
3301 | regulator_put(base->lcpa_regulator); | |
3302 | } | |
3303 | ||
8d318a50 LW |
3304 | kfree(base->lcla_pool.alloc_map); |
3305 | kfree(base->lookup_log_chans); | |
3306 | kfree(base->lookup_phy_chans); | |
3307 | kfree(base->phy_res); | |
3308 | kfree(base); | |
3309 | } | |
3310 | ||
6db5a8ba | 3311 | d40_err(&pdev->dev, "probe failed\n"); |
8d318a50 LW |
3312 | return ret; |
3313 | } | |
3314 | ||
3315 | static struct platform_driver d40_driver = { | |
3316 | .driver = { | |
3317 | .owner = THIS_MODULE, | |
3318 | .name = D40_NAME, | |
7fb3e75e | 3319 | .pm = DMA40_PM_OPS, |
8d318a50 LW |
3320 | }, |
3321 | }; | |
3322 | ||
cb9ab2d8 | 3323 | static int __init stedma40_init(void) |
8d318a50 LW |
3324 | { |
3325 | return platform_driver_probe(&d40_driver, d40_probe); | |
3326 | } | |
a0eb221a | 3327 | subsys_initcall(stedma40_init); |