]>
Commit | Line | Data |
---|---|---|
8d318a50 LW |
1 | /* |
2 | * driver/dma/ste_dma40.c | |
3 | * | |
4 | * Copyright (C) ST-Ericsson 2007-2010 | |
5 | * License terms: GNU General Public License (GPL) version 2 | |
6 | * Author: Per Friden <per.friden@stericsson.com> | |
7 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> | |
8 | * | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/dmaengine.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/delay.h> | |
17 | ||
18 | #include <plat/ste_dma40.h> | |
19 | ||
20 | #include "ste_dma40_ll.h" | |
21 | ||
22 | #define D40_NAME "dma40" | |
23 | ||
24 | #define D40_PHY_CHAN -1 | |
25 | ||
26 | /* For masking out/in 2 bit channel positions */ | |
27 | #define D40_CHAN_POS(chan) (2 * (chan / 2)) | |
28 | #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan)) | |
29 | ||
30 | /* Maximum iterations taken before giving up suspending a channel */ | |
31 | #define D40_SUSPEND_MAX_IT 500 | |
32 | ||
508849ad LW |
33 | /* Hardware requirement on LCLA alignment */ |
34 | #define LCLA_ALIGNMENT 0x40000 | |
35 | /* Attempts before giving up to trying to get pages that are aligned */ | |
36 | #define MAX_LCLA_ALLOC_ATTEMPTS 256 | |
37 | ||
38 | /* Bit markings for allocation map */ | |
8d318a50 LW |
39 | #define D40_ALLOC_FREE (1 << 31) |
40 | #define D40_ALLOC_PHY (1 << 30) | |
41 | #define D40_ALLOC_LOG_FREE 0 | |
42 | ||
8d318a50 | 43 | /* Hardware designer of the block */ |
3ae0267f | 44 | #define D40_HW_DESIGNER 0x8 |
8d318a50 LW |
45 | |
46 | /** | |
47 | * enum 40_command - The different commands and/or statuses. | |
48 | * | |
49 | * @D40_DMA_STOP: DMA channel command STOP or status STOPPED, | |
50 | * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN. | |
51 | * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible. | |
52 | * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED. | |
53 | */ | |
54 | enum d40_command { | |
55 | D40_DMA_STOP = 0, | |
56 | D40_DMA_RUN = 1, | |
57 | D40_DMA_SUSPEND_REQ = 2, | |
58 | D40_DMA_SUSPENDED = 3 | |
59 | }; | |
60 | ||
61 | /** | |
62 | * struct d40_lli_pool - Structure for keeping LLIs in memory | |
63 | * | |
64 | * @base: Pointer to memory area when the pre_alloc_lli's are not large | |
65 | * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if | |
66 | * pre_alloc_lli is used. | |
67 | * @size: The size in bytes of the memory at base or the size of pre_alloc_lli. | |
68 | * @pre_alloc_lli: Pre allocated area for the most common case of transfers, | |
69 | * one buffer to one buffer. | |
70 | */ | |
71 | struct d40_lli_pool { | |
72 | void *base; | |
508849ad | 73 | int size; |
8d318a50 | 74 | /* Space for dst and src, plus an extra for padding */ |
508849ad | 75 | u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)]; |
8d318a50 LW |
76 | }; |
77 | ||
78 | /** | |
79 | * struct d40_desc - A descriptor is one DMA job. | |
80 | * | |
81 | * @lli_phy: LLI settings for physical channel. Both src and dst= | |
82 | * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if | |
83 | * lli_len equals one. | |
84 | * @lli_log: Same as above but for logical channels. | |
85 | * @lli_pool: The pool with two entries pre-allocated. | |
941b77a3 PF |
86 | * @lli_len: Number of llis of current descriptor. |
87 | * @lli_count: Number of transfered llis. | |
88 | * @lli_tx_len: Max number of LLIs per transfer, there can be | |
89 | * many transfer for one descriptor. | |
8d318a50 LW |
90 | * @txd: DMA engine struct. Used for among other things for communication |
91 | * during a transfer. | |
92 | * @node: List entry. | |
93 | * @dir: The transfer direction of this job. | |
94 | * @is_in_client_list: true if the client owns this descriptor. | |
aa182ae2 JA |
95 | * @is_hw_linked: true if this job will automatically be continued for |
96 | * the previous one. | |
8d318a50 LW |
97 | * |
98 | * This descriptor is used for both logical and physical transfers. | |
99 | */ | |
100 | ||
101 | struct d40_desc { | |
102 | /* LLI physical */ | |
103 | struct d40_phy_lli_bidir lli_phy; | |
104 | /* LLI logical */ | |
105 | struct d40_log_lli_bidir lli_log; | |
106 | ||
107 | struct d40_lli_pool lli_pool; | |
941b77a3 PF |
108 | int lli_len; |
109 | int lli_count; | |
110 | u32 lli_tx_len; | |
8d318a50 LW |
111 | |
112 | struct dma_async_tx_descriptor txd; | |
113 | struct list_head node; | |
114 | ||
115 | enum dma_data_direction dir; | |
116 | bool is_in_client_list; | |
aa182ae2 | 117 | bool is_hw_linked; |
8d318a50 LW |
118 | }; |
119 | ||
120 | /** | |
121 | * struct d40_lcla_pool - LCLA pool settings and data. | |
122 | * | |
508849ad LW |
123 | * @base: The virtual address of LCLA. 18 bit aligned. |
124 | * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used. | |
125 | * This pointer is only there for clean-up on error. | |
126 | * @pages: The number of pages needed for all physical channels. | |
127 | * Only used later for clean-up on error | |
8d318a50 | 128 | * @lock: Lock to protect the content in this struct. |
508849ad | 129 | * @alloc_map: Bitmap mapping between physical channel and LCLA entries. |
8d318a50 LW |
130 | * @num_blocks: The number of entries of alloc_map. Equals to the |
131 | * number of physical channels. | |
132 | */ | |
133 | struct d40_lcla_pool { | |
134 | void *base; | |
508849ad LW |
135 | void *base_unaligned; |
136 | int pages; | |
8d318a50 LW |
137 | spinlock_t lock; |
138 | u32 *alloc_map; | |
139 | int num_blocks; | |
140 | }; | |
141 | ||
142 | /** | |
143 | * struct d40_phy_res - struct for handling eventlines mapped to physical | |
144 | * channels. | |
145 | * | |
146 | * @lock: A lock protection this entity. | |
147 | * @num: The physical channel number of this entity. | |
148 | * @allocated_src: Bit mapped to show which src event line's are mapped to | |
149 | * this physical channel. Can also be free or physically allocated. | |
150 | * @allocated_dst: Same as for src but is dst. | |
151 | * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as | |
152 | * event line number. Both allocated_src and allocated_dst can not be | |
153 | * allocated to a physical channel, since the interrupt handler has then | |
154 | * no way of figure out which one the interrupt belongs to. | |
155 | */ | |
156 | struct d40_phy_res { | |
157 | spinlock_t lock; | |
158 | int num; | |
159 | u32 allocated_src; | |
160 | u32 allocated_dst; | |
161 | }; | |
162 | ||
163 | struct d40_base; | |
164 | ||
165 | /** | |
166 | * struct d40_chan - Struct that describes a channel. | |
167 | * | |
168 | * @lock: A spinlock to protect this struct. | |
169 | * @log_num: The logical number, if any of this channel. | |
170 | * @completed: Starts with 1, after first interrupt it is set to dma engine's | |
171 | * current cookie. | |
172 | * @pending_tx: The number of pending transfers. Used between interrupt handler | |
173 | * and tasklet. | |
174 | * @busy: Set to true when transfer is ongoing on this channel. | |
2a614340 JA |
175 | * @phy_chan: Pointer to physical channel which this instance runs on. If this |
176 | * point is NULL, then the channel is not allocated. | |
8d318a50 LW |
177 | * @chan: DMA engine handle. |
178 | * @tasklet: Tasklet that gets scheduled from interrupt context to complete a | |
179 | * transfer and call client callback. | |
180 | * @client: Cliented owned descriptor list. | |
181 | * @active: Active descriptor. | |
182 | * @queue: Queued jobs. | |
8d318a50 LW |
183 | * @dma_cfg: The client configuration of this dma channel. |
184 | * @base: Pointer to the device instance struct. | |
185 | * @src_def_cfg: Default cfg register setting for src. | |
186 | * @dst_def_cfg: Default cfg register setting for dst. | |
187 | * @log_def: Default logical channel settings. | |
188 | * @lcla: Space for one dst src pair for logical channel transfers. | |
189 | * @lcpa: Pointer to dst and src lcpa settings. | |
190 | * | |
191 | * This struct can either "be" a logical or a physical channel. | |
192 | */ | |
193 | struct d40_chan { | |
194 | spinlock_t lock; | |
195 | int log_num; | |
196 | /* ID of the most recent completed transfer */ | |
197 | int completed; | |
198 | int pending_tx; | |
199 | bool busy; | |
200 | struct d40_phy_res *phy_chan; | |
201 | struct dma_chan chan; | |
202 | struct tasklet_struct tasklet; | |
203 | struct list_head client; | |
204 | struct list_head active; | |
205 | struct list_head queue; | |
8d318a50 LW |
206 | struct stedma40_chan_cfg dma_cfg; |
207 | struct d40_base *base; | |
208 | /* Default register configurations */ | |
209 | u32 src_def_cfg; | |
210 | u32 dst_def_cfg; | |
211 | struct d40_def_lcsp log_def; | |
212 | struct d40_lcla_elem lcla; | |
213 | struct d40_log_lli_full *lcpa; | |
95e1400f LW |
214 | /* Runtime reconfiguration */ |
215 | dma_addr_t runtime_addr; | |
216 | enum dma_data_direction runtime_direction; | |
8d318a50 LW |
217 | }; |
218 | ||
219 | /** | |
220 | * struct d40_base - The big global struct, one for each probe'd instance. | |
221 | * | |
222 | * @interrupt_lock: Lock used to make sure one interrupt is handle a time. | |
223 | * @execmd_lock: Lock for execute command usage since several channels share | |
224 | * the same physical register. | |
225 | * @dev: The device structure. | |
226 | * @virtbase: The virtual base address of the DMA's register. | |
f4185592 | 227 | * @rev: silicon revision detected. |
8d318a50 LW |
228 | * @clk: Pointer to the DMA clock structure. |
229 | * @phy_start: Physical memory start of the DMA registers. | |
230 | * @phy_size: Size of the DMA register map. | |
231 | * @irq: The IRQ number. | |
232 | * @num_phy_chans: The number of physical channels. Read from HW. This | |
233 | * is the number of available channels for this driver, not counting "Secure | |
234 | * mode" allocated physical channels. | |
235 | * @num_log_chans: The number of logical channels. Calculated from | |
236 | * num_phy_chans. | |
237 | * @dma_both: dma_device channels that can do both memcpy and slave transfers. | |
238 | * @dma_slave: dma_device channels that can do only do slave transfers. | |
239 | * @dma_memcpy: dma_device channels that can do only do memcpy transfers. | |
240 | * @phy_chans: Room for all possible physical channels in system. | |
241 | * @log_chans: Room for all possible logical channels in system. | |
242 | * @lookup_log_chans: Used to map interrupt number to logical channel. Points | |
243 | * to log_chans entries. | |
244 | * @lookup_phy_chans: Used to map interrupt number to physical channel. Points | |
245 | * to phy_chans entries. | |
246 | * @plat_data: Pointer to provided platform_data which is the driver | |
247 | * configuration. | |
248 | * @phy_res: Vector containing all physical channels. | |
249 | * @lcla_pool: lcla pool settings and data. | |
250 | * @lcpa_base: The virtual mapped address of LCPA. | |
251 | * @phy_lcpa: The physical address of the LCPA. | |
252 | * @lcpa_size: The size of the LCPA area. | |
c675b1b4 | 253 | * @desc_slab: cache for descriptors. |
8d318a50 LW |
254 | */ |
255 | struct d40_base { | |
256 | spinlock_t interrupt_lock; | |
257 | spinlock_t execmd_lock; | |
258 | struct device *dev; | |
259 | void __iomem *virtbase; | |
f4185592 | 260 | u8 rev:4; |
8d318a50 LW |
261 | struct clk *clk; |
262 | phys_addr_t phy_start; | |
263 | resource_size_t phy_size; | |
264 | int irq; | |
265 | int num_phy_chans; | |
266 | int num_log_chans; | |
267 | struct dma_device dma_both; | |
268 | struct dma_device dma_slave; | |
269 | struct dma_device dma_memcpy; | |
270 | struct d40_chan *phy_chans; | |
271 | struct d40_chan *log_chans; | |
272 | struct d40_chan **lookup_log_chans; | |
273 | struct d40_chan **lookup_phy_chans; | |
274 | struct stedma40_platform_data *plat_data; | |
275 | /* Physical half channels */ | |
276 | struct d40_phy_res *phy_res; | |
277 | struct d40_lcla_pool lcla_pool; | |
278 | void *lcpa_base; | |
279 | dma_addr_t phy_lcpa; | |
280 | resource_size_t lcpa_size; | |
c675b1b4 | 281 | struct kmem_cache *desc_slab; |
8d318a50 LW |
282 | }; |
283 | ||
284 | /** | |
285 | * struct d40_interrupt_lookup - lookup table for interrupt handler | |
286 | * | |
287 | * @src: Interrupt mask register. | |
288 | * @clr: Interrupt clear register. | |
289 | * @is_error: true if this is an error interrupt. | |
290 | * @offset: start delta in the lookup_log_chans in d40_base. If equals to | |
291 | * D40_PHY_CHAN, the lookup_phy_chans shall be used instead. | |
292 | */ | |
293 | struct d40_interrupt_lookup { | |
294 | u32 src; | |
295 | u32 clr; | |
296 | bool is_error; | |
297 | int offset; | |
298 | }; | |
299 | ||
300 | /** | |
301 | * struct d40_reg_val - simple lookup struct | |
302 | * | |
303 | * @reg: The register. | |
304 | * @val: The value that belongs to the register in reg. | |
305 | */ | |
306 | struct d40_reg_val { | |
307 | unsigned int reg; | |
308 | unsigned int val; | |
309 | }; | |
310 | ||
311 | static int d40_pool_lli_alloc(struct d40_desc *d40d, | |
312 | int lli_len, bool is_log) | |
313 | { | |
314 | u32 align; | |
315 | void *base; | |
316 | ||
317 | if (is_log) | |
318 | align = sizeof(struct d40_log_lli); | |
319 | else | |
320 | align = sizeof(struct d40_phy_lli); | |
321 | ||
322 | if (lli_len == 1) { | |
323 | base = d40d->lli_pool.pre_alloc_lli; | |
324 | d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli); | |
325 | d40d->lli_pool.base = NULL; | |
326 | } else { | |
327 | d40d->lli_pool.size = ALIGN(lli_len * 2 * align, align); | |
328 | ||
329 | base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); | |
330 | d40d->lli_pool.base = base; | |
331 | ||
332 | if (d40d->lli_pool.base == NULL) | |
333 | return -ENOMEM; | |
334 | } | |
335 | ||
336 | if (is_log) { | |
337 | d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base, | |
338 | align); | |
339 | d40d->lli_log.dst = PTR_ALIGN(d40d->lli_log.src + lli_len, | |
340 | align); | |
341 | } else { | |
342 | d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base, | |
343 | align); | |
344 | d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len, | |
345 | align); | |
8d318a50 LW |
346 | } |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | static void d40_pool_lli_free(struct d40_desc *d40d) | |
352 | { | |
353 | kfree(d40d->lli_pool.base); | |
354 | d40d->lli_pool.base = NULL; | |
355 | d40d->lli_pool.size = 0; | |
356 | d40d->lli_log.src = NULL; | |
357 | d40d->lli_log.dst = NULL; | |
358 | d40d->lli_phy.src = NULL; | |
359 | d40d->lli_phy.dst = NULL; | |
8d318a50 LW |
360 | } |
361 | ||
8d318a50 LW |
362 | static void d40_desc_remove(struct d40_desc *d40d) |
363 | { | |
364 | list_del(&d40d->node); | |
365 | } | |
366 | ||
367 | static struct d40_desc *d40_desc_get(struct d40_chan *d40c) | |
368 | { | |
8d318a50 LW |
369 | struct d40_desc *d; |
370 | struct d40_desc *_d; | |
371 | ||
372 | if (!list_empty(&d40c->client)) { | |
373 | list_for_each_entry_safe(d, _d, &d40c->client, node) | |
374 | if (async_tx_test_ack(&d->txd)) { | |
375 | d40_pool_lli_free(d); | |
376 | d40_desc_remove(d); | |
c675b1b4 | 377 | break; |
8d318a50 | 378 | } |
8d318a50 | 379 | } else { |
c675b1b4 JA |
380 | d = kmem_cache_alloc(d40c->base->desc_slab, GFP_NOWAIT); |
381 | if (d != NULL) { | |
382 | memset(d, 0, sizeof(struct d40_desc)); | |
383 | INIT_LIST_HEAD(&d->node); | |
384 | } | |
8d318a50 | 385 | } |
c675b1b4 | 386 | return d; |
8d318a50 LW |
387 | } |
388 | ||
389 | static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d) | |
390 | { | |
c675b1b4 | 391 | kmem_cache_free(d40c->base->desc_slab, d40d); |
8d318a50 LW |
392 | } |
393 | ||
394 | static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc) | |
395 | { | |
396 | list_add_tail(&desc->node, &d40c->active); | |
397 | } | |
398 | ||
399 | static struct d40_desc *d40_first_active_get(struct d40_chan *d40c) | |
400 | { | |
401 | struct d40_desc *d; | |
402 | ||
403 | if (list_empty(&d40c->active)) | |
404 | return NULL; | |
405 | ||
406 | d = list_first_entry(&d40c->active, | |
407 | struct d40_desc, | |
408 | node); | |
409 | return d; | |
410 | } | |
411 | ||
412 | static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc) | |
413 | { | |
414 | list_add_tail(&desc->node, &d40c->queue); | |
415 | } | |
416 | ||
417 | static struct d40_desc *d40_first_queued(struct d40_chan *d40c) | |
418 | { | |
419 | struct d40_desc *d; | |
420 | ||
421 | if (list_empty(&d40c->queue)) | |
422 | return NULL; | |
423 | ||
424 | d = list_first_entry(&d40c->queue, | |
425 | struct d40_desc, | |
426 | node); | |
427 | return d; | |
428 | } | |
429 | ||
aa182ae2 JA |
430 | static struct d40_desc *d40_last_queued(struct d40_chan *d40c) |
431 | { | |
432 | struct d40_desc *d; | |
433 | ||
434 | if (list_empty(&d40c->queue)) | |
435 | return NULL; | |
436 | list_for_each_entry(d, &d40c->queue, node) | |
437 | if (list_is_last(&d->node, &d40c->queue)) | |
438 | break; | |
439 | return d; | |
440 | } | |
441 | ||
8d318a50 LW |
442 | /* Support functions for logical channels */ |
443 | ||
508849ad | 444 | static int d40_lcla_id_get(struct d40_chan *d40c) |
8d318a50 LW |
445 | { |
446 | int src_id = 0; | |
447 | int dst_id = 0; | |
448 | struct d40_log_lli *lcla_lidx_base = | |
508849ad | 449 | d40c->base->lcla_pool.base + d40c->phy_chan->num * 1024; |
8d318a50 LW |
450 | int i; |
451 | int lli_per_log = d40c->base->plat_data->llis_per_log; | |
2292b880 | 452 | unsigned long flags; |
8d318a50 LW |
453 | |
454 | if (d40c->lcla.src_id >= 0 && d40c->lcla.dst_id >= 0) | |
455 | return 0; | |
456 | ||
508849ad | 457 | if (d40c->base->lcla_pool.num_blocks > 32) |
8d318a50 LW |
458 | return -EINVAL; |
459 | ||
508849ad | 460 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); |
8d318a50 | 461 | |
508849ad LW |
462 | for (i = 0; i < d40c->base->lcla_pool.num_blocks; i++) { |
463 | if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] & | |
464 | (0x1 << i))) { | |
465 | d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |= | |
466 | (0x1 << i); | |
8d318a50 LW |
467 | break; |
468 | } | |
469 | } | |
470 | src_id = i; | |
508849ad | 471 | if (src_id >= d40c->base->lcla_pool.num_blocks) |
8d318a50 LW |
472 | goto err; |
473 | ||
508849ad LW |
474 | for (; i < d40c->base->lcla_pool.num_blocks; i++) { |
475 | if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] & | |
476 | (0x1 << i))) { | |
477 | d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |= | |
478 | (0x1 << i); | |
8d318a50 LW |
479 | break; |
480 | } | |
481 | } | |
482 | ||
483 | dst_id = i; | |
484 | if (dst_id == src_id) | |
485 | goto err; | |
486 | ||
487 | d40c->lcla.src_id = src_id; | |
488 | d40c->lcla.dst_id = dst_id; | |
489 | d40c->lcla.dst = lcla_lidx_base + dst_id * lli_per_log + 1; | |
490 | d40c->lcla.src = lcla_lidx_base + src_id * lli_per_log + 1; | |
491 | ||
508849ad | 492 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); |
8d318a50 LW |
493 | return 0; |
494 | err: | |
508849ad | 495 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); |
8d318a50 LW |
496 | return -EINVAL; |
497 | } | |
498 | ||
8d318a50 LW |
499 | |
500 | static int d40_channel_execute_command(struct d40_chan *d40c, | |
501 | enum d40_command command) | |
502 | { | |
503 | int status, i; | |
504 | void __iomem *active_reg; | |
505 | int ret = 0; | |
506 | unsigned long flags; | |
1d392a7b | 507 | u32 wmask; |
8d318a50 LW |
508 | |
509 | spin_lock_irqsave(&d40c->base->execmd_lock, flags); | |
510 | ||
511 | if (d40c->phy_chan->num % 2 == 0) | |
512 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; | |
513 | else | |
514 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; | |
515 | ||
516 | if (command == D40_DMA_SUSPEND_REQ) { | |
517 | status = (readl(active_reg) & | |
518 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
519 | D40_CHAN_POS(d40c->phy_chan->num); | |
520 | ||
521 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) | |
522 | goto done; | |
523 | } | |
524 | ||
1d392a7b JA |
525 | wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num)); |
526 | writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)), | |
527 | active_reg); | |
8d318a50 LW |
528 | |
529 | if (command == D40_DMA_SUSPEND_REQ) { | |
530 | ||
531 | for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) { | |
532 | status = (readl(active_reg) & | |
533 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
534 | D40_CHAN_POS(d40c->phy_chan->num); | |
535 | ||
536 | cpu_relax(); | |
537 | /* | |
538 | * Reduce the number of bus accesses while | |
539 | * waiting for the DMA to suspend. | |
540 | */ | |
541 | udelay(3); | |
542 | ||
543 | if (status == D40_DMA_STOP || | |
544 | status == D40_DMA_SUSPENDED) | |
545 | break; | |
546 | } | |
547 | ||
548 | if (i == D40_SUSPEND_MAX_IT) { | |
549 | dev_err(&d40c->chan.dev->device, | |
550 | "[%s]: unable to suspend the chl %d (log: %d) status %x\n", | |
551 | __func__, d40c->phy_chan->num, d40c->log_num, | |
552 | status); | |
553 | dump_stack(); | |
554 | ret = -EBUSY; | |
555 | } | |
556 | ||
557 | } | |
558 | done: | |
559 | spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); | |
560 | return ret; | |
561 | } | |
562 | ||
563 | static void d40_term_all(struct d40_chan *d40c) | |
564 | { | |
565 | struct d40_desc *d40d; | |
508849ad | 566 | unsigned long flags; |
8d318a50 LW |
567 | |
568 | /* Release active descriptors */ | |
569 | while ((d40d = d40_first_active_get(d40c))) { | |
570 | d40_desc_remove(d40d); | |
571 | ||
572 | /* Return desc to free-list */ | |
573 | d40_desc_free(d40c, d40d); | |
574 | } | |
575 | ||
576 | /* Release queued descriptors waiting for transfer */ | |
577 | while ((d40d = d40_first_queued(d40c))) { | |
578 | d40_desc_remove(d40d); | |
579 | ||
580 | /* Return desc to free-list */ | |
581 | d40_desc_free(d40c, d40d); | |
582 | } | |
583 | ||
508849ad LW |
584 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); |
585 | ||
586 | d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &= | |
587 | (~(0x1 << d40c->lcla.dst_id)); | |
588 | d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &= | |
589 | (~(0x1 << d40c->lcla.src_id)); | |
590 | ||
591 | d40c->lcla.src_id = -1; | |
592 | d40c->lcla.dst_id = -1; | |
593 | ||
594 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); | |
8d318a50 LW |
595 | |
596 | d40c->pending_tx = 0; | |
597 | d40c->busy = false; | |
598 | } | |
599 | ||
600 | static void d40_config_set_event(struct d40_chan *d40c, bool do_enable) | |
601 | { | |
602 | u32 val; | |
603 | unsigned long flags; | |
604 | ||
0c32269d | 605 | /* Notice, that disable requires the physical channel to be stopped */ |
8d318a50 LW |
606 | if (do_enable) |
607 | val = D40_ACTIVATE_EVENTLINE; | |
608 | else | |
609 | val = D40_DEACTIVATE_EVENTLINE; | |
610 | ||
611 | spin_lock_irqsave(&d40c->phy_chan->lock, flags); | |
612 | ||
613 | /* Enable event line connected to device (or memcpy) */ | |
614 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || | |
615 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) { | |
616 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
617 | ||
618 | writel((val << D40_EVENTLINE_POS(event)) | | |
619 | ~D40_EVENTLINE_MASK(event), | |
620 | d40c->base->virtbase + D40_DREG_PCBASE + | |
621 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
622 | D40_CHAN_REG_SSLNK); | |
623 | } | |
624 | if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) { | |
625 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
626 | ||
627 | writel((val << D40_EVENTLINE_POS(event)) | | |
628 | ~D40_EVENTLINE_MASK(event), | |
629 | d40c->base->virtbase + D40_DREG_PCBASE + | |
630 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
631 | D40_CHAN_REG_SDLNK); | |
632 | } | |
633 | ||
634 | spin_unlock_irqrestore(&d40c->phy_chan->lock, flags); | |
635 | } | |
636 | ||
a5ebca47 | 637 | static u32 d40_chan_has_events(struct d40_chan *d40c) |
8d318a50 | 638 | { |
be8cb7df | 639 | u32 val; |
8d318a50 | 640 | |
be8cb7df JA |
641 | val = readl(d40c->base->virtbase + D40_DREG_PCBASE + |
642 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
643 | D40_CHAN_REG_SSLNK); | |
644 | ||
645 | val |= readl(d40c->base->virtbase + D40_DREG_PCBASE + | |
646 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
647 | D40_CHAN_REG_SDLNK); | |
a5ebca47 | 648 | return val; |
8d318a50 LW |
649 | } |
650 | ||
b55912c6 | 651 | static void d40_config_write(struct d40_chan *d40c) |
8d318a50 LW |
652 | { |
653 | u32 addr_base; | |
654 | u32 var; | |
8d318a50 LW |
655 | |
656 | /* Odd addresses are even addresses + 4 */ | |
657 | addr_base = (d40c->phy_chan->num % 2) * 4; | |
658 | /* Setup channel mode to logical or physical */ | |
659 | var = ((u32)(d40c->log_num != D40_PHY_CHAN) + 1) << | |
660 | D40_CHAN_POS(d40c->phy_chan->num); | |
661 | writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); | |
662 | ||
663 | /* Setup operational mode option register */ | |
664 | var = ((d40c->dma_cfg.channel_type >> STEDMA40_INFO_CH_MODE_OPT_POS) & | |
665 | 0x3) << D40_CHAN_POS(d40c->phy_chan->num); | |
666 | ||
667 | writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); | |
668 | ||
669 | if (d40c->log_num != D40_PHY_CHAN) { | |
670 | /* Set default config for CFG reg */ | |
671 | writel(d40c->src_def_cfg, | |
672 | d40c->base->virtbase + D40_DREG_PCBASE + | |
673 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
674 | D40_CHAN_REG_SSCFG); | |
675 | writel(d40c->dst_def_cfg, | |
676 | d40c->base->virtbase + D40_DREG_PCBASE + | |
677 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
678 | D40_CHAN_REG_SDCFG); | |
679 | ||
b55912c6 JA |
680 | /* Set LIDX for lcla */ |
681 | writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) & | |
682 | D40_SREG_ELEM_LOG_LIDX_MASK, | |
683 | d40c->base->virtbase + D40_DREG_PCBASE + | |
684 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
685 | D40_CHAN_REG_SDELT); | |
686 | ||
687 | writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) & | |
688 | D40_SREG_ELEM_LOG_LIDX_MASK, | |
689 | d40c->base->virtbase + D40_DREG_PCBASE + | |
690 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
691 | D40_CHAN_REG_SSELT); | |
692 | ||
8d318a50 | 693 | } |
8d318a50 LW |
694 | } |
695 | ||
696 | static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d) | |
697 | { | |
8d318a50 LW |
698 | if (d40d->lli_phy.dst && d40d->lli_phy.src) { |
699 | d40_phy_lli_write(d40c->base->virtbase, | |
700 | d40c->phy_chan->num, | |
701 | d40d->lli_phy.dst, | |
702 | d40d->lli_phy.src); | |
8d318a50 | 703 | } else if (d40d->lli_log.dst && d40d->lli_log.src) { |
8d318a50 LW |
704 | struct d40_log_lli *src = d40d->lli_log.src; |
705 | struct d40_log_lli *dst = d40d->lli_log.dst; | |
508849ad | 706 | int s; |
8d318a50 | 707 | |
941b77a3 PF |
708 | src += d40d->lli_count; |
709 | dst += d40d->lli_count; | |
508849ad LW |
710 | s = d40_log_lli_write(d40c->lcpa, |
711 | d40c->lcla.src, d40c->lcla.dst, | |
712 | dst, src, | |
713 | d40c->base->plat_data->llis_per_log); | |
714 | ||
715 | /* If s equals to zero, the job is not linked */ | |
716 | if (s > 0) { | |
717 | (void) dma_map_single(d40c->base->dev, d40c->lcla.src, | |
718 | s * sizeof(struct d40_log_lli), | |
719 | DMA_TO_DEVICE); | |
720 | (void) dma_map_single(d40c->base->dev, d40c->lcla.dst, | |
721 | s * sizeof(struct d40_log_lli), | |
722 | DMA_TO_DEVICE); | |
723 | } | |
8d318a50 | 724 | } |
941b77a3 | 725 | d40d->lli_count += d40d->lli_tx_len; |
8d318a50 LW |
726 | } |
727 | ||
aa182ae2 JA |
728 | static u32 d40_residue(struct d40_chan *d40c) |
729 | { | |
730 | u32 num_elt; | |
731 | ||
732 | if (d40c->log_num != D40_PHY_CHAN) | |
733 | num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK) | |
734 | >> D40_MEM_LCSP2_ECNT_POS; | |
735 | else | |
736 | num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE + | |
737 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
738 | D40_CHAN_REG_SDELT) & | |
739 | D40_SREG_ELEM_PHY_ECNT_MASK) >> | |
740 | D40_SREG_ELEM_PHY_ECNT_POS; | |
741 | return num_elt * (1 << d40c->dma_cfg.dst_info.data_width); | |
742 | } | |
743 | ||
744 | static bool d40_tx_is_linked(struct d40_chan *d40c) | |
745 | { | |
746 | bool is_link; | |
747 | ||
748 | if (d40c->log_num != D40_PHY_CHAN) | |
749 | is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK; | |
750 | else | |
751 | is_link = readl(d40c->base->virtbase + D40_DREG_PCBASE + | |
752 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
753 | D40_CHAN_REG_SDLNK) & | |
754 | D40_SREG_LNK_PHYS_LNK_MASK; | |
755 | return is_link; | |
756 | } | |
757 | ||
758 | static int d40_pause(struct dma_chan *chan) | |
759 | { | |
760 | struct d40_chan *d40c = | |
761 | container_of(chan, struct d40_chan, chan); | |
762 | int res = 0; | |
763 | unsigned long flags; | |
764 | ||
765 | spin_lock_irqsave(&d40c->lock, flags); | |
766 | ||
767 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); | |
768 | if (res == 0) { | |
769 | if (d40c->log_num != D40_PHY_CHAN) { | |
770 | d40_config_set_event(d40c, false); | |
771 | /* Resume the other logical channels if any */ | |
772 | if (d40_chan_has_events(d40c)) | |
773 | res = d40_channel_execute_command(d40c, | |
774 | D40_DMA_RUN); | |
775 | } | |
776 | } | |
777 | ||
778 | spin_unlock_irqrestore(&d40c->lock, flags); | |
779 | return res; | |
780 | } | |
781 | ||
782 | static int d40_resume(struct dma_chan *chan) | |
783 | { | |
784 | struct d40_chan *d40c = | |
785 | container_of(chan, struct d40_chan, chan); | |
786 | int res = 0; | |
787 | unsigned long flags; | |
788 | ||
789 | spin_lock_irqsave(&d40c->lock, flags); | |
790 | ||
791 | if (d40c->base->rev == 0) | |
792 | if (d40c->log_num != D40_PHY_CHAN) { | |
793 | res = d40_channel_execute_command(d40c, | |
794 | D40_DMA_SUSPEND_REQ); | |
795 | goto no_suspend; | |
796 | } | |
797 | ||
798 | /* If bytes left to transfer or linked tx resume job */ | |
799 | if (d40_residue(d40c) || d40_tx_is_linked(d40c)) { | |
800 | ||
801 | if (d40c->log_num != D40_PHY_CHAN) | |
802 | d40_config_set_event(d40c, true); | |
803 | ||
804 | res = d40_channel_execute_command(d40c, D40_DMA_RUN); | |
805 | } | |
806 | ||
807 | no_suspend: | |
808 | spin_unlock_irqrestore(&d40c->lock, flags); | |
809 | return res; | |
810 | } | |
811 | ||
812 | static void d40_tx_submit_log(struct d40_chan *d40c, struct d40_desc *d40d) | |
813 | { | |
814 | /* TODO: Write */ | |
815 | } | |
816 | ||
817 | static void d40_tx_submit_phy(struct d40_chan *d40c, struct d40_desc *d40d) | |
818 | { | |
819 | struct d40_desc *d40d_prev = NULL; | |
820 | int i; | |
821 | u32 val; | |
822 | ||
823 | if (!list_empty(&d40c->queue)) | |
824 | d40d_prev = d40_last_queued(d40c); | |
825 | else if (!list_empty(&d40c->active)) | |
826 | d40d_prev = d40_first_active_get(d40c); | |
827 | ||
828 | if (!d40d_prev) | |
829 | return; | |
830 | ||
831 | /* Here we try to join this job with previous jobs */ | |
832 | val = readl(d40c->base->virtbase + D40_DREG_PCBASE + | |
833 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
834 | D40_CHAN_REG_SSLNK); | |
835 | ||
836 | /* Figure out which link we're currently transmitting */ | |
837 | for (i = 0; i < d40d_prev->lli_len; i++) | |
838 | if (val == d40d_prev->lli_phy.src[i].reg_lnk) | |
839 | break; | |
840 | ||
841 | val = readl(d40c->base->virtbase + D40_DREG_PCBASE + | |
842 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
843 | D40_CHAN_REG_SSELT) >> D40_SREG_ELEM_LOG_ECNT_POS; | |
844 | ||
845 | if (i == (d40d_prev->lli_len - 1) && val > 0) { | |
846 | /* Change the current one */ | |
847 | writel(virt_to_phys(d40d->lli_phy.src), | |
848 | d40c->base->virtbase + D40_DREG_PCBASE + | |
849 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
850 | D40_CHAN_REG_SSLNK); | |
851 | writel(virt_to_phys(d40d->lli_phy.dst), | |
852 | d40c->base->virtbase + D40_DREG_PCBASE + | |
853 | d40c->phy_chan->num * D40_DREG_PCDELTA + | |
854 | D40_CHAN_REG_SDLNK); | |
855 | ||
856 | d40d->is_hw_linked = true; | |
857 | ||
858 | } else if (i < d40d_prev->lli_len) { | |
859 | (void) dma_unmap_single(d40c->base->dev, | |
860 | virt_to_phys(d40d_prev->lli_phy.src), | |
861 | d40d_prev->lli_pool.size, | |
862 | DMA_TO_DEVICE); | |
863 | ||
864 | /* Keep the settings */ | |
865 | val = d40d_prev->lli_phy.src[d40d_prev->lli_len - 1].reg_lnk & | |
866 | ~D40_SREG_LNK_PHYS_LNK_MASK; | |
867 | d40d_prev->lli_phy.src[d40d_prev->lli_len - 1].reg_lnk = | |
868 | val | virt_to_phys(d40d->lli_phy.src); | |
869 | ||
870 | val = d40d_prev->lli_phy.dst[d40d_prev->lli_len - 1].reg_lnk & | |
871 | ~D40_SREG_LNK_PHYS_LNK_MASK; | |
872 | d40d_prev->lli_phy.dst[d40d_prev->lli_len - 1].reg_lnk = | |
873 | val | virt_to_phys(d40d->lli_phy.dst); | |
874 | ||
875 | (void) dma_map_single(d40c->base->dev, | |
876 | d40d_prev->lli_phy.src, | |
877 | d40d_prev->lli_pool.size, | |
878 | DMA_TO_DEVICE); | |
879 | d40d->is_hw_linked = true; | |
880 | } | |
881 | } | |
882 | ||
8d318a50 LW |
883 | static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx) |
884 | { | |
885 | struct d40_chan *d40c = container_of(tx->chan, | |
886 | struct d40_chan, | |
887 | chan); | |
888 | struct d40_desc *d40d = container_of(tx, struct d40_desc, txd); | |
889 | unsigned long flags; | |
890 | ||
aa182ae2 JA |
891 | (void) d40_pause(&d40c->chan); |
892 | ||
8d318a50 LW |
893 | spin_lock_irqsave(&d40c->lock, flags); |
894 | ||
aa182ae2 JA |
895 | d40c->chan.cookie++; |
896 | ||
897 | if (d40c->chan.cookie < 0) | |
898 | d40c->chan.cookie = 1; | |
899 | ||
900 | d40d->txd.cookie = d40c->chan.cookie; | |
901 | ||
902 | if (d40c->log_num == D40_PHY_CHAN) | |
903 | d40_tx_submit_phy(d40c, d40d); | |
904 | else | |
905 | d40_tx_submit_log(d40c, d40d); | |
8d318a50 LW |
906 | |
907 | d40_desc_queue(d40c, d40d); | |
908 | ||
909 | spin_unlock_irqrestore(&d40c->lock, flags); | |
910 | ||
aa182ae2 JA |
911 | (void) d40_resume(&d40c->chan); |
912 | ||
8d318a50 LW |
913 | return tx->cookie; |
914 | } | |
915 | ||
916 | static int d40_start(struct d40_chan *d40c) | |
917 | { | |
f4185592 LW |
918 | if (d40c->base->rev == 0) { |
919 | int err; | |
920 | ||
921 | if (d40c->log_num != D40_PHY_CHAN) { | |
922 | err = d40_channel_execute_command(d40c, | |
923 | D40_DMA_SUSPEND_REQ); | |
924 | if (err) | |
925 | return err; | |
926 | } | |
927 | } | |
928 | ||
0c32269d | 929 | if (d40c->log_num != D40_PHY_CHAN) |
8d318a50 | 930 | d40_config_set_event(d40c, true); |
8d318a50 | 931 | |
0c32269d | 932 | return d40_channel_execute_command(d40c, D40_DMA_RUN); |
8d318a50 LW |
933 | } |
934 | ||
935 | static struct d40_desc *d40_queue_start(struct d40_chan *d40c) | |
936 | { | |
937 | struct d40_desc *d40d; | |
938 | int err; | |
939 | ||
940 | /* Start queued jobs, if any */ | |
941 | d40d = d40_first_queued(d40c); | |
942 | ||
943 | if (d40d != NULL) { | |
944 | d40c->busy = true; | |
945 | ||
946 | /* Remove from queue */ | |
947 | d40_desc_remove(d40d); | |
948 | ||
949 | /* Add to active queue */ | |
950 | d40_desc_submit(d40c, d40d); | |
951 | ||
aa182ae2 JA |
952 | /* |
953 | * If this job is already linked in hw, | |
954 | * do not submit it. | |
955 | */ | |
956 | if (!d40d->is_hw_linked) { | |
957 | /* Initiate DMA job */ | |
958 | d40_desc_load(d40c, d40d); | |
8d318a50 | 959 | |
aa182ae2 JA |
960 | /* Start dma job */ |
961 | err = d40_start(d40c); | |
8d318a50 | 962 | |
aa182ae2 JA |
963 | if (err) |
964 | return NULL; | |
965 | } | |
8d318a50 LW |
966 | } |
967 | ||
968 | return d40d; | |
969 | } | |
970 | ||
971 | /* called from interrupt context */ | |
972 | static void dma_tc_handle(struct d40_chan *d40c) | |
973 | { | |
974 | struct d40_desc *d40d; | |
975 | ||
976 | if (!d40c->phy_chan) | |
977 | return; | |
978 | ||
979 | /* Get first active entry from list */ | |
980 | d40d = d40_first_active_get(d40c); | |
981 | ||
982 | if (d40d == NULL) | |
983 | return; | |
984 | ||
941b77a3 | 985 | if (d40d->lli_count < d40d->lli_len) { |
8d318a50 LW |
986 | |
987 | d40_desc_load(d40c, d40d); | |
988 | /* Start dma job */ | |
989 | (void) d40_start(d40c); | |
990 | return; | |
991 | } | |
992 | ||
993 | if (d40_queue_start(d40c) == NULL) | |
994 | d40c->busy = false; | |
995 | ||
996 | d40c->pending_tx++; | |
997 | tasklet_schedule(&d40c->tasklet); | |
998 | ||
999 | } | |
1000 | ||
1001 | static void dma_tasklet(unsigned long data) | |
1002 | { | |
1003 | struct d40_chan *d40c = (struct d40_chan *) data; | |
1004 | struct d40_desc *d40d_fin; | |
1005 | unsigned long flags; | |
1006 | dma_async_tx_callback callback; | |
1007 | void *callback_param; | |
1008 | ||
1009 | spin_lock_irqsave(&d40c->lock, flags); | |
1010 | ||
1011 | /* Get first active entry from list */ | |
1012 | d40d_fin = d40_first_active_get(d40c); | |
1013 | ||
1014 | if (d40d_fin == NULL) | |
1015 | goto err; | |
1016 | ||
1017 | d40c->completed = d40d_fin->txd.cookie; | |
1018 | ||
1019 | /* | |
1020 | * If terminating a channel pending_tx is set to zero. | |
1021 | * This prevents any finished active jobs to return to the client. | |
1022 | */ | |
1023 | if (d40c->pending_tx == 0) { | |
1024 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1025 | return; | |
1026 | } | |
1027 | ||
1028 | /* Callback to client */ | |
1029 | callback = d40d_fin->txd.callback; | |
1030 | callback_param = d40d_fin->txd.callback_param; | |
1031 | ||
1032 | if (async_tx_test_ack(&d40d_fin->txd)) { | |
1033 | d40_pool_lli_free(d40d_fin); | |
1034 | d40_desc_remove(d40d_fin); | |
1035 | /* Return desc to free-list */ | |
1036 | d40_desc_free(d40c, d40d_fin); | |
1037 | } else { | |
8d318a50 LW |
1038 | if (!d40d_fin->is_in_client_list) { |
1039 | d40_desc_remove(d40d_fin); | |
1040 | list_add_tail(&d40d_fin->node, &d40c->client); | |
1041 | d40d_fin->is_in_client_list = true; | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | d40c->pending_tx--; | |
1046 | ||
1047 | if (d40c->pending_tx) | |
1048 | tasklet_schedule(&d40c->tasklet); | |
1049 | ||
1050 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1051 | ||
0246e77b | 1052 | if (callback && (d40d_fin->txd.flags & DMA_PREP_INTERRUPT)) |
8d318a50 LW |
1053 | callback(callback_param); |
1054 | ||
1055 | return; | |
1056 | ||
1057 | err: | |
1058 | /* Rescue manouver if receiving double interrupts */ | |
1059 | if (d40c->pending_tx > 0) | |
1060 | d40c->pending_tx--; | |
1061 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1062 | } | |
1063 | ||
1064 | static irqreturn_t d40_handle_interrupt(int irq, void *data) | |
1065 | { | |
1066 | static const struct d40_interrupt_lookup il[] = { | |
1067 | {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0}, | |
1068 | {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32}, | |
1069 | {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64}, | |
1070 | {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96}, | |
1071 | {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0}, | |
1072 | {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32}, | |
1073 | {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64}, | |
1074 | {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96}, | |
1075 | {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN}, | |
1076 | {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN}, | |
1077 | }; | |
1078 | ||
1079 | int i; | |
1080 | u32 regs[ARRAY_SIZE(il)]; | |
8d318a50 LW |
1081 | u32 idx; |
1082 | u32 row; | |
1083 | long chan = -1; | |
1084 | struct d40_chan *d40c; | |
1085 | unsigned long flags; | |
1086 | struct d40_base *base = data; | |
1087 | ||
1088 | spin_lock_irqsave(&base->interrupt_lock, flags); | |
1089 | ||
1090 | /* Read interrupt status of both logical and physical channels */ | |
1091 | for (i = 0; i < ARRAY_SIZE(il); i++) | |
1092 | regs[i] = readl(base->virtbase + il[i].src); | |
1093 | ||
1094 | for (;;) { | |
1095 | ||
1096 | chan = find_next_bit((unsigned long *)regs, | |
1097 | BITS_PER_LONG * ARRAY_SIZE(il), chan + 1); | |
1098 | ||
1099 | /* No more set bits found? */ | |
1100 | if (chan == BITS_PER_LONG * ARRAY_SIZE(il)) | |
1101 | break; | |
1102 | ||
1103 | row = chan / BITS_PER_LONG; | |
1104 | idx = chan & (BITS_PER_LONG - 1); | |
1105 | ||
1106 | /* ACK interrupt */ | |
1b00348d | 1107 | writel(1 << idx, base->virtbase + il[row].clr); |
8d318a50 LW |
1108 | |
1109 | if (il[row].offset == D40_PHY_CHAN) | |
1110 | d40c = base->lookup_phy_chans[idx]; | |
1111 | else | |
1112 | d40c = base->lookup_log_chans[il[row].offset + idx]; | |
1113 | spin_lock(&d40c->lock); | |
1114 | ||
1115 | if (!il[row].is_error) | |
1116 | dma_tc_handle(d40c); | |
1117 | else | |
508849ad LW |
1118 | dev_err(base->dev, |
1119 | "[%s] IRQ chan: %ld offset %d idx %d\n", | |
8d318a50 LW |
1120 | __func__, chan, il[row].offset, idx); |
1121 | ||
1122 | spin_unlock(&d40c->lock); | |
1123 | } | |
1124 | ||
1125 | spin_unlock_irqrestore(&base->interrupt_lock, flags); | |
1126 | ||
1127 | return IRQ_HANDLED; | |
1128 | } | |
1129 | ||
1130 | ||
1131 | static int d40_validate_conf(struct d40_chan *d40c, | |
1132 | struct stedma40_chan_cfg *conf) | |
1133 | { | |
1134 | int res = 0; | |
1135 | u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type); | |
1136 | u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type); | |
1137 | bool is_log = (conf->channel_type & STEDMA40_CHANNEL_IN_OPER_MODE) | |
1138 | == STEDMA40_CHANNEL_IN_LOG_MODE; | |
1139 | ||
0747c7ba LW |
1140 | if (!conf->dir) { |
1141 | dev_err(&d40c->chan.dev->device, "[%s] Invalid direction.\n", | |
1142 | __func__); | |
1143 | res = -EINVAL; | |
1144 | } | |
1145 | ||
1146 | if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY && | |
1147 | d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 && | |
1148 | d40c->runtime_addr == 0) { | |
1149 | ||
1150 | dev_err(&d40c->chan.dev->device, | |
1151 | "[%s] Invalid TX channel address (%d)\n", | |
1152 | __func__, conf->dst_dev_type); | |
1153 | res = -EINVAL; | |
1154 | } | |
1155 | ||
1156 | if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY && | |
1157 | d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 && | |
1158 | d40c->runtime_addr == 0) { | |
1159 | dev_err(&d40c->chan.dev->device, | |
1160 | "[%s] Invalid RX channel address (%d)\n", | |
1161 | __func__, conf->src_dev_type); | |
1162 | res = -EINVAL; | |
1163 | } | |
1164 | ||
1165 | if (conf->dir == STEDMA40_MEM_TO_PERIPH && | |
8d318a50 LW |
1166 | dst_event_group == STEDMA40_DEV_DST_MEMORY) { |
1167 | dev_err(&d40c->chan.dev->device, "[%s] Invalid dst\n", | |
1168 | __func__); | |
1169 | res = -EINVAL; | |
1170 | } | |
1171 | ||
0747c7ba | 1172 | if (conf->dir == STEDMA40_PERIPH_TO_MEM && |
8d318a50 LW |
1173 | src_event_group == STEDMA40_DEV_SRC_MEMORY) { |
1174 | dev_err(&d40c->chan.dev->device, "[%s] Invalid src\n", | |
1175 | __func__); | |
1176 | res = -EINVAL; | |
1177 | } | |
1178 | ||
1179 | if (src_event_group == STEDMA40_DEV_SRC_MEMORY && | |
1180 | dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) { | |
1181 | dev_err(&d40c->chan.dev->device, | |
1182 | "[%s] No event line\n", __func__); | |
1183 | res = -EINVAL; | |
1184 | } | |
1185 | ||
1186 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH && | |
1187 | (src_event_group != dst_event_group)) { | |
1188 | dev_err(&d40c->chan.dev->device, | |
1189 | "[%s] Invalid event group\n", __func__); | |
1190 | res = -EINVAL; | |
1191 | } | |
1192 | ||
1193 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) { | |
1194 | /* | |
1195 | * DMAC HW supports it. Will be added to this driver, | |
1196 | * in case any dma client requires it. | |
1197 | */ | |
1198 | dev_err(&d40c->chan.dev->device, | |
1199 | "[%s] periph to periph not supported\n", | |
1200 | __func__); | |
1201 | res = -EINVAL; | |
1202 | } | |
1203 | ||
1204 | return res; | |
1205 | } | |
1206 | ||
1207 | static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src, | |
4aed79b2 | 1208 | int log_event_line, bool is_log) |
8d318a50 LW |
1209 | { |
1210 | unsigned long flags; | |
1211 | spin_lock_irqsave(&phy->lock, flags); | |
4aed79b2 | 1212 | if (!is_log) { |
8d318a50 LW |
1213 | /* Physical interrupts are masked per physical full channel */ |
1214 | if (phy->allocated_src == D40_ALLOC_FREE && | |
1215 | phy->allocated_dst == D40_ALLOC_FREE) { | |
1216 | phy->allocated_dst = D40_ALLOC_PHY; | |
1217 | phy->allocated_src = D40_ALLOC_PHY; | |
1218 | goto found; | |
1219 | } else | |
1220 | goto not_found; | |
1221 | } | |
1222 | ||
1223 | /* Logical channel */ | |
1224 | if (is_src) { | |
1225 | if (phy->allocated_src == D40_ALLOC_PHY) | |
1226 | goto not_found; | |
1227 | ||
1228 | if (phy->allocated_src == D40_ALLOC_FREE) | |
1229 | phy->allocated_src = D40_ALLOC_LOG_FREE; | |
1230 | ||
1231 | if (!(phy->allocated_src & (1 << log_event_line))) { | |
1232 | phy->allocated_src |= 1 << log_event_line; | |
1233 | goto found; | |
1234 | } else | |
1235 | goto not_found; | |
1236 | } else { | |
1237 | if (phy->allocated_dst == D40_ALLOC_PHY) | |
1238 | goto not_found; | |
1239 | ||
1240 | if (phy->allocated_dst == D40_ALLOC_FREE) | |
1241 | phy->allocated_dst = D40_ALLOC_LOG_FREE; | |
1242 | ||
1243 | if (!(phy->allocated_dst & (1 << log_event_line))) { | |
1244 | phy->allocated_dst |= 1 << log_event_line; | |
1245 | goto found; | |
1246 | } else | |
1247 | goto not_found; | |
1248 | } | |
1249 | ||
1250 | not_found: | |
1251 | spin_unlock_irqrestore(&phy->lock, flags); | |
1252 | return false; | |
1253 | found: | |
1254 | spin_unlock_irqrestore(&phy->lock, flags); | |
1255 | return true; | |
1256 | } | |
1257 | ||
1258 | static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, | |
1259 | int log_event_line) | |
1260 | { | |
1261 | unsigned long flags; | |
1262 | bool is_free = false; | |
1263 | ||
1264 | spin_lock_irqsave(&phy->lock, flags); | |
1265 | if (!log_event_line) { | |
1266 | /* Physical interrupts are masked per physical full channel */ | |
1267 | phy->allocated_dst = D40_ALLOC_FREE; | |
1268 | phy->allocated_src = D40_ALLOC_FREE; | |
1269 | is_free = true; | |
1270 | goto out; | |
1271 | } | |
1272 | ||
1273 | /* Logical channel */ | |
1274 | if (is_src) { | |
1275 | phy->allocated_src &= ~(1 << log_event_line); | |
1276 | if (phy->allocated_src == D40_ALLOC_LOG_FREE) | |
1277 | phy->allocated_src = D40_ALLOC_FREE; | |
1278 | } else { | |
1279 | phy->allocated_dst &= ~(1 << log_event_line); | |
1280 | if (phy->allocated_dst == D40_ALLOC_LOG_FREE) | |
1281 | phy->allocated_dst = D40_ALLOC_FREE; | |
1282 | } | |
1283 | ||
1284 | is_free = ((phy->allocated_src | phy->allocated_dst) == | |
1285 | D40_ALLOC_FREE); | |
1286 | ||
1287 | out: | |
1288 | spin_unlock_irqrestore(&phy->lock, flags); | |
1289 | ||
1290 | return is_free; | |
1291 | } | |
1292 | ||
1293 | static int d40_allocate_channel(struct d40_chan *d40c) | |
1294 | { | |
1295 | int dev_type; | |
1296 | int event_group; | |
1297 | int event_line; | |
1298 | struct d40_phy_res *phys; | |
1299 | int i; | |
1300 | int j; | |
1301 | int log_num; | |
1302 | bool is_src; | |
508849ad LW |
1303 | bool is_log = (d40c->dma_cfg.channel_type & |
1304 | STEDMA40_CHANNEL_IN_OPER_MODE) | |
8d318a50 LW |
1305 | == STEDMA40_CHANNEL_IN_LOG_MODE; |
1306 | ||
1307 | ||
1308 | phys = d40c->base->phy_res; | |
1309 | ||
1310 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { | |
1311 | dev_type = d40c->dma_cfg.src_dev_type; | |
1312 | log_num = 2 * dev_type; | |
1313 | is_src = true; | |
1314 | } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || | |
1315 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1316 | /* dst event lines are used for logical memcpy */ | |
1317 | dev_type = d40c->dma_cfg.dst_dev_type; | |
1318 | log_num = 2 * dev_type + 1; | |
1319 | is_src = false; | |
1320 | } else | |
1321 | return -EINVAL; | |
1322 | ||
1323 | event_group = D40_TYPE_TO_GROUP(dev_type); | |
1324 | event_line = D40_TYPE_TO_EVENT(dev_type); | |
1325 | ||
1326 | if (!is_log) { | |
1327 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1328 | /* Find physical half channel */ | |
1329 | for (i = 0; i < d40c->base->num_phy_chans; i++) { | |
1330 | ||
4aed79b2 MM |
1331 | if (d40_alloc_mask_set(&phys[i], is_src, |
1332 | 0, is_log)) | |
8d318a50 LW |
1333 | goto found_phy; |
1334 | } | |
1335 | } else | |
1336 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { | |
1337 | int phy_num = j + event_group * 2; | |
1338 | for (i = phy_num; i < phy_num + 2; i++) { | |
508849ad LW |
1339 | if (d40_alloc_mask_set(&phys[i], |
1340 | is_src, | |
1341 | 0, | |
1342 | is_log)) | |
8d318a50 LW |
1343 | goto found_phy; |
1344 | } | |
1345 | } | |
1346 | return -EINVAL; | |
1347 | found_phy: | |
1348 | d40c->phy_chan = &phys[i]; | |
1349 | d40c->log_num = D40_PHY_CHAN; | |
1350 | goto out; | |
1351 | } | |
1352 | if (dev_type == -1) | |
1353 | return -EINVAL; | |
1354 | ||
1355 | /* Find logical channel */ | |
1356 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { | |
1357 | int phy_num = j + event_group * 2; | |
1358 | /* | |
1359 | * Spread logical channels across all available physical rather | |
1360 | * than pack every logical channel at the first available phy | |
1361 | * channels. | |
1362 | */ | |
1363 | if (is_src) { | |
1364 | for (i = phy_num; i < phy_num + 2; i++) { | |
1365 | if (d40_alloc_mask_set(&phys[i], is_src, | |
4aed79b2 | 1366 | event_line, is_log)) |
8d318a50 LW |
1367 | goto found_log; |
1368 | } | |
1369 | } else { | |
1370 | for (i = phy_num + 1; i >= phy_num; i--) { | |
1371 | if (d40_alloc_mask_set(&phys[i], is_src, | |
4aed79b2 | 1372 | event_line, is_log)) |
8d318a50 LW |
1373 | goto found_log; |
1374 | } | |
1375 | } | |
1376 | } | |
1377 | return -EINVAL; | |
1378 | ||
1379 | found_log: | |
1380 | d40c->phy_chan = &phys[i]; | |
1381 | d40c->log_num = log_num; | |
1382 | out: | |
1383 | ||
1384 | if (is_log) | |
1385 | d40c->base->lookup_log_chans[d40c->log_num] = d40c; | |
1386 | else | |
1387 | d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; | |
1388 | ||
1389 | return 0; | |
1390 | ||
1391 | } | |
1392 | ||
8d318a50 LW |
1393 | static int d40_config_memcpy(struct d40_chan *d40c) |
1394 | { | |
1395 | dma_cap_mask_t cap = d40c->chan.device->cap_mask; | |
1396 | ||
1397 | if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { | |
1398 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log; | |
1399 | d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY; | |
1400 | d40c->dma_cfg.dst_dev_type = d40c->base->plat_data-> | |
1401 | memcpy[d40c->chan.chan_id]; | |
1402 | ||
1403 | } else if (dma_has_cap(DMA_MEMCPY, cap) && | |
1404 | dma_has_cap(DMA_SLAVE, cap)) { | |
1405 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy; | |
1406 | } else { | |
1407 | dev_err(&d40c->chan.dev->device, "[%s] No memcpy\n", | |
1408 | __func__); | |
1409 | return -EINVAL; | |
1410 | } | |
1411 | ||
1412 | return 0; | |
1413 | } | |
1414 | ||
1415 | ||
1416 | static int d40_free_dma(struct d40_chan *d40c) | |
1417 | { | |
1418 | ||
1419 | int res = 0; | |
d181b3a8 | 1420 | u32 event; |
8d318a50 LW |
1421 | struct d40_phy_res *phy = d40c->phy_chan; |
1422 | bool is_src; | |
a8be8627 PF |
1423 | struct d40_desc *d; |
1424 | struct d40_desc *_d; | |
1425 | ||
8d318a50 LW |
1426 | |
1427 | /* Terminate all queued and active transfers */ | |
1428 | d40_term_all(d40c); | |
1429 | ||
a8be8627 PF |
1430 | /* Release client owned descriptors */ |
1431 | if (!list_empty(&d40c->client)) | |
1432 | list_for_each_entry_safe(d, _d, &d40c->client, node) { | |
1433 | d40_pool_lli_free(d); | |
1434 | d40_desc_remove(d); | |
1435 | /* Return desc to free-list */ | |
1436 | d40_desc_free(d40c, d); | |
1437 | } | |
1438 | ||
8d318a50 LW |
1439 | if (phy == NULL) { |
1440 | dev_err(&d40c->chan.dev->device, "[%s] phy == null\n", | |
1441 | __func__); | |
1442 | return -EINVAL; | |
1443 | } | |
1444 | ||
1445 | if (phy->allocated_src == D40_ALLOC_FREE && | |
1446 | phy->allocated_dst == D40_ALLOC_FREE) { | |
1447 | dev_err(&d40c->chan.dev->device, "[%s] channel already free\n", | |
1448 | __func__); | |
1449 | return -EINVAL; | |
1450 | } | |
1451 | ||
8d318a50 LW |
1452 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
1453 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1454 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
8d318a50 LW |
1455 | is_src = false; |
1456 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { | |
1457 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
8d318a50 LW |
1458 | is_src = true; |
1459 | } else { | |
1460 | dev_err(&d40c->chan.dev->device, | |
1461 | "[%s] Unknown direction\n", __func__); | |
1462 | return -EINVAL; | |
1463 | } | |
1464 | ||
d181b3a8 JA |
1465 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); |
1466 | if (res) { | |
1467 | dev_err(&d40c->chan.dev->device, "[%s] suspend failed\n", | |
1468 | __func__); | |
1469 | return res; | |
1470 | } | |
1471 | ||
8d318a50 | 1472 | if (d40c->log_num != D40_PHY_CHAN) { |
d181b3a8 | 1473 | /* Release logical channel, deactivate the event line */ |
8d318a50 | 1474 | |
d181b3a8 | 1475 | d40_config_set_event(d40c, false); |
8d318a50 LW |
1476 | d40c->base->lookup_log_chans[d40c->log_num] = NULL; |
1477 | ||
1478 | /* | |
1479 | * Check if there are more logical allocation | |
1480 | * on this phy channel. | |
1481 | */ | |
1482 | if (!d40_alloc_mask_free(phy, is_src, event)) { | |
1483 | /* Resume the other logical channels if any */ | |
1484 | if (d40_chan_has_events(d40c)) { | |
1485 | res = d40_channel_execute_command(d40c, | |
1486 | D40_DMA_RUN); | |
1487 | if (res) { | |
1488 | dev_err(&d40c->chan.dev->device, | |
1489 | "[%s] Executing RUN command\n", | |
1490 | __func__); | |
1491 | return res; | |
1492 | } | |
1493 | } | |
1494 | return 0; | |
1495 | } | |
d181b3a8 JA |
1496 | } else { |
1497 | (void) d40_alloc_mask_free(phy, is_src, 0); | |
1498 | } | |
8d318a50 LW |
1499 | |
1500 | /* Release physical channel */ | |
1501 | res = d40_channel_execute_command(d40c, D40_DMA_STOP); | |
1502 | if (res) { | |
1503 | dev_err(&d40c->chan.dev->device, | |
1504 | "[%s] Failed to stop channel\n", __func__); | |
1505 | return res; | |
1506 | } | |
1507 | d40c->phy_chan = NULL; | |
1508 | /* Invalidate channel type */ | |
1509 | d40c->dma_cfg.channel_type = 0; | |
1510 | d40c->base->lookup_phy_chans[phy->num] = NULL; | |
1511 | ||
1512 | return 0; | |
8d318a50 LW |
1513 | } |
1514 | ||
a5ebca47 JA |
1515 | static bool d40_is_paused(struct d40_chan *d40c) |
1516 | { | |
1517 | bool is_paused = false; | |
1518 | unsigned long flags; | |
1519 | void __iomem *active_reg; | |
1520 | u32 status; | |
1521 | u32 event; | |
a5ebca47 JA |
1522 | |
1523 | spin_lock_irqsave(&d40c->lock, flags); | |
1524 | ||
1525 | if (d40c->log_num == D40_PHY_CHAN) { | |
1526 | if (d40c->phy_chan->num % 2 == 0) | |
1527 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; | |
1528 | else | |
1529 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; | |
1530 | ||
1531 | status = (readl(active_reg) & | |
1532 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
1533 | D40_CHAN_POS(d40c->phy_chan->num); | |
1534 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) | |
1535 | is_paused = true; | |
1536 | ||
1537 | goto _exit; | |
1538 | } | |
1539 | ||
a5ebca47 JA |
1540 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
1541 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) | |
1542 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
1543 | else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) | |
1544 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
1545 | else { | |
1546 | dev_err(&d40c->chan.dev->device, | |
1547 | "[%s] Unknown direction\n", __func__); | |
1548 | goto _exit; | |
1549 | } | |
1550 | status = d40_chan_has_events(d40c); | |
1551 | status = (status & D40_EVENTLINE_MASK(event)) >> | |
1552 | D40_EVENTLINE_POS(event); | |
1553 | ||
1554 | if (status != D40_DMA_RUN) | |
1555 | is_paused = true; | |
a5ebca47 JA |
1556 | _exit: |
1557 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1558 | return is_paused; | |
1559 | ||
1560 | } | |
1561 | ||
1562 | ||
8d318a50 LW |
1563 | static u32 stedma40_residue(struct dma_chan *chan) |
1564 | { | |
1565 | struct d40_chan *d40c = | |
1566 | container_of(chan, struct d40_chan, chan); | |
1567 | u32 bytes_left; | |
1568 | unsigned long flags; | |
1569 | ||
1570 | spin_lock_irqsave(&d40c->lock, flags); | |
1571 | bytes_left = d40_residue(d40c); | |
1572 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1573 | ||
1574 | return bytes_left; | |
1575 | } | |
1576 | ||
1577 | /* Public DMA functions in addition to the DMA engine framework */ | |
1578 | ||
1579 | int stedma40_set_psize(struct dma_chan *chan, | |
1580 | int src_psize, | |
1581 | int dst_psize) | |
1582 | { | |
1583 | struct d40_chan *d40c = | |
1584 | container_of(chan, struct d40_chan, chan); | |
1585 | unsigned long flags; | |
1586 | ||
1587 | spin_lock_irqsave(&d40c->lock, flags); | |
1588 | ||
1589 | if (d40c->log_num != D40_PHY_CHAN) { | |
1590 | d40c->log_def.lcsp1 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK; | |
1591 | d40c->log_def.lcsp3 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK; | |
508849ad LW |
1592 | d40c->log_def.lcsp1 |= src_psize << |
1593 | D40_MEM_LCSP1_SCFG_PSIZE_POS; | |
1594 | d40c->log_def.lcsp3 |= dst_psize << | |
1595 | D40_MEM_LCSP1_SCFG_PSIZE_POS; | |
8d318a50 LW |
1596 | goto out; |
1597 | } | |
1598 | ||
1599 | if (src_psize == STEDMA40_PSIZE_PHY_1) | |
1600 | d40c->src_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS); | |
1601 | else { | |
1602 | d40c->src_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS; | |
1603 | d40c->src_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 << | |
1604 | D40_SREG_CFG_PSIZE_POS); | |
1605 | d40c->src_def_cfg |= src_psize << D40_SREG_CFG_PSIZE_POS; | |
1606 | } | |
1607 | ||
1608 | if (dst_psize == STEDMA40_PSIZE_PHY_1) | |
1609 | d40c->dst_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS); | |
1610 | else { | |
1611 | d40c->dst_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS; | |
1612 | d40c->dst_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 << | |
1613 | D40_SREG_CFG_PSIZE_POS); | |
1614 | d40c->dst_def_cfg |= dst_psize << D40_SREG_CFG_PSIZE_POS; | |
1615 | } | |
1616 | out: | |
1617 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1618 | return 0; | |
1619 | } | |
1620 | EXPORT_SYMBOL(stedma40_set_psize); | |
1621 | ||
1622 | struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan, | |
1623 | struct scatterlist *sgl_dst, | |
1624 | struct scatterlist *sgl_src, | |
1625 | unsigned int sgl_len, | |
2a614340 | 1626 | unsigned long dma_flags) |
8d318a50 LW |
1627 | { |
1628 | int res; | |
1629 | struct d40_desc *d40d; | |
1630 | struct d40_chan *d40c = container_of(chan, struct d40_chan, | |
1631 | chan); | |
2a614340 | 1632 | unsigned long flags; |
8d318a50 | 1633 | |
0d0f6b8b JA |
1634 | if (d40c->phy_chan == NULL) { |
1635 | dev_err(&d40c->chan.dev->device, | |
1636 | "[%s] Unallocated channel.\n", __func__); | |
1637 | return ERR_PTR(-EINVAL); | |
1638 | } | |
1639 | ||
2a614340 | 1640 | spin_lock_irqsave(&d40c->lock, flags); |
8d318a50 LW |
1641 | d40d = d40_desc_get(d40c); |
1642 | ||
1643 | if (d40d == NULL) | |
1644 | goto err; | |
1645 | ||
8d318a50 | 1646 | d40d->lli_len = sgl_len; |
941b77a3 | 1647 | d40d->lli_tx_len = d40d->lli_len; |
2a614340 | 1648 | d40d->txd.flags = dma_flags; |
8d318a50 LW |
1649 | |
1650 | if (d40c->log_num != D40_PHY_CHAN) { | |
941b77a3 PF |
1651 | if (d40d->lli_len > d40c->base->plat_data->llis_per_log) |
1652 | d40d->lli_tx_len = d40c->base->plat_data->llis_per_log; | |
1653 | ||
8d318a50 LW |
1654 | if (sgl_len > 1) |
1655 | /* | |
1656 | * Check if there is space available in lcla. If not, | |
1657 | * split list into 1-length and run only in lcpa | |
1658 | * space. | |
1659 | */ | |
508849ad | 1660 | if (d40_lcla_id_get(d40c) != 0) |
941b77a3 | 1661 | d40d->lli_tx_len = 1; |
8d318a50 LW |
1662 | |
1663 | if (d40_pool_lli_alloc(d40d, sgl_len, true) < 0) { | |
1664 | dev_err(&d40c->chan.dev->device, | |
1665 | "[%s] Out of memory\n", __func__); | |
1666 | goto err; | |
1667 | } | |
1668 | ||
1669 | (void) d40_log_sg_to_lli(d40c->lcla.src_id, | |
1670 | sgl_src, | |
1671 | sgl_len, | |
1672 | d40d->lli_log.src, | |
1673 | d40c->log_def.lcsp1, | |
1674 | d40c->dma_cfg.src_info.data_width, | |
941b77a3 | 1675 | d40d->lli_tx_len, |
8d318a50 LW |
1676 | d40c->base->plat_data->llis_per_log); |
1677 | ||
1678 | (void) d40_log_sg_to_lli(d40c->lcla.dst_id, | |
1679 | sgl_dst, | |
1680 | sgl_len, | |
1681 | d40d->lli_log.dst, | |
1682 | d40c->log_def.lcsp3, | |
1683 | d40c->dma_cfg.dst_info.data_width, | |
941b77a3 | 1684 | d40d->lli_tx_len, |
8d318a50 LW |
1685 | d40c->base->plat_data->llis_per_log); |
1686 | ||
1687 | ||
1688 | } else { | |
1689 | if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) { | |
1690 | dev_err(&d40c->chan.dev->device, | |
1691 | "[%s] Out of memory\n", __func__); | |
1692 | goto err; | |
1693 | } | |
1694 | ||
1695 | res = d40_phy_sg_to_lli(sgl_src, | |
1696 | sgl_len, | |
1697 | 0, | |
1698 | d40d->lli_phy.src, | |
aa182ae2 | 1699 | virt_to_phys(d40d->lli_phy.src), |
8d318a50 LW |
1700 | d40c->src_def_cfg, |
1701 | d40c->dma_cfg.src_info.data_width, | |
0246e77b | 1702 | d40c->dma_cfg.src_info.psize); |
8d318a50 LW |
1703 | |
1704 | if (res < 0) | |
1705 | goto err; | |
1706 | ||
1707 | res = d40_phy_sg_to_lli(sgl_dst, | |
1708 | sgl_len, | |
1709 | 0, | |
1710 | d40d->lli_phy.dst, | |
aa182ae2 | 1711 | virt_to_phys(d40d->lli_phy.dst), |
8d318a50 LW |
1712 | d40c->dst_def_cfg, |
1713 | d40c->dma_cfg.dst_info.data_width, | |
0246e77b | 1714 | d40c->dma_cfg.dst_info.psize); |
8d318a50 LW |
1715 | |
1716 | if (res < 0) | |
1717 | goto err; | |
1718 | ||
1719 | (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src, | |
1720 | d40d->lli_pool.size, DMA_TO_DEVICE); | |
1721 | } | |
1722 | ||
1723 | dma_async_tx_descriptor_init(&d40d->txd, chan); | |
1724 | ||
1725 | d40d->txd.tx_submit = d40_tx_submit; | |
1726 | ||
2a614340 | 1727 | spin_unlock_irqrestore(&d40c->lock, flags); |
8d318a50 LW |
1728 | |
1729 | return &d40d->txd; | |
1730 | err: | |
2a614340 | 1731 | spin_unlock_irqrestore(&d40c->lock, flags); |
8d318a50 LW |
1732 | return NULL; |
1733 | } | |
1734 | EXPORT_SYMBOL(stedma40_memcpy_sg); | |
1735 | ||
1736 | bool stedma40_filter(struct dma_chan *chan, void *data) | |
1737 | { | |
1738 | struct stedma40_chan_cfg *info = data; | |
1739 | struct d40_chan *d40c = | |
1740 | container_of(chan, struct d40_chan, chan); | |
1741 | int err; | |
1742 | ||
1743 | if (data) { | |
1744 | err = d40_validate_conf(d40c, info); | |
1745 | if (!err) | |
1746 | d40c->dma_cfg = *info; | |
1747 | } else | |
1748 | err = d40_config_memcpy(d40c); | |
1749 | ||
1750 | return err == 0; | |
1751 | } | |
1752 | EXPORT_SYMBOL(stedma40_filter); | |
1753 | ||
1754 | /* DMA ENGINE functions */ | |
1755 | static int d40_alloc_chan_resources(struct dma_chan *chan) | |
1756 | { | |
1757 | int err; | |
1758 | unsigned long flags; | |
1759 | struct d40_chan *d40c = | |
1760 | container_of(chan, struct d40_chan, chan); | |
ef1872ec | 1761 | bool is_free_phy; |
8d318a50 LW |
1762 | spin_lock_irqsave(&d40c->lock, flags); |
1763 | ||
1764 | d40c->completed = chan->cookie = 1; | |
1765 | ||
1766 | /* | |
1767 | * If no dma configuration is set (channel_type == 0) | |
ef1872ec | 1768 | * use default configuration (memcpy) |
8d318a50 LW |
1769 | */ |
1770 | if (d40c->dma_cfg.channel_type == 0) { | |
aa182ae2 | 1771 | |
8d318a50 | 1772 | err = d40_config_memcpy(d40c); |
ff0b12ba JA |
1773 | if (err) { |
1774 | dev_err(&d40c->chan.dev->device, | |
1775 | "[%s] Failed to configure memcpy channel\n", | |
1776 | __func__); | |
1777 | goto fail; | |
1778 | } | |
8d318a50 | 1779 | } |
ef1872ec | 1780 | is_free_phy = (d40c->phy_chan == NULL); |
8d318a50 LW |
1781 | |
1782 | err = d40_allocate_channel(d40c); | |
1783 | if (err) { | |
1784 | dev_err(&d40c->chan.dev->device, | |
1785 | "[%s] Failed to allocate channel\n", __func__); | |
ff0b12ba | 1786 | goto fail; |
8d318a50 LW |
1787 | } |
1788 | ||
ef1872ec LW |
1789 | /* Fill in basic CFG register values */ |
1790 | d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, | |
1791 | &d40c->dst_def_cfg, d40c->log_num != D40_PHY_CHAN); | |
1792 | ||
1793 | if (d40c->log_num != D40_PHY_CHAN) { | |
1794 | d40_log_cfg(&d40c->dma_cfg, | |
1795 | &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); | |
1796 | ||
1797 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) | |
1798 | d40c->lcpa = d40c->base->lcpa_base + | |
1799 | d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE; | |
1800 | else | |
1801 | d40c->lcpa = d40c->base->lcpa_base + | |
1802 | d40c->dma_cfg.dst_dev_type * | |
1803 | D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; | |
1804 | } | |
1805 | ||
1806 | /* | |
1807 | * Only write channel configuration to the DMA if the physical | |
1808 | * resource is free. In case of multiple logical channels | |
1809 | * on the same physical resource, only the first write is necessary. | |
1810 | */ | |
b55912c6 JA |
1811 | if (is_free_phy) |
1812 | d40_config_write(d40c); | |
ff0b12ba | 1813 | fail: |
8d318a50 | 1814 | spin_unlock_irqrestore(&d40c->lock, flags); |
ff0b12ba | 1815 | return err; |
8d318a50 LW |
1816 | } |
1817 | ||
1818 | static void d40_free_chan_resources(struct dma_chan *chan) | |
1819 | { | |
1820 | struct d40_chan *d40c = | |
1821 | container_of(chan, struct d40_chan, chan); | |
1822 | int err; | |
1823 | unsigned long flags; | |
1824 | ||
0d0f6b8b JA |
1825 | if (d40c->phy_chan == NULL) { |
1826 | dev_err(&d40c->chan.dev->device, | |
1827 | "[%s] Cannot free unallocated channel\n", __func__); | |
1828 | return; | |
1829 | } | |
1830 | ||
1831 | ||
8d318a50 LW |
1832 | spin_lock_irqsave(&d40c->lock, flags); |
1833 | ||
1834 | err = d40_free_dma(d40c); | |
1835 | ||
1836 | if (err) | |
1837 | dev_err(&d40c->chan.dev->device, | |
1838 | "[%s] Failed to free channel\n", __func__); | |
1839 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1840 | } | |
1841 | ||
1842 | static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan, | |
1843 | dma_addr_t dst, | |
1844 | dma_addr_t src, | |
1845 | size_t size, | |
2a614340 | 1846 | unsigned long dma_flags) |
8d318a50 LW |
1847 | { |
1848 | struct d40_desc *d40d; | |
1849 | struct d40_chan *d40c = container_of(chan, struct d40_chan, | |
1850 | chan); | |
2a614340 | 1851 | unsigned long flags; |
8d318a50 LW |
1852 | int err = 0; |
1853 | ||
0d0f6b8b JA |
1854 | if (d40c->phy_chan == NULL) { |
1855 | dev_err(&d40c->chan.dev->device, | |
1856 | "[%s] Channel is not allocated.\n", __func__); | |
1857 | return ERR_PTR(-EINVAL); | |
1858 | } | |
1859 | ||
2a614340 | 1860 | spin_lock_irqsave(&d40c->lock, flags); |
8d318a50 LW |
1861 | d40d = d40_desc_get(d40c); |
1862 | ||
1863 | if (d40d == NULL) { | |
1864 | dev_err(&d40c->chan.dev->device, | |
1865 | "[%s] Descriptor is NULL\n", __func__); | |
1866 | goto err; | |
1867 | } | |
1868 | ||
2a614340 | 1869 | d40d->txd.flags = dma_flags; |
8d318a50 LW |
1870 | |
1871 | dma_async_tx_descriptor_init(&d40d->txd, chan); | |
1872 | ||
1873 | d40d->txd.tx_submit = d40_tx_submit; | |
1874 | ||
1875 | if (d40c->log_num != D40_PHY_CHAN) { | |
1876 | ||
1877 | if (d40_pool_lli_alloc(d40d, 1, true) < 0) { | |
1878 | dev_err(&d40c->chan.dev->device, | |
1879 | "[%s] Out of memory\n", __func__); | |
1880 | goto err; | |
1881 | } | |
1882 | d40d->lli_len = 1; | |
941b77a3 | 1883 | d40d->lli_tx_len = 1; |
8d318a50 LW |
1884 | |
1885 | d40_log_fill_lli(d40d->lli_log.src, | |
1886 | src, | |
1887 | size, | |
1888 | 0, | |
1889 | d40c->log_def.lcsp1, | |
1890 | d40c->dma_cfg.src_info.data_width, | |
2123a61e | 1891 | false, true); |
8d318a50 LW |
1892 | |
1893 | d40_log_fill_lli(d40d->lli_log.dst, | |
1894 | dst, | |
1895 | size, | |
1896 | 0, | |
1897 | d40c->log_def.lcsp3, | |
1898 | d40c->dma_cfg.dst_info.data_width, | |
1899 | true, true); | |
1900 | ||
1901 | } else { | |
1902 | ||
1903 | if (d40_pool_lli_alloc(d40d, 1, false) < 0) { | |
1904 | dev_err(&d40c->chan.dev->device, | |
1905 | "[%s] Out of memory\n", __func__); | |
1906 | goto err; | |
1907 | } | |
1908 | ||
1909 | err = d40_phy_fill_lli(d40d->lli_phy.src, | |
1910 | src, | |
1911 | size, | |
1912 | d40c->dma_cfg.src_info.psize, | |
1913 | 0, | |
1914 | d40c->src_def_cfg, | |
1915 | true, | |
1916 | d40c->dma_cfg.src_info.data_width, | |
1917 | false); | |
1918 | if (err) | |
1919 | goto err_fill_lli; | |
1920 | ||
1921 | err = d40_phy_fill_lli(d40d->lli_phy.dst, | |
1922 | dst, | |
1923 | size, | |
1924 | d40c->dma_cfg.dst_info.psize, | |
1925 | 0, | |
1926 | d40c->dst_def_cfg, | |
1927 | true, | |
1928 | d40c->dma_cfg.dst_info.data_width, | |
1929 | false); | |
1930 | ||
1931 | if (err) | |
1932 | goto err_fill_lli; | |
1933 | ||
1934 | (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src, | |
1935 | d40d->lli_pool.size, DMA_TO_DEVICE); | |
1936 | } | |
1937 | ||
2a614340 | 1938 | spin_unlock_irqrestore(&d40c->lock, flags); |
8d318a50 LW |
1939 | return &d40d->txd; |
1940 | ||
1941 | err_fill_lli: | |
1942 | dev_err(&d40c->chan.dev->device, | |
1943 | "[%s] Failed filling in PHY LLI\n", __func__); | |
1944 | d40_pool_lli_free(d40d); | |
1945 | err: | |
2a614340 | 1946 | spin_unlock_irqrestore(&d40c->lock, flags); |
8d318a50 LW |
1947 | return NULL; |
1948 | } | |
1949 | ||
1950 | static int d40_prep_slave_sg_log(struct d40_desc *d40d, | |
1951 | struct d40_chan *d40c, | |
1952 | struct scatterlist *sgl, | |
1953 | unsigned int sg_len, | |
1954 | enum dma_data_direction direction, | |
2a614340 | 1955 | unsigned long dma_flags) |
8d318a50 LW |
1956 | { |
1957 | dma_addr_t dev_addr = 0; | |
1958 | int total_size; | |
8d318a50 LW |
1959 | |
1960 | if (d40_pool_lli_alloc(d40d, sg_len, true) < 0) { | |
1961 | dev_err(&d40c->chan.dev->device, | |
1962 | "[%s] Out of memory\n", __func__); | |
1963 | return -ENOMEM; | |
1964 | } | |
1965 | ||
1966 | d40d->lli_len = sg_len; | |
941b77a3 PF |
1967 | if (d40d->lli_len <= d40c->base->plat_data->llis_per_log) |
1968 | d40d->lli_tx_len = d40d->lli_len; | |
1969 | else | |
1970 | d40d->lli_tx_len = d40c->base->plat_data->llis_per_log; | |
8d318a50 LW |
1971 | |
1972 | if (sg_len > 1) | |
1973 | /* | |
1974 | * Check if there is space available in lcla. | |
1975 | * If not, split list into 1-length and run only | |
1976 | * in lcpa space. | |
1977 | */ | |
508849ad | 1978 | if (d40_lcla_id_get(d40c) != 0) |
941b77a3 | 1979 | d40d->lli_tx_len = 1; |
8d318a50 | 1980 | |
2a614340 | 1981 | if (direction == DMA_FROM_DEVICE) |
95e1400f LW |
1982 | if (d40c->runtime_addr) |
1983 | dev_addr = d40c->runtime_addr; | |
1984 | else | |
1985 | dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type]; | |
2a614340 | 1986 | else if (direction == DMA_TO_DEVICE) |
95e1400f LW |
1987 | if (d40c->runtime_addr) |
1988 | dev_addr = d40c->runtime_addr; | |
1989 | else | |
1990 | dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type]; | |
1991 | ||
2a614340 | 1992 | else |
8d318a50 | 1993 | return -EINVAL; |
2a614340 JA |
1994 | |
1995 | total_size = d40_log_sg_to_dev(&d40c->lcla, | |
1996 | sgl, sg_len, | |
1997 | &d40d->lli_log, | |
1998 | &d40c->log_def, | |
1999 | d40c->dma_cfg.src_info.data_width, | |
2000 | d40c->dma_cfg.dst_info.data_width, | |
2001 | direction, | |
2a614340 JA |
2002 | dev_addr, d40d->lli_tx_len, |
2003 | d40c->base->plat_data->llis_per_log); | |
2004 | ||
8d318a50 LW |
2005 | if (total_size < 0) |
2006 | return -EINVAL; | |
2007 | ||
2008 | return 0; | |
2009 | } | |
2010 | ||
2011 | static int d40_prep_slave_sg_phy(struct d40_desc *d40d, | |
2012 | struct d40_chan *d40c, | |
2013 | struct scatterlist *sgl, | |
2014 | unsigned int sgl_len, | |
2015 | enum dma_data_direction direction, | |
2a614340 | 2016 | unsigned long dma_flags) |
8d318a50 LW |
2017 | { |
2018 | dma_addr_t src_dev_addr; | |
2019 | dma_addr_t dst_dev_addr; | |
2020 | int res; | |
2021 | ||
2022 | if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) { | |
2023 | dev_err(&d40c->chan.dev->device, | |
2024 | "[%s] Out of memory\n", __func__); | |
2025 | return -ENOMEM; | |
2026 | } | |
2027 | ||
2028 | d40d->lli_len = sgl_len; | |
941b77a3 | 2029 | d40d->lli_tx_len = sgl_len; |
8d318a50 LW |
2030 | |
2031 | if (direction == DMA_FROM_DEVICE) { | |
2032 | dst_dev_addr = 0; | |
95e1400f LW |
2033 | if (d40c->runtime_addr) |
2034 | src_dev_addr = d40c->runtime_addr; | |
2035 | else | |
2036 | src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type]; | |
8d318a50 | 2037 | } else if (direction == DMA_TO_DEVICE) { |
95e1400f LW |
2038 | if (d40c->runtime_addr) |
2039 | dst_dev_addr = d40c->runtime_addr; | |
2040 | else | |
2041 | dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type]; | |
8d318a50 LW |
2042 | src_dev_addr = 0; |
2043 | } else | |
2044 | return -EINVAL; | |
2045 | ||
2046 | res = d40_phy_sg_to_lli(sgl, | |
2047 | sgl_len, | |
2048 | src_dev_addr, | |
2049 | d40d->lli_phy.src, | |
aa182ae2 | 2050 | virt_to_phys(d40d->lli_phy.src), |
8d318a50 LW |
2051 | d40c->src_def_cfg, |
2052 | d40c->dma_cfg.src_info.data_width, | |
0246e77b | 2053 | d40c->dma_cfg.src_info.psize); |
8d318a50 LW |
2054 | if (res < 0) |
2055 | return res; | |
2056 | ||
2057 | res = d40_phy_sg_to_lli(sgl, | |
2058 | sgl_len, | |
2059 | dst_dev_addr, | |
2060 | d40d->lli_phy.dst, | |
aa182ae2 | 2061 | virt_to_phys(d40d->lli_phy.dst), |
8d318a50 LW |
2062 | d40c->dst_def_cfg, |
2063 | d40c->dma_cfg.dst_info.data_width, | |
0246e77b | 2064 | d40c->dma_cfg.dst_info.psize); |
8d318a50 LW |
2065 | if (res < 0) |
2066 | return res; | |
2067 | ||
2068 | (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src, | |
2069 | d40d->lli_pool.size, DMA_TO_DEVICE); | |
2070 | return 0; | |
2071 | } | |
2072 | ||
2073 | static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan, | |
2074 | struct scatterlist *sgl, | |
2075 | unsigned int sg_len, | |
2076 | enum dma_data_direction direction, | |
2a614340 | 2077 | unsigned long dma_flags) |
8d318a50 LW |
2078 | { |
2079 | struct d40_desc *d40d; | |
2080 | struct d40_chan *d40c = container_of(chan, struct d40_chan, | |
2081 | chan); | |
2a614340 | 2082 | unsigned long flags; |
8d318a50 LW |
2083 | int err; |
2084 | ||
0d0f6b8b JA |
2085 | if (d40c->phy_chan == NULL) { |
2086 | dev_err(&d40c->chan.dev->device, | |
2087 | "[%s] Cannot prepare unallocated channel\n", __func__); | |
2088 | return ERR_PTR(-EINVAL); | |
2089 | } | |
2090 | ||
8d318a50 LW |
2091 | if (d40c->dma_cfg.pre_transfer) |
2092 | d40c->dma_cfg.pre_transfer(chan, | |
2093 | d40c->dma_cfg.pre_transfer_data, | |
2094 | sg_dma_len(sgl)); | |
2095 | ||
2a614340 | 2096 | spin_lock_irqsave(&d40c->lock, flags); |
8d318a50 | 2097 | d40d = d40_desc_get(d40c); |
2a614340 | 2098 | spin_unlock_irqrestore(&d40c->lock, flags); |
8d318a50 LW |
2099 | |
2100 | if (d40d == NULL) | |
2101 | return NULL; | |
2102 | ||
8d318a50 LW |
2103 | if (d40c->log_num != D40_PHY_CHAN) |
2104 | err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len, | |
2a614340 | 2105 | direction, dma_flags); |
8d318a50 LW |
2106 | else |
2107 | err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len, | |
2a614340 | 2108 | direction, dma_flags); |
8d318a50 LW |
2109 | if (err) { |
2110 | dev_err(&d40c->chan.dev->device, | |
2111 | "[%s] Failed to prepare %s slave sg job: %d\n", | |
2112 | __func__, | |
2113 | d40c->log_num != D40_PHY_CHAN ? "log" : "phy", err); | |
2114 | return NULL; | |
2115 | } | |
2116 | ||
2a614340 | 2117 | d40d->txd.flags = dma_flags; |
8d318a50 LW |
2118 | |
2119 | dma_async_tx_descriptor_init(&d40d->txd, chan); | |
2120 | ||
2121 | d40d->txd.tx_submit = d40_tx_submit; | |
2122 | ||
2123 | return &d40d->txd; | |
2124 | } | |
2125 | ||
2126 | static enum dma_status d40_tx_status(struct dma_chan *chan, | |
2127 | dma_cookie_t cookie, | |
2128 | struct dma_tx_state *txstate) | |
2129 | { | |
2130 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2131 | dma_cookie_t last_used; | |
2132 | dma_cookie_t last_complete; | |
2133 | int ret; | |
2134 | ||
0d0f6b8b JA |
2135 | if (d40c->phy_chan == NULL) { |
2136 | dev_err(&d40c->chan.dev->device, | |
2137 | "[%s] Cannot read status of unallocated channel\n", | |
2138 | __func__); | |
2139 | return -EINVAL; | |
2140 | } | |
2141 | ||
8d318a50 LW |
2142 | last_complete = d40c->completed; |
2143 | last_used = chan->cookie; | |
2144 | ||
a5ebca47 JA |
2145 | if (d40_is_paused(d40c)) |
2146 | ret = DMA_PAUSED; | |
2147 | else | |
2148 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
8d318a50 | 2149 | |
a5ebca47 JA |
2150 | dma_set_tx_state(txstate, last_complete, last_used, |
2151 | stedma40_residue(chan)); | |
8d318a50 LW |
2152 | |
2153 | return ret; | |
2154 | } | |
2155 | ||
2156 | static void d40_issue_pending(struct dma_chan *chan) | |
2157 | { | |
2158 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2159 | unsigned long flags; | |
2160 | ||
0d0f6b8b JA |
2161 | if (d40c->phy_chan == NULL) { |
2162 | dev_err(&d40c->chan.dev->device, | |
2163 | "[%s] Channel is not allocated!\n", __func__); | |
2164 | return; | |
2165 | } | |
2166 | ||
8d318a50 LW |
2167 | spin_lock_irqsave(&d40c->lock, flags); |
2168 | ||
2169 | /* Busy means that pending jobs are already being processed */ | |
2170 | if (!d40c->busy) | |
2171 | (void) d40_queue_start(d40c); | |
2172 | ||
2173 | spin_unlock_irqrestore(&d40c->lock, flags); | |
2174 | } | |
2175 | ||
95e1400f LW |
2176 | /* Runtime reconfiguration extension */ |
2177 | static void d40_set_runtime_config(struct dma_chan *chan, | |
2178 | struct dma_slave_config *config) | |
2179 | { | |
2180 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2181 | struct stedma40_chan_cfg *cfg = &d40c->dma_cfg; | |
2182 | enum dma_slave_buswidth config_addr_width; | |
2183 | dma_addr_t config_addr; | |
2184 | u32 config_maxburst; | |
2185 | enum stedma40_periph_data_width addr_width; | |
2186 | int psize; | |
2187 | ||
2188 | if (config->direction == DMA_FROM_DEVICE) { | |
2189 | dma_addr_t dev_addr_rx = | |
2190 | d40c->base->plat_data->dev_rx[cfg->src_dev_type]; | |
2191 | ||
2192 | config_addr = config->src_addr; | |
2193 | if (dev_addr_rx) | |
2194 | dev_dbg(d40c->base->dev, | |
2195 | "channel has a pre-wired RX address %08x " | |
2196 | "overriding with %08x\n", | |
2197 | dev_addr_rx, config_addr); | |
2198 | if (cfg->dir != STEDMA40_PERIPH_TO_MEM) | |
2199 | dev_dbg(d40c->base->dev, | |
2200 | "channel was not configured for peripheral " | |
2201 | "to memory transfer (%d) overriding\n", | |
2202 | cfg->dir); | |
2203 | cfg->dir = STEDMA40_PERIPH_TO_MEM; | |
2204 | ||
2205 | config_addr_width = config->src_addr_width; | |
2206 | config_maxburst = config->src_maxburst; | |
2207 | ||
2208 | } else if (config->direction == DMA_TO_DEVICE) { | |
2209 | dma_addr_t dev_addr_tx = | |
2210 | d40c->base->plat_data->dev_tx[cfg->dst_dev_type]; | |
2211 | ||
2212 | config_addr = config->dst_addr; | |
2213 | if (dev_addr_tx) | |
2214 | dev_dbg(d40c->base->dev, | |
2215 | "channel has a pre-wired TX address %08x " | |
2216 | "overriding with %08x\n", | |
2217 | dev_addr_tx, config_addr); | |
2218 | if (cfg->dir != STEDMA40_MEM_TO_PERIPH) | |
2219 | dev_dbg(d40c->base->dev, | |
2220 | "channel was not configured for memory " | |
2221 | "to peripheral transfer (%d) overriding\n", | |
2222 | cfg->dir); | |
2223 | cfg->dir = STEDMA40_MEM_TO_PERIPH; | |
2224 | ||
2225 | config_addr_width = config->dst_addr_width; | |
2226 | config_maxburst = config->dst_maxburst; | |
2227 | ||
2228 | } else { | |
2229 | dev_err(d40c->base->dev, | |
2230 | "unrecognized channel direction %d\n", | |
2231 | config->direction); | |
2232 | return; | |
2233 | } | |
2234 | ||
2235 | switch (config_addr_width) { | |
2236 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
2237 | addr_width = STEDMA40_BYTE_WIDTH; | |
2238 | break; | |
2239 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
2240 | addr_width = STEDMA40_HALFWORD_WIDTH; | |
2241 | break; | |
2242 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
2243 | addr_width = STEDMA40_WORD_WIDTH; | |
2244 | break; | |
2245 | case DMA_SLAVE_BUSWIDTH_8_BYTES: | |
2246 | addr_width = STEDMA40_DOUBLEWORD_WIDTH; | |
2247 | break; | |
2248 | default: | |
2249 | dev_err(d40c->base->dev, | |
2250 | "illegal peripheral address width " | |
2251 | "requested (%d)\n", | |
2252 | config->src_addr_width); | |
2253 | return; | |
2254 | } | |
2255 | ||
2256 | if (config_maxburst >= 16) | |
2257 | psize = STEDMA40_PSIZE_LOG_16; | |
2258 | else if (config_maxburst >= 8) | |
2259 | psize = STEDMA40_PSIZE_LOG_8; | |
2260 | else if (config_maxburst >= 4) | |
2261 | psize = STEDMA40_PSIZE_LOG_4; | |
2262 | else | |
2263 | psize = STEDMA40_PSIZE_LOG_1; | |
2264 | ||
2265 | /* Set up all the endpoint configs */ | |
2266 | cfg->src_info.data_width = addr_width; | |
2267 | cfg->src_info.psize = psize; | |
2268 | cfg->src_info.endianess = STEDMA40_LITTLE_ENDIAN; | |
2269 | cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL; | |
2270 | cfg->dst_info.data_width = addr_width; | |
2271 | cfg->dst_info.psize = psize; | |
2272 | cfg->dst_info.endianess = STEDMA40_LITTLE_ENDIAN; | |
2273 | cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL; | |
2274 | ||
2275 | /* These settings will take precedence later */ | |
2276 | d40c->runtime_addr = config_addr; | |
2277 | d40c->runtime_direction = config->direction; | |
2278 | dev_dbg(d40c->base->dev, | |
2279 | "configured channel %s for %s, data width %d, " | |
2280 | "maxburst %d bytes, LE, no flow control\n", | |
2281 | dma_chan_name(chan), | |
2282 | (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", | |
2283 | config_addr_width, | |
2284 | config_maxburst); | |
2285 | } | |
2286 | ||
05827630 LW |
2287 | static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
2288 | unsigned long arg) | |
8d318a50 LW |
2289 | { |
2290 | unsigned long flags; | |
2291 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2292 | ||
0d0f6b8b JA |
2293 | if (d40c->phy_chan == NULL) { |
2294 | dev_err(&d40c->chan.dev->device, | |
2295 | "[%s] Channel is not allocated!\n", __func__); | |
2296 | return -EINVAL; | |
2297 | } | |
2298 | ||
8d318a50 LW |
2299 | switch (cmd) { |
2300 | case DMA_TERMINATE_ALL: | |
2301 | spin_lock_irqsave(&d40c->lock, flags); | |
2302 | d40_term_all(d40c); | |
2303 | spin_unlock_irqrestore(&d40c->lock, flags); | |
2304 | return 0; | |
2305 | case DMA_PAUSE: | |
2306 | return d40_pause(chan); | |
2307 | case DMA_RESUME: | |
2308 | return d40_resume(chan); | |
95e1400f LW |
2309 | case DMA_SLAVE_CONFIG: |
2310 | d40_set_runtime_config(chan, | |
2311 | (struct dma_slave_config *) arg); | |
2312 | return 0; | |
2313 | default: | |
2314 | break; | |
8d318a50 LW |
2315 | } |
2316 | ||
2317 | /* Other commands are unimplemented */ | |
2318 | return -ENXIO; | |
2319 | } | |
2320 | ||
2321 | /* Initialization functions */ | |
2322 | ||
2323 | static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, | |
2324 | struct d40_chan *chans, int offset, | |
2325 | int num_chans) | |
2326 | { | |
2327 | int i = 0; | |
2328 | struct d40_chan *d40c; | |
2329 | ||
2330 | INIT_LIST_HEAD(&dma->channels); | |
2331 | ||
2332 | for (i = offset; i < offset + num_chans; i++) { | |
2333 | d40c = &chans[i]; | |
2334 | d40c->base = base; | |
2335 | d40c->chan.device = dma; | |
2336 | ||
2337 | /* Invalidate lcla element */ | |
2338 | d40c->lcla.src_id = -1; | |
2339 | d40c->lcla.dst_id = -1; | |
2340 | ||
2341 | spin_lock_init(&d40c->lock); | |
2342 | ||
2343 | d40c->log_num = D40_PHY_CHAN; | |
2344 | ||
8d318a50 LW |
2345 | INIT_LIST_HEAD(&d40c->active); |
2346 | INIT_LIST_HEAD(&d40c->queue); | |
2347 | INIT_LIST_HEAD(&d40c->client); | |
2348 | ||
8d318a50 LW |
2349 | tasklet_init(&d40c->tasklet, dma_tasklet, |
2350 | (unsigned long) d40c); | |
2351 | ||
2352 | list_add_tail(&d40c->chan.device_node, | |
2353 | &dma->channels); | |
2354 | } | |
2355 | } | |
2356 | ||
2357 | static int __init d40_dmaengine_init(struct d40_base *base, | |
2358 | int num_reserved_chans) | |
2359 | { | |
2360 | int err ; | |
2361 | ||
2362 | d40_chan_init(base, &base->dma_slave, base->log_chans, | |
2363 | 0, base->num_log_chans); | |
2364 | ||
2365 | dma_cap_zero(base->dma_slave.cap_mask); | |
2366 | dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); | |
2367 | ||
2368 | base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources; | |
2369 | base->dma_slave.device_free_chan_resources = d40_free_chan_resources; | |
2370 | base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy; | |
2371 | base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg; | |
2372 | base->dma_slave.device_tx_status = d40_tx_status; | |
2373 | base->dma_slave.device_issue_pending = d40_issue_pending; | |
2374 | base->dma_slave.device_control = d40_control; | |
2375 | base->dma_slave.dev = base->dev; | |
2376 | ||
2377 | err = dma_async_device_register(&base->dma_slave); | |
2378 | ||
2379 | if (err) { | |
2380 | dev_err(base->dev, | |
2381 | "[%s] Failed to register slave channels\n", | |
2382 | __func__); | |
2383 | goto failure1; | |
2384 | } | |
2385 | ||
2386 | d40_chan_init(base, &base->dma_memcpy, base->log_chans, | |
2387 | base->num_log_chans, base->plat_data->memcpy_len); | |
2388 | ||
2389 | dma_cap_zero(base->dma_memcpy.cap_mask); | |
2390 | dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); | |
2391 | ||
2392 | base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources; | |
2393 | base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources; | |
2394 | base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy; | |
2395 | base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg; | |
2396 | base->dma_memcpy.device_tx_status = d40_tx_status; | |
2397 | base->dma_memcpy.device_issue_pending = d40_issue_pending; | |
2398 | base->dma_memcpy.device_control = d40_control; | |
2399 | base->dma_memcpy.dev = base->dev; | |
2400 | /* | |
2401 | * This controller can only access address at even | |
2402 | * 32bit boundaries, i.e. 2^2 | |
2403 | */ | |
2404 | base->dma_memcpy.copy_align = 2; | |
2405 | ||
2406 | err = dma_async_device_register(&base->dma_memcpy); | |
2407 | ||
2408 | if (err) { | |
2409 | dev_err(base->dev, | |
2410 | "[%s] Failed to regsiter memcpy only channels\n", | |
2411 | __func__); | |
2412 | goto failure2; | |
2413 | } | |
2414 | ||
2415 | d40_chan_init(base, &base->dma_both, base->phy_chans, | |
2416 | 0, num_reserved_chans); | |
2417 | ||
2418 | dma_cap_zero(base->dma_both.cap_mask); | |
2419 | dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); | |
2420 | dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); | |
2421 | ||
2422 | base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources; | |
2423 | base->dma_both.device_free_chan_resources = d40_free_chan_resources; | |
2424 | base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy; | |
2425 | base->dma_both.device_prep_slave_sg = d40_prep_slave_sg; | |
2426 | base->dma_both.device_tx_status = d40_tx_status; | |
2427 | base->dma_both.device_issue_pending = d40_issue_pending; | |
2428 | base->dma_both.device_control = d40_control; | |
2429 | base->dma_both.dev = base->dev; | |
2430 | base->dma_both.copy_align = 2; | |
2431 | err = dma_async_device_register(&base->dma_both); | |
2432 | ||
2433 | if (err) { | |
2434 | dev_err(base->dev, | |
2435 | "[%s] Failed to register logical and physical capable channels\n", | |
2436 | __func__); | |
2437 | goto failure3; | |
2438 | } | |
2439 | return 0; | |
2440 | failure3: | |
2441 | dma_async_device_unregister(&base->dma_memcpy); | |
2442 | failure2: | |
2443 | dma_async_device_unregister(&base->dma_slave); | |
2444 | failure1: | |
2445 | return err; | |
2446 | } | |
2447 | ||
2448 | /* Initialization functions. */ | |
2449 | ||
2450 | static int __init d40_phy_res_init(struct d40_base *base) | |
2451 | { | |
2452 | int i; | |
2453 | int num_phy_chans_avail = 0; | |
2454 | u32 val[2]; | |
2455 | int odd_even_bit = -2; | |
2456 | ||
2457 | val[0] = readl(base->virtbase + D40_DREG_PRSME); | |
2458 | val[1] = readl(base->virtbase + D40_DREG_PRSMO); | |
2459 | ||
2460 | for (i = 0; i < base->num_phy_chans; i++) { | |
2461 | base->phy_res[i].num = i; | |
2462 | odd_even_bit += 2 * ((i % 2) == 0); | |
2463 | if (((val[i % 2] >> odd_even_bit) & 3) == 1) { | |
2464 | /* Mark security only channels as occupied */ | |
2465 | base->phy_res[i].allocated_src = D40_ALLOC_PHY; | |
2466 | base->phy_res[i].allocated_dst = D40_ALLOC_PHY; | |
2467 | } else { | |
2468 | base->phy_res[i].allocated_src = D40_ALLOC_FREE; | |
2469 | base->phy_res[i].allocated_dst = D40_ALLOC_FREE; | |
2470 | num_phy_chans_avail++; | |
2471 | } | |
2472 | spin_lock_init(&base->phy_res[i].lock); | |
2473 | } | |
6b7acd84 JA |
2474 | |
2475 | /* Mark disabled channels as occupied */ | |
2476 | for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { | |
2477 | base->phy_res[i].allocated_src = D40_ALLOC_PHY; | |
2478 | base->phy_res[i].allocated_dst = D40_ALLOC_PHY; | |
2479 | num_phy_chans_avail--; | |
2480 | } | |
2481 | ||
8d318a50 LW |
2482 | dev_info(base->dev, "%d of %d physical DMA channels available\n", |
2483 | num_phy_chans_avail, base->num_phy_chans); | |
2484 | ||
2485 | /* Verify settings extended vs standard */ | |
2486 | val[0] = readl(base->virtbase + D40_DREG_PRTYP); | |
2487 | ||
2488 | for (i = 0; i < base->num_phy_chans; i++) { | |
2489 | ||
2490 | if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && | |
2491 | (val[0] & 0x3) != 1) | |
2492 | dev_info(base->dev, | |
2493 | "[%s] INFO: channel %d is misconfigured (%d)\n", | |
2494 | __func__, i, val[0] & 0x3); | |
2495 | ||
2496 | val[0] = val[0] >> 2; | |
2497 | } | |
2498 | ||
2499 | return num_phy_chans_avail; | |
2500 | } | |
2501 | ||
2502 | static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) | |
2503 | { | |
2504 | static const struct d40_reg_val dma_id_regs[] = { | |
2505 | /* Peripheral Id */ | |
2506 | { .reg = D40_DREG_PERIPHID0, .val = 0x0040}, | |
2507 | { .reg = D40_DREG_PERIPHID1, .val = 0x0000}, | |
2508 | /* | |
2509 | * D40_DREG_PERIPHID2 Depends on HW revision: | |
2510 | * MOP500/HREF ED has 0x0008, | |
2511 | * ? has 0x0018, | |
2512 | * HREF V1 has 0x0028 | |
2513 | */ | |
2514 | { .reg = D40_DREG_PERIPHID3, .val = 0x0000}, | |
2515 | ||
2516 | /* PCell Id */ | |
2517 | { .reg = D40_DREG_CELLID0, .val = 0x000d}, | |
2518 | { .reg = D40_DREG_CELLID1, .val = 0x00f0}, | |
2519 | { .reg = D40_DREG_CELLID2, .val = 0x0005}, | |
2520 | { .reg = D40_DREG_CELLID3, .val = 0x00b1} | |
2521 | }; | |
2522 | struct stedma40_platform_data *plat_data; | |
2523 | struct clk *clk = NULL; | |
2524 | void __iomem *virtbase = NULL; | |
2525 | struct resource *res = NULL; | |
2526 | struct d40_base *base = NULL; | |
2527 | int num_log_chans = 0; | |
2528 | int num_phy_chans; | |
2529 | int i; | |
f4185592 | 2530 | u32 val; |
3ae0267f | 2531 | u32 rev; |
8d318a50 LW |
2532 | |
2533 | clk = clk_get(&pdev->dev, NULL); | |
2534 | ||
2535 | if (IS_ERR(clk)) { | |
2536 | dev_err(&pdev->dev, "[%s] No matching clock found\n", | |
2537 | __func__); | |
2538 | goto failure; | |
2539 | } | |
2540 | ||
2541 | clk_enable(clk); | |
2542 | ||
2543 | /* Get IO for DMAC base address */ | |
2544 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); | |
2545 | if (!res) | |
2546 | goto failure; | |
2547 | ||
2548 | if (request_mem_region(res->start, resource_size(res), | |
2549 | D40_NAME " I/O base") == NULL) | |
2550 | goto failure; | |
2551 | ||
2552 | virtbase = ioremap(res->start, resource_size(res)); | |
2553 | if (!virtbase) | |
2554 | goto failure; | |
2555 | ||
2556 | /* HW version check */ | |
2557 | for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) { | |
2558 | if (dma_id_regs[i].val != | |
2559 | readl(virtbase + dma_id_regs[i].reg)) { | |
2560 | dev_err(&pdev->dev, | |
2561 | "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n", | |
2562 | __func__, | |
2563 | dma_id_regs[i].val, | |
2564 | dma_id_regs[i].reg, | |
2565 | readl(virtbase + dma_id_regs[i].reg)); | |
2566 | goto failure; | |
2567 | } | |
2568 | } | |
2569 | ||
3ae0267f | 2570 | /* Get silicon revision and designer */ |
f4185592 | 2571 | val = readl(virtbase + D40_DREG_PERIPHID2); |
8d318a50 | 2572 | |
3ae0267f JA |
2573 | if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) != |
2574 | D40_HW_DESIGNER) { | |
8d318a50 LW |
2575 | dev_err(&pdev->dev, |
2576 | "[%s] Unknown designer! Got %x wanted %x\n", | |
3ae0267f JA |
2577 | __func__, val & D40_DREG_PERIPHID2_DESIGNER_MASK, |
2578 | D40_HW_DESIGNER); | |
8d318a50 LW |
2579 | goto failure; |
2580 | } | |
2581 | ||
3ae0267f JA |
2582 | rev = (val & D40_DREG_PERIPHID2_REV_MASK) >> |
2583 | D40_DREG_PERIPHID2_REV_POS; | |
2584 | ||
8d318a50 LW |
2585 | /* The number of physical channels on this HW */ |
2586 | num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; | |
2587 | ||
2588 | dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n", | |
3ae0267f | 2589 | rev, res->start); |
8d318a50 LW |
2590 | |
2591 | plat_data = pdev->dev.platform_data; | |
2592 | ||
2593 | /* Count the number of logical channels in use */ | |
2594 | for (i = 0; i < plat_data->dev_len; i++) | |
2595 | if (plat_data->dev_rx[i] != 0) | |
2596 | num_log_chans++; | |
2597 | ||
2598 | for (i = 0; i < plat_data->dev_len; i++) | |
2599 | if (plat_data->dev_tx[i] != 0) | |
2600 | num_log_chans++; | |
2601 | ||
2602 | base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + | |
2603 | (num_phy_chans + num_log_chans + plat_data->memcpy_len) * | |
2604 | sizeof(struct d40_chan), GFP_KERNEL); | |
2605 | ||
2606 | if (base == NULL) { | |
2607 | dev_err(&pdev->dev, "[%s] Out of memory\n", __func__); | |
2608 | goto failure; | |
2609 | } | |
2610 | ||
3ae0267f | 2611 | base->rev = rev; |
8d318a50 LW |
2612 | base->clk = clk; |
2613 | base->num_phy_chans = num_phy_chans; | |
2614 | base->num_log_chans = num_log_chans; | |
2615 | base->phy_start = res->start; | |
2616 | base->phy_size = resource_size(res); | |
2617 | base->virtbase = virtbase; | |
2618 | base->plat_data = plat_data; | |
2619 | base->dev = &pdev->dev; | |
2620 | base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); | |
2621 | base->log_chans = &base->phy_chans[num_phy_chans]; | |
2622 | ||
2623 | base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res), | |
2624 | GFP_KERNEL); | |
2625 | if (!base->phy_res) | |
2626 | goto failure; | |
2627 | ||
2628 | base->lookup_phy_chans = kzalloc(num_phy_chans * | |
2629 | sizeof(struct d40_chan *), | |
2630 | GFP_KERNEL); | |
2631 | if (!base->lookup_phy_chans) | |
2632 | goto failure; | |
2633 | ||
2634 | if (num_log_chans + plat_data->memcpy_len) { | |
2635 | /* | |
2636 | * The max number of logical channels are event lines for all | |
2637 | * src devices and dst devices | |
2638 | */ | |
2639 | base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 * | |
2640 | sizeof(struct d40_chan *), | |
2641 | GFP_KERNEL); | |
2642 | if (!base->lookup_log_chans) | |
2643 | goto failure; | |
2644 | } | |
2645 | base->lcla_pool.alloc_map = kzalloc(num_phy_chans * sizeof(u32), | |
2646 | GFP_KERNEL); | |
2647 | if (!base->lcla_pool.alloc_map) | |
2648 | goto failure; | |
2649 | ||
c675b1b4 JA |
2650 | base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), |
2651 | 0, SLAB_HWCACHE_ALIGN, | |
2652 | NULL); | |
2653 | if (base->desc_slab == NULL) | |
2654 | goto failure; | |
2655 | ||
8d318a50 LW |
2656 | return base; |
2657 | ||
2658 | failure: | |
2659 | if (clk) { | |
2660 | clk_disable(clk); | |
2661 | clk_put(clk); | |
2662 | } | |
2663 | if (virtbase) | |
2664 | iounmap(virtbase); | |
2665 | if (res) | |
2666 | release_mem_region(res->start, | |
2667 | resource_size(res)); | |
2668 | if (virtbase) | |
2669 | iounmap(virtbase); | |
2670 | ||
2671 | if (base) { | |
2672 | kfree(base->lcla_pool.alloc_map); | |
2673 | kfree(base->lookup_log_chans); | |
2674 | kfree(base->lookup_phy_chans); | |
2675 | kfree(base->phy_res); | |
2676 | kfree(base); | |
2677 | } | |
2678 | ||
2679 | return NULL; | |
2680 | } | |
2681 | ||
2682 | static void __init d40_hw_init(struct d40_base *base) | |
2683 | { | |
2684 | ||
2685 | static const struct d40_reg_val dma_init_reg[] = { | |
2686 | /* Clock every part of the DMA block from start */ | |
2687 | { .reg = D40_DREG_GCC, .val = 0x0000ff01}, | |
2688 | ||
2689 | /* Interrupts on all logical channels */ | |
2690 | { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, | |
2691 | { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, | |
2692 | { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, | |
2693 | { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, | |
2694 | { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, | |
2695 | { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, | |
2696 | { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, | |
2697 | { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, | |
2698 | { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, | |
2699 | { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, | |
2700 | { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, | |
2701 | { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} | |
2702 | }; | |
2703 | int i; | |
2704 | u32 prmseo[2] = {0, 0}; | |
2705 | u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF}; | |
2706 | u32 pcmis = 0; | |
2707 | u32 pcicr = 0; | |
2708 | ||
2709 | for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++) | |
2710 | writel(dma_init_reg[i].val, | |
2711 | base->virtbase + dma_init_reg[i].reg); | |
2712 | ||
2713 | /* Configure all our dma channels to default settings */ | |
2714 | for (i = 0; i < base->num_phy_chans; i++) { | |
2715 | ||
2716 | activeo[i % 2] = activeo[i % 2] << 2; | |
2717 | ||
2718 | if (base->phy_res[base->num_phy_chans - i - 1].allocated_src | |
2719 | == D40_ALLOC_PHY) { | |
2720 | activeo[i % 2] |= 3; | |
2721 | continue; | |
2722 | } | |
2723 | ||
2724 | /* Enable interrupt # */ | |
2725 | pcmis = (pcmis << 1) | 1; | |
2726 | ||
2727 | /* Clear interrupt # */ | |
2728 | pcicr = (pcicr << 1) | 1; | |
2729 | ||
2730 | /* Set channel to physical mode */ | |
2731 | prmseo[i % 2] = prmseo[i % 2] << 2; | |
2732 | prmseo[i % 2] |= 1; | |
2733 | ||
2734 | } | |
2735 | ||
2736 | writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); | |
2737 | writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); | |
2738 | writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); | |
2739 | writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); | |
2740 | ||
2741 | /* Write which interrupt to enable */ | |
2742 | writel(pcmis, base->virtbase + D40_DREG_PCMIS); | |
2743 | ||
2744 | /* Write which interrupt to clear */ | |
2745 | writel(pcicr, base->virtbase + D40_DREG_PCICR); | |
2746 | ||
2747 | } | |
2748 | ||
508849ad LW |
2749 | static int __init d40_lcla_allocate(struct d40_base *base) |
2750 | { | |
2751 | unsigned long *page_list; | |
2752 | int i, j; | |
2753 | int ret = 0; | |
2754 | ||
2755 | /* | |
2756 | * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned, | |
2757 | * To full fill this hardware requirement without wasting 256 kb | |
2758 | * we allocate pages until we get an aligned one. | |
2759 | */ | |
2760 | page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS, | |
2761 | GFP_KERNEL); | |
2762 | ||
2763 | if (!page_list) { | |
2764 | ret = -ENOMEM; | |
2765 | goto failure; | |
2766 | } | |
2767 | ||
2768 | /* Calculating how many pages that are required */ | |
2769 | base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; | |
2770 | ||
2771 | for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) { | |
2772 | page_list[i] = __get_free_pages(GFP_KERNEL, | |
2773 | base->lcla_pool.pages); | |
2774 | if (!page_list[i]) { | |
2775 | ||
2776 | dev_err(base->dev, | |
2777 | "[%s] Failed to allocate %d pages.\n", | |
2778 | __func__, base->lcla_pool.pages); | |
2779 | ||
2780 | for (j = 0; j < i; j++) | |
2781 | free_pages(page_list[j], base->lcla_pool.pages); | |
2782 | goto failure; | |
2783 | } | |
2784 | ||
2785 | if ((virt_to_phys((void *)page_list[i]) & | |
2786 | (LCLA_ALIGNMENT - 1)) == 0) | |
2787 | break; | |
2788 | } | |
2789 | ||
2790 | for (j = 0; j < i; j++) | |
2791 | free_pages(page_list[j], base->lcla_pool.pages); | |
2792 | ||
2793 | if (i < MAX_LCLA_ALLOC_ATTEMPTS) { | |
2794 | base->lcla_pool.base = (void *)page_list[i]; | |
2795 | } else { | |
2796 | /* After many attempts, no succees with finding the correct | |
2797 | * alignment try with allocating a big buffer */ | |
2798 | dev_warn(base->dev, | |
2799 | "[%s] Failed to get %d pages @ 18 bit align.\n", | |
2800 | __func__, base->lcla_pool.pages); | |
2801 | base->lcla_pool.base_unaligned = kmalloc(SZ_1K * | |
2802 | base->num_phy_chans + | |
2803 | LCLA_ALIGNMENT, | |
2804 | GFP_KERNEL); | |
2805 | if (!base->lcla_pool.base_unaligned) { | |
2806 | ret = -ENOMEM; | |
2807 | goto failure; | |
2808 | } | |
2809 | ||
2810 | base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, | |
2811 | LCLA_ALIGNMENT); | |
2812 | } | |
2813 | ||
2814 | writel(virt_to_phys(base->lcla_pool.base), | |
2815 | base->virtbase + D40_DREG_LCLA); | |
2816 | failure: | |
2817 | kfree(page_list); | |
2818 | return ret; | |
2819 | } | |
2820 | ||
8d318a50 LW |
2821 | static int __init d40_probe(struct platform_device *pdev) |
2822 | { | |
2823 | int err; | |
2824 | int ret = -ENOENT; | |
2825 | struct d40_base *base; | |
2826 | struct resource *res = NULL; | |
2827 | int num_reserved_chans; | |
2828 | u32 val; | |
2829 | ||
2830 | base = d40_hw_detect_init(pdev); | |
2831 | ||
2832 | if (!base) | |
2833 | goto failure; | |
2834 | ||
2835 | num_reserved_chans = d40_phy_res_init(base); | |
2836 | ||
2837 | platform_set_drvdata(pdev, base); | |
2838 | ||
2839 | spin_lock_init(&base->interrupt_lock); | |
2840 | spin_lock_init(&base->execmd_lock); | |
2841 | ||
2842 | /* Get IO for logical channel parameter address */ | |
2843 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa"); | |
2844 | if (!res) { | |
2845 | ret = -ENOENT; | |
2846 | dev_err(&pdev->dev, | |
2847 | "[%s] No \"lcpa\" memory resource\n", | |
2848 | __func__); | |
2849 | goto failure; | |
2850 | } | |
2851 | base->lcpa_size = resource_size(res); | |
2852 | base->phy_lcpa = res->start; | |
2853 | ||
2854 | if (request_mem_region(res->start, resource_size(res), | |
2855 | D40_NAME " I/O lcpa") == NULL) { | |
2856 | ret = -EBUSY; | |
2857 | dev_err(&pdev->dev, | |
2858 | "[%s] Failed to request LCPA region 0x%x-0x%x\n", | |
2859 | __func__, res->start, res->end); | |
2860 | goto failure; | |
2861 | } | |
2862 | ||
2863 | /* We make use of ESRAM memory for this. */ | |
2864 | val = readl(base->virtbase + D40_DREG_LCPA); | |
2865 | if (res->start != val && val != 0) { | |
2866 | dev_warn(&pdev->dev, | |
2867 | "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n", | |
2868 | __func__, val, res->start); | |
2869 | } else | |
2870 | writel(res->start, base->virtbase + D40_DREG_LCPA); | |
2871 | ||
2872 | base->lcpa_base = ioremap(res->start, resource_size(res)); | |
2873 | if (!base->lcpa_base) { | |
2874 | ret = -ENOMEM; | |
2875 | dev_err(&pdev->dev, | |
2876 | "[%s] Failed to ioremap LCPA region\n", | |
2877 | __func__); | |
2878 | goto failure; | |
2879 | } | |
8d318a50 | 2880 | |
508849ad LW |
2881 | ret = d40_lcla_allocate(base); |
2882 | if (ret) { | |
2883 | dev_err(&pdev->dev, "[%s] Failed to allocate LCLA area\n", | |
2884 | __func__); | |
8d318a50 LW |
2885 | goto failure; |
2886 | } | |
2887 | ||
2888 | spin_lock_init(&base->lcla_pool.lock); | |
2889 | ||
2890 | base->lcla_pool.num_blocks = base->num_phy_chans; | |
2891 | ||
2892 | base->irq = platform_get_irq(pdev, 0); | |
2893 | ||
2894 | ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); | |
2895 | ||
2896 | if (ret) { | |
2897 | dev_err(&pdev->dev, "[%s] No IRQ defined\n", __func__); | |
2898 | goto failure; | |
2899 | } | |
2900 | ||
2901 | err = d40_dmaengine_init(base, num_reserved_chans); | |
2902 | if (err) | |
2903 | goto failure; | |
2904 | ||
2905 | d40_hw_init(base); | |
2906 | ||
2907 | dev_info(base->dev, "initialized\n"); | |
2908 | return 0; | |
2909 | ||
2910 | failure: | |
2911 | if (base) { | |
c675b1b4 JA |
2912 | if (base->desc_slab) |
2913 | kmem_cache_destroy(base->desc_slab); | |
8d318a50 LW |
2914 | if (base->virtbase) |
2915 | iounmap(base->virtbase); | |
508849ad LW |
2916 | if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) |
2917 | free_pages((unsigned long)base->lcla_pool.base, | |
2918 | base->lcla_pool.pages); | |
2919 | if (base->lcla_pool.base_unaligned) | |
2920 | kfree(base->lcla_pool.base_unaligned); | |
8d318a50 LW |
2921 | if (base->phy_lcpa) |
2922 | release_mem_region(base->phy_lcpa, | |
2923 | base->lcpa_size); | |
2924 | if (base->phy_start) | |
2925 | release_mem_region(base->phy_start, | |
2926 | base->phy_size); | |
2927 | if (base->clk) { | |
2928 | clk_disable(base->clk); | |
2929 | clk_put(base->clk); | |
2930 | } | |
2931 | ||
2932 | kfree(base->lcla_pool.alloc_map); | |
2933 | kfree(base->lookup_log_chans); | |
2934 | kfree(base->lookup_phy_chans); | |
2935 | kfree(base->phy_res); | |
2936 | kfree(base); | |
2937 | } | |
2938 | ||
2939 | dev_err(&pdev->dev, "[%s] probe failed\n", __func__); | |
2940 | return ret; | |
2941 | } | |
2942 | ||
2943 | static struct platform_driver d40_driver = { | |
2944 | .driver = { | |
2945 | .owner = THIS_MODULE, | |
2946 | .name = D40_NAME, | |
2947 | }, | |
2948 | }; | |
2949 | ||
2950 | int __init stedma40_init(void) | |
2951 | { | |
2952 | return platform_driver_probe(&d40_driver, d40_probe); | |
2953 | } | |
2954 | arch_initcall(stedma40_init); |