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dma40: fix DMA API usage for LLIs
[mirror_ubuntu-bionic-kernel.git] / drivers / dma / ste_dma40.c
CommitLineData
8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
9#include <linux/kernel.h>
10#include <linux/slab.h>
11#include <linux/dmaengine.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
698e4732 15#include <linux/err.h>
8d318a50
LW		 16
17#include <plat/ste_dma40.h>
18
19#include "ste_dma40_ll.h"
20
21#define D40_NAME "dma40"
22
23#define D40_PHY_CHAN -1
24
25/* For masking out/in 2 bit channel positions */
26#define D40_CHAN_POS(chan) (2 * (chan / 2))
27#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
28
29/* Maximum iterations taken before giving up suspending a channel */
30#define D40_SUSPEND_MAX_IT 500
31
508849ad
LW		 32/* Hardware requirement on LCLA alignment */
33#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 34
35/* Max number of links per event group */
36#define D40_LCLA_LINK_PER_EVENT_GRP 128
37#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
38
508849ad
LW		 39/* Attempts before giving up to trying to get pages that are aligned */
40#define MAX_LCLA_ALLOC_ATTEMPTS 256
41
42/* Bit markings for allocation map */
8d318a50
LW		 43#define D40_ALLOC_FREE (1 << 31)
44#define D40_ALLOC_PHY (1 << 30)
45#define D40_ALLOC_LOG_FREE 0
46
8d318a50 47/* Hardware designer of the block */
3ae0267f 48#define D40_HW_DESIGNER 0x8
8d318a50
LW		 49
50/**
51 * enum 40_command - The different commands and/or statuses.
52 *
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 */
58enum d40_command {
59 D40_DMA_STOP = 0,
60 D40_DMA_RUN = 1,
61 D40_DMA_SUSPEND_REQ = 2,
62 D40_DMA_SUSPENDED = 3
63};
64
65/**
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
67 *
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
b00f938c 71 * @dma_addr: DMA address, if mapped
8d318a50
LW		 72 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
73 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
74 * one buffer to one buffer.
75 */
76struct d40_lli_pool {
77 void *base;
508849ad 78 int size;
b00f938c 79 dma_addr_t dma_addr;
8d318a50 80 /* Space for dst and src, plus an extra for padding */
508849ad 81 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 82};
83
84/**
85 * struct d40_desc - A descriptor is one DMA job.
86 *
87 * @lli_phy: LLI settings for physical channel. Both src and dst=
88 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
89 * lli_len equals one.
90 * @lli_log: Same as above but for logical channels.
91 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 92 * @lli_len: Number of llis of current descriptor.
698e4732
JA		 93 * @lli_current: Number of transfered llis.
94 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 95 * @txd: DMA engine struct. Used for among other things for communication
96 * during a transfer.
97 * @node: List entry.
8d318a50 98 * @is_in_client_list: true if the client owns this descriptor.
aa182ae2 99 * the previous one.
8d318a50
LW		 100 *
101 * This descriptor is used for both logical and physical transfers.
102 */
8d318a50
LW		 103struct d40_desc {
104 /* LLI physical */
105 struct d40_phy_lli_bidir lli_phy;
106 /* LLI logical */
107 struct d40_log_lli_bidir lli_log;
108
109 struct d40_lli_pool lli_pool;
941b77a3 110 int lli_len;
698e4732
JA		 111 int lli_current;
112 int lcla_alloc;
8d318a50
LW		 113
114 struct dma_async_tx_descriptor txd;
115 struct list_head node;
116
8d318a50
LW		 117 bool is_in_client_list;
118};
119
120/**
121 * struct d40_lcla_pool - LCLA pool settings and data.
122 *
508849ad
LW		 123 * @base: The virtual address of LCLA. 18 bit aligned.
124 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
125 * This pointer is only there for clean-up on error.
126 * @pages: The number of pages needed for all physical channels.
127 * Only used later for clean-up on error
8d318a50 128 * @lock: Lock to protect the content in this struct.
698e4732 129 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 130 */
131struct d40_lcla_pool {
132 void *base;
026cbc42 133 dma_addr_t dma_addr;
508849ad
LW		 134 void *base_unaligned;
135 int pages;
8d318a50 136 spinlock_t lock;
698e4732 137 struct d40_desc **alloc_map;
8d318a50
LW		 138};
139
140/**
141 * struct d40_phy_res - struct for handling eventlines mapped to physical
142 * channels.
143 *
144 * @lock: A lock protection this entity.
145 * @num: The physical channel number of this entity.
146 * @allocated_src: Bit mapped to show which src event line's are mapped to
147 * this physical channel. Can also be free or physically allocated.
148 * @allocated_dst: Same as for src but is dst.
149 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 150 * event line number.
8d318a50
LW		 151 */
152struct d40_phy_res {
153 spinlock_t lock;
154 int num;
155 u32 allocated_src;
156 u32 allocated_dst;
157};
158
159struct d40_base;
160
161/**
162 * struct d40_chan - Struct that describes a channel.
163 *
164 * @lock: A spinlock to protect this struct.
165 * @log_num: The logical number, if any of this channel.
166 * @completed: Starts with 1, after first interrupt it is set to dma engine's
167 * current cookie.
168 * @pending_tx: The number of pending transfers. Used between interrupt handler
169 * and tasklet.
170 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 171 * @phy_chan: Pointer to physical channel which this instance runs on. If this
172 * point is NULL, then the channel is not allocated.
8d318a50
LW		 173 * @chan: DMA engine handle.
174 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
175 * transfer and call client callback.
176 * @client: Cliented owned descriptor list.
177 * @active: Active descriptor.
178 * @queue: Queued jobs.
8d318a50 179 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 180 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
187 *
188 * This struct can either "be" a logical or a physical channel.
189 */
190struct d40_chan {
191 spinlock_t lock;
192 int log_num;
193 /* ID of the most recent completed transfer */
194 int completed;
195 int pending_tx;
196 bool busy;
197 struct d40_phy_res *phy_chan;
198 struct dma_chan chan;
199 struct tasklet_struct tasklet;
200 struct list_head client;
201 struct list_head active;
202 struct list_head queue;
8d318a50 203 struct stedma40_chan_cfg dma_cfg;
ce2ca125 204 bool configured;
8d318a50
LW		 205 struct d40_base *base;
206 /* Default register configurations */
207 u32 src_def_cfg;
208 u32 dst_def_cfg;
209 struct d40_def_lcsp log_def;
8d318a50 210 struct d40_log_lli_full *lcpa;
95e1400f
LW		 211 /* Runtime reconfiguration */
212 dma_addr_t runtime_addr;
213 enum dma_data_direction runtime_direction;
8d318a50
LW		 214};
215
216/**
217 * struct d40_base - The big global struct, one for each probe'd instance.
218 *
219 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220 * @execmd_lock: Lock for execute command usage since several channels share
221 * the same physical register.
222 * @dev: The device structure.
223 * @virtbase: The virtual base address of the DMA's register.
f4185592 224 * @rev: silicon revision detected.
8d318a50
LW		 225 * @clk: Pointer to the DMA clock structure.
226 * @phy_start: Physical memory start of the DMA registers.
227 * @phy_size: Size of the DMA register map.
228 * @irq: The IRQ number.
229 * @num_phy_chans: The number of physical channels. Read from HW. This
230 * is the number of available channels for this driver, not counting "Secure
231 * mode" allocated physical channels.
232 * @num_log_chans: The number of logical channels. Calculated from
233 * num_phy_chans.
234 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235 * @dma_slave: dma_device channels that can do only do slave transfers.
236 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
8d318a50
LW		 237 * @log_chans: Room for all possible logical channels in system.
238 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
239 * to log_chans entries.
240 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
241 * to phy_chans entries.
242 * @plat_data: Pointer to provided platform_data which is the driver
243 * configuration.
244 * @phy_res: Vector containing all physical channels.
245 * @lcla_pool: lcla pool settings and data.
246 * @lcpa_base: The virtual mapped address of LCPA.
247 * @phy_lcpa: The physical address of the LCPA.
248 * @lcpa_size: The size of the LCPA area.
c675b1b4 249 * @desc_slab: cache for descriptors.
8d318a50
LW		 250 */
251struct d40_base {
252 spinlock_t interrupt_lock;
253 spinlock_t execmd_lock;
254 struct device *dev;
255 void __iomem *virtbase;
f4185592 256 u8 rev:4;
8d318a50
LW		 257 struct clk *clk;
258 phys_addr_t phy_start;
259 resource_size_t phy_size;
260 int irq;
261 int num_phy_chans;
262 int num_log_chans;
263 struct dma_device dma_both;
264 struct dma_device dma_slave;
265 struct dma_device dma_memcpy;
266 struct d40_chan *phy_chans;
267 struct d40_chan *log_chans;
268 struct d40_chan **lookup_log_chans;
269 struct d40_chan **lookup_phy_chans;
270 struct stedma40_platform_data *plat_data;
271 /* Physical half channels */
272 struct d40_phy_res *phy_res;
273 struct d40_lcla_pool lcla_pool;
274 void *lcpa_base;
275 dma_addr_t phy_lcpa;
276 resource_size_t lcpa_size;
c675b1b4 277 struct kmem_cache *desc_slab;
8d318a50
LW		 278};
279
280/**
281 * struct d40_interrupt_lookup - lookup table for interrupt handler
282 *
283 * @src: Interrupt mask register.
284 * @clr: Interrupt clear register.
285 * @is_error: true if this is an error interrupt.
286 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
287 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
288 */
289struct d40_interrupt_lookup {
290 u32 src;
291 u32 clr;
292 bool is_error;
293 int offset;
294};
295
296/**
297 * struct d40_reg_val - simple lookup struct
298 *
299 * @reg: The register.
300 * @val: The value that belongs to the register in reg.
301 */
302struct d40_reg_val {
303 unsigned int reg;
304 unsigned int val;
305};
306
262d2915
RV		 307static struct device *chan2dev(struct d40_chan *d40c)
308{
309 return &d40c->chan.dev->device;
310}
311
724a8577
RV		 312static bool chan_is_physical(struct d40_chan *chan)
313{
314 return chan->log_num == D40_PHY_CHAN;
315}
316
317static bool chan_is_logical(struct d40_chan *chan)
318{
319 return !chan_is_physical(chan);
320}
321
8ca84687
RV		 322static void __iomem *chan_base(struct d40_chan *chan)
323{
324 return chan->base->virtbase + D40_DREG_PCBASE +
325 chan->phy_chan->num * D40_DREG_PCDELTA;
326}
327
6db5a8ba
RV		 328#define d40_err(dev, format, arg...) \
329 dev_err(dev, "[%s] " format, __func__, ## arg)
330
331#define chan_err(d40c, format, arg...) \
332 d40_err(chan2dev(d40c), format, ## arg)
333
b00f938c 334static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
8d318a50
LW		 335 int lli_len, bool is_log)
336{
337 u32 align;
338 void *base;
339
340 if (is_log)
341 align = sizeof(struct d40_log_lli);
342 else
343 align = sizeof(struct d40_phy_lli);
344
345 if (lli_len == 1) {
346 base = d40d->lli_pool.pre_alloc_lli;
347 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
348 d40d->lli_pool.base = NULL;
349 } else {
594ece4d 350 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 351
352 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
353 d40d->lli_pool.base = base;
354
355 if (d40d->lli_pool.base == NULL)
356 return -ENOMEM;
357 }
358
359 if (is_log) {
360 d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base,
361 align);
594ece4d 362 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 363
364 d40d->lli_pool.dma_addr = 0;
8d318a50
LW		 365 } else {
366 d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base,
367 align);
594ece4d 368 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 369
370 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
371 d40d->lli_phy.src,
372 d40d->lli_pool.size,
373 DMA_TO_DEVICE);
374
375 if (dma_mapping_error(d40c->base->dev,
376 d40d->lli_pool.dma_addr)) {
377 kfree(d40d->lli_pool.base);
378 d40d->lli_pool.base = NULL;
379 d40d->lli_pool.dma_addr = 0;
380 return -ENOMEM;
381 }
8d318a50
LW		 382 }
383
384 return 0;
385}
386
b00f938c 387static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 388{
b00f938c
RV		 389 if (d40d->lli_pool.dma_addr)
390 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
391 d40d->lli_pool.size, DMA_TO_DEVICE);
392
8d318a50
LW		 393 kfree(d40d->lli_pool.base);
394 d40d->lli_pool.base = NULL;
395 d40d->lli_pool.size = 0;
396 d40d->lli_log.src = NULL;
397 d40d->lli_log.dst = NULL;
398 d40d->lli_phy.src = NULL;
399 d40d->lli_phy.dst = NULL;
8d318a50
LW		 400}
401
698e4732
JA		 402static int d40_lcla_alloc_one(struct d40_chan *d40c,
403 struct d40_desc *d40d)
404{
405 unsigned long flags;
406 int i;
407 int ret = -EINVAL;
408 int p;
409
410 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
411
412 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
413
414 /*
415 * Allocate both src and dst at the same time, therefore the half
416 * start on 1 since 0 can't be used since zero is used as end marker.
417 */
418 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
419 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
420 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
421 d40d->lcla_alloc++;
422 ret = i;
423 break;
424 }
425 }
426
427 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
428
429 return ret;
430}
431
432static int d40_lcla_free_all(struct d40_chan *d40c,
433 struct d40_desc *d40d)
434{
435 unsigned long flags;
436 int i;
437 int ret = -EINVAL;
438
724a8577 439 if (chan_is_physical(d40c))
698e4732
JA		 440 return 0;
441
442 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
443
444 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
445 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
446 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
447 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
448 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
449 d40d->lcla_alloc--;
450 if (d40d->lcla_alloc == 0) {
451 ret = 0;
452 break;
453 }
454 }
455 }
456
457 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
458
459 return ret;
460
461}
462
8d318a50
LW		 463static void d40_desc_remove(struct d40_desc *d40d)
464{
465 list_del(&d40d->node);
466}
467
468static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
469{
a2c15fa4 470 struct d40_desc *desc = NULL;
8d318a50
LW		 471
472 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 473 struct d40_desc *d;
474 struct d40_desc *_d;
475
8d318a50
LW		 476 list_for_each_entry_safe(d, _d, &d40c->client, node)
477 if (async_tx_test_ack(&d->txd)) {
b00f938c 478 d40_pool_lli_free(d40c, d);
8d318a50 479 d40_desc_remove(d);
a2c15fa4
RV		 480 desc = d;
481 memset(desc, 0, sizeof(*desc));
c675b1b4 482 break;
8d318a50 483 }
8d318a50 484 }
a2c15fa4
RV		 485
486 if (!desc)
487 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
488
489 if (desc)
490 INIT_LIST_HEAD(&desc->node);
491
492 return desc;
8d318a50
LW		 493}
494
495static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
496{
698e4732 497
b00f938c 498 d40_pool_lli_free(d40c, d40d);
698e4732 499 d40_lcla_free_all(d40c, d40d);
c675b1b4 500 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 501}
502
503static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
504{
505 list_add_tail(&desc->node, &d40c->active);
506}
507
698e4732
JA		 508static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
509{
510 int curr_lcla = -EINVAL, next_lcla;
511
724a8577 512 if (chan_is_physical(d40c)) {
698e4732
JA		 513 d40_phy_lli_write(d40c->base->virtbase,
514 d40c->phy_chan->num,
515 d40d->lli_phy.dst,
516 d40d->lli_phy.src);
517 d40d->lli_current = d40d->lli_len;
518 } else {
519
520 if ((d40d->lli_len - d40d->lli_current) > 1)
521 curr_lcla = d40_lcla_alloc_one(d40c, d40d);
522
523 d40_log_lli_lcpa_write(d40c->lcpa,
524 &d40d->lli_log.dst[d40d->lli_current],
525 &d40d->lli_log.src[d40d->lli_current],
526 curr_lcla);
527
528 d40d->lli_current++;
529 for (; d40d->lli_current < d40d->lli_len; d40d->lli_current++) {
026cbc42
RV		 530 unsigned int lcla_offset = d40c->phy_chan->num * 1024 +
531 8 * curr_lcla * 2;
532 struct d40_lcla_pool *pool = &d40c->base->lcla_pool;
533 struct d40_log_lli *lcla = pool->base + lcla_offset;
698e4732
JA		 534
535 if (d40d->lli_current + 1 < d40d->lli_len)
536 next_lcla = d40_lcla_alloc_one(d40c, d40d);
537 else
538 next_lcla = -EINVAL;
539
698e4732
JA		 540 d40_log_lli_lcla_write(lcla,
541 &d40d->lli_log.dst[d40d->lli_current],
542 &d40d->lli_log.src[d40d->lli_current],
543 next_lcla);
544
026cbc42
RV		 545 dma_sync_single_range_for_device(d40c->base->dev,
546 pool->dma_addr, lcla_offset,
547 2 * sizeof(struct d40_log_lli),
548 DMA_TO_DEVICE);
698e4732
JA		 549
550 curr_lcla = next_lcla;
551
552 if (curr_lcla == -EINVAL) {
553 d40d->lli_current++;
554 break;
555 }
556
557 }
558 }
559}
560
8d318a50
LW		 561static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
562{
563 struct d40_desc *d;
564
565 if (list_empty(&d40c->active))
566 return NULL;
567
568 d = list_first_entry(&d40c->active,
569 struct d40_desc,
570 node);
571 return d;
572}
573
574static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
575{
576 list_add_tail(&desc->node, &d40c->queue);
577}
578
579static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
580{
581 struct d40_desc *d;
582
583 if (list_empty(&d40c->queue))
584 return NULL;
585
586 d = list_first_entry(&d40c->queue,
587 struct d40_desc,
588 node);
589 return d;
590}
591
d49278e3
PF		 592static int d40_psize_2_burst_size(bool is_log, int psize)
593{
594 if (is_log) {
595 if (psize == STEDMA40_PSIZE_LOG_1)
596 return 1;
597 } else {
598 if (psize == STEDMA40_PSIZE_PHY_1)
599 return 1;
600 }
601
602 return 2 << psize;
603}
604
605/*
606 * The dma only supports transmitting packages up to
607 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
608 * dma elements required to send the entire sg list
609 */
610static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
611{
612 int dmalen;
613 u32 max_w = max(data_width1, data_width2);
614 u32 min_w = min(data_width1, data_width2);
615 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
616
617 if (seg_max > STEDMA40_MAX_SEG_SIZE)
618 seg_max -= (1 << max_w);
619
620 if (!IS_ALIGNED(size, 1 << max_w))
621 return -EINVAL;
622
623 if (size <= seg_max)
624 dmalen = 1;
625 else {
626 dmalen = size / seg_max;
627 if (dmalen * seg_max < size)
628 dmalen++;
629 }
630 return dmalen;
631}
632
633static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
634 u32 data_width1, u32 data_width2)
635{
636 struct scatterlist *sg;
637 int i;
638 int len = 0;
639 int ret;
640
641 for_each_sg(sgl, sg, sg_len, i) {
642 ret = d40_size_2_dmalen(sg_dma_len(sg),
643 data_width1, data_width2);
644 if (ret < 0)
645 return ret;
646 len += ret;
647 }
648 return len;
649}
8d318a50 650
d49278e3 651/* Support functions for logical channels */
8d318a50
LW		 652
653static int d40_channel_execute_command(struct d40_chan *d40c,
654 enum d40_command command)
655{
767a9675
JA		 656 u32 status;
657 int i;
8d318a50
LW		 658 void __iomem *active_reg;
659 int ret = 0;
660 unsigned long flags;
1d392a7b 661 u32 wmask;
8d318a50
LW		 662
663 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
664
665 if (d40c->phy_chan->num % 2 == 0)
666 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
667 else
668 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
669
670 if (command == D40_DMA_SUSPEND_REQ) {
671 status = (readl(active_reg) &
672 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
673 D40_CHAN_POS(d40c->phy_chan->num);
674
675 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
676 goto done;
677 }
678
1d392a7b
JA		 679 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
680 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
681 active_reg);
8d318a50
LW		 682
683 if (command == D40_DMA_SUSPEND_REQ) {
684
685 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
686 status = (readl(active_reg) &
687 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
688 D40_CHAN_POS(d40c->phy_chan->num);
689
690 cpu_relax();
691 /*
692 * Reduce the number of bus accesses while
693 * waiting for the DMA to suspend.
694 */
695 udelay(3);
696
697 if (status == D40_DMA_STOP ||
698 status == D40_DMA_SUSPENDED)
699 break;
700 }
701
702 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 703 chan_err(d40c,
704 "unable to suspend the chl %d (log: %d) status %x\n",
705 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 706 status);
707 dump_stack();
708 ret = -EBUSY;
709 }
710
711 }
712done:
713 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
714 return ret;
715}
716
717static void d40_term_all(struct d40_chan *d40c)
718{
719 struct d40_desc *d40d;
8d318a50
LW		 720
721 /* Release active descriptors */
722 while ((d40d = d40_first_active_get(d40c))) {
723 d40_desc_remove(d40d);
8d318a50
LW		 724 d40_desc_free(d40c, d40d);
725 }
726
727 /* Release queued descriptors waiting for transfer */
728 while ((d40d = d40_first_queued(d40c))) {
729 d40_desc_remove(d40d);
8d318a50
LW		 730 d40_desc_free(d40c, d40d);
731 }
732
8d318a50
LW		 733
734 d40c->pending_tx = 0;
735 d40c->busy = false;
736}
737
262d2915
RV		 738static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
739 u32 event, int reg)
740{
8ca84687 741 void __iomem *addr = chan_base(d40c) + reg;
262d2915
RV		 742 int tries;
743
744 if (!enable) {
745 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
746 | ~D40_EVENTLINE_MASK(event), addr);
747 return;
748 }
749
750 /*
751 * The hardware sometimes doesn't register the enable when src and dst
752 * event lines are active on the same logical channel. Retry to ensure
753 * it does. Usually only one retry is sufficient.
754 */
755 tries = 100;
756 while (--tries) {
757 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
758 | ~D40_EVENTLINE_MASK(event), addr);
759
760 if (readl(addr) & D40_EVENTLINE_MASK(event))
761 break;
762 }
763
764 if (tries != 99)
765 dev_dbg(chan2dev(d40c),
766 "[%s] workaround enable S%cLNK (%d tries)\n",
767 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
768 100 - tries);
769
770 WARN_ON(!tries);
771}
772
8d318a50
LW		 773static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
774{
8d318a50
LW		 775 unsigned long flags;
776
8d318a50
LW		 777 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
778
779 /* Enable event line connected to device (or memcpy) */
780 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
781 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
782 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
783
262d2915
RV		 784 __d40_config_set_event(d40c, do_enable, event,
785 D40_CHAN_REG_SSLNK);
8d318a50 786 }
262d2915 787
8d318a50
LW		 788 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
789 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
790
262d2915
RV		 791 __d40_config_set_event(d40c, do_enable, event,
792 D40_CHAN_REG_SDLNK);
8d318a50
LW		 793 }
794
795 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
796}
797
a5ebca47 798static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 799{
8ca84687 800 void __iomem *chanbase = chan_base(d40c);
be8cb7df 801 u32 val;
8d318a50 802
8ca84687
RV		 803 val = readl(chanbase + D40_CHAN_REG_SSLNK);
804 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 805
a5ebca47 806 return val;
8d318a50
LW		 807}
808
20a5b6d0
RV		 809static u32 d40_get_prmo(struct d40_chan *d40c)
810{
811 static const unsigned int phy_map[] = {
812 [STEDMA40_PCHAN_BASIC_MODE]
813 = D40_DREG_PRMO_PCHAN_BASIC,
814 [STEDMA40_PCHAN_MODULO_MODE]
815 = D40_DREG_PRMO_PCHAN_MODULO,
816 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
817 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
818 };
819 static const unsigned int log_map[] = {
820 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
821 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
822 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
823 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
824 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
825 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
826 };
827
724a8577 828 if (chan_is_physical(d40c))
20a5b6d0
RV		 829 return phy_map[d40c->dma_cfg.mode_opt];
830 else
831 return log_map[d40c->dma_cfg.mode_opt];
832}
833
b55912c6 834static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 835{
836 u32 addr_base;
837 u32 var;
8d318a50
LW		 838
839 /* Odd addresses are even addresses + 4 */
840 addr_base = (d40c->phy_chan->num % 2) * 4;
841 /* Setup channel mode to logical or physical */
724a8577 842 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 843 D40_CHAN_POS(d40c->phy_chan->num);
844 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
845
846 /* Setup operational mode option register */
20a5b6d0 847 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 848
849 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
850
724a8577 851 if (chan_is_logical(d40c)) {
8ca84687
RV		 852 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
853 & D40_SREG_ELEM_LOG_LIDX_MASK;
854 void __iomem *chanbase = chan_base(d40c);
855
8d318a50 856 /* Set default config for CFG reg */
8ca84687
RV		 857 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
858 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 859
b55912c6 860 /* Set LIDX for lcla */
8ca84687
RV		 861 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
862 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
8d318a50 863 }
8d318a50
LW		 864}
865
aa182ae2
JA		 866static u32 d40_residue(struct d40_chan *d40c)
867{
868 u32 num_elt;
869
724a8577 870 if (chan_is_logical(d40c))
aa182ae2
JA		 871 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
872 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 873 else {
874 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
875 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
876 >> D40_SREG_ELEM_PHY_ECNT_POS;
877 }
878
aa182ae2
JA		 879 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
880}
881
882static bool d40_tx_is_linked(struct d40_chan *d40c)
883{
884 bool is_link;
885
724a8577 886 if (chan_is_logical(d40c))
aa182ae2
JA		 887 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
888 else
8ca84687
RV		 889 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
890 & D40_SREG_LNK_PHYS_LNK_MASK;
891
aa182ae2
JA		 892 return is_link;
893}
894
895static int d40_pause(struct dma_chan *chan)
896{
897 struct d40_chan *d40c =
898 container_of(chan, struct d40_chan, chan);
899 int res = 0;
900 unsigned long flags;
901
3ac012af
JA		 902 if (!d40c->busy)
903 return 0;
904
aa182ae2
JA		 905 spin_lock_irqsave(&d40c->lock, flags);
906
907 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
908 if (res == 0) {
724a8577 909 if (chan_is_logical(d40c)) {
aa182ae2
JA		 910 d40_config_set_event(d40c, false);
911 /* Resume the other logical channels if any */
912 if (d40_chan_has_events(d40c))
913 res = d40_channel_execute_command(d40c,
914 D40_DMA_RUN);
915 }
916 }
917
918 spin_unlock_irqrestore(&d40c->lock, flags);
919 return res;
920}
921
922static int d40_resume(struct dma_chan *chan)
923{
924 struct d40_chan *d40c =
925 container_of(chan, struct d40_chan, chan);
926 int res = 0;
927 unsigned long flags;
928
3ac012af
JA		 929 if (!d40c->busy)
930 return 0;
931
aa182ae2
JA		 932 spin_lock_irqsave(&d40c->lock, flags);
933
934 if (d40c->base->rev == 0)
724a8577 935 if (chan_is_logical(d40c)) {
aa182ae2
JA		 936 res = d40_channel_execute_command(d40c,
937 D40_DMA_SUSPEND_REQ);
938 goto no_suspend;
939 }
940
941 /* If bytes left to transfer or linked tx resume job */
942 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
943
724a8577 944 if (chan_is_logical(d40c))
aa182ae2
JA		 945 d40_config_set_event(d40c, true);
946
947 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
948 }
949
950no_suspend:
951 spin_unlock_irqrestore(&d40c->lock, flags);
952 return res;
953}
954
8d318a50
LW		 955static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
956{
957 struct d40_chan *d40c = container_of(tx->chan,
958 struct d40_chan,
959 chan);
960 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
961 unsigned long flags;
962
963 spin_lock_irqsave(&d40c->lock, flags);
964
aa182ae2
JA		 965 d40c->chan.cookie++;
966
967 if (d40c->chan.cookie < 0)
968 d40c->chan.cookie = 1;
969
970 d40d->txd.cookie = d40c->chan.cookie;
971
8d318a50
LW		 972 d40_desc_queue(d40c, d40d);
973
974 spin_unlock_irqrestore(&d40c->lock, flags);
975
976 return tx->cookie;
977}
978
979static int d40_start(struct d40_chan *d40c)
980{
f4185592
LW		 981 if (d40c->base->rev == 0) {
982 int err;
983
724a8577 984 if (chan_is_logical(d40c)) {
f4185592
LW		 985 err = d40_channel_execute_command(d40c,
986 D40_DMA_SUSPEND_REQ);
987 if (err)
988 return err;
989 }
990 }
991
724a8577 992 if (chan_is_logical(d40c))
8d318a50 993 d40_config_set_event(d40c, true);
8d318a50 994
0c32269d 995 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 996}
997
998static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
999{
1000 struct d40_desc *d40d;
1001 int err;
1002
1003 /* Start queued jobs, if any */
1004 d40d = d40_first_queued(d40c);
1005
1006 if (d40d != NULL) {
1007 d40c->busy = true;
1008
1009 /* Remove from queue */
1010 d40_desc_remove(d40d);
1011
1012 /* Add to active queue */
1013 d40_desc_submit(d40c, d40d);
1014
7d83a854
RV		 1015 /* Initiate DMA job */
1016 d40_desc_load(d40c, d40d);
8d318a50 1017
7d83a854
RV		 1018 /* Start dma job */
1019 err = d40_start(d40c);
8d318a50 1020
7d83a854
RV		 1021 if (err)
1022 return NULL;
8d318a50
LW		 1023 }
1024
1025 return d40d;
1026}
1027
1028/* called from interrupt context */
1029static void dma_tc_handle(struct d40_chan *d40c)
1030{
1031 struct d40_desc *d40d;
1032
8d318a50
LW		 1033 /* Get first active entry from list */
1034 d40d = d40_first_active_get(d40c);
1035
1036 if (d40d == NULL)
1037 return;
1038
698e4732 1039 d40_lcla_free_all(d40c, d40d);
8d318a50 1040
698e4732 1041 if (d40d->lli_current < d40d->lli_len) {
8d318a50
LW		 1042 d40_desc_load(d40c, d40d);
1043 /* Start dma job */
1044 (void) d40_start(d40c);
1045 return;
1046 }
1047
1048 if (d40_queue_start(d40c) == NULL)
1049 d40c->busy = false;
1050
1051 d40c->pending_tx++;
1052 tasklet_schedule(&d40c->tasklet);
1053
1054}
1055
1056static void dma_tasklet(unsigned long data)
1057{
1058 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1059 struct d40_desc *d40d;
8d318a50
LW		 1060 unsigned long flags;
1061 dma_async_tx_callback callback;
1062 void *callback_param;
1063
1064 spin_lock_irqsave(&d40c->lock, flags);
1065
1066 /* Get first active entry from list */
767a9675 1067 d40d = d40_first_active_get(d40c);
8d318a50 1068
767a9675 1069 if (d40d == NULL)
8d318a50
LW		 1070 goto err;
1071
767a9675 1072 d40c->completed = d40d->txd.cookie;
8d318a50
LW		 1073
1074 /*
1075 * If terminating a channel pending_tx is set to zero.
1076 * This prevents any finished active jobs to return to the client.
1077 */
1078 if (d40c->pending_tx == 0) {
1079 spin_unlock_irqrestore(&d40c->lock, flags);
1080 return;
1081 }
1082
1083 /* Callback to client */
767a9675
JA		 1084 callback = d40d->txd.callback;
1085 callback_param = d40d->txd.callback_param;
1086
1087 if (async_tx_test_ack(&d40d->txd)) {
b00f938c 1088 d40_pool_lli_free(d40c, d40d);
767a9675
JA		 1089 d40_desc_remove(d40d);
1090 d40_desc_free(d40c, d40d);
8d318a50 1091 } else {
767a9675
JA		 1092 if (!d40d->is_in_client_list) {
1093 d40_desc_remove(d40d);
698e4732 1094 d40_lcla_free_all(d40c, d40d);
767a9675
JA		 1095 list_add_tail(&d40d->node, &d40c->client);
1096 d40d->is_in_client_list = true;
8d318a50
LW		 1097 }
1098 }
1099
1100 d40c->pending_tx--;
1101
1102 if (d40c->pending_tx)
1103 tasklet_schedule(&d40c->tasklet);
1104
1105 spin_unlock_irqrestore(&d40c->lock, flags);
1106
767a9675 1107 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
8d318a50
LW		 1108 callback(callback_param);
1109
1110 return;
1111
1112 err:
1113 /* Rescue manouver if receiving double interrupts */
1114 if (d40c->pending_tx > 0)
1115 d40c->pending_tx--;
1116 spin_unlock_irqrestore(&d40c->lock, flags);
1117}
1118
1119static irqreturn_t d40_handle_interrupt(int irq, void *data)
1120{
1121 static const struct d40_interrupt_lookup il[] = {
1122 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1123 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1124 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1125 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1126 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1127 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1128 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1129 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1130 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1131 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1132 };
1133
1134 int i;
1135 u32 regs[ARRAY_SIZE(il)];
8d318a50
LW		 1136 u32 idx;
1137 u32 row;
1138 long chan = -1;
1139 struct d40_chan *d40c;
1140 unsigned long flags;
1141 struct d40_base *base = data;
1142
1143 spin_lock_irqsave(&base->interrupt_lock, flags);
1144
1145 /* Read interrupt status of both logical and physical channels */
1146 for (i = 0; i < ARRAY_SIZE(il); i++)
1147 regs[i] = readl(base->virtbase + il[i].src);
1148
1149 for (;;) {
1150
1151 chan = find_next_bit((unsigned long *)regs,
1152 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1153
1154 /* No more set bits found? */
1155 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1156 break;
1157
1158 row = chan / BITS_PER_LONG;
1159 idx = chan & (BITS_PER_LONG - 1);
1160
1161 /* ACK interrupt */
1b00348d 1162 writel(1 << idx, base->virtbase + il[row].clr);
8d318a50
LW		 1163
1164 if (il[row].offset == D40_PHY_CHAN)
1165 d40c = base->lookup_phy_chans[idx];
1166 else
1167 d40c = base->lookup_log_chans[il[row].offset + idx];
1168 spin_lock(&d40c->lock);
1169
1170 if (!il[row].is_error)
1171 dma_tc_handle(d40c);
1172 else
6db5a8ba
RV		 1173 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1174 chan, il[row].offset, idx);
8d318a50
LW		 1175
1176 spin_unlock(&d40c->lock);
1177 }
1178
1179 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1180
1181 return IRQ_HANDLED;
1182}
1183
8d318a50
LW		 1184static int d40_validate_conf(struct d40_chan *d40c,
1185 struct stedma40_chan_cfg *conf)
1186{
1187 int res = 0;
1188 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1189 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
38bdbf02 1190 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1191
0747c7ba 1192 if (!conf->dir) {
6db5a8ba 1193 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1194 res = -EINVAL;
1195 }
1196
1197 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1198 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1199 d40c->runtime_addr == 0) {
1200
6db5a8ba
RV		 1201 chan_err(d40c, "Invalid TX channel address (%d)\n",
1202 conf->dst_dev_type);
0747c7ba
LW		 1203 res = -EINVAL;
1204 }
1205
1206 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1207 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1208 d40c->runtime_addr == 0) {
6db5a8ba
RV		 1209 chan_err(d40c, "Invalid RX channel address (%d)\n",
1210 conf->src_dev_type);
0747c7ba
LW		 1211 res = -EINVAL;
1212 }
1213
1214 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
8d318a50 1215 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
6db5a8ba 1216 chan_err(d40c, "Invalid dst\n");
8d318a50
LW		 1217 res = -EINVAL;
1218 }
1219
0747c7ba 1220 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
8d318a50 1221 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
6db5a8ba 1222 chan_err(d40c, "Invalid src\n");
8d318a50
LW		 1223 res = -EINVAL;
1224 }
1225
1226 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1227 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
6db5a8ba 1228 chan_err(d40c, "No event line\n");
8d318a50
LW		 1229 res = -EINVAL;
1230 }
1231
1232 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1233 (src_event_group != dst_event_group)) {
6db5a8ba 1234 chan_err(d40c, "Invalid event group\n");
8d318a50
LW		 1235 res = -EINVAL;
1236 }
1237
1238 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1239 /*
1240 * DMAC HW supports it. Will be added to this driver,
1241 * in case any dma client requires it.
1242 */
6db5a8ba 1243 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1244 res = -EINVAL;
1245 }
1246
d49278e3
PF		 1247 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1248 (1 << conf->src_info.data_width) !=
1249 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1250 (1 << conf->dst_info.data_width)) {
1251 /*
1252 * The DMAC hardware only supports
1253 * src (burst x width) == dst (burst x width)
1254 */
1255
6db5a8ba 1256 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1257 res = -EINVAL;
1258 }
1259
8d318a50
LW		 1260 return res;
1261}
1262
1263static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
4aed79b2 1264 int log_event_line, bool is_log)
8d318a50
LW		 1265{
1266 unsigned long flags;
1267 spin_lock_irqsave(&phy->lock, flags);
4aed79b2 1268 if (!is_log) {
8d318a50
LW		 1269 /* Physical interrupts are masked per physical full channel */
1270 if (phy->allocated_src == D40_ALLOC_FREE &&
1271 phy->allocated_dst == D40_ALLOC_FREE) {
1272 phy->allocated_dst = D40_ALLOC_PHY;
1273 phy->allocated_src = D40_ALLOC_PHY;
1274 goto found;
1275 } else
1276 goto not_found;
1277 }
1278
1279 /* Logical channel */
1280 if (is_src) {
1281 if (phy->allocated_src == D40_ALLOC_PHY)
1282 goto not_found;
1283
1284 if (phy->allocated_src == D40_ALLOC_FREE)
1285 phy->allocated_src = D40_ALLOC_LOG_FREE;
1286
1287 if (!(phy->allocated_src & (1 << log_event_line))) {
1288 phy->allocated_src |= 1 << log_event_line;
1289 goto found;
1290 } else
1291 goto not_found;
1292 } else {
1293 if (phy->allocated_dst == D40_ALLOC_PHY)
1294 goto not_found;
1295
1296 if (phy->allocated_dst == D40_ALLOC_FREE)
1297 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1298
1299 if (!(phy->allocated_dst & (1 << log_event_line))) {
1300 phy->allocated_dst |= 1 << log_event_line;
1301 goto found;
1302 } else
1303 goto not_found;
1304 }
1305
1306not_found:
1307 spin_unlock_irqrestore(&phy->lock, flags);
1308 return false;
1309found:
1310 spin_unlock_irqrestore(&phy->lock, flags);
1311 return true;
1312}
1313
1314static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1315 int log_event_line)
1316{
1317 unsigned long flags;
1318 bool is_free = false;
1319
1320 spin_lock_irqsave(&phy->lock, flags);
1321 if (!log_event_line) {
8d318a50
LW		 1322 phy->allocated_dst = D40_ALLOC_FREE;
1323 phy->allocated_src = D40_ALLOC_FREE;
1324 is_free = true;
1325 goto out;
1326 }
1327
1328 /* Logical channel */
1329 if (is_src) {
1330 phy->allocated_src &= ~(1 << log_event_line);
1331 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1332 phy->allocated_src = D40_ALLOC_FREE;
1333 } else {
1334 phy->allocated_dst &= ~(1 << log_event_line);
1335 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1336 phy->allocated_dst = D40_ALLOC_FREE;
1337 }
1338
1339 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1340 D40_ALLOC_FREE);
1341
1342out:
1343 spin_unlock_irqrestore(&phy->lock, flags);
1344
1345 return is_free;
1346}
1347
1348static int d40_allocate_channel(struct d40_chan *d40c)
1349{
1350 int dev_type;
1351 int event_group;
1352 int event_line;
1353 struct d40_phy_res *phys;
1354 int i;
1355 int j;
1356 int log_num;
1357 bool is_src;
38bdbf02 1358 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1359
1360 phys = d40c->base->phy_res;
1361
1362 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1363 dev_type = d40c->dma_cfg.src_dev_type;
1364 log_num = 2 * dev_type;
1365 is_src = true;
1366 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1367 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1368 /* dst event lines are used for logical memcpy */
1369 dev_type = d40c->dma_cfg.dst_dev_type;
1370 log_num = 2 * dev_type + 1;
1371 is_src = false;
1372 } else
1373 return -EINVAL;
1374
1375 event_group = D40_TYPE_TO_GROUP(dev_type);
1376 event_line = D40_TYPE_TO_EVENT(dev_type);
1377
1378 if (!is_log) {
1379 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1380 /* Find physical half channel */
1381 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1382
4aed79b2
MM		 1383 if (d40_alloc_mask_set(&phys[i], is_src,
1384 0, is_log))
8d318a50
LW		 1385 goto found_phy;
1386 }
1387 } else
1388 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1389 int phy_num = j + event_group * 2;
1390 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1391 if (d40_alloc_mask_set(&phys[i],
1392 is_src,
1393 0,
1394 is_log))
8d318a50
LW		 1395 goto found_phy;
1396 }
1397 }
1398 return -EINVAL;
1399found_phy:
1400 d40c->phy_chan = &phys[i];
1401 d40c->log_num = D40_PHY_CHAN;
1402 goto out;
1403 }
1404 if (dev_type == -1)
1405 return -EINVAL;
1406
1407 /* Find logical channel */
1408 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1409 int phy_num = j + event_group * 2;
1410 /*
1411 * Spread logical channels across all available physical rather
1412 * than pack every logical channel at the first available phy
1413 * channels.
1414 */
1415 if (is_src) {
1416 for (i = phy_num; i < phy_num + 2; i++) {
1417 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1418 event_line, is_log))
8d318a50
LW		 1419 goto found_log;
1420 }
1421 } else {
1422 for (i = phy_num + 1; i >= phy_num; i--) {
1423 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1424 event_line, is_log))
8d318a50
LW		 1425 goto found_log;
1426 }
1427 }
1428 }
1429 return -EINVAL;
1430
1431found_log:
1432 d40c->phy_chan = &phys[i];
1433 d40c->log_num = log_num;
1434out:
1435
1436 if (is_log)
1437 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1438 else
1439 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1440
1441 return 0;
1442
1443}
1444
8d318a50
LW		 1445static int d40_config_memcpy(struct d40_chan *d40c)
1446{
1447 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1448
1449 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1450 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1451 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1452 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1453 memcpy[d40c->chan.chan_id];
1454
1455 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1456 dma_has_cap(DMA_SLAVE, cap)) {
1457 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1458 } else {
6db5a8ba 1459 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 1460 return -EINVAL;
1461 }
1462
1463 return 0;
1464}
1465
1466
1467static int d40_free_dma(struct d40_chan *d40c)
1468{
1469
1470 int res = 0;
d181b3a8 1471 u32 event;
8d318a50
LW		 1472 struct d40_phy_res *phy = d40c->phy_chan;
1473 bool is_src;
a8be8627
PF		 1474 struct d40_desc *d;
1475 struct d40_desc *_d;
1476
8d318a50
LW		 1477
1478 /* Terminate all queued and active transfers */
1479 d40_term_all(d40c);
1480
a8be8627
PF		 1481 /* Release client owned descriptors */
1482 if (!list_empty(&d40c->client))
1483 list_for_each_entry_safe(d, _d, &d40c->client, node) {
b00f938c 1484 d40_pool_lli_free(d40c, d);
a8be8627 1485 d40_desc_remove(d);
a8be8627
PF		 1486 d40_desc_free(d40c, d);
1487 }
1488
8d318a50 1489 if (phy == NULL) {
6db5a8ba 1490 chan_err(d40c, "phy == null\n");
8d318a50
LW		 1491 return -EINVAL;
1492 }
1493
1494 if (phy->allocated_src == D40_ALLOC_FREE &&
1495 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 1496 chan_err(d40c, "channel already free\n");
8d318a50
LW		 1497 return -EINVAL;
1498 }
1499
8d318a50
LW		 1500 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1501 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1502 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8d318a50
LW		 1503 is_src = false;
1504 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1505 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8d318a50
LW		 1506 is_src = true;
1507 } else {
6db5a8ba 1508 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 1509 return -EINVAL;
1510 }
1511
d181b3a8
JA		 1512 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1513 if (res) {
6db5a8ba 1514 chan_err(d40c, "suspend failed\n");
d181b3a8
JA		 1515 return res;
1516 }
1517
724a8577 1518 if (chan_is_logical(d40c)) {
d181b3a8 1519 /* Release logical channel, deactivate the event line */
8d318a50 1520
d181b3a8 1521 d40_config_set_event(d40c, false);
8d318a50
LW		 1522 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1523
1524 /*
1525 * Check if there are more logical allocation
1526 * on this phy channel.
1527 */
1528 if (!d40_alloc_mask_free(phy, is_src, event)) {
1529 /* Resume the other logical channels if any */
1530 if (d40_chan_has_events(d40c)) {
1531 res = d40_channel_execute_command(d40c,
1532 D40_DMA_RUN);
1533 if (res) {
6db5a8ba
RV		 1534 chan_err(d40c,
1535 "Executing RUN command\n");
8d318a50
LW		 1536 return res;
1537 }
1538 }
1539 return 0;
1540 }
d181b3a8
JA		 1541 } else {
1542 (void) d40_alloc_mask_free(phy, is_src, 0);
1543 }
8d318a50
LW		 1544
1545 /* Release physical channel */
1546 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1547 if (res) {
6db5a8ba 1548 chan_err(d40c, "Failed to stop channel\n");
8d318a50
LW		 1549 return res;
1550 }
1551 d40c->phy_chan = NULL;
ce2ca125 1552 d40c->configured = false;
8d318a50
LW		 1553 d40c->base->lookup_phy_chans[phy->num] = NULL;
1554
1555 return 0;
8d318a50
LW		 1556}
1557
a5ebca47
JA		 1558static bool d40_is_paused(struct d40_chan *d40c)
1559{
8ca84687 1560 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 1561 bool is_paused = false;
1562 unsigned long flags;
1563 void __iomem *active_reg;
1564 u32 status;
1565 u32 event;
a5ebca47
JA		 1566
1567 spin_lock_irqsave(&d40c->lock, flags);
1568
724a8577 1569 if (chan_is_physical(d40c)) {
a5ebca47
JA		 1570 if (d40c->phy_chan->num % 2 == 0)
1571 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1572 else
1573 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1574
1575 status = (readl(active_reg) &
1576 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1577 D40_CHAN_POS(d40c->phy_chan->num);
1578 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1579 is_paused = true;
1580
1581 goto _exit;
1582 }
1583
a5ebca47 1584 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
9dbfbd35 1585 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
a5ebca47 1586 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8ca84687 1587 status = readl(chanbase + D40_CHAN_REG_SDLNK);
9dbfbd35 1588 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
a5ebca47 1589 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8ca84687 1590 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 1591 } else {
6db5a8ba 1592 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 1593 goto _exit;
1594 }
9dbfbd35 1595
a5ebca47
JA		 1596 status = (status & D40_EVENTLINE_MASK(event)) >>
1597 D40_EVENTLINE_POS(event);
1598
1599 if (status != D40_DMA_RUN)
1600 is_paused = true;
a5ebca47
JA		 1601_exit:
1602 spin_unlock_irqrestore(&d40c->lock, flags);
1603 return is_paused;
1604
1605}
1606
1607
8d318a50
LW		 1608static u32 stedma40_residue(struct dma_chan *chan)
1609{
1610 struct d40_chan *d40c =
1611 container_of(chan, struct d40_chan, chan);
1612 u32 bytes_left;
1613 unsigned long flags;
1614
1615 spin_lock_irqsave(&d40c->lock, flags);
1616 bytes_left = d40_residue(d40c);
1617 spin_unlock_irqrestore(&d40c->lock, flags);
1618
1619 return bytes_left;
1620}
1621
8d318a50
LW		 1622struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
1623 struct scatterlist *sgl_dst,
1624 struct scatterlist *sgl_src,
1625 unsigned int sgl_len,
2a614340 1626 unsigned long dma_flags)
8d318a50
LW		 1627{
1628 int res;
1629 struct d40_desc *d40d;
1630 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1631 chan);
2a614340 1632 unsigned long flags;
8d318a50 1633
0d0f6b8b 1634 if (d40c->phy_chan == NULL) {
6db5a8ba 1635 chan_err(d40c, "Unallocated channel.\n");
0d0f6b8b
JA		 1636 return ERR_PTR(-EINVAL);
1637 }
1638
2a614340 1639 spin_lock_irqsave(&d40c->lock, flags);
8d318a50
LW		 1640 d40d = d40_desc_get(d40c);
1641
1642 if (d40d == NULL)
1643 goto err;
1644
d49278e3
PF		 1645 d40d->lli_len = d40_sg_2_dmalen(sgl_dst, sgl_len,
1646 d40c->dma_cfg.src_info.data_width,
1647 d40c->dma_cfg.dst_info.data_width);
1648 if (d40d->lli_len < 0) {
6db5a8ba 1649 chan_err(d40c, "Unaligned size\n");
d49278e3
PF		 1650 goto err;
1651 }
1652
698e4732 1653 d40d->lli_current = 0;
2a614340 1654 d40d->txd.flags = dma_flags;
8d318a50 1655
724a8577 1656 if (chan_is_logical(d40c)) {
8d318a50 1657
b00f938c 1658 if (d40_pool_lli_alloc(d40c, d40d, d40d->lli_len, true) < 0) {
6db5a8ba 1659 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 1660 goto err;
1661 }
1662
698e4732 1663 (void) d40_log_sg_to_lli(sgl_src,
8d318a50
LW		 1664 sgl_len,
1665 d40d->lli_log.src,
1666 d40c->log_def.lcsp1,
d49278e3
PF		 1667 d40c->dma_cfg.src_info.data_width,
1668 d40c->dma_cfg.dst_info.data_width);
8d318a50 1669
698e4732 1670 (void) d40_log_sg_to_lli(sgl_dst,
8d318a50
LW		 1671 sgl_len,
1672 d40d->lli_log.dst,
1673 d40c->log_def.lcsp3,
d49278e3
PF		 1674 d40c->dma_cfg.dst_info.data_width,
1675 d40c->dma_cfg.src_info.data_width);
8d318a50 1676 } else {
b00f938c 1677 if (d40_pool_lli_alloc(d40c, d40d, d40d->lli_len, false) < 0) {
6db5a8ba 1678 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 1679 goto err;
1680 }
1681
1682 res = d40_phy_sg_to_lli(sgl_src,
1683 sgl_len,
1684 0,
1685 d40d->lli_phy.src,
aa182ae2 1686 virt_to_phys(d40d->lli_phy.src),
8d318a50
LW		 1687 d40c->src_def_cfg,
1688 d40c->dma_cfg.src_info.data_width,
d49278e3 1689 d40c->dma_cfg.dst_info.data_width,
0246e77b 1690 d40c->dma_cfg.src_info.psize);
8d318a50
LW		 1691
1692 if (res < 0)
1693 goto err;
1694
1695 res = d40_phy_sg_to_lli(sgl_dst,
1696 sgl_len,
1697 0,
1698 d40d->lli_phy.dst,
aa182ae2 1699 virt_to_phys(d40d->lli_phy.dst),
8d318a50
LW		 1700 d40c->dst_def_cfg,
1701 d40c->dma_cfg.dst_info.data_width,
d49278e3 1702 d40c->dma_cfg.src_info.data_width,
0246e77b 1703 d40c->dma_cfg.dst_info.psize);
8d318a50
LW		 1704
1705 if (res < 0)
1706 goto err;
1707
b00f938c
RV		 1708 dma_sync_single_for_device(d40c->base->dev,
1709 d40d->lli_pool.dma_addr,
1710 d40d->lli_pool.size, DMA_TO_DEVICE);
8d318a50
LW		 1711 }
1712
1713 dma_async_tx_descriptor_init(&d40d->txd, chan);
1714
1715 d40d->txd.tx_submit = d40_tx_submit;
1716
2a614340 1717 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1718
1719 return &d40d->txd;
1720err:
819504f4
RV		 1721 if (d40d)
1722 d40_desc_free(d40c, d40d);
2a614340 1723 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1724 return NULL;
1725}
1726EXPORT_SYMBOL(stedma40_memcpy_sg);
1727
1728bool stedma40_filter(struct dma_chan *chan, void *data)
1729{
1730 struct stedma40_chan_cfg *info = data;
1731 struct d40_chan *d40c =
1732 container_of(chan, struct d40_chan, chan);
1733 int err;
1734
1735 if (data) {
1736 err = d40_validate_conf(d40c, info);
1737 if (!err)
1738 d40c->dma_cfg = *info;
1739 } else
1740 err = d40_config_memcpy(d40c);
1741
ce2ca125
RV		 1742 if (!err)
1743 d40c->configured = true;
1744
8d318a50
LW		 1745 return err == 0;
1746}
1747EXPORT_SYMBOL(stedma40_filter);
1748
ac2c0a38
RV		 1749static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
1750{
1751 bool realtime = d40c->dma_cfg.realtime;
1752 bool highprio = d40c->dma_cfg.high_priority;
1753 u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
1754 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
1755 u32 event = D40_TYPE_TO_EVENT(dev_type);
1756 u32 group = D40_TYPE_TO_GROUP(dev_type);
1757 u32 bit = 1 << event;
1758
1759 /* Destination event lines are stored in the upper halfword */
1760 if (!src)
1761 bit <<= 16;
1762
1763 writel(bit, d40c->base->virtbase + prioreg + group * 4);
1764 writel(bit, d40c->base->virtbase + rtreg + group * 4);
1765}
1766
1767static void d40_set_prio_realtime(struct d40_chan *d40c)
1768{
1769 if (d40c->base->rev < 3)
1770 return;
1771
1772 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1773 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1774 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
1775
1776 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
1777 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1778 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
1779}
1780
8d318a50
LW		 1781/* DMA ENGINE functions */
1782static int d40_alloc_chan_resources(struct dma_chan *chan)
1783{
1784 int err;
1785 unsigned long flags;
1786 struct d40_chan *d40c =
1787 container_of(chan, struct d40_chan, chan);
ef1872ec 1788 bool is_free_phy;
8d318a50
LW		 1789 spin_lock_irqsave(&d40c->lock, flags);
1790
1791 d40c->completed = chan->cookie = 1;
1792
ce2ca125
RV		 1793 /* If no dma configuration is set use default configuration (memcpy) */
1794 if (!d40c->configured) {
8d318a50 1795 err = d40_config_memcpy(d40c);
ff0b12ba 1796 if (err) {
6db5a8ba 1797 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 1798 goto fail;
1799 }
8d318a50 1800 }
ef1872ec 1801 is_free_phy = (d40c->phy_chan == NULL);
8d318a50
LW		 1802
1803 err = d40_allocate_channel(d40c);
1804 if (err) {
6db5a8ba 1805 chan_err(d40c, "Failed to allocate channel\n");
ff0b12ba 1806 goto fail;
8d318a50
LW		 1807 }
1808
ef1872ec
LW		 1809 /* Fill in basic CFG register values */
1810 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
724a8577 1811 &d40c->dst_def_cfg, chan_is_logical(d40c));
ef1872ec 1812
ac2c0a38
RV		 1813 d40_set_prio_realtime(d40c);
1814
724a8577 1815 if (chan_is_logical(d40c)) {
ef1872ec
LW		 1816 d40_log_cfg(&d40c->dma_cfg,
1817 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1818
1819 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1820 d40c->lcpa = d40c->base->lcpa_base +
1821 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1822 else
1823 d40c->lcpa = d40c->base->lcpa_base +
1824 d40c->dma_cfg.dst_dev_type *
1825 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1826 }
1827
1828 /*
1829 * Only write channel configuration to the DMA if the physical
1830 * resource is free. In case of multiple logical channels
1831 * on the same physical resource, only the first write is necessary.
1832 */
b55912c6
JA		 1833 if (is_free_phy)
1834 d40_config_write(d40c);
ff0b12ba 1835fail:
8d318a50 1836 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 1837 return err;
8d318a50
LW		 1838}
1839
1840static void d40_free_chan_resources(struct dma_chan *chan)
1841{
1842 struct d40_chan *d40c =
1843 container_of(chan, struct d40_chan, chan);
1844 int err;
1845 unsigned long flags;
1846
0d0f6b8b 1847 if (d40c->phy_chan == NULL) {
6db5a8ba 1848 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 1849 return;
1850 }
1851
1852
8d318a50
LW		 1853 spin_lock_irqsave(&d40c->lock, flags);
1854
1855 err = d40_free_dma(d40c);
1856
1857 if (err)
6db5a8ba 1858 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 1859 spin_unlock_irqrestore(&d40c->lock, flags);
1860}
1861
1862static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1863 dma_addr_t dst,
1864 dma_addr_t src,
1865 size_t size,
2a614340 1866 unsigned long dma_flags)
8d318a50
LW		 1867{
1868 struct d40_desc *d40d;
1869 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1870 chan);
2a614340 1871 unsigned long flags;
8d318a50 1872
0d0f6b8b 1873 if (d40c->phy_chan == NULL) {
6db5a8ba 1874 chan_err(d40c, "Channel is not allocated.\n");
0d0f6b8b
JA		 1875 return ERR_PTR(-EINVAL);
1876 }
1877
2a614340 1878 spin_lock_irqsave(&d40c->lock, flags);
8d318a50
LW		 1879 d40d = d40_desc_get(d40c);
1880
1881 if (d40d == NULL) {
6db5a8ba 1882 chan_err(d40c, "Descriptor is NULL\n");
8d318a50
LW		 1883 goto err;
1884 }
1885
2a614340 1886 d40d->txd.flags = dma_flags;
d49278e3
PF		 1887 d40d->lli_len = d40_size_2_dmalen(size,
1888 d40c->dma_cfg.src_info.data_width,
1889 d40c->dma_cfg.dst_info.data_width);
1890 if (d40d->lli_len < 0) {
6db5a8ba 1891 chan_err(d40c, "Unaligned size\n");
d49278e3
PF		 1892 goto err;
1893 }
1894
8d318a50
LW		 1895
1896 dma_async_tx_descriptor_init(&d40d->txd, chan);
1897
1898 d40d->txd.tx_submit = d40_tx_submit;
1899
724a8577 1900 if (chan_is_logical(d40c)) {
8d318a50 1901
b00f938c 1902 if (d40_pool_lli_alloc(d40c,d40d, d40d->lli_len, true) < 0) {
6db5a8ba 1903 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 1904 goto err;
1905 }
698e4732 1906 d40d->lli_current = 0;
8d318a50 1907
d49278e3
PF		 1908 if (d40_log_buf_to_lli(d40d->lli_log.src,
1909 src,
1910 size,
1911 d40c->log_def.lcsp1,
1912 d40c->dma_cfg.src_info.data_width,
1913 d40c->dma_cfg.dst_info.data_width,
1914 true) == NULL)
1915 goto err;
8d318a50 1916
d49278e3
PF		 1917 if (d40_log_buf_to_lli(d40d->lli_log.dst,
1918 dst,
1919 size,
1920 d40c->log_def.lcsp3,
1921 d40c->dma_cfg.dst_info.data_width,
1922 d40c->dma_cfg.src_info.data_width,
1923 true) == NULL)
1924 goto err;
8d318a50
LW		 1925
1926 } else {
1927
b00f938c 1928 if (d40_pool_lli_alloc(d40c, d40d, d40d->lli_len, false) < 0) {
6db5a8ba 1929 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 1930 goto err;
1931 }
1932
d49278e3 1933 if (d40_phy_buf_to_lli(d40d->lli_phy.src,
8d318a50
LW		 1934 src,
1935 size,
1936 d40c->dma_cfg.src_info.psize,
1937 0,
1938 d40c->src_def_cfg,
1939 true,
1940 d40c->dma_cfg.src_info.data_width,
d49278e3
PF		 1941 d40c->dma_cfg.dst_info.data_width,
1942 false) == NULL)
1943 goto err;
8d318a50 1944
d49278e3 1945 if (d40_phy_buf_to_lli(d40d->lli_phy.dst,
8d318a50
LW		 1946 dst,
1947 size,
1948 d40c->dma_cfg.dst_info.psize,
1949 0,
1950 d40c->dst_def_cfg,
1951 true,
1952 d40c->dma_cfg.dst_info.data_width,
d49278e3
PF		 1953 d40c->dma_cfg.src_info.data_width,
1954 false) == NULL)
1955 goto err;
8d318a50 1956
b00f938c
RV		 1957 dma_sync_single_for_device(d40c->base->dev,
1958 d40d->lli_pool.dma_addr,
1959 d40d->lli_pool.size, DMA_TO_DEVICE);
8d318a50
LW		 1960 }
1961
2a614340 1962 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1963 return &d40d->txd;
1964
8d318a50 1965err:
819504f4
RV		 1966 if (d40d)
1967 d40_desc_free(d40c, d40d);
2a614340 1968 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1969 return NULL;
1970}
1971
0d688662
IS		 1972static struct dma_async_tx_descriptor *
1973d40_prep_sg(struct dma_chan *chan,
1974 struct scatterlist *dst_sg, unsigned int dst_nents,
1975 struct scatterlist *src_sg, unsigned int src_nents,
1976 unsigned long dma_flags)
1977{
1978 if (dst_nents != src_nents)
1979 return NULL;
1980
1981 return stedma40_memcpy_sg(chan, dst_sg, src_sg, dst_nents, dma_flags);
1982}
1983
8d318a50
LW		 1984static int d40_prep_slave_sg_log(struct d40_desc *d40d,
1985 struct d40_chan *d40c,
1986 struct scatterlist *sgl,
1987 unsigned int sg_len,
1988 enum dma_data_direction direction,
2a614340 1989 unsigned long dma_flags)
8d318a50
LW		 1990{
1991 dma_addr_t dev_addr = 0;
1992 int total_size;
8d318a50 1993
d49278e3
PF		 1994 d40d->lli_len = d40_sg_2_dmalen(sgl, sg_len,
1995 d40c->dma_cfg.src_info.data_width,
1996 d40c->dma_cfg.dst_info.data_width);
1997 if (d40d->lli_len < 0) {
6db5a8ba 1998 chan_err(d40c, "Unaligned size\n");
d49278e3
PF		 1999 return -EINVAL;
2000 }
2001
b00f938c 2002 if (d40_pool_lli_alloc(d40c, d40d, d40d->lli_len, true) < 0) {
6db5a8ba 2003 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 2004 return -ENOMEM;
2005 }
2006
698e4732 2007 d40d->lli_current = 0;
8d318a50 2008
2a614340 2009 if (direction == DMA_FROM_DEVICE)
95e1400f
LW		 2010 if (d40c->runtime_addr)
2011 dev_addr = d40c->runtime_addr;
2012 else
2013 dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
2a614340 2014 else if (direction == DMA_TO_DEVICE)
95e1400f
LW		 2015 if (d40c->runtime_addr)
2016 dev_addr = d40c->runtime_addr;
2017 else
2018 dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
2019
2a614340 2020 else
8d318a50 2021 return -EINVAL;
2a614340 2022
698e4732 2023 total_size = d40_log_sg_to_dev(sgl, sg_len,
2a614340
JA		 2024 &d40d->lli_log,
2025 &d40c->log_def,
2026 d40c->dma_cfg.src_info.data_width,
2027 d40c->dma_cfg.dst_info.data_width,
2028 direction,
698e4732 2029 dev_addr);
2a614340 2030
8d318a50
LW		 2031 if (total_size < 0)
2032 return -EINVAL;
2033
2034 return 0;
2035}
2036
2037static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
2038 struct d40_chan *d40c,
2039 struct scatterlist *sgl,
2040 unsigned int sgl_len,
2041 enum dma_data_direction direction,
2a614340 2042 unsigned long dma_flags)
8d318a50
LW		 2043{
2044 dma_addr_t src_dev_addr;
2045 dma_addr_t dst_dev_addr;
2046 int res;
2047
d49278e3
PF		 2048 d40d->lli_len = d40_sg_2_dmalen(sgl, sgl_len,
2049 d40c->dma_cfg.src_info.data_width,
2050 d40c->dma_cfg.dst_info.data_width);
2051 if (d40d->lli_len < 0) {
6db5a8ba 2052 chan_err(d40c, "Unaligned size\n");
d49278e3
PF		 2053 return -EINVAL;
2054 }
2055
b00f938c 2056 if (d40_pool_lli_alloc(d40c, d40d, d40d->lli_len, false) < 0) {
6db5a8ba 2057 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 2058 return -ENOMEM;
2059 }
2060
698e4732 2061 d40d->lli_current = 0;
8d318a50
LW		 2062
2063 if (direction == DMA_FROM_DEVICE) {
2064 dst_dev_addr = 0;
95e1400f
LW		 2065 if (d40c->runtime_addr)
2066 src_dev_addr = d40c->runtime_addr;
2067 else
2068 src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
8d318a50 2069 } else if (direction == DMA_TO_DEVICE) {
95e1400f
LW		 2070 if (d40c->runtime_addr)
2071 dst_dev_addr = d40c->runtime_addr;
2072 else
2073 dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
8d318a50
LW		 2074 src_dev_addr = 0;
2075 } else
2076 return -EINVAL;
2077
2078 res = d40_phy_sg_to_lli(sgl,
2079 sgl_len,
2080 src_dev_addr,
2081 d40d->lli_phy.src,
aa182ae2 2082 virt_to_phys(d40d->lli_phy.src),
8d318a50
LW		 2083 d40c->src_def_cfg,
2084 d40c->dma_cfg.src_info.data_width,
d49278e3 2085 d40c->dma_cfg.dst_info.data_width,
0246e77b 2086 d40c->dma_cfg.src_info.psize);
8d318a50
LW		 2087 if (res < 0)
2088 return res;
2089
2090 res = d40_phy_sg_to_lli(sgl,
2091 sgl_len,
2092 dst_dev_addr,
2093 d40d->lli_phy.dst,
aa182ae2 2094 virt_to_phys(d40d->lli_phy.dst),
8d318a50
LW		 2095 d40c->dst_def_cfg,
2096 d40c->dma_cfg.dst_info.data_width,
d49278e3 2097 d40c->dma_cfg.src_info.data_width,
0246e77b 2098 d40c->dma_cfg.dst_info.psize);
8d318a50
LW		 2099 if (res < 0)
2100 return res;
2101
b00f938c
RV		 2102 dma_sync_single_for_device(d40c->base->dev, d40d->lli_pool.dma_addr,
2103 d40d->lli_pool.size, DMA_TO_DEVICE);
8d318a50
LW		 2104 return 0;
2105}
2106
2107static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2108 struct scatterlist *sgl,
2109 unsigned int sg_len,
2110 enum dma_data_direction direction,
2a614340 2111 unsigned long dma_flags)
8d318a50
LW		 2112{
2113 struct d40_desc *d40d;
2114 struct d40_chan *d40c = container_of(chan, struct d40_chan,
2115 chan);
2a614340 2116 unsigned long flags;
8d318a50
LW		 2117 int err;
2118
0d0f6b8b 2119 if (d40c->phy_chan == NULL) {
6db5a8ba 2120 chan_err(d40c, "Cannot prepare unallocated channel\n");
0d0f6b8b
JA		 2121 return ERR_PTR(-EINVAL);
2122 }
2123
2a614340 2124 spin_lock_irqsave(&d40c->lock, flags);
8d318a50 2125 d40d = d40_desc_get(d40c);
8d318a50
LW		 2126
2127 if (d40d == NULL)
819504f4 2128 goto err;
8d318a50 2129
724a8577 2130 if (chan_is_logical(d40c))
8d318a50 2131 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2a614340 2132 direction, dma_flags);
8d318a50
LW		 2133 else
2134 err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
2a614340 2135 direction, dma_flags);
8d318a50 2136 if (err) {
6db5a8ba 2137 chan_err(d40c, "Failed to prepare %s slave sg job: %d\n",
724a8577 2138 chan_is_logical(d40c) ? "log" : "phy", err);
819504f4 2139 goto err;
8d318a50
LW		 2140 }
2141
2a614340 2142 d40d->txd.flags = dma_flags;
8d318a50
LW		 2143
2144 dma_async_tx_descriptor_init(&d40d->txd, chan);
2145
2146 d40d->txd.tx_submit = d40_tx_submit;
2147
819504f4 2148 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50 2149 return &d40d->txd;
819504f4
RV		 2150
2151err:
2152 if (d40d)
2153 d40_desc_free(d40c, d40d);
2154 spin_unlock_irqrestore(&d40c->lock, flags);
2155 return NULL;
8d318a50
LW		 2156}
2157
2158static enum dma_status d40_tx_status(struct dma_chan *chan,
2159 dma_cookie_t cookie,
2160 struct dma_tx_state *txstate)
2161{
2162 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2163 dma_cookie_t last_used;
2164 dma_cookie_t last_complete;
2165 int ret;
2166
0d0f6b8b 2167 if (d40c->phy_chan == NULL) {
6db5a8ba 2168 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2169 return -EINVAL;
2170 }
2171
8d318a50
LW		 2172 last_complete = d40c->completed;
2173 last_used = chan->cookie;
2174
a5ebca47
JA		 2175 if (d40_is_paused(d40c))
2176 ret = DMA_PAUSED;
2177 else
2178 ret = dma_async_is_complete(cookie, last_complete, last_used);
8d318a50 2179
a5ebca47
JA		 2180 dma_set_tx_state(txstate, last_complete, last_used,
2181 stedma40_residue(chan));
8d318a50
LW		 2182
2183 return ret;
2184}
2185
2186static void d40_issue_pending(struct dma_chan *chan)
2187{
2188 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2189 unsigned long flags;
2190
0d0f6b8b 2191 if (d40c->phy_chan == NULL) {
6db5a8ba 2192 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2193 return;
2194 }
2195
8d318a50
LW		 2196 spin_lock_irqsave(&d40c->lock, flags);
2197
2198 /* Busy means that pending jobs are already being processed */
2199 if (!d40c->busy)
2200 (void) d40_queue_start(d40c);
2201
2202 spin_unlock_irqrestore(&d40c->lock, flags);
2203}
2204
95e1400f
LW		 2205/* Runtime reconfiguration extension */
2206static void d40_set_runtime_config(struct dma_chan *chan,
2207 struct dma_slave_config *config)
2208{
2209 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2210 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2211 enum dma_slave_buswidth config_addr_width;
2212 dma_addr_t config_addr;
2213 u32 config_maxburst;
2214 enum stedma40_periph_data_width addr_width;
2215 int psize;
2216
2217 if (config->direction == DMA_FROM_DEVICE) {
2218 dma_addr_t dev_addr_rx =
2219 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2220
2221 config_addr = config->src_addr;
2222 if (dev_addr_rx)
2223 dev_dbg(d40c->base->dev,
2224 "channel has a pre-wired RX address %08x "
2225 "overriding with %08x\n",
2226 dev_addr_rx, config_addr);
2227 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2228 dev_dbg(d40c->base->dev,
2229 "channel was not configured for peripheral "
2230 "to memory transfer (%d) overriding\n",
2231 cfg->dir);
2232 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2233
2234 config_addr_width = config->src_addr_width;
2235 config_maxburst = config->src_maxburst;
2236
2237 } else if (config->direction == DMA_TO_DEVICE) {
2238 dma_addr_t dev_addr_tx =
2239 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2240
2241 config_addr = config->dst_addr;
2242 if (dev_addr_tx)
2243 dev_dbg(d40c->base->dev,
2244 "channel has a pre-wired TX address %08x "
2245 "overriding with %08x\n",
2246 dev_addr_tx, config_addr);
2247 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2248 dev_dbg(d40c->base->dev,
2249 "channel was not configured for memory "
2250 "to peripheral transfer (%d) overriding\n",
2251 cfg->dir);
2252 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2253
2254 config_addr_width = config->dst_addr_width;
2255 config_maxburst = config->dst_maxburst;
2256
2257 } else {
2258 dev_err(d40c->base->dev,
2259 "unrecognized channel direction %d\n",
2260 config->direction);
2261 return;
2262 }
2263
2264 switch (config_addr_width) {
2265 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2266 addr_width = STEDMA40_BYTE_WIDTH;
2267 break;
2268 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2269 addr_width = STEDMA40_HALFWORD_WIDTH;
2270 break;
2271 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2272 addr_width = STEDMA40_WORD_WIDTH;
2273 break;
2274 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2275 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2276 break;
2277 default:
2278 dev_err(d40c->base->dev,
2279 "illegal peripheral address width "
2280 "requested (%d)\n",
2281 config->src_addr_width);
2282 return;
2283 }
2284
724a8577 2285 if (chan_is_logical(d40c)) {
a59670a4
PF		 2286 if (config_maxburst >= 16)
2287 psize = STEDMA40_PSIZE_LOG_16;
2288 else if (config_maxburst >= 8)
2289 psize = STEDMA40_PSIZE_LOG_8;
2290 else if (config_maxburst >= 4)
2291 psize = STEDMA40_PSIZE_LOG_4;
2292 else
2293 psize = STEDMA40_PSIZE_LOG_1;
2294 } else {
2295 if (config_maxburst >= 16)
2296 psize = STEDMA40_PSIZE_PHY_16;
2297 else if (config_maxburst >= 8)
2298 psize = STEDMA40_PSIZE_PHY_8;
2299 else if (config_maxburst >= 4)
2300 psize = STEDMA40_PSIZE_PHY_4;
d49278e3
PF		 2301 else if (config_maxburst >= 2)
2302 psize = STEDMA40_PSIZE_PHY_2;
a59670a4
PF		 2303 else
2304 psize = STEDMA40_PSIZE_PHY_1;
2305 }
95e1400f
LW		 2306
2307 /* Set up all the endpoint configs */
2308 cfg->src_info.data_width = addr_width;
2309 cfg->src_info.psize = psize;
51f5d744 2310 cfg->src_info.big_endian = false;
95e1400f
LW		 2311 cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2312 cfg->dst_info.data_width = addr_width;
2313 cfg->dst_info.psize = psize;
51f5d744 2314 cfg->dst_info.big_endian = false;
95e1400f
LW		 2315 cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2316
a59670a4 2317 /* Fill in register values */
724a8577 2318 if (chan_is_logical(d40c))
a59670a4
PF		 2319 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2320 else
2321 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2322 &d40c->dst_def_cfg, false);
2323
95e1400f
LW		 2324 /* These settings will take precedence later */
2325 d40c->runtime_addr = config_addr;
2326 d40c->runtime_direction = config->direction;
2327 dev_dbg(d40c->base->dev,
2328 "configured channel %s for %s, data width %d, "
2329 "maxburst %d bytes, LE, no flow control\n",
2330 dma_chan_name(chan),
2331 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2332 config_addr_width,
2333 config_maxburst);
2334}
2335
05827630
LW		 2336static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2337 unsigned long arg)
8d318a50
LW		 2338{
2339 unsigned long flags;
2340 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2341
0d0f6b8b 2342 if (d40c->phy_chan == NULL) {
6db5a8ba 2343 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2344 return -EINVAL;
2345 }
2346
8d318a50
LW		 2347 switch (cmd) {
2348 case DMA_TERMINATE_ALL:
2349 spin_lock_irqsave(&d40c->lock, flags);
2350 d40_term_all(d40c);
2351 spin_unlock_irqrestore(&d40c->lock, flags);
2352 return 0;
2353 case DMA_PAUSE:
2354 return d40_pause(chan);
2355 case DMA_RESUME:
2356 return d40_resume(chan);
95e1400f
LW		 2357 case DMA_SLAVE_CONFIG:
2358 d40_set_runtime_config(chan,
2359 (struct dma_slave_config *) arg);
2360 return 0;
2361 default:
2362 break;
8d318a50
LW		 2363 }
2364
2365 /* Other commands are unimplemented */
2366 return -ENXIO;
2367}
2368
2369/* Initialization functions */
2370
2371static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2372 struct d40_chan *chans, int offset,
2373 int num_chans)
2374{
2375 int i = 0;
2376 struct d40_chan *d40c;
2377
2378 INIT_LIST_HEAD(&dma->channels);
2379
2380 for (i = offset; i < offset + num_chans; i++) {
2381 d40c = &chans[i];
2382 d40c->base = base;
2383 d40c->chan.device = dma;
2384
8d318a50
LW		 2385 spin_lock_init(&d40c->lock);
2386
2387 d40c->log_num = D40_PHY_CHAN;
2388
8d318a50
LW		 2389 INIT_LIST_HEAD(&d40c->active);
2390 INIT_LIST_HEAD(&d40c->queue);
2391 INIT_LIST_HEAD(&d40c->client);
2392
8d318a50
LW		 2393 tasklet_init(&d40c->tasklet, dma_tasklet,
2394 (unsigned long) d40c);
2395
2396 list_add_tail(&d40c->chan.device_node,
2397 &dma->channels);
2398 }
2399}
2400
2401static int __init d40_dmaengine_init(struct d40_base *base,
2402 int num_reserved_chans)
2403{
2404 int err ;
2405
2406 d40_chan_init(base, &base->dma_slave, base->log_chans,
2407 0, base->num_log_chans);
2408
2409 dma_cap_zero(base->dma_slave.cap_mask);
2410 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2411
2412 base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2413 base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2414 base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
0d688662 2415 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
8d318a50
LW		 2416 base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2417 base->dma_slave.device_tx_status = d40_tx_status;
2418 base->dma_slave.device_issue_pending = d40_issue_pending;
2419 base->dma_slave.device_control = d40_control;
2420 base->dma_slave.dev = base->dev;
2421
2422 err = dma_async_device_register(&base->dma_slave);
2423
2424 if (err) {
6db5a8ba 2425 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2426 goto failure1;
2427 }
2428
2429 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2430 base->num_log_chans, base->plat_data->memcpy_len);
2431
2432 dma_cap_zero(base->dma_memcpy.cap_mask);
2433 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
0d688662 2434 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
8d318a50
LW		 2435
2436 base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2437 base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2438 base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
0d688662 2439 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
8d318a50
LW		 2440 base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2441 base->dma_memcpy.device_tx_status = d40_tx_status;
2442 base->dma_memcpy.device_issue_pending = d40_issue_pending;
2443 base->dma_memcpy.device_control = d40_control;
2444 base->dma_memcpy.dev = base->dev;
2445 /*
2446 * This controller can only access address at even
2447 * 32bit boundaries, i.e. 2^2
2448 */
2449 base->dma_memcpy.copy_align = 2;
2450
2451 err = dma_async_device_register(&base->dma_memcpy);
2452
2453 if (err) {
6db5a8ba
RV		 2454 d40_err(base->dev,
2455 "Failed to regsiter memcpy only channels\n");
8d318a50
LW		 2456 goto failure2;
2457 }
2458
2459 d40_chan_init(base, &base->dma_both, base->phy_chans,
2460 0, num_reserved_chans);
2461
2462 dma_cap_zero(base->dma_both.cap_mask);
2463 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2464 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
0d688662 2465 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
8d318a50
LW		 2466
2467 base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2468 base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2469 base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
0d688662 2470 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
8d318a50
LW		 2471 base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2472 base->dma_both.device_tx_status = d40_tx_status;
2473 base->dma_both.device_issue_pending = d40_issue_pending;
2474 base->dma_both.device_control = d40_control;
2475 base->dma_both.dev = base->dev;
2476 base->dma_both.copy_align = 2;
2477 err = dma_async_device_register(&base->dma_both);
2478
2479 if (err) {
6db5a8ba
RV		 2480 d40_err(base->dev,
2481 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2482 goto failure3;
2483 }
2484 return 0;
2485failure3:
2486 dma_async_device_unregister(&base->dma_memcpy);
2487failure2:
2488 dma_async_device_unregister(&base->dma_slave);
2489failure1:
2490 return err;
2491}
2492
2493/* Initialization functions. */
2494
2495static int __init d40_phy_res_init(struct d40_base *base)
2496{
2497 int i;
2498 int num_phy_chans_avail = 0;
2499 u32 val[2];
2500 int odd_even_bit = -2;
2501
2502 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2503 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2504
2505 for (i = 0; i < base->num_phy_chans; i++) {
2506 base->phy_res[i].num = i;
2507 odd_even_bit += 2 * ((i % 2) == 0);
2508 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2509 /* Mark security only channels as occupied */
2510 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2511 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2512 } else {
2513 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2514 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2515 num_phy_chans_avail++;
2516 }
2517 spin_lock_init(&base->phy_res[i].lock);
2518 }
6b7acd84
JA		 2519
2520 /* Mark disabled channels as occupied */
2521 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 2522 int chan = base->plat_data->disabled_channels[i];
2523
2524 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2525 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2526 num_phy_chans_avail--;
6b7acd84
JA		 2527 }
2528
8d318a50
LW		 2529 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2530 num_phy_chans_avail, base->num_phy_chans);
2531
2532 /* Verify settings extended vs standard */
2533 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2534
2535 for (i = 0; i < base->num_phy_chans; i++) {
2536
2537 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2538 (val[0] & 0x3) != 1)
2539 dev_info(base->dev,
2540 "[%s] INFO: channel %d is misconfigured (%d)\n",
2541 __func__, i, val[0] & 0x3);
2542
2543 val[0] = val[0] >> 2;
2544 }
2545
2546 return num_phy_chans_avail;
2547}
2548
2549static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2550{
2551 static const struct d40_reg_val dma_id_regs[] = {
2552 /* Peripheral Id */
2553 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2554 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2555 /*
2556 * D40_DREG_PERIPHID2 Depends on HW revision:
4d594900 2557 * DB8500ed has 0x0008,
8d318a50 2558 * ? has 0x0018,
4d594900
RV		 2559 * DB8500v1 has 0x0028
2560 * DB8500v2 has 0x0038
8d318a50
LW		 2561 */
2562 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2563
2564 /* PCell Id */
2565 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2566 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2567 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2568 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2569 };
2570 struct stedma40_platform_data *plat_data;
2571 struct clk *clk = NULL;
2572 void __iomem *virtbase = NULL;
2573 struct resource *res = NULL;
2574 struct d40_base *base = NULL;
2575 int num_log_chans = 0;
2576 int num_phy_chans;
2577 int i;
f4185592 2578 u32 val;
3ae0267f 2579 u32 rev;
8d318a50
LW		 2580
2581 clk = clk_get(&pdev->dev, NULL);
2582
2583 if (IS_ERR(clk)) {
6db5a8ba 2584 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 2585 goto failure;
2586 }
2587
2588 clk_enable(clk);
2589
2590 /* Get IO for DMAC base address */
2591 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2592 if (!res)
2593 goto failure;
2594
2595 if (request_mem_region(res->start, resource_size(res),
2596 D40_NAME " I/O base") == NULL)
2597 goto failure;
2598
2599 virtbase = ioremap(res->start, resource_size(res));
2600 if (!virtbase)
2601 goto failure;
2602
2603 /* HW version check */
2604 for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2605 if (dma_id_regs[i].val !=
2606 readl(virtbase + dma_id_regs[i].reg)) {
6db5a8ba
RV		 2607 d40_err(&pdev->dev,
2608 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
8d318a50
LW		 2609 dma_id_regs[i].val,
2610 dma_id_regs[i].reg,
2611 readl(virtbase + dma_id_regs[i].reg));
2612 goto failure;
2613 }
2614 }
2615
3ae0267f 2616 /* Get silicon revision and designer */
f4185592 2617 val = readl(virtbase + D40_DREG_PERIPHID2);
8d318a50 2618
3ae0267f
JA		 2619 if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2620 D40_HW_DESIGNER) {
6db5a8ba
RV		 2621 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
2622 val & D40_DREG_PERIPHID2_DESIGNER_MASK,
3ae0267f 2623 D40_HW_DESIGNER);
8d318a50
LW		 2624 goto failure;
2625 }
2626
3ae0267f
JA		 2627 rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2628 D40_DREG_PERIPHID2_REV_POS;
2629
8d318a50
LW		 2630 /* The number of physical channels on this HW */
2631 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2632
2633 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
3ae0267f 2634 rev, res->start);
8d318a50
LW		 2635
2636 plat_data = pdev->dev.platform_data;
2637
2638 /* Count the number of logical channels in use */
2639 for (i = 0; i < plat_data->dev_len; i++)
2640 if (plat_data->dev_rx[i] != 0)
2641 num_log_chans++;
2642
2643 for (i = 0; i < plat_data->dev_len; i++)
2644 if (plat_data->dev_tx[i] != 0)
2645 num_log_chans++;
2646
2647 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2648 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2649 sizeof(struct d40_chan), GFP_KERNEL);
2650
2651 if (base == NULL) {
6db5a8ba 2652 d40_err(&pdev->dev, "Out of memory\n");
8d318a50
LW		 2653 goto failure;
2654 }
2655
3ae0267f 2656 base->rev = rev;
8d318a50
LW		 2657 base->clk = clk;
2658 base->num_phy_chans = num_phy_chans;
2659 base->num_log_chans = num_log_chans;
2660 base->phy_start = res->start;
2661 base->phy_size = resource_size(res);
2662 base->virtbase = virtbase;
2663 base->plat_data = plat_data;
2664 base->dev = &pdev->dev;
2665 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2666 base->log_chans = &base->phy_chans[num_phy_chans];
2667
2668 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2669 GFP_KERNEL);
2670 if (!base->phy_res)
2671 goto failure;
2672
2673 base->lookup_phy_chans = kzalloc(num_phy_chans *
2674 sizeof(struct d40_chan *),
2675 GFP_KERNEL);
2676 if (!base->lookup_phy_chans)
2677 goto failure;
2678
2679 if (num_log_chans + plat_data->memcpy_len) {
2680 /*
2681 * The max number of logical channels are event lines for all
2682 * src devices and dst devices
2683 */
2684 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2685 sizeof(struct d40_chan *),
2686 GFP_KERNEL);
2687 if (!base->lookup_log_chans)
2688 goto failure;
2689 }
698e4732
JA		 2690
2691 base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
2692 sizeof(struct d40_desc *) *
2693 D40_LCLA_LINK_PER_EVENT_GRP,
8d318a50
LW		 2694 GFP_KERNEL);
2695 if (!base->lcla_pool.alloc_map)
2696 goto failure;
2697
c675b1b4
JA		 2698 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2699 0, SLAB_HWCACHE_ALIGN,
2700 NULL);
2701 if (base->desc_slab == NULL)
2702 goto failure;
2703
8d318a50
LW		 2704 return base;
2705
2706failure:
c6134c96 2707 if (!IS_ERR(clk)) {
8d318a50
LW		 2708 clk_disable(clk);
2709 clk_put(clk);
2710 }
2711 if (virtbase)
2712 iounmap(virtbase);
2713 if (res)
2714 release_mem_region(res->start,
2715 resource_size(res));
2716 if (virtbase)
2717 iounmap(virtbase);
2718
2719 if (base) {
2720 kfree(base->lcla_pool.alloc_map);
2721 kfree(base->lookup_log_chans);
2722 kfree(base->lookup_phy_chans);
2723 kfree(base->phy_res);
2724 kfree(base);
2725 }
2726
2727 return NULL;
2728}
2729
2730static void __init d40_hw_init(struct d40_base *base)
2731{
2732
2733 static const struct d40_reg_val dma_init_reg[] = {
2734 /* Clock every part of the DMA block from start */
2735 { .reg = D40_DREG_GCC, .val = 0x0000ff01},
2736
2737 /* Interrupts on all logical channels */
2738 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2739 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2740 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2741 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2742 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2743 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2744 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2745 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2746 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2747 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2748 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2749 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2750 };
2751 int i;
2752 u32 prmseo[2] = {0, 0};
2753 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2754 u32 pcmis = 0;
2755 u32 pcicr = 0;
2756
2757 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2758 writel(dma_init_reg[i].val,
2759 base->virtbase + dma_init_reg[i].reg);
2760
2761 /* Configure all our dma channels to default settings */
2762 for (i = 0; i < base->num_phy_chans; i++) {
2763
2764 activeo[i % 2] = activeo[i % 2] << 2;
2765
2766 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2767 == D40_ALLOC_PHY) {
2768 activeo[i % 2] |= 3;
2769 continue;
2770 }
2771
2772 /* Enable interrupt # */
2773 pcmis = (pcmis << 1) | 1;
2774
2775 /* Clear interrupt # */
2776 pcicr = (pcicr << 1) | 1;
2777
2778 /* Set channel to physical mode */
2779 prmseo[i % 2] = prmseo[i % 2] << 2;
2780 prmseo[i % 2] |= 1;
2781
2782 }
2783
2784 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2785 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2786 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2787 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2788
2789 /* Write which interrupt to enable */
2790 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2791
2792 /* Write which interrupt to clear */
2793 writel(pcicr, base->virtbase + D40_DREG_PCICR);
2794
2795}
2796
508849ad
LW		 2797static int __init d40_lcla_allocate(struct d40_base *base)
2798{
026cbc42 2799 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 2800 unsigned long *page_list;
2801 int i, j;
2802 int ret = 0;
2803
2804 /*
2805 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2806 * To full fill this hardware requirement without wasting 256 kb
2807 * we allocate pages until we get an aligned one.
2808 */
2809 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2810 GFP_KERNEL);
2811
2812 if (!page_list) {
2813 ret = -ENOMEM;
2814 goto failure;
2815 }
2816
2817 /* Calculating how many pages that are required */
2818 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2819
2820 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2821 page_list[i] = __get_free_pages(GFP_KERNEL,
2822 base->lcla_pool.pages);
2823 if (!page_list[i]) {
2824
6db5a8ba
RV		 2825 d40_err(base->dev, "Failed to allocate %d pages.\n",
2826 base->lcla_pool.pages);
508849ad
LW		 2827
2828 for (j = 0; j < i; j++)
2829 free_pages(page_list[j], base->lcla_pool.pages);
2830 goto failure;
2831 }
2832
2833 if ((virt_to_phys((void *)page_list[i]) &
2834 (LCLA_ALIGNMENT - 1)) == 0)
2835 break;
2836 }
2837
2838 for (j = 0; j < i; j++)
2839 free_pages(page_list[j], base->lcla_pool.pages);
2840
2841 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2842 base->lcla_pool.base = (void *)page_list[i];
2843 } else {
767a9675
JA		 2844 /*
2845 * After many attempts and no succees with finding the correct
2846 * alignment, try with allocating a big buffer.
2847 */
508849ad
LW		 2848 dev_warn(base->dev,
2849 "[%s] Failed to get %d pages @ 18 bit align.\n",
2850 __func__, base->lcla_pool.pages);
2851 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2852 base->num_phy_chans +
2853 LCLA_ALIGNMENT,
2854 GFP_KERNEL);
2855 if (!base->lcla_pool.base_unaligned) {
2856 ret = -ENOMEM;
2857 goto failure;
2858 }
2859
2860 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2861 LCLA_ALIGNMENT);
2862 }
2863
026cbc42
RV		 2864 pool->dma_addr = dma_map_single(base->dev, pool->base,
2865 SZ_1K * base->num_phy_chans,
2866 DMA_TO_DEVICE);
2867 if (dma_mapping_error(base->dev, pool->dma_addr)) {
2868 pool->dma_addr = 0;
2869 ret = -ENOMEM;
2870 goto failure;
2871 }
2872
508849ad
LW		 2873 writel(virt_to_phys(base->lcla_pool.base),
2874 base->virtbase + D40_DREG_LCLA);
2875failure:
2876 kfree(page_list);
2877 return ret;
2878}
2879
8d318a50
LW		 2880static int __init d40_probe(struct platform_device *pdev)
2881{
2882 int err;
2883 int ret = -ENOENT;
2884 struct d40_base *base;
2885 struct resource *res = NULL;
2886 int num_reserved_chans;
2887 u32 val;
2888
2889 base = d40_hw_detect_init(pdev);
2890
2891 if (!base)
2892 goto failure;
2893
2894 num_reserved_chans = d40_phy_res_init(base);
2895
2896 platform_set_drvdata(pdev, base);
2897
2898 spin_lock_init(&base->interrupt_lock);
2899 spin_lock_init(&base->execmd_lock);
2900
2901 /* Get IO for logical channel parameter address */
2902 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2903 if (!res) {
2904 ret = -ENOENT;
6db5a8ba 2905 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 2906 goto failure;
2907 }
2908 base->lcpa_size = resource_size(res);
2909 base->phy_lcpa = res->start;
2910
2911 if (request_mem_region(res->start, resource_size(res),
2912 D40_NAME " I/O lcpa") == NULL) {
2913 ret = -EBUSY;
6db5a8ba
RV		 2914 d40_err(&pdev->dev,
2915 "Failed to request LCPA region 0x%x-0x%x\n",
2916 res->start, res->end);
8d318a50
LW		 2917 goto failure;
2918 }
2919
2920 /* We make use of ESRAM memory for this. */
2921 val = readl(base->virtbase + D40_DREG_LCPA);
2922 if (res->start != val && val != 0) {
2923 dev_warn(&pdev->dev,
2924 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2925 __func__, val, res->start);
2926 } else
2927 writel(res->start, base->virtbase + D40_DREG_LCPA);
2928
2929 base->lcpa_base = ioremap(res->start, resource_size(res));
2930 if (!base->lcpa_base) {
2931 ret = -ENOMEM;
6db5a8ba 2932 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 2933 goto failure;
2934 }
8d318a50 2935
508849ad
LW		 2936 ret = d40_lcla_allocate(base);
2937 if (ret) {
6db5a8ba 2938 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
8d318a50
LW		 2939 goto failure;
2940 }
2941
2942 spin_lock_init(&base->lcla_pool.lock);
2943
8d318a50
LW		 2944 base->irq = platform_get_irq(pdev, 0);
2945
2946 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 2947 if (ret) {
6db5a8ba 2948 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 2949 goto failure;
2950 }
2951
2952 err = d40_dmaengine_init(base, num_reserved_chans);
2953 if (err)
2954 goto failure;
2955
2956 d40_hw_init(base);
2957
2958 dev_info(base->dev, "initialized\n");
2959 return 0;
2960
2961failure:
2962 if (base) {
c675b1b4
JA		 2963 if (base->desc_slab)
2964 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 2965 if (base->virtbase)
2966 iounmap(base->virtbase);
026cbc42
RV		 2967
2968 if (base->lcla_pool.dma_addr)
2969 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
2970 SZ_1K * base->num_phy_chans,
2971 DMA_TO_DEVICE);
2972
508849ad
LW		 2973 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2974 free_pages((unsigned long)base->lcla_pool.base,
2975 base->lcla_pool.pages);
767a9675
JA		 2976
2977 kfree(base->lcla_pool.base_unaligned);
2978
8d318a50
LW		 2979 if (base->phy_lcpa)
2980 release_mem_region(base->phy_lcpa,
2981 base->lcpa_size);
2982 if (base->phy_start)
2983 release_mem_region(base->phy_start,
2984 base->phy_size);
2985 if (base->clk) {
2986 clk_disable(base->clk);
2987 clk_put(base->clk);
2988 }
2989
2990 kfree(base->lcla_pool.alloc_map);
2991 kfree(base->lookup_log_chans);
2992 kfree(base->lookup_phy_chans);
2993 kfree(base->phy_res);
2994 kfree(base);
2995 }
2996
6db5a8ba 2997 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 2998 return ret;
2999}
3000
3001static struct platform_driver d40_driver = {
3002 .driver = {
3003 .owner = THIS_MODULE,
3004 .name = D40_NAME,
3005 },
3006};
3007
cb9ab2d8 3008static int __init stedma40_init(void)
8d318a50
LW		 3009{
3010 return platform_driver_probe(&d40_driver, d40_probe);
3011}
3012arch_initcall(stedma40_init);
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