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dmaengine: dw: convert to use SET_LATE_SYSTEM_SLEEP_PM_OPS
[mirror_ubuntu-bionic-kernel.git] / drivers / dma / ste_dma40.c
CommitLineData
8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
b7f080cf 9#include <linux/dma-mapping.h>
8d318a50
LW		 10#include <linux/kernel.h>
11#include <linux/slab.h>
f492b210 12#include <linux/export.h>
8d318a50
LW		 13#include <linux/dmaengine.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
c95905a6 17#include <linux/log2.h>
7fb3e75e
N		 18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
698e4732 20#include <linux/err.h>
1814a170 21#include <linux/of.h>
fa332de5 22#include <linux/of_dma.h>
f4b89764 23#include <linux/amba/bus.h>
15e4b78d 24#include <linux/regulator/consumer.h>
865fab60 25#include <linux/platform_data/dma-ste-dma40.h>
8d318a50 26
d2ebfb33 27#include "dmaengine.h"
8d318a50
LW		 28#include "ste_dma40_ll.h"
29
30#define D40_NAME "dma40"
31
32#define D40_PHY_CHAN -1
33
34/* For masking out/in 2 bit channel positions */
35#define D40_CHAN_POS(chan) (2 * (chan / 2))
36#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
37
38/* Maximum iterations taken before giving up suspending a channel */
39#define D40_SUSPEND_MAX_IT 500
40
7fb3e75e
N		 41/* Milliseconds */
42#define DMA40_AUTOSUSPEND_DELAY 100
43
508849ad
LW		 44/* Hardware requirement on LCLA alignment */
45#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 46
47/* Max number of links per event group */
48#define D40_LCLA_LINK_PER_EVENT_GRP 128
49#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
50
db72da92
LJ		 51/* Max number of logical channels per physical channel */
52#define D40_MAX_LOG_CHAN_PER_PHY 32
53
508849ad
LW		 54/* Attempts before giving up to trying to get pages that are aligned */
55#define MAX_LCLA_ALLOC_ATTEMPTS 256
56
57/* Bit markings for allocation map */
8a3b6e14
LJ		 58#define D40_ALLOC_FREE BIT(31)
59#define D40_ALLOC_PHY BIT(30)
8d318a50
LW		 60#define D40_ALLOC_LOG_FREE 0
61
a7dacb68
LJ		 62#define D40_MEMCPY_MAX_CHANS 8
63
664a57ec 64/* Reserved event lines for memcpy only. */
a2acaa21
LW		 65#define DB8500_DMA_MEMCPY_EV_0 51
66#define DB8500_DMA_MEMCPY_EV_1 56
67#define DB8500_DMA_MEMCPY_EV_2 57
68#define DB8500_DMA_MEMCPY_EV_3 58
69#define DB8500_DMA_MEMCPY_EV_4 59
70#define DB8500_DMA_MEMCPY_EV_5 60
71
72static int dma40_memcpy_channels[] = {
73 DB8500_DMA_MEMCPY_EV_0,
74 DB8500_DMA_MEMCPY_EV_1,
75 DB8500_DMA_MEMCPY_EV_2,
76 DB8500_DMA_MEMCPY_EV_3,
77 DB8500_DMA_MEMCPY_EV_4,
78 DB8500_DMA_MEMCPY_EV_5,
79};
664a57ec 80
29027a1e 81/* Default configuration for physcial memcpy */
b4a1ccdf 82static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
29027a1e 83 .mode = STEDMA40_MODE_PHYSICAL,
2c2b62d5 84 .dir = DMA_MEM_TO_MEM,
29027a1e 85
43f2e1a3 86 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 87 .src_info.psize = STEDMA40_PSIZE_PHY_1,
88 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
89
43f2e1a3 90 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 91 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
92 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
93};
94
95/* Default configuration for logical memcpy */
b4a1ccdf 96static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
29027a1e 97 .mode = STEDMA40_MODE_LOGICAL,
2c2b62d5 98 .dir = DMA_MEM_TO_MEM,
29027a1e 99
43f2e1a3 100 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 101 .src_info.psize = STEDMA40_PSIZE_LOG_1,
102 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
103
43f2e1a3 104 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 105 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
106 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
107};
108
8d318a50
LW		 109/**
110 * enum 40_command - The different commands and/or statuses.
111 *
112 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
113 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
114 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
115 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
116 */
117enum d40_command {
118 D40_DMA_STOP = 0,
119 D40_DMA_RUN = 1,
120 D40_DMA_SUSPEND_REQ = 2,
121 D40_DMA_SUSPENDED = 3
122};
123
1bdae6f4
N		 124/*
125 * enum d40_events - The different Event Enables for the event lines.
126 *
127 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
128 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
129 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
130 * @D40_ROUND_EVENTLINE: Status check for event line.
131 */
132
133enum d40_events {
134 D40_DEACTIVATE_EVENTLINE = 0,
135 D40_ACTIVATE_EVENTLINE = 1,
136 D40_SUSPEND_REQ_EVENTLINE = 2,
137 D40_ROUND_EVENTLINE = 3
138};
139
7fb3e75e
N		 140/*
141 * These are the registers that has to be saved and later restored
142 * when the DMA hw is powered off.
143 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
144 */
145static u32 d40_backup_regs[] = {
146 D40_DREG_LCPA,
147 D40_DREG_LCLA,
148 D40_DREG_PRMSE,
149 D40_DREG_PRMSO,
150 D40_DREG_PRMOE,
151 D40_DREG_PRMOO,
152};
153
154#define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
155
3cb645dc
TL		 156/*
157 * since 9540 and 8540 has the same HW revision
158 * use v4a for 9540 or ealier
159 * use v4b for 8540 or later
160 * HW revision:
161 * DB8500ed has revision 0
162 * DB8500v1 has revision 2
163 * DB8500v2 has revision 3
164 * AP9540v1 has revision 4
165 * DB8540v1 has revision 4
166 * TODO: Check if all these registers have to be saved/restored on dma40 v4a
167 */
168static u32 d40_backup_regs_v4a[] = {
7fb3e75e
N		 169 D40_DREG_PSEG1,
170 D40_DREG_PSEG2,
171 D40_DREG_PSEG3,
172 D40_DREG_PSEG4,
173 D40_DREG_PCEG1,
174 D40_DREG_PCEG2,
175 D40_DREG_PCEG3,
176 D40_DREG_PCEG4,
177 D40_DREG_RSEG1,
178 D40_DREG_RSEG2,
179 D40_DREG_RSEG3,
180 D40_DREG_RSEG4,
181 D40_DREG_RCEG1,
182 D40_DREG_RCEG2,
183 D40_DREG_RCEG3,
184 D40_DREG_RCEG4,
185};
186
3cb645dc
TL		 187#define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
188
189static u32 d40_backup_regs_v4b[] = {
190 D40_DREG_CPSEG1,
191 D40_DREG_CPSEG2,
192 D40_DREG_CPSEG3,
193 D40_DREG_CPSEG4,
194 D40_DREG_CPSEG5,
195 D40_DREG_CPCEG1,
196 D40_DREG_CPCEG2,
197 D40_DREG_CPCEG3,
198 D40_DREG_CPCEG4,
199 D40_DREG_CPCEG5,
200 D40_DREG_CRSEG1,
201 D40_DREG_CRSEG2,
202 D40_DREG_CRSEG3,
203 D40_DREG_CRSEG4,
204 D40_DREG_CRSEG5,
205 D40_DREG_CRCEG1,
206 D40_DREG_CRCEG2,
207 D40_DREG_CRCEG3,
208 D40_DREG_CRCEG4,
209 D40_DREG_CRCEG5,
210};
211
212#define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
7fb3e75e
N		 213
214static u32 d40_backup_regs_chan[] = {
215 D40_CHAN_REG_SSCFG,
216 D40_CHAN_REG_SSELT,
217 D40_CHAN_REG_SSPTR,
218 D40_CHAN_REG_SSLNK,
219 D40_CHAN_REG_SDCFG,
220 D40_CHAN_REG_SDELT,
221 D40_CHAN_REG_SDPTR,
222 D40_CHAN_REG_SDLNK,
223};
224
84b3da14
LJ		 225#define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
226 BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
227
3cb645dc
TL		 228/**
229 * struct d40_interrupt_lookup - lookup table for interrupt handler
230 *
231 * @src: Interrupt mask register.
232 * @clr: Interrupt clear register.
233 * @is_error: true if this is an error interrupt.
234 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
235 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
236 */
237struct d40_interrupt_lookup {
238 u32 src;
239 u32 clr;
240 bool is_error;
241 int offset;
242};
243
244
245static struct d40_interrupt_lookup il_v4a[] = {
246 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
247 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
248 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
249 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
250 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
251 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
252 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
253 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
254 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
255 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
256};
257
258static struct d40_interrupt_lookup il_v4b[] = {
259 {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0},
260 {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
261 {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
262 {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
263 {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
264 {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0},
265 {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32},
266 {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64},
267 {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96},
268 {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128},
269 {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN},
270 {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN},
271};
272
273/**
274 * struct d40_reg_val - simple lookup struct
275 *
276 * @reg: The register.
277 * @val: The value that belongs to the register in reg.
278 */
279struct d40_reg_val {
280 unsigned int reg;
281 unsigned int val;
282};
283
284static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
285 /* Clock every part of the DMA block from start */
286 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
287
288 /* Interrupts on all logical channels */
289 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
290 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
291 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
292 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
293 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
294 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
295 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
296 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
297 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
298 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
299 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
300 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
301};
302static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
303 /* Clock every part of the DMA block from start */
304 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
305
306 /* Interrupts on all logical channels */
307 { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
308 { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
309 { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
310 { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
311 { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
312 { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
313 { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
314 { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
315 { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
316 { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
317 { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
318 { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
319 { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
320 { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
321 { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
322};
323
8d318a50
LW		 324/**
325 * struct d40_lli_pool - Structure for keeping LLIs in memory
326 *
327 * @base: Pointer to memory area when the pre_alloc_lli's are not large
328 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
329 * pre_alloc_lli is used.
b00f938c 330 * @dma_addr: DMA address, if mapped
8d318a50
LW		 331 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
332 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
333 * one buffer to one buffer.
334 */
335struct d40_lli_pool {
336 void *base;
508849ad 337 int size;
b00f938c 338 dma_addr_t dma_addr;
8d318a50 339 /* Space for dst and src, plus an extra for padding */
508849ad 340 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 341};
342
343/**
344 * struct d40_desc - A descriptor is one DMA job.
345 *
346 * @lli_phy: LLI settings for physical channel. Both src and dst=
347 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
348 * lli_len equals one.
349 * @lli_log: Same as above but for logical channels.
350 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 351 * @lli_len: Number of llis of current descriptor.
25985edc 352 * @lli_current: Number of transferred llis.
698e4732 353 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 354 * @txd: DMA engine struct. Used for among other things for communication
355 * during a transfer.
356 * @node: List entry.
8d318a50 357 * @is_in_client_list: true if the client owns this descriptor.
7fb3e75e 358 * @cyclic: true if this is a cyclic job
8d318a50
LW		 359 *
360 * This descriptor is used for both logical and physical transfers.
361 */
8d318a50
LW		 362struct d40_desc {
363 /* LLI physical */
364 struct d40_phy_lli_bidir lli_phy;
365 /* LLI logical */
366 struct d40_log_lli_bidir lli_log;
367
368 struct d40_lli_pool lli_pool;
941b77a3 369 int lli_len;
698e4732
JA		 370 int lli_current;
371 int lcla_alloc;
8d318a50
LW		 372
373 struct dma_async_tx_descriptor txd;
374 struct list_head node;
375
8d318a50 376 bool is_in_client_list;
0c842b55 377 bool cyclic;
8d318a50
LW		 378};
379
380/**
381 * struct d40_lcla_pool - LCLA pool settings and data.
382 *
508849ad
LW		 383 * @base: The virtual address of LCLA. 18 bit aligned.
384 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
385 * This pointer is only there for clean-up on error.
386 * @pages: The number of pages needed for all physical channels.
387 * Only used later for clean-up on error
8d318a50 388 * @lock: Lock to protect the content in this struct.
698e4732 389 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 390 */
391struct d40_lcla_pool {
392 void *base;
026cbc42 393 dma_addr_t dma_addr;
508849ad
LW		 394 void *base_unaligned;
395 int pages;
8d318a50 396 spinlock_t lock;
698e4732 397 struct d40_desc **alloc_map;
8d318a50
LW		 398};
399
400/**
401 * struct d40_phy_res - struct for handling eventlines mapped to physical
402 * channels.
403 *
404 * @lock: A lock protection this entity.
7fb3e75e 405 * @reserved: True if used by secure world or otherwise.
8d318a50
LW		 406 * @num: The physical channel number of this entity.
407 * @allocated_src: Bit mapped to show which src event line's are mapped to
408 * this physical channel. Can also be free or physically allocated.
409 * @allocated_dst: Same as for src but is dst.
410 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 411 * event line number.
7407048b 412 * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
8d318a50
LW		 413 */
414struct d40_phy_res {
415 spinlock_t lock;
7fb3e75e 416 bool reserved;
8d318a50
LW		 417 int num;
418 u32 allocated_src;
419 u32 allocated_dst;
7407048b 420 bool use_soft_lli;
8d318a50
LW		 421};
422
423struct d40_base;
424
425/**
426 * struct d40_chan - Struct that describes a channel.
427 *
428 * @lock: A spinlock to protect this struct.
429 * @log_num: The logical number, if any of this channel.
8d318a50
LW		 430 * @pending_tx: The number of pending transfers. Used between interrupt handler
431 * and tasklet.
432 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 433 * @phy_chan: Pointer to physical channel which this instance runs on. If this
434 * point is NULL, then the channel is not allocated.
8d318a50
LW		 435 * @chan: DMA engine handle.
436 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
437 * transfer and call client callback.
438 * @client: Cliented owned descriptor list.
da063d26 439 * @pending_queue: Submitted jobs, to be issued by issue_pending()
8d318a50 440 * @active: Active descriptor.
4226dd86 441 * @done: Completed jobs
8d318a50 442 * @queue: Queued jobs.
82babbb3 443 * @prepare_queue: Prepared jobs.
8d318a50 444 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 445 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 446 * @base: Pointer to the device instance struct.
447 * @src_def_cfg: Default cfg register setting for src.
448 * @dst_def_cfg: Default cfg register setting for dst.
449 * @log_def: Default logical channel settings.
8d318a50 450 * @lcpa: Pointer to dst and src lcpa settings.
ae752bf4 451 * @runtime_addr: runtime configured address.
452 * @runtime_direction: runtime configured direction.
8d318a50
LW		 453 *
454 * This struct can either "be" a logical or a physical channel.
455 */
456struct d40_chan {
457 spinlock_t lock;
458 int log_num;
8d318a50
LW		 459 int pending_tx;
460 bool busy;
461 struct d40_phy_res *phy_chan;
462 struct dma_chan chan;
463 struct tasklet_struct tasklet;
464 struct list_head client;
a8f3067b 465 struct list_head pending_queue;
8d318a50 466 struct list_head active;
4226dd86 467 struct list_head done;
8d318a50 468 struct list_head queue;
82babbb3 469 struct list_head prepare_queue;
8d318a50 470 struct stedma40_chan_cfg dma_cfg;
ce2ca125 471 bool configured;
8d318a50
LW		 472 struct d40_base *base;
473 /* Default register configurations */
474 u32 src_def_cfg;
475 u32 dst_def_cfg;
476 struct d40_def_lcsp log_def;
8d318a50 477 struct d40_log_lli_full *lcpa;
95e1400f
LW		 478 /* Runtime reconfiguration */
479 dma_addr_t runtime_addr;
db8196df 480 enum dma_transfer_direction runtime_direction;
8d318a50
LW		 481};
482
3cb645dc
TL		 483/**
484 * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
485 * controller
486 *
487 * @backup: the pointer to the registers address array for backup
488 * @backup_size: the size of the registers address array for backup
489 * @realtime_en: the realtime enable register
490 * @realtime_clear: the realtime clear register
491 * @high_prio_en: the high priority enable register
492 * @high_prio_clear: the high priority clear register
493 * @interrupt_en: the interrupt enable register
494 * @interrupt_clear: the interrupt clear register
495 * @il: the pointer to struct d40_interrupt_lookup
496 * @il_size: the size of d40_interrupt_lookup array
497 * @init_reg: the pointer to the struct d40_reg_val
498 * @init_reg_size: the size of d40_reg_val array
499 */
500struct d40_gen_dmac {
501 u32 *backup;
502 u32 backup_size;
503 u32 realtime_en;
504 u32 realtime_clear;
505 u32 high_prio_en;
506 u32 high_prio_clear;
507 u32 interrupt_en;
508 u32 interrupt_clear;
509 struct d40_interrupt_lookup *il;
510 u32 il_size;
511 struct d40_reg_val *init_reg;
512 u32 init_reg_size;
513};
514
8d318a50
LW		 515/**
516 * struct d40_base - The big global struct, one for each probe'd instance.
517 *
518 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
519 * @execmd_lock: Lock for execute command usage since several channels share
520 * the same physical register.
521 * @dev: The device structure.
522 * @virtbase: The virtual base address of the DMA's register.
f4185592 523 * @rev: silicon revision detected.
8d318a50
LW		 524 * @clk: Pointer to the DMA clock structure.
525 * @phy_start: Physical memory start of the DMA registers.
526 * @phy_size: Size of the DMA register map.
527 * @irq: The IRQ number.
a7dacb68
LJ		 528 * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
529 * transfers).
8d318a50
LW		 530 * @num_phy_chans: The number of physical channels. Read from HW. This
531 * is the number of available channels for this driver, not counting "Secure
532 * mode" allocated physical channels.
533 * @num_log_chans: The number of logical channels. Calculated from
534 * num_phy_chans.
535 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
536 * @dma_slave: dma_device channels that can do only do slave transfers.
537 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
7fb3e75e 538 * @phy_chans: Room for all possible physical channels in system.
8d318a50
LW		 539 * @log_chans: Room for all possible logical channels in system.
540 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
541 * to log_chans entries.
542 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
543 * to phy_chans entries.
544 * @plat_data: Pointer to provided platform_data which is the driver
545 * configuration.
28c7a19d 546 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
8d318a50
LW		 547 * @phy_res: Vector containing all physical channels.
548 * @lcla_pool: lcla pool settings and data.
549 * @lcpa_base: The virtual mapped address of LCPA.
550 * @phy_lcpa: The physical address of the LCPA.
551 * @lcpa_size: The size of the LCPA area.
c675b1b4 552 * @desc_slab: cache for descriptors.
7fb3e75e
N		 553 * @reg_val_backup: Here the values of some hardware registers are stored
554 * before the DMA is powered off. They are restored when the power is back on.
3cb645dc
TL		 555 * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
556 * later
7fb3e75e
N		 557 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
558 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
559 * @initialized: true if the dma has been initialized
3cb645dc
TL		 560 * @gen_dmac: the struct for generic registers values to represent u8500/8540
561 * DMA controller
8d318a50
LW		 562 */
563struct d40_base {
564 spinlock_t interrupt_lock;
565 spinlock_t execmd_lock;
566 struct device *dev;
567 void __iomem *virtbase;
f4185592 568 u8 rev:4;
8d318a50
LW		 569 struct clk *clk;
570 phys_addr_t phy_start;
571 resource_size_t phy_size;
572 int irq;
a7dacb68 573 int num_memcpy_chans;
8d318a50
LW		 574 int num_phy_chans;
575 int num_log_chans;
b96710e5 576 struct device_dma_parameters dma_parms;
8d318a50
LW		 577 struct dma_device dma_both;
578 struct dma_device dma_slave;
579 struct dma_device dma_memcpy;
580 struct d40_chan *phy_chans;
581 struct d40_chan *log_chans;
582 struct d40_chan **lookup_log_chans;
583 struct d40_chan **lookup_phy_chans;
584 struct stedma40_platform_data *plat_data;
28c7a19d 585 struct regulator *lcpa_regulator;
8d318a50
LW		 586 /* Physical half channels */
587 struct d40_phy_res *phy_res;
588 struct d40_lcla_pool lcla_pool;
589 void *lcpa_base;
590 dma_addr_t phy_lcpa;
591 resource_size_t lcpa_size;
c675b1b4 592 struct kmem_cache *desc_slab;
7fb3e75e 593 u32 reg_val_backup[BACKUP_REGS_SZ];
84b3da14 594 u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
7fb3e75e
N		 595 u32 *reg_val_backup_chan;
596 u16 gcc_pwr_off_mask;
597 bool initialized;
3cb645dc 598 struct d40_gen_dmac gen_dmac;
8d318a50
LW		 599};
600
262d2915
RV		 601static struct device *chan2dev(struct d40_chan *d40c)
602{
603 return &d40c->chan.dev->device;
604}
605
724a8577
RV		 606static bool chan_is_physical(struct d40_chan *chan)
607{
608 return chan->log_num == D40_PHY_CHAN;
609}
610
611static bool chan_is_logical(struct d40_chan *chan)
612{
613 return !chan_is_physical(chan);
614}
615
8ca84687
RV		 616static void __iomem *chan_base(struct d40_chan *chan)
617{
618 return chan->base->virtbase + D40_DREG_PCBASE +
619 chan->phy_chan->num * D40_DREG_PCDELTA;
620}
621
6db5a8ba
RV		 622#define d40_err(dev, format, arg...) \
623 dev_err(dev, "[%s] " format, __func__, ## arg)
624
625#define chan_err(d40c, format, arg...) \
626 d40_err(chan2dev(d40c), format, ## arg)
627
b00f938c 628static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
dbd88788 629 int lli_len)
8d318a50 630{
dbd88788 631 bool is_log = chan_is_logical(d40c);
8d318a50
LW		 632 u32 align;
633 void *base;
634
635 if (is_log)
636 align = sizeof(struct d40_log_lli);
637 else
638 align = sizeof(struct d40_phy_lli);
639
640 if (lli_len == 1) {
641 base = d40d->lli_pool.pre_alloc_lli;
642 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
643 d40d->lli_pool.base = NULL;
644 } else {
594ece4d 645 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 646
647 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
648 d40d->lli_pool.base = base;
649
650 if (d40d->lli_pool.base == NULL)
651 return -ENOMEM;
652 }
653
654 if (is_log) {
d924abad 655 d40d->lli_log.src = PTR_ALIGN(base, align);
594ece4d 656 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 657
658 d40d->lli_pool.dma_addr = 0;
8d318a50 659 } else {
d924abad 660 d40d->lli_phy.src = PTR_ALIGN(base, align);
594ece4d 661 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 662
663 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
664 d40d->lli_phy.src,
665 d40d->lli_pool.size,
666 DMA_TO_DEVICE);
667
668 if (dma_mapping_error(d40c->base->dev,
669 d40d->lli_pool.dma_addr)) {
670 kfree(d40d->lli_pool.base);
671 d40d->lli_pool.base = NULL;
672 d40d->lli_pool.dma_addr = 0;
673 return -ENOMEM;
674 }
8d318a50
LW		 675 }
676
677 return 0;
678}
679
b00f938c 680static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 681{
b00f938c
RV		 682 if (d40d->lli_pool.dma_addr)
683 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
684 d40d->lli_pool.size, DMA_TO_DEVICE);
685
8d318a50
LW		 686 kfree(d40d->lli_pool.base);
687 d40d->lli_pool.base = NULL;
688 d40d->lli_pool.size = 0;
689 d40d->lli_log.src = NULL;
690 d40d->lli_log.dst = NULL;
691 d40d->lli_phy.src = NULL;
692 d40d->lli_phy.dst = NULL;
8d318a50
LW		 693}
694
698e4732
JA		 695static int d40_lcla_alloc_one(struct d40_chan *d40c,
696 struct d40_desc *d40d)
697{
698 unsigned long flags;
699 int i;
700 int ret = -EINVAL;
698e4732
JA		 701
702 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
703
698e4732
JA		 704 /*
705 * Allocate both src and dst at the same time, therefore the half
706 * start on 1 since 0 can't be used since zero is used as end marker.
707 */
708 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
7ce529ef
FB		 709 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
710
711 if (!d40c->base->lcla_pool.alloc_map[idx]) {
712 d40c->base->lcla_pool.alloc_map[idx] = d40d;
698e4732
JA		 713 d40d->lcla_alloc++;
714 ret = i;
715 break;
716 }
717 }
718
719 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
720
721 return ret;
722}
723
724static int d40_lcla_free_all(struct d40_chan *d40c,
725 struct d40_desc *d40d)
726{
727 unsigned long flags;
728 int i;
729 int ret = -EINVAL;
730
724a8577 731 if (chan_is_physical(d40c))
698e4732
JA		 732 return 0;
733
734 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
735
736 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
7ce529ef
FB		 737 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
738
739 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
740 d40c->base->lcla_pool.alloc_map[idx] = NULL;
698e4732
JA		 741 d40d->lcla_alloc--;
742 if (d40d->lcla_alloc == 0) {
743 ret = 0;
744 break;
745 }
746 }
747 }
748
749 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
750
751 return ret;
752
753}
754
8d318a50
LW		 755static void d40_desc_remove(struct d40_desc *d40d)
756{
757 list_del(&d40d->node);
758}
759
760static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
761{
a2c15fa4 762 struct d40_desc *desc = NULL;
8d318a50
LW		 763
764 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 765 struct d40_desc *d;
766 struct d40_desc *_d;
767
7fb3e75e 768 list_for_each_entry_safe(d, _d, &d40c->client, node) {
8d318a50 769 if (async_tx_test_ack(&d->txd)) {
8d318a50 770 d40_desc_remove(d);
a2c15fa4
RV		 771 desc = d;
772 memset(desc, 0, sizeof(*desc));
c675b1b4 773 break;
8d318a50 774 }
7fb3e75e 775 }
8d318a50 776 }
a2c15fa4
RV		 777
778 if (!desc)
779 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
780
781 if (desc)
782 INIT_LIST_HEAD(&desc->node);
783
784 return desc;
8d318a50
LW		 785}
786
787static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
788{
698e4732 789
b00f938c 790 d40_pool_lli_free(d40c, d40d);
698e4732 791 d40_lcla_free_all(d40c, d40d);
c675b1b4 792 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 793}
794
795static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
796{
797 list_add_tail(&desc->node, &d40c->active);
798}
799
1c4b0927
RV		 800static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
801{
802 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
803 struct d40_phy_lli *lli_src = desc->lli_phy.src;
804 void __iomem *base = chan_base(chan);
805
806 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
807 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
808 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
809 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
810
811 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
812 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
813 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
814 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
815}
816
4226dd86
FB		 817static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
818{
819 list_add_tail(&desc->node, &d40c->done);
820}
821
e65889c7 822static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
698e4732 823{
e65889c7
RV		 824 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
825 struct d40_log_lli_bidir *lli = &desc->lli_log;
826 int lli_current = desc->lli_current;
827 int lli_len = desc->lli_len;
0c842b55 828 bool cyclic = desc->cyclic;
e65889c7 829 int curr_lcla = -EINVAL;
0c842b55 830 int first_lcla = 0;
28c7a19d 831 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
0c842b55 832 bool linkback;
e65889c7 833
0c842b55
RV		 834 /*
835 * We may have partially running cyclic transfers, in case we did't get
836 * enough LCLA entries.
837 */
838 linkback = cyclic && lli_current == 0;
839
840 /*
841 * For linkback, we need one LCLA even with only one link, because we
842 * can't link back to the one in LCPA space
843 */
844 if (linkback || (lli_len - lli_current > 1)) {
7407048b
FB		 845 /*
846 * If the channel is expected to use only soft_lli don't
847 * allocate a lcla. This is to avoid a HW issue that exists
848 * in some controller during a peripheral to memory transfer
849 * that uses linked lists.
850 */
851 if (!(chan->phy_chan->use_soft_lli &&
2c2b62d5 852 chan->dma_cfg.dir == DMA_DEV_TO_MEM))
7407048b
FB		 853 curr_lcla = d40_lcla_alloc_one(chan, desc);
854
0c842b55
RV		 855 first_lcla = curr_lcla;
856 }
857
858 /*
859 * For linkback, we normally load the LCPA in the loop since we need to
860 * link it to the second LCLA and not the first. However, if we
861 * couldn't even get a first LCLA, then we have to run in LCPA and
862 * reload manually.
863 */
864 if (!linkback || curr_lcla == -EINVAL) {
865 unsigned int flags = 0;
e65889c7 866
0c842b55
RV		 867 if (curr_lcla == -EINVAL)
868 flags |= LLI_TERM_INT;
e65889c7 869
0c842b55
RV		 870 d40_log_lli_lcpa_write(chan->lcpa,
871 &lli->dst[lli_current],
872 &lli->src[lli_current],
873 curr_lcla,
874 flags);
875 lli_current++;
876 }
6045f0bb
RV		 877
878 if (curr_lcla < 0)
879 goto out;
880
e65889c7
RV		 881 for (; lli_current < lli_len; lli_current++) {
882 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
883 8 * curr_lcla * 2;
884 struct d40_log_lli *lcla = pool->base + lcla_offset;
0c842b55 885 unsigned int flags = 0;
e65889c7
RV		 886 int next_lcla;
887
888 if (lli_current + 1 < lli_len)
889 next_lcla = d40_lcla_alloc_one(chan, desc);
890 else
0c842b55
RV		 891 next_lcla = linkback ? first_lcla : -EINVAL;
892
893 if (cyclic || next_lcla == -EINVAL)
894 flags |= LLI_TERM_INT;
e65889c7 895
0c842b55
RV		 896 if (linkback && curr_lcla == first_lcla) {
897 /* First link goes in both LCPA and LCLA */
898 d40_log_lli_lcpa_write(chan->lcpa,
899 &lli->dst[lli_current],
900 &lli->src[lli_current],
901 next_lcla, flags);
902 }
903
904 /*
905 * One unused LCLA in the cyclic case if the very first
906 * next_lcla fails...
907 */
e65889c7
RV		 908 d40_log_lli_lcla_write(lcla,
909 &lli->dst[lli_current],
910 &lli->src[lli_current],
0c842b55 911 next_lcla, flags);
e65889c7 912
28c7a19d
N		 913 /*
914 * Cache maintenance is not needed if lcla is
915 * mapped in esram
916 */
917 if (!use_esram_lcla) {
918 dma_sync_single_range_for_device(chan->base->dev,
919 pool->dma_addr, lcla_offset,
920 2 * sizeof(struct d40_log_lli),
921 DMA_TO_DEVICE);
922 }
e65889c7
RV		 923 curr_lcla = next_lcla;
924
0c842b55 925 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
e65889c7
RV		 926 lli_current++;
927 break;
928 }
929 }
930
6045f0bb 931out:
e65889c7
RV		 932 desc->lli_current = lli_current;
933}
698e4732 934
e65889c7
RV		 935static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
936{
724a8577 937 if (chan_is_physical(d40c)) {
1c4b0927 938 d40_phy_lli_load(d40c, d40d);
698e4732 939 d40d->lli_current = d40d->lli_len;
e65889c7
RV		 940 } else
941 d40_log_lli_to_lcxa(d40c, d40d);
698e4732
JA		 942}
943
8d318a50
LW		 944static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
945{
946 struct d40_desc *d;
947
948 if (list_empty(&d40c->active))
949 return NULL;
950
951 d = list_first_entry(&d40c->active,
952 struct d40_desc,
953 node);
954 return d;
955}
956
7404368c 957/* remove desc from current queue and add it to the pending_queue */
8d318a50
LW		 958static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
959{
7404368c
PF		 960 d40_desc_remove(desc);
961 desc->is_in_client_list = false;
a8f3067b
PF		 962 list_add_tail(&desc->node, &d40c->pending_queue);
963}
964
965static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
966{
967 struct d40_desc *d;
968
969 if (list_empty(&d40c->pending_queue))
970 return NULL;
971
972 d = list_first_entry(&d40c->pending_queue,
973 struct d40_desc,
974 node);
975 return d;
8d318a50
LW		 976}
977
978static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
979{
980 struct d40_desc *d;
981
982 if (list_empty(&d40c->queue))
983 return NULL;
984
985 d = list_first_entry(&d40c->queue,
986 struct d40_desc,
987 node);
988 return d;
989}
990
4226dd86
FB		 991static struct d40_desc *d40_first_done(struct d40_chan *d40c)
992{
993 if (list_empty(&d40c->done))
994 return NULL;
995
996 return list_first_entry(&d40c->done, struct d40_desc, node);
997}
998
d49278e3
PF		 999static int d40_psize_2_burst_size(bool is_log, int psize)
1000{
1001 if (is_log) {
1002 if (psize == STEDMA40_PSIZE_LOG_1)
1003 return 1;
1004 } else {
1005 if (psize == STEDMA40_PSIZE_PHY_1)
1006 return 1;
1007 }
1008
1009 return 2 << psize;
1010}
1011
1012/*
1013 * The dma only supports transmitting packages up to
43f2e1a3
LJ		 1014 * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
1015 *
1016 * Calculate the total number of dma elements required to send the entire sg list.
d49278e3
PF		 1017 */
1018static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
1019{
1020 int dmalen;
1021 u32 max_w = max(data_width1, data_width2);
1022 u32 min_w = min(data_width1, data_width2);
43f2e1a3 1023 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
d49278e3
PF		 1024
1025 if (seg_max > STEDMA40_MAX_SEG_SIZE)
43f2e1a3 1026 seg_max -= max_w;
d49278e3 1027
43f2e1a3 1028 if (!IS_ALIGNED(size, max_w))
d49278e3
PF		 1029 return -EINVAL;
1030
1031 if (size <= seg_max)
1032 dmalen = 1;
1033 else {
1034 dmalen = size / seg_max;
1035 if (dmalen * seg_max < size)
1036 dmalen++;
1037 }
1038 return dmalen;
1039}
1040
1041static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
1042 u32 data_width1, u32 data_width2)
1043{
1044 struct scatterlist *sg;
1045 int i;
1046 int len = 0;
1047 int ret;
1048
1049 for_each_sg(sgl, sg, sg_len, i) {
1050 ret = d40_size_2_dmalen(sg_dma_len(sg),
1051 data_width1, data_width2);
1052 if (ret < 0)
1053 return ret;
1054 len += ret;
1055 }
1056 return len;
1057}
8d318a50 1058
7fb3e75e
N		 1059
1060#ifdef CONFIG_PM
1061static void dma40_backup(void __iomem *baseaddr, u32 *backup,
1062 u32 *regaddr, int num, bool save)
1063{
1064 int i;
1065
1066 for (i = 0; i < num; i++) {
1067 void __iomem *addr = baseaddr + regaddr[i];
1068
1069 if (save)
1070 backup[i] = readl_relaxed(addr);
1071 else
1072 writel_relaxed(backup[i], addr);
1073 }
1074}
1075
1076static void d40_save_restore_registers(struct d40_base *base, bool save)
1077{
1078 int i;
1079
1080 /* Save/Restore channel specific registers */
1081 for (i = 0; i < base->num_phy_chans; i++) {
1082 void __iomem *addr;
1083 int idx;
1084
1085 if (base->phy_res[i].reserved)
1086 continue;
1087
1088 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
1089 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
1090
1091 dma40_backup(addr, &base->reg_val_backup_chan[idx],
1092 d40_backup_regs_chan,
1093 ARRAY_SIZE(d40_backup_regs_chan),
1094 save);
1095 }
1096
1097 /* Save/Restore global registers */
1098 dma40_backup(base->virtbase, base->reg_val_backup,
1099 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
1100 save);
1101
1102 /* Save/Restore registers only existing on dma40 v3 and later */
3cb645dc
TL		 1103 if (base->gen_dmac.backup)
1104 dma40_backup(base->virtbase, base->reg_val_backup_v4,
1105 base->gen_dmac.backup,
1106 base->gen_dmac.backup_size,
1107 save);
7fb3e75e
N		 1108}
1109#else
1110static void d40_save_restore_registers(struct d40_base *base, bool save)
1111{
1112}
1113#endif
8d318a50 1114
1bdae6f4
N		 1115static int __d40_execute_command_phy(struct d40_chan *d40c,
1116 enum d40_command command)
8d318a50 1117{
767a9675
JA		 1118 u32 status;
1119 int i;
8d318a50
LW		 1120 void __iomem *active_reg;
1121 int ret = 0;
1122 unsigned long flags;
1d392a7b 1123 u32 wmask;
8d318a50 1124
1bdae6f4
N		 1125 if (command == D40_DMA_STOP) {
1126 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1127 if (ret)
1128 return ret;
1129 }
1130
8d318a50
LW		 1131 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1132
1133 if (d40c->phy_chan->num % 2 == 0)
1134 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1135 else
1136 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1137
1138 if (command == D40_DMA_SUSPEND_REQ) {
1139 status = (readl(active_reg) &
1140 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1141 D40_CHAN_POS(d40c->phy_chan->num);
1142
1143 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1144 goto done;
1145 }
1146
1d392a7b
JA		 1147 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1148 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1149 active_reg);
8d318a50
LW		 1150
1151 if (command == D40_DMA_SUSPEND_REQ) {
1152
1153 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1154 status = (readl(active_reg) &
1155 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1156 D40_CHAN_POS(d40c->phy_chan->num);
1157
1158 cpu_relax();
1159 /*
1160 * Reduce the number of bus accesses while
1161 * waiting for the DMA to suspend.
1162 */
1163 udelay(3);
1164
1165 if (status == D40_DMA_STOP ||
1166 status == D40_DMA_SUSPENDED)
1167 break;
1168 }
1169
1170 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 1171 chan_err(d40c,
1172 "unable to suspend the chl %d (log: %d) status %x\n",
1173 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 1174 status);
1175 dump_stack();
1176 ret = -EBUSY;
1177 }
1178
1179 }
1180done:
1181 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1182 return ret;
1183}
1184
1185static void d40_term_all(struct d40_chan *d40c)
1186{
1187 struct d40_desc *d40d;
7404368c 1188 struct d40_desc *_d;
8d318a50 1189
4226dd86
FB		 1190 /* Release completed descriptors */
1191 while ((d40d = d40_first_done(d40c))) {
1192 d40_desc_remove(d40d);
1193 d40_desc_free(d40c, d40d);
1194 }
1195
8d318a50
LW		 1196 /* Release active descriptors */
1197 while ((d40d = d40_first_active_get(d40c))) {
1198 d40_desc_remove(d40d);
8d318a50
LW		 1199 d40_desc_free(d40c, d40d);
1200 }
1201
1202 /* Release queued descriptors waiting for transfer */
1203 while ((d40d = d40_first_queued(d40c))) {
1204 d40_desc_remove(d40d);
8d318a50
LW		 1205 d40_desc_free(d40c, d40d);
1206 }
1207
a8f3067b
PF		 1208 /* Release pending descriptors */
1209 while ((d40d = d40_first_pending(d40c))) {
1210 d40_desc_remove(d40d);
1211 d40_desc_free(d40c, d40d);
1212 }
8d318a50 1213
7404368c
PF		 1214 /* Release client owned descriptors */
1215 if (!list_empty(&d40c->client))
1216 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1217 d40_desc_remove(d40d);
1218 d40_desc_free(d40c, d40d);
1219 }
1220
82babbb3
PF		 1221 /* Release descriptors in prepare queue */
1222 if (!list_empty(&d40c->prepare_queue))
1223 list_for_each_entry_safe(d40d, _d,
1224 &d40c->prepare_queue, node) {
1225 d40_desc_remove(d40d);
1226 d40_desc_free(d40c, d40d);
1227 }
7404368c 1228
8d318a50 1229 d40c->pending_tx = 0;
8d318a50
LW		 1230}
1231
1bdae6f4
N		 1232static void __d40_config_set_event(struct d40_chan *d40c,
1233 enum d40_events event_type, u32 event,
1234 int reg)
262d2915 1235{
8ca84687 1236 void __iomem *addr = chan_base(d40c) + reg;
262d2915 1237 int tries;
1bdae6f4
N		 1238 u32 status;
1239
1240 switch (event_type) {
1241
1242 case D40_DEACTIVATE_EVENTLINE:
262d2915 1243
262d2915
RV		 1244 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1245 | ~D40_EVENTLINE_MASK(event), addr);
1bdae6f4
N		 1246 break;
1247
1248 case D40_SUSPEND_REQ_EVENTLINE:
1249 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1250 D40_EVENTLINE_POS(event);
1251
1252 if (status == D40_DEACTIVATE_EVENTLINE ||
1253 status == D40_SUSPEND_REQ_EVENTLINE)
1254 break;
262d2915 1255
1bdae6f4
N		 1256 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1257 | ~D40_EVENTLINE_MASK(event), addr);
1258
1259 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1260
1261 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1262 D40_EVENTLINE_POS(event);
1263
1264 cpu_relax();
1265 /*
1266 * Reduce the number of bus accesses while
1267 * waiting for the DMA to suspend.
1268 */
1269 udelay(3);
1270
1271 if (status == D40_DEACTIVATE_EVENTLINE)
1272 break;
1273 }
1274
1275 if (tries == D40_SUSPEND_MAX_IT) {
1276 chan_err(d40c,
1277 "unable to stop the event_line chl %d (log: %d)"
1278 "status %x\n", d40c->phy_chan->num,
1279 d40c->log_num, status);
1280 }
1281 break;
1282
1283 case D40_ACTIVATE_EVENTLINE:
262d2915
RV		 1284 /*
1285 * The hardware sometimes doesn't register the enable when src and dst
1286 * event lines are active on the same logical channel. Retry to ensure
1287 * it does. Usually only one retry is sufficient.
1288 */
1bdae6f4
N		 1289 tries = 100;
1290 while (--tries) {
1291 writel((D40_ACTIVATE_EVENTLINE <<
1292 D40_EVENTLINE_POS(event)) |
1293 ~D40_EVENTLINE_MASK(event), addr);
262d2915 1294
1bdae6f4
N		 1295 if (readl(addr) & D40_EVENTLINE_MASK(event))
1296 break;
1297 }
262d2915 1298
1bdae6f4
N		 1299 if (tries != 99)
1300 dev_dbg(chan2dev(d40c),
1301 "[%s] workaround enable S%cLNK (%d tries)\n",
1302 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1303 100 - tries);
262d2915 1304
1bdae6f4
N		 1305 WARN_ON(!tries);
1306 break;
262d2915 1307
1bdae6f4
N		 1308 case D40_ROUND_EVENTLINE:
1309 BUG();
1310 break;
8d318a50 1311
1bdae6f4
N		 1312 }
1313}
8d318a50 1314
1bdae6f4
N		 1315static void d40_config_set_event(struct d40_chan *d40c,
1316 enum d40_events event_type)
1317{
26955c07
LJ		 1318 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1319
8d318a50 1320 /* Enable event line connected to device (or memcpy) */
2c2b62d5
LJ		 1321 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1322 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1bdae6f4 1323 __d40_config_set_event(d40c, event_type, event,
262d2915 1324 D40_CHAN_REG_SSLNK);
8d318a50 1325
2c2b62d5 1326 if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM)
1bdae6f4 1327 __d40_config_set_event(d40c, event_type, event,
262d2915 1328 D40_CHAN_REG_SDLNK);
8d318a50
LW		 1329}
1330
a5ebca47 1331static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 1332{
8ca84687 1333 void __iomem *chanbase = chan_base(d40c);
be8cb7df 1334 u32 val;
8d318a50 1335
8ca84687
RV		 1336 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1337 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 1338
a5ebca47 1339 return val;
8d318a50
LW		 1340}
1341
1bdae6f4
N		 1342static int
1343__d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1344{
1345 unsigned long flags;
1346 int ret = 0;
1347 u32 active_status;
1348 void __iomem *active_reg;
1349
1350 if (d40c->phy_chan->num % 2 == 0)
1351 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1352 else
1353 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1354
1355
1356 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1357
1358 switch (command) {
1359 case D40_DMA_STOP:
1360 case D40_DMA_SUSPEND_REQ:
1361
1362 active_status = (readl(active_reg) &
1363 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1364 D40_CHAN_POS(d40c->phy_chan->num);
1365
1366 if (active_status == D40_DMA_RUN)
1367 d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1368 else
1369 d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1370
1371 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1372 ret = __d40_execute_command_phy(d40c, command);
1373
1374 break;
1375
1376 case D40_DMA_RUN:
1377
1378 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1379 ret = __d40_execute_command_phy(d40c, command);
1380 break;
1381
1382 case D40_DMA_SUSPENDED:
1383 BUG();
1384 break;
1385 }
1386
1387 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1388 return ret;
1389}
1390
1391static int d40_channel_execute_command(struct d40_chan *d40c,
1392 enum d40_command command)
1393{
1394 if (chan_is_logical(d40c))
1395 return __d40_execute_command_log(d40c, command);
1396 else
1397 return __d40_execute_command_phy(d40c, command);
1398}
1399
20a5b6d0
RV		 1400static u32 d40_get_prmo(struct d40_chan *d40c)
1401{
1402 static const unsigned int phy_map[] = {
1403 [STEDMA40_PCHAN_BASIC_MODE]
1404 = D40_DREG_PRMO_PCHAN_BASIC,
1405 [STEDMA40_PCHAN_MODULO_MODE]
1406 = D40_DREG_PRMO_PCHAN_MODULO,
1407 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1408 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1409 };
1410 static const unsigned int log_map[] = {
1411 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1412 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1413 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1414 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1415 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1416 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1417 };
1418
724a8577 1419 if (chan_is_physical(d40c))
20a5b6d0
RV		 1420 return phy_map[d40c->dma_cfg.mode_opt];
1421 else
1422 return log_map[d40c->dma_cfg.mode_opt];
1423}
1424
b55912c6 1425static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 1426{
1427 u32 addr_base;
1428 u32 var;
8d318a50
LW		 1429
1430 /* Odd addresses are even addresses + 4 */
1431 addr_base = (d40c->phy_chan->num % 2) * 4;
1432 /* Setup channel mode to logical or physical */
724a8577 1433 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 1434 D40_CHAN_POS(d40c->phy_chan->num);
1435 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1436
1437 /* Setup operational mode option register */
20a5b6d0 1438 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 1439
1440 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1441
724a8577 1442 if (chan_is_logical(d40c)) {
8ca84687
RV		 1443 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1444 & D40_SREG_ELEM_LOG_LIDX_MASK;
1445 void __iomem *chanbase = chan_base(d40c);
1446
8d318a50 1447 /* Set default config for CFG reg */
8ca84687
RV		 1448 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1449 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 1450
b55912c6 1451 /* Set LIDX for lcla */
8ca84687
RV		 1452 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1453 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
e9f3a49c
RV		 1454
1455 /* Clear LNK which will be used by d40_chan_has_events() */
1456 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1457 writel(0, chanbase + D40_CHAN_REG_SDLNK);
8d318a50 1458 }
8d318a50
LW		 1459}
1460
aa182ae2
JA		 1461static u32 d40_residue(struct d40_chan *d40c)
1462{
1463 u32 num_elt;
1464
724a8577 1465 if (chan_is_logical(d40c))
aa182ae2
JA		 1466 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1467 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 1468 else {
1469 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1470 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1471 >> D40_SREG_ELEM_PHY_ECNT_POS;
1472 }
1473
43f2e1a3 1474 return num_elt * d40c->dma_cfg.dst_info.data_width;
aa182ae2
JA		 1475}
1476
1477static bool d40_tx_is_linked(struct d40_chan *d40c)
1478{
1479 bool is_link;
1480
724a8577 1481 if (chan_is_logical(d40c))
aa182ae2
JA		 1482 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1483 else
8ca84687
RV		 1484 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1485 & D40_SREG_LNK_PHYS_LNK_MASK;
1486
aa182ae2
JA		 1487 return is_link;
1488}
1489
86eb5fb6 1490static int d40_pause(struct d40_chan *d40c)
aa182ae2 1491{
aa182ae2
JA		 1492 int res = 0;
1493 unsigned long flags;
1494
3ac012af
JA		 1495 if (!d40c->busy)
1496 return 0;
1497
7fb3e75e 1498 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1499 spin_lock_irqsave(&d40c->lock, flags);
1500
1501 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1bdae6f4 1502
7fb3e75e
N		 1503 pm_runtime_mark_last_busy(d40c->base->dev);
1504 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1505 spin_unlock_irqrestore(&d40c->lock, flags);
1506 return res;
1507}
1508
86eb5fb6 1509static int d40_resume(struct d40_chan *d40c)
aa182ae2 1510{
aa182ae2
JA		 1511 int res = 0;
1512 unsigned long flags;
1513
3ac012af
JA		 1514 if (!d40c->busy)
1515 return 0;
1516
aa182ae2 1517 spin_lock_irqsave(&d40c->lock, flags);
7fb3e75e 1518 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1519
1520 /* If bytes left to transfer or linked tx resume job */
1bdae6f4 1521 if (d40_residue(d40c) || d40_tx_is_linked(d40c))
aa182ae2 1522 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
aa182ae2 1523
7fb3e75e
N		 1524 pm_runtime_mark_last_busy(d40c->base->dev);
1525 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1526 spin_unlock_irqrestore(&d40c->lock, flags);
1527 return res;
1528}
1529
8d318a50
LW		 1530static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1531{
1532 struct d40_chan *d40c = container_of(tx->chan,
1533 struct d40_chan,
1534 chan);
1535 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1536 unsigned long flags;
884485e1 1537 dma_cookie_t cookie;
8d318a50
LW		 1538
1539 spin_lock_irqsave(&d40c->lock, flags);
884485e1 1540 cookie = dma_cookie_assign(tx);
8d318a50 1541 d40_desc_queue(d40c, d40d);
8d318a50
LW		 1542 spin_unlock_irqrestore(&d40c->lock, flags);
1543
884485e1 1544 return cookie;
8d318a50
LW		 1545}
1546
1547static int d40_start(struct d40_chan *d40c)
1548{
0c32269d 1549 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 1550}
1551
1552static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1553{
1554 struct d40_desc *d40d;
1555 int err;
1556
1557 /* Start queued jobs, if any */
1558 d40d = d40_first_queued(d40c);
1559
1560 if (d40d != NULL) {
1bdae6f4 1561 if (!d40c->busy) {
7fb3e75e 1562 d40c->busy = true;
1bdae6f4
N		 1563 pm_runtime_get_sync(d40c->base->dev);
1564 }
8d318a50
LW		 1565
1566 /* Remove from queue */
1567 d40_desc_remove(d40d);
1568
1569 /* Add to active queue */
1570 d40_desc_submit(d40c, d40d);
1571
7d83a854
RV		 1572 /* Initiate DMA job */
1573 d40_desc_load(d40c, d40d);
8d318a50 1574
7d83a854
RV		 1575 /* Start dma job */
1576 err = d40_start(d40c);
8d318a50 1577
7d83a854
RV		 1578 if (err)
1579 return NULL;
8d318a50
LW		 1580 }
1581
1582 return d40d;
1583}
1584
1585/* called from interrupt context */
1586static void dma_tc_handle(struct d40_chan *d40c)
1587{
1588 struct d40_desc *d40d;
1589
8d318a50
LW		 1590 /* Get first active entry from list */
1591 d40d = d40_first_active_get(d40c);
1592
1593 if (d40d == NULL)
1594 return;
1595
0c842b55
RV		 1596 if (d40d->cyclic) {
1597 /*
1598 * If this was a paritially loaded list, we need to reloaded
1599 * it, and only when the list is completed. We need to check
1600 * for done because the interrupt will hit for every link, and
1601 * not just the last one.
1602 */
1603 if (d40d->lli_current < d40d->lli_len
1604 && !d40_tx_is_linked(d40c)
1605 && !d40_residue(d40c)) {
1606 d40_lcla_free_all(d40c, d40d);
1607 d40_desc_load(d40c, d40d);
1608 (void) d40_start(d40c);
8d318a50 1609
0c842b55
RV		 1610 if (d40d->lli_current == d40d->lli_len)
1611 d40d->lli_current = 0;
1612 }
1613 } else {
1614 d40_lcla_free_all(d40c, d40d);
8d318a50 1615
0c842b55
RV		 1616 if (d40d->lli_current < d40d->lli_len) {
1617 d40_desc_load(d40c, d40d);
1618 /* Start dma job */
1619 (void) d40_start(d40c);
1620 return;
1621 }
1622
9ecb41bd 1623 if (d40_queue_start(d40c) == NULL) {
0c842b55 1624 d40c->busy = false;
9ecb41bd
RV		 1625
1626 pm_runtime_mark_last_busy(d40c->base->dev);
1627 pm_runtime_put_autosuspend(d40c->base->dev);
1628 }
8d318a50 1629
7dd14525
FB		 1630 d40_desc_remove(d40d);
1631 d40_desc_done(d40c, d40d);
1632 }
4226dd86 1633
8d318a50
LW		 1634 d40c->pending_tx++;
1635 tasklet_schedule(&d40c->tasklet);
1636
1637}
1638
1639static void dma_tasklet(unsigned long data)
1640{
1641 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1642 struct d40_desc *d40d;
8d318a50 1643 unsigned long flags;
e9baa9d9 1644 bool callback_active;
8d318a50
LW		 1645 dma_async_tx_callback callback;
1646 void *callback_param;
1647
1648 spin_lock_irqsave(&d40c->lock, flags);
1649
4226dd86
FB		 1650 /* Get first entry from the done list */
1651 d40d = d40_first_done(d40c);
1652 if (d40d == NULL) {
1653 /* Check if we have reached here for cyclic job */
1654 d40d = d40_first_active_get(d40c);
1655 if (d40d == NULL || !d40d->cyclic)
1656 goto err;
1657 }
8d318a50 1658
0c842b55 1659 if (!d40d->cyclic)
f7fbce07 1660 dma_cookie_complete(&d40d->txd);
8d318a50
LW		 1661
1662 /*
1663 * If terminating a channel pending_tx is set to zero.
1664 * This prevents any finished active jobs to return to the client.
1665 */
1666 if (d40c->pending_tx == 0) {
1667 spin_unlock_irqrestore(&d40c->lock, flags);
1668 return;
1669 }
1670
1671 /* Callback to client */
e9baa9d9 1672 callback_active = !!(d40d->txd.flags & DMA_PREP_INTERRUPT);
767a9675
JA		 1673 callback = d40d->txd.callback;
1674 callback_param = d40d->txd.callback_param;
1675
0c842b55
RV		 1676 if (!d40d->cyclic) {
1677 if (async_tx_test_ack(&d40d->txd)) {
767a9675 1678 d40_desc_remove(d40d);
0c842b55 1679 d40_desc_free(d40c, d40d);
f26e03ad
FB		 1680 } else if (!d40d->is_in_client_list) {
1681 d40_desc_remove(d40d);
1682 d40_lcla_free_all(d40c, d40d);
1683 list_add_tail(&d40d->node, &d40c->client);
1684 d40d->is_in_client_list = true;
8d318a50
LW		 1685 }
1686 }
1687
1688 d40c->pending_tx--;
1689
1690 if (d40c->pending_tx)
1691 tasklet_schedule(&d40c->tasklet);
1692
1693 spin_unlock_irqrestore(&d40c->lock, flags);
1694
e9baa9d9 1695 if (callback_active && callback)
8d318a50
LW		 1696 callback(callback_param);
1697
1698 return;
1699
1bdae6f4
N		 1700err:
1701 /* Rescue manouver if receiving double interrupts */
8d318a50
LW		 1702 if (d40c->pending_tx > 0)
1703 d40c->pending_tx--;
1704 spin_unlock_irqrestore(&d40c->lock, flags);
1705}
1706
1707static irqreturn_t d40_handle_interrupt(int irq, void *data)
1708{
8d318a50 1709 int i;
8d318a50
LW		 1710 u32 idx;
1711 u32 row;
1712 long chan = -1;
1713 struct d40_chan *d40c;
1714 unsigned long flags;
1715 struct d40_base *base = data;
3cb645dc
TL		 1716 u32 regs[base->gen_dmac.il_size];
1717 struct d40_interrupt_lookup *il = base->gen_dmac.il;
1718 u32 il_size = base->gen_dmac.il_size;
8d318a50
LW		 1719
1720 spin_lock_irqsave(&base->interrupt_lock, flags);
1721
1722 /* Read interrupt status of both logical and physical channels */
3cb645dc 1723 for (i = 0; i < il_size; i++)
8d318a50
LW		 1724 regs[i] = readl(base->virtbase + il[i].src);
1725
1726 for (;;) {
1727
1728 chan = find_next_bit((unsigned long *)regs,
3cb645dc 1729 BITS_PER_LONG * il_size, chan + 1);
8d318a50
LW		 1730
1731 /* No more set bits found? */
3cb645dc 1732 if (chan == BITS_PER_LONG * il_size)
8d318a50
LW		 1733 break;
1734
1735 row = chan / BITS_PER_LONG;
1736 idx = chan & (BITS_PER_LONG - 1);
1737
8d318a50
LW		 1738 if (il[row].offset == D40_PHY_CHAN)
1739 d40c = base->lookup_phy_chans[idx];
1740 else
1741 d40c = base->lookup_log_chans[il[row].offset + idx];
53d6d68f
FB		 1742
1743 if (!d40c) {
1744 /*
1745 * No error because this can happen if something else
1746 * in the system is using the channel.
1747 */
1748 continue;
1749 }
1750
1751 /* ACK interrupt */
8a3b6e14 1752 writel(BIT(idx), base->virtbase + il[row].clr);
53d6d68f 1753
8d318a50
LW		 1754 spin_lock(&d40c->lock);
1755
1756 if (!il[row].is_error)
1757 dma_tc_handle(d40c);
1758 else
6db5a8ba
RV		 1759 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1760 chan, il[row].offset, idx);
8d318a50
LW		 1761
1762 spin_unlock(&d40c->lock);
1763 }
1764
1765 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1766
1767 return IRQ_HANDLED;
1768}
1769
8d318a50
LW		 1770static int d40_validate_conf(struct d40_chan *d40c,
1771 struct stedma40_chan_cfg *conf)
1772{
1773 int res = 0;
38bdbf02 1774 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1775
0747c7ba 1776 if (!conf->dir) {
6db5a8ba 1777 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1778 res = -EINVAL;
1779 }
1780
26955c07
LJ		 1781 if ((is_log && conf->dev_type > d40c->base->num_log_chans) ||
1782 (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
1783 (conf->dev_type < 0)) {
1784 chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
0747c7ba
LW		 1785 res = -EINVAL;
1786 }
1787
2c2b62d5 1788 if (conf->dir == DMA_DEV_TO_DEV) {
8d318a50
LW		 1789 /*
1790 * DMAC HW supports it. Will be added to this driver,
1791 * in case any dma client requires it.
1792 */
6db5a8ba 1793 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1794 res = -EINVAL;
1795 }
1796
d49278e3 1797 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
43f2e1a3 1798 conf->src_info.data_width !=
d49278e3 1799 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
43f2e1a3 1800 conf->dst_info.data_width) {
d49278e3
PF		 1801 /*
1802 * The DMAC hardware only supports
1803 * src (burst x width) == dst (burst x width)
1804 */
1805
6db5a8ba 1806 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1807 res = -EINVAL;
1808 }
1809
8d318a50
LW		 1810 return res;
1811}
1812
5cd326fd
N		 1813static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1814 bool is_src, int log_event_line, bool is_log,
1815 bool *first_user)
8d318a50
LW		 1816{
1817 unsigned long flags;
1818 spin_lock_irqsave(&phy->lock, flags);
5cd326fd
N		 1819
1820 *first_user = ((phy->allocated_src | phy->allocated_dst)
1821 == D40_ALLOC_FREE);
1822
4aed79b2 1823 if (!is_log) {
8d318a50
LW		 1824 /* Physical interrupts are masked per physical full channel */
1825 if (phy->allocated_src == D40_ALLOC_FREE &&
1826 phy->allocated_dst == D40_ALLOC_FREE) {
1827 phy->allocated_dst = D40_ALLOC_PHY;
1828 phy->allocated_src = D40_ALLOC_PHY;
1829 goto found;
1830 } else
1831 goto not_found;
1832 }
1833
1834 /* Logical channel */
1835 if (is_src) {
1836 if (phy->allocated_src == D40_ALLOC_PHY)
1837 goto not_found;
1838
1839 if (phy->allocated_src == D40_ALLOC_FREE)
1840 phy->allocated_src = D40_ALLOC_LOG_FREE;
1841
8a3b6e14
LJ		 1842 if (!(phy->allocated_src & BIT(log_event_line))) {
1843 phy->allocated_src |= BIT(log_event_line);
8d318a50
LW		 1844 goto found;
1845 } else
1846 goto not_found;
1847 } else {
1848 if (phy->allocated_dst == D40_ALLOC_PHY)
1849 goto not_found;
1850
1851 if (phy->allocated_dst == D40_ALLOC_FREE)
1852 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1853
8a3b6e14
LJ		 1854 if (!(phy->allocated_dst & BIT(log_event_line))) {
1855 phy->allocated_dst |= BIT(log_event_line);
8d318a50
LW		 1856 goto found;
1857 } else
1858 goto not_found;
1859 }
1860
1861not_found:
1862 spin_unlock_irqrestore(&phy->lock, flags);
1863 return false;
1864found:
1865 spin_unlock_irqrestore(&phy->lock, flags);
1866 return true;
1867}
1868
1869static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1870 int log_event_line)
1871{
1872 unsigned long flags;
1873 bool is_free = false;
1874
1875 spin_lock_irqsave(&phy->lock, flags);
1876 if (!log_event_line) {
8d318a50
LW		 1877 phy->allocated_dst = D40_ALLOC_FREE;
1878 phy->allocated_src = D40_ALLOC_FREE;
1879 is_free = true;
1880 goto out;
1881 }
1882
1883 /* Logical channel */
1884 if (is_src) {
8a3b6e14 1885 phy->allocated_src &= ~BIT(log_event_line);
8d318a50
LW		 1886 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1887 phy->allocated_src = D40_ALLOC_FREE;
1888 } else {
8a3b6e14 1889 phy->allocated_dst &= ~BIT(log_event_line);
8d318a50
LW		 1890 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1891 phy->allocated_dst = D40_ALLOC_FREE;
1892 }
1893
1894 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1895 D40_ALLOC_FREE);
1896
1897out:
1898 spin_unlock_irqrestore(&phy->lock, flags);
1899
1900 return is_free;
1901}
1902
5cd326fd 1903static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
8d318a50 1904{
26955c07 1905 int dev_type = d40c->dma_cfg.dev_type;
8d318a50
LW		 1906 int event_group;
1907 int event_line;
1908 struct d40_phy_res *phys;
1909 int i;
1910 int j;
1911 int log_num;
f000df8c 1912 int num_phy_chans;
8d318a50 1913 bool is_src;
38bdbf02 1914 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1915
1916 phys = d40c->base->phy_res;
f000df8c 1917 num_phy_chans = d40c->base->num_phy_chans;
8d318a50 1918
2c2b62d5 1919 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
8d318a50
LW		 1920 log_num = 2 * dev_type;
1921 is_src = true;
2c2b62d5
LJ		 1922 } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
1923 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
8d318a50 1924 /* dst event lines are used for logical memcpy */
8d318a50
LW		 1925 log_num = 2 * dev_type + 1;
1926 is_src = false;
1927 } else
1928 return -EINVAL;
1929
1930 event_group = D40_TYPE_TO_GROUP(dev_type);
1931 event_line = D40_TYPE_TO_EVENT(dev_type);
1932
1933 if (!is_log) {
2c2b62d5 1934 if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
8d318a50 1935 /* Find physical half channel */
f000df8c
GB		 1936 if (d40c->dma_cfg.use_fixed_channel) {
1937 i = d40c->dma_cfg.phy_channel;
4aed79b2 1938 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1939 0, is_log,
1940 first_phy_user))
8d318a50 1941 goto found_phy;
f000df8c
GB		 1942 } else {
1943 for (i = 0; i < num_phy_chans; i++) {
1944 if (d40_alloc_mask_set(&phys[i], is_src,
1945 0, is_log,
1946 first_phy_user))
1947 goto found_phy;
1948 }
8d318a50
LW		 1949 }
1950 } else
1951 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1952 int phy_num = j + event_group * 2;
1953 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1954 if (d40_alloc_mask_set(&phys[i],
1955 is_src,
1956 0,
5cd326fd
N		 1957 is_log,
1958 first_phy_user))
8d318a50
LW		 1959 goto found_phy;
1960 }
1961 }
1962 return -EINVAL;
1963found_phy:
1964 d40c->phy_chan = &phys[i];
1965 d40c->log_num = D40_PHY_CHAN;
1966 goto out;
1967 }
1968 if (dev_type == -1)
1969 return -EINVAL;
1970
1971 /* Find logical channel */
1972 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1973 int phy_num = j + event_group * 2;
5cd326fd
N		 1974
1975 if (d40c->dma_cfg.use_fixed_channel) {
1976 i = d40c->dma_cfg.phy_channel;
1977
1978 if ((i != phy_num) && (i != phy_num + 1)) {
1979 dev_err(chan2dev(d40c),
1980 "invalid fixed phy channel %d\n", i);
1981 return -EINVAL;
1982 }
1983
1984 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1985 is_log, first_phy_user))
1986 goto found_log;
1987
1988 dev_err(chan2dev(d40c),
1989 "could not allocate fixed phy channel %d\n", i);
1990 return -EINVAL;
1991 }
1992
8d318a50
LW		 1993 /*
1994 * Spread logical channels across all available physical rather
1995 * than pack every logical channel at the first available phy
1996 * channels.
1997 */
1998 if (is_src) {
1999 for (i = phy_num; i < phy_num + 2; i++) {
2000 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 2001 event_line, is_log,
2002 first_phy_user))
8d318a50
LW		 2003 goto found_log;
2004 }
2005 } else {
2006 for (i = phy_num + 1; i >= phy_num; i--) {
2007 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 2008 event_line, is_log,
2009 first_phy_user))
8d318a50
LW		 2010 goto found_log;
2011 }
2012 }
2013 }
2014 return -EINVAL;
2015
2016found_log:
2017 d40c->phy_chan = &phys[i];
2018 d40c->log_num = log_num;
2019out:
2020
2021 if (is_log)
2022 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
2023 else
2024 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
2025
2026 return 0;
2027
2028}
2029
8d318a50
LW		 2030static int d40_config_memcpy(struct d40_chan *d40c)
2031{
2032 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
2033
2034 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
29027a1e 2035 d40c->dma_cfg = dma40_memcpy_conf_log;
26955c07 2036 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
8d318a50 2037
9b233f9b
LJ		 2038 d40_log_cfg(&d40c->dma_cfg,
2039 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2040
8d318a50
LW		 2041 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
2042 dma_has_cap(DMA_SLAVE, cap)) {
29027a1e 2043 d40c->dma_cfg = dma40_memcpy_conf_phy;
57e65ad7
LJ		 2044
2045 /* Generate interrrupt at end of transfer or relink. */
2046 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
2047
2048 /* Generate interrupt on error. */
2049 d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2050 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2051
8d318a50 2052 } else {
6db5a8ba 2053 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 2054 return -EINVAL;
2055 }
2056
2057 return 0;
2058}
2059
8d318a50
LW		 2060static int d40_free_dma(struct d40_chan *d40c)
2061{
2062
2063 int res = 0;
26955c07 2064 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
8d318a50
LW		 2065 struct d40_phy_res *phy = d40c->phy_chan;
2066 bool is_src;
2067
2068 /* Terminate all queued and active transfers */
2069 d40_term_all(d40c);
2070
2071 if (phy == NULL) {
6db5a8ba 2072 chan_err(d40c, "phy == null\n");
8d318a50
LW		 2073 return -EINVAL;
2074 }
2075
2076 if (phy->allocated_src == D40_ALLOC_FREE &&
2077 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 2078 chan_err(d40c, "channel already free\n");
8d318a50
LW		 2079 return -EINVAL;
2080 }
2081
2c2b62d5
LJ		 2082 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2083 d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
8d318a50 2084 is_src = false;
2c2b62d5 2085 else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
8d318a50 2086 is_src = true;
26955c07 2087 else {
6db5a8ba 2088 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 2089 return -EINVAL;
2090 }
2091
7fb3e75e 2092 pm_runtime_get_sync(d40c->base->dev);
1bdae6f4 2093 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
d181b3a8 2094 if (res) {
1bdae6f4 2095 chan_err(d40c, "stop failed\n");
7fb3e75e 2096 goto out;
d181b3a8
JA		 2097 }
2098
1bdae6f4 2099 d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
8d318a50 2100
1bdae6f4 2101 if (chan_is_logical(d40c))
8d318a50 2102 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1bdae6f4
N		 2103 else
2104 d40c->base->lookup_phy_chans[phy->num] = NULL;
7fb3e75e
N		 2105
2106 if (d40c->busy) {
2107 pm_runtime_mark_last_busy(d40c->base->dev);
2108 pm_runtime_put_autosuspend(d40c->base->dev);
2109 }
2110
2111 d40c->busy = false;
8d318a50 2112 d40c->phy_chan = NULL;
ce2ca125 2113 d40c->configured = false;
7fb3e75e 2114out:
8d318a50 2115
7fb3e75e
N		 2116 pm_runtime_mark_last_busy(d40c->base->dev);
2117 pm_runtime_put_autosuspend(d40c->base->dev);
2118 return res;
8d318a50
LW		 2119}
2120
a5ebca47
JA		 2121static bool d40_is_paused(struct d40_chan *d40c)
2122{
8ca84687 2123 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 2124 bool is_paused = false;
2125 unsigned long flags;
2126 void __iomem *active_reg;
2127 u32 status;
26955c07 2128 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
a5ebca47
JA		 2129
2130 spin_lock_irqsave(&d40c->lock, flags);
2131
724a8577 2132 if (chan_is_physical(d40c)) {
a5ebca47
JA		 2133 if (d40c->phy_chan->num % 2 == 0)
2134 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2135 else
2136 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2137
2138 status = (readl(active_reg) &
2139 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
2140 D40_CHAN_POS(d40c->phy_chan->num);
2141 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
2142 is_paused = true;
2143
2144 goto _exit;
2145 }
2146
2c2b62d5
LJ		 2147 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2148 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
8ca84687 2149 status = readl(chanbase + D40_CHAN_REG_SDLNK);
2c2b62d5 2150 } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
8ca84687 2151 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 2152 } else {
6db5a8ba 2153 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 2154 goto _exit;
2155 }
9dbfbd35 2156
a5ebca47
JA		 2157 status = (status & D40_EVENTLINE_MASK(event)) >>
2158 D40_EVENTLINE_POS(event);
2159
2160 if (status != D40_DMA_RUN)
2161 is_paused = true;
a5ebca47
JA		 2162_exit:
2163 spin_unlock_irqrestore(&d40c->lock, flags);
2164 return is_paused;
2165
2166}
2167
8d318a50
LW		 2168static u32 stedma40_residue(struct dma_chan *chan)
2169{
2170 struct d40_chan *d40c =
2171 container_of(chan, struct d40_chan, chan);
2172 u32 bytes_left;
2173 unsigned long flags;
2174
2175 spin_lock_irqsave(&d40c->lock, flags);
2176 bytes_left = d40_residue(d40c);
2177 spin_unlock_irqrestore(&d40c->lock, flags);
2178
2179 return bytes_left;
2180}
2181
3e3a0763
RV		 2182static int
2183d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
2184 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 2185 unsigned int sg_len, dma_addr_t src_dev_addr,
2186 dma_addr_t dst_dev_addr)
3e3a0763
RV		 2187{
2188 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2189 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2190 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
5ed04b85 2191 int ret;
3e3a0763 2192
5ed04b85
RV		 2193 ret = d40_log_sg_to_lli(sg_src, sg_len,
2194 src_dev_addr,
2195 desc->lli_log.src,
2196 chan->log_def.lcsp1,
2197 src_info->data_width,
2198 dst_info->data_width);
2199
2200 ret = d40_log_sg_to_lli(sg_dst, sg_len,
2201 dst_dev_addr,
2202 desc->lli_log.dst,
2203 chan->log_def.lcsp3,
2204 dst_info->data_width,
2205 src_info->data_width);
2206
2207 return ret < 0 ? ret : 0;
3e3a0763
RV		 2208}
2209
2210static int
2211d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2212 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 2213 unsigned int sg_len, dma_addr_t src_dev_addr,
2214 dma_addr_t dst_dev_addr)
3e3a0763 2215{
3e3a0763
RV		 2216 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2217 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2218 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
0c842b55 2219 unsigned long flags = 0;
3e3a0763
RV		 2220 int ret;
2221
0c842b55
RV		 2222 if (desc->cyclic)
2223 flags |= LLI_CYCLIC | LLI_TERM_INT;
2224
3e3a0763
RV		 2225 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2226 desc->lli_phy.src,
2227 virt_to_phys(desc->lli_phy.src),
2228 chan->src_def_cfg,
0c842b55 2229 src_info, dst_info, flags);
3e3a0763
RV		 2230
2231 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2232 desc->lli_phy.dst,
2233 virt_to_phys(desc->lli_phy.dst),
2234 chan->dst_def_cfg,
0c842b55 2235 dst_info, src_info, flags);
3e3a0763
RV		 2236
2237 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2238 desc->lli_pool.size, DMA_TO_DEVICE);
2239
2240 return ret < 0 ? ret : 0;
2241}
2242
5f81158f
RV		 2243static struct d40_desc *
2244d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2245 unsigned int sg_len, unsigned long dma_flags)
2246{
2247 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2248 struct d40_desc *desc;
dbd88788 2249 int ret;
5f81158f
RV		 2250
2251 desc = d40_desc_get(chan);
2252 if (!desc)
2253 return NULL;
2254
2255 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2256 cfg->dst_info.data_width);
2257 if (desc->lli_len < 0) {
2258 chan_err(chan, "Unaligned size\n");
dbd88788
RV		 2259 goto err;
2260 }
5f81158f 2261
dbd88788
RV		 2262 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2263 if (ret < 0) {
2264 chan_err(chan, "Could not allocate lli\n");
2265 goto err;
5f81158f
RV		 2266 }
2267
2268 desc->lli_current = 0;
2269 desc->txd.flags = dma_flags;
2270 desc->txd.tx_submit = d40_tx_submit;
2271
2272 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2273
2274 return desc;
dbd88788
RV		 2275
2276err:
2277 d40_desc_free(chan, desc);
2278 return NULL;
5f81158f
RV		 2279}
2280
cade1d30
RV		 2281static struct dma_async_tx_descriptor *
2282d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2283 struct scatterlist *sg_dst, unsigned int sg_len,
db8196df 2284 enum dma_transfer_direction direction, unsigned long dma_flags)
cade1d30
RV		 2285{
2286 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
822c5676
RV		 2287 dma_addr_t src_dev_addr = 0;
2288 dma_addr_t dst_dev_addr = 0;
cade1d30 2289 struct d40_desc *desc;
2a614340 2290 unsigned long flags;
cade1d30 2291 int ret;
8d318a50 2292
cade1d30
RV		 2293 if (!chan->phy_chan) {
2294 chan_err(chan, "Cannot prepare unallocated channel\n");
2295 return NULL;
0d0f6b8b
JA		 2296 }
2297
cade1d30 2298 spin_lock_irqsave(&chan->lock, flags);
8d318a50 2299
cade1d30
RV		 2300 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2301 if (desc == NULL)
8d318a50
LW		 2302 goto err;
2303
0c842b55
RV		 2304 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2305 desc->cyclic = true;
2306
ef9c89b3
LJ		 2307 if (direction == DMA_DEV_TO_MEM)
2308 src_dev_addr = chan->runtime_addr;
2309 else if (direction == DMA_MEM_TO_DEV)
2310 dst_dev_addr = chan->runtime_addr;
cade1d30
RV		 2311
2312 if (chan_is_logical(chan))
2313 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
822c5676 2314 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2315 else
2316 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
822c5676 2317 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2318
2319 if (ret) {
2320 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2321 chan_is_logical(chan) ? "log" : "phy", ret);
2322 goto err;
8d318a50
LW		 2323 }
2324
82babbb3
PF		 2325 /*
2326 * add descriptor to the prepare queue in order to be able
2327 * to free them later in terminate_all
2328 */
2329 list_add_tail(&desc->node, &chan->prepare_queue);
2330
cade1d30
RV		 2331 spin_unlock_irqrestore(&chan->lock, flags);
2332
2333 return &desc->txd;
8d318a50 2334
8d318a50 2335err:
cade1d30
RV		 2336 if (desc)
2337 d40_desc_free(chan, desc);
2338 spin_unlock_irqrestore(&chan->lock, flags);
8d318a50
LW		 2339 return NULL;
2340}
8d318a50
LW		 2341
2342bool stedma40_filter(struct dma_chan *chan, void *data)
2343{
2344 struct stedma40_chan_cfg *info = data;
2345 struct d40_chan *d40c =
2346 container_of(chan, struct d40_chan, chan);
2347 int err;
2348
2349 if (data) {
2350 err = d40_validate_conf(d40c, info);
2351 if (!err)
2352 d40c->dma_cfg = *info;
2353 } else
2354 err = d40_config_memcpy(d40c);
2355
ce2ca125
RV		 2356 if (!err)
2357 d40c->configured = true;
2358
8d318a50
LW		 2359 return err == 0;
2360}
2361EXPORT_SYMBOL(stedma40_filter);
2362
ac2c0a38
RV		 2363static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2364{
2365 bool realtime = d40c->dma_cfg.realtime;
2366 bool highprio = d40c->dma_cfg.high_priority;
3cb645dc 2367 u32 rtreg;
ac2c0a38
RV		 2368 u32 event = D40_TYPE_TO_EVENT(dev_type);
2369 u32 group = D40_TYPE_TO_GROUP(dev_type);
8a3b6e14 2370 u32 bit = BIT(event);
ccc3d697 2371 u32 prioreg;
3cb645dc 2372 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
ccc3d697 2373
3cb645dc 2374 rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
ccc3d697
RV		 2375 /*
2376 * Due to a hardware bug, in some cases a logical channel triggered by
2377 * a high priority destination event line can generate extra packet
2378 * transactions.
2379 *
2380 * The workaround is to not set the high priority level for the
2381 * destination event lines that trigger logical channels.
2382 */
2383 if (!src && chan_is_logical(d40c))
2384 highprio = false;
2385
3cb645dc 2386 prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
ac2c0a38
RV		 2387
2388 /* Destination event lines are stored in the upper halfword */
2389 if (!src)
2390 bit <<= 16;
2391
2392 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2393 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2394}
2395
2396static void d40_set_prio_realtime(struct d40_chan *d40c)
2397{
2398 if (d40c->base->rev < 3)
2399 return;
2400
2c2b62d5
LJ		 2401 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
2402 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
26955c07 2403 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
ac2c0a38 2404
2c2b62d5
LJ		 2405 if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) ||
2406 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
26955c07 2407 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
ac2c0a38
RV		 2408}
2409
fa332de5
LJ		 2410#define D40_DT_FLAGS_MODE(flags) ((flags >> 0) & 0x1)
2411#define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
2412#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2413#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
bddd5a2b 2414#define D40_DT_FLAGS_HIGH_PRIO(flags) ((flags >> 4) & 0x1)
fa332de5
LJ		 2415
2416static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2417 struct of_dma *ofdma)
2418{
2419 struct stedma40_chan_cfg cfg;
2420 dma_cap_mask_t cap;
2421 u32 flags;
2422
2423 memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
2424
2425 dma_cap_zero(cap);
2426 dma_cap_set(DMA_SLAVE, cap);
2427
2428 cfg.dev_type = dma_spec->args[0];
2429 flags = dma_spec->args[2];
2430
2431 switch (D40_DT_FLAGS_MODE(flags)) {
2432 case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
2433 case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
2434 }
2435
2436 switch (D40_DT_FLAGS_DIR(flags)) {
2437 case 0:
2c2b62d5 2438 cfg.dir = DMA_MEM_TO_DEV;
fa332de5
LJ		 2439 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2440 break;
2441 case 1:
2c2b62d5 2442 cfg.dir = DMA_DEV_TO_MEM;
fa332de5
LJ		 2443 cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2444 break;
2445 }
2446
2447 if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
2448 cfg.phy_channel = dma_spec->args[1];
2449 cfg.use_fixed_channel = true;
2450 }
2451
bddd5a2b
LJ		 2452 if (D40_DT_FLAGS_HIGH_PRIO(flags))
2453 cfg.high_priority = true;
2454
fa332de5
LJ		 2455 return dma_request_channel(cap, stedma40_filter, &cfg);
2456}
2457
8d318a50
LW		 2458/* DMA ENGINE functions */
2459static int d40_alloc_chan_resources(struct dma_chan *chan)
2460{
2461 int err;
2462 unsigned long flags;
2463 struct d40_chan *d40c =
2464 container_of(chan, struct d40_chan, chan);
ef1872ec 2465 bool is_free_phy;
8d318a50
LW		 2466 spin_lock_irqsave(&d40c->lock, flags);
2467
d3ee98cd 2468 dma_cookie_init(chan);
8d318a50 2469
ce2ca125
RV		 2470 /* If no dma configuration is set use default configuration (memcpy) */
2471 if (!d40c->configured) {
8d318a50 2472 err = d40_config_memcpy(d40c);
ff0b12ba 2473 if (err) {
6db5a8ba 2474 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 2475 goto fail;
2476 }
8d318a50
LW		 2477 }
2478
5cd326fd 2479 err = d40_allocate_channel(d40c, &is_free_phy);
8d318a50 2480 if (err) {
6db5a8ba 2481 chan_err(d40c, "Failed to allocate channel\n");
7fb3e75e 2482 d40c->configured = false;
ff0b12ba 2483 goto fail;
8d318a50
LW		 2484 }
2485
7fb3e75e 2486 pm_runtime_get_sync(d40c->base->dev);
ef1872ec 2487
ac2c0a38
RV		 2488 d40_set_prio_realtime(d40c);
2489
724a8577 2490 if (chan_is_logical(d40c)) {
2c2b62d5 2491 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
ef1872ec 2492 d40c->lcpa = d40c->base->lcpa_base +
26955c07 2493 d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
ef1872ec
LW		 2494 else
2495 d40c->lcpa = d40c->base->lcpa_base +
26955c07 2496 d40c->dma_cfg.dev_type *
f26e03ad 2497 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
9778256b
LJ		 2498
2499 /* Unmask the Global Interrupt Mask. */
2500 d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2501 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
ef1872ec
LW		 2502 }
2503
5cd326fd
N		 2504 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2505 chan_is_logical(d40c) ? "logical" : "physical",
2506 d40c->phy_chan->num,
2507 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2508
2509
ef1872ec
LW		 2510 /*
2511 * Only write channel configuration to the DMA if the physical
2512 * resource is free. In case of multiple logical channels
2513 * on the same physical resource, only the first write is necessary.
2514 */
b55912c6
JA		 2515 if (is_free_phy)
2516 d40_config_write(d40c);
ff0b12ba 2517fail:
7fb3e75e
N		 2518 pm_runtime_mark_last_busy(d40c->base->dev);
2519 pm_runtime_put_autosuspend(d40c->base->dev);
8d318a50 2520 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 2521 return err;
8d318a50
LW		 2522}
2523
2524static void d40_free_chan_resources(struct dma_chan *chan)
2525{
2526 struct d40_chan *d40c =
2527 container_of(chan, struct d40_chan, chan);
2528 int err;
2529 unsigned long flags;
2530
0d0f6b8b 2531 if (d40c->phy_chan == NULL) {
6db5a8ba 2532 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 2533 return;
2534 }
2535
8d318a50
LW		 2536 spin_lock_irqsave(&d40c->lock, flags);
2537
2538 err = d40_free_dma(d40c);
2539
2540 if (err)
6db5a8ba 2541 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 2542 spin_unlock_irqrestore(&d40c->lock, flags);
2543}
2544
2545static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2546 dma_addr_t dst,
2547 dma_addr_t src,
2548 size_t size,
2a614340 2549 unsigned long dma_flags)
8d318a50 2550{
95944c6e
RV		 2551 struct scatterlist dst_sg;
2552 struct scatterlist src_sg;
8d318a50 2553
95944c6e
RV		 2554 sg_init_table(&dst_sg, 1);
2555 sg_init_table(&src_sg, 1);
8d318a50 2556
95944c6e
RV		 2557 sg_dma_address(&dst_sg) = dst;
2558 sg_dma_address(&src_sg) = src;
8d318a50 2559
95944c6e
RV		 2560 sg_dma_len(&dst_sg) = size;
2561 sg_dma_len(&src_sg) = size;
8d318a50 2562
cade1d30 2563 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
8d318a50
LW		 2564}
2565
0d688662 2566static struct dma_async_tx_descriptor *
cade1d30
RV		 2567d40_prep_memcpy_sg(struct dma_chan *chan,
2568 struct scatterlist *dst_sg, unsigned int dst_nents,
2569 struct scatterlist *src_sg, unsigned int src_nents,
2570 unsigned long dma_flags)
0d688662
IS		 2571{
2572 if (dst_nents != src_nents)
2573 return NULL;
2574
cade1d30 2575 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
00ac0341
RV		 2576}
2577
f26e03ad
FB		 2578static struct dma_async_tx_descriptor *
2579d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2580 unsigned int sg_len, enum dma_transfer_direction direction,
2581 unsigned long dma_flags, void *context)
8d318a50 2582{
a725dcc0 2583 if (!is_slave_direction(direction))
00ac0341
RV		 2584 return NULL;
2585
cade1d30 2586 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
8d318a50
LW		 2587}
2588
0c842b55
RV		 2589static struct dma_async_tx_descriptor *
2590dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2591 size_t buf_len, size_t period_len,
ec8b5e48
PU		 2592 enum dma_transfer_direction direction, unsigned long flags,
2593 void *context)
0c842b55
RV		 2594{
2595 unsigned int periods = buf_len / period_len;
2596 struct dma_async_tx_descriptor *txd;
2597 struct scatterlist *sg;
2598 int i;
2599
79ca7ec3 2600 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
2ec7e2e7
SK		 2601 if (!sg)
2602 return NULL;
2603
0c842b55
RV		 2604 for (i = 0; i < periods; i++) {
2605 sg_dma_address(&sg[i]) = dma_addr;
2606 sg_dma_len(&sg[i]) = period_len;
2607 dma_addr += period_len;
2608 }
2609
2610 sg[periods].offset = 0;
fdaf9c4b 2611 sg_dma_len(&sg[periods]) = 0;
0c842b55
RV		 2612 sg[periods].page_link =
2613 ((unsigned long)sg | 0x01) & ~0x02;
2614
2615 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2616 DMA_PREP_INTERRUPT);
2617
2618 kfree(sg);
2619
2620 return txd;
2621}
2622
8d318a50
LW		 2623static enum dma_status d40_tx_status(struct dma_chan *chan,
2624 dma_cookie_t cookie,
2625 struct dma_tx_state *txstate)
2626{
2627 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
96a2af41 2628 enum dma_status ret;
8d318a50 2629
0d0f6b8b 2630 if (d40c->phy_chan == NULL) {
6db5a8ba 2631 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2632 return -EINVAL;
2633 }
2634
96a2af41 2635 ret = dma_cookie_status(chan, cookie, txstate);
e2360adb 2636 if (ret != DMA_COMPLETE)
96a2af41 2637 dma_set_residue(txstate, stedma40_residue(chan));
8d318a50 2638
a5ebca47
JA		 2639 if (d40_is_paused(d40c))
2640 ret = DMA_PAUSED;
8d318a50
LW		 2641
2642 return ret;
2643}
2644
2645static void d40_issue_pending(struct dma_chan *chan)
2646{
2647 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2648 unsigned long flags;
2649
0d0f6b8b 2650 if (d40c->phy_chan == NULL) {
6db5a8ba 2651 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2652 return;
2653 }
2654
8d318a50
LW		 2655 spin_lock_irqsave(&d40c->lock, flags);
2656
a8f3067b
PF		 2657 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2658
2659 /* Busy means that queued jobs are already being processed */
8d318a50
LW		 2660 if (!d40c->busy)
2661 (void) d40_queue_start(d40c);
2662
2663 spin_unlock_irqrestore(&d40c->lock, flags);
2664}
2665
1bdae6f4
N		 2666static void d40_terminate_all(struct dma_chan *chan)
2667{
2668 unsigned long flags;
2669 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2670 int ret;
2671
2672 spin_lock_irqsave(&d40c->lock, flags);
2673
2674 pm_runtime_get_sync(d40c->base->dev);
2675 ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2676 if (ret)
2677 chan_err(d40c, "Failed to stop channel\n");
2678
2679 d40_term_all(d40c);
2680 pm_runtime_mark_last_busy(d40c->base->dev);
2681 pm_runtime_put_autosuspend(d40c->base->dev);
2682 if (d40c->busy) {
2683 pm_runtime_mark_last_busy(d40c->base->dev);
2684 pm_runtime_put_autosuspend(d40c->base->dev);
2685 }
2686 d40c->busy = false;
2687
2688 spin_unlock_irqrestore(&d40c->lock, flags);
2689}
2690
98ca5289
RV		 2691static int
2692dma40_config_to_halfchannel(struct d40_chan *d40c,
2693 struct stedma40_half_channel_info *info,
98ca5289
RV		 2694 u32 maxburst)
2695{
98ca5289
RV		 2696 int psize;
2697
98ca5289
RV		 2698 if (chan_is_logical(d40c)) {
2699 if (maxburst >= 16)
2700 psize = STEDMA40_PSIZE_LOG_16;
2701 else if (maxburst >= 8)
2702 psize = STEDMA40_PSIZE_LOG_8;
2703 else if (maxburst >= 4)
2704 psize = STEDMA40_PSIZE_LOG_4;
2705 else
2706 psize = STEDMA40_PSIZE_LOG_1;
2707 } else {
2708 if (maxburst >= 16)
2709 psize = STEDMA40_PSIZE_PHY_16;
2710 else if (maxburst >= 8)
2711 psize = STEDMA40_PSIZE_PHY_8;
2712 else if (maxburst >= 4)
2713 psize = STEDMA40_PSIZE_PHY_4;
2714 else
2715 psize = STEDMA40_PSIZE_PHY_1;
2716 }
2717
98ca5289
RV		 2718 info->psize = psize;
2719 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2720
2721 return 0;
2722}
2723
95e1400f 2724/* Runtime reconfiguration extension */
98ca5289
RV		 2725static int d40_set_runtime_config(struct dma_chan *chan,
2726 struct dma_slave_config *config)
95e1400f
LW		 2727{
2728 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2729 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
98ca5289 2730 enum dma_slave_buswidth src_addr_width, dst_addr_width;
95e1400f 2731 dma_addr_t config_addr;
98ca5289
RV		 2732 u32 src_maxburst, dst_maxburst;
2733 int ret;
2734
2735 src_addr_width = config->src_addr_width;
2736 src_maxburst = config->src_maxburst;
2737 dst_addr_width = config->dst_addr_width;
2738 dst_maxburst = config->dst_maxburst;
95e1400f 2739
db8196df 2740 if (config->direction == DMA_DEV_TO_MEM) {
95e1400f 2741 config_addr = config->src_addr;
ef9c89b3 2742
2c2b62d5 2743 if (cfg->dir != DMA_DEV_TO_MEM)
95e1400f
LW		 2744 dev_dbg(d40c->base->dev,
2745 "channel was not configured for peripheral "
2746 "to memory transfer (%d) overriding\n",
2747 cfg->dir);
2c2b62d5 2748 cfg->dir = DMA_DEV_TO_MEM;
95e1400f 2749
98ca5289
RV		 2750 /* Configure the memory side */
2751 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2752 dst_addr_width = src_addr_width;
2753 if (dst_maxburst == 0)
2754 dst_maxburst = src_maxburst;
95e1400f 2755
db8196df 2756 } else if (config->direction == DMA_MEM_TO_DEV) {
95e1400f 2757 config_addr = config->dst_addr;
ef9c89b3 2758
2c2b62d5 2759 if (cfg->dir != DMA_MEM_TO_DEV)
95e1400f
LW		 2760 dev_dbg(d40c->base->dev,
2761 "channel was not configured for memory "
2762 "to peripheral transfer (%d) overriding\n",
2763 cfg->dir);
2c2b62d5 2764 cfg->dir = DMA_MEM_TO_DEV;
95e1400f 2765
98ca5289
RV		 2766 /* Configure the memory side */
2767 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2768 src_addr_width = dst_addr_width;
2769 if (src_maxburst == 0)
2770 src_maxburst = dst_maxburst;
95e1400f
LW		 2771 } else {
2772 dev_err(d40c->base->dev,
2773 "unrecognized channel direction %d\n",
2774 config->direction);
98ca5289 2775 return -EINVAL;
95e1400f
LW		 2776 }
2777
ef9c89b3
LJ		 2778 if (config_addr <= 0) {
2779 dev_err(d40c->base->dev, "no address supplied\n");
2780 return -EINVAL;
2781 }
2782
98ca5289 2783 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
95e1400f 2784 dev_err(d40c->base->dev,
98ca5289
RV		 2785 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2786 src_maxburst,
2787 src_addr_width,
2788 dst_maxburst,
2789 dst_addr_width);
2790 return -EINVAL;
95e1400f
LW		 2791 }
2792
92bb6cdb
PF		 2793 if (src_maxburst > 16) {
2794 src_maxburst = 16;
2795 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2796 } else if (dst_maxburst > 16) {
2797 dst_maxburst = 16;
2798 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2799 }
2800
43f2e1a3
LJ		 2801 /* Only valid widths are; 1, 2, 4 and 8. */
2802 if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2803 src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
2804 dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2805 dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
c95905a6
GL		 2806 !is_power_of_2(src_addr_width) ||
2807 !is_power_of_2(dst_addr_width))
43f2e1a3
LJ		 2808 return -EINVAL;
2809
2810 cfg->src_info.data_width = src_addr_width;
2811 cfg->dst_info.data_width = dst_addr_width;
2812
98ca5289 2813 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
98ca5289
RV		 2814 src_maxburst);
2815 if (ret)
2816 return ret;
95e1400f 2817
98ca5289 2818 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
98ca5289
RV		 2819 dst_maxburst);
2820 if (ret)
2821 return ret;
95e1400f 2822
a59670a4 2823 /* Fill in register values */
724a8577 2824 if (chan_is_logical(d40c))
a59670a4
PF		 2825 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2826 else
57e65ad7 2827 d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
a59670a4 2828
95e1400f
LW		 2829 /* These settings will take precedence later */
2830 d40c->runtime_addr = config_addr;
2831 d40c->runtime_direction = config->direction;
2832 dev_dbg(d40c->base->dev,
98ca5289
RV		 2833 "configured channel %s for %s, data width %d/%d, "
2834 "maxburst %d/%d elements, LE, no flow control\n",
95e1400f 2835 dma_chan_name(chan),
db8196df 2836 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
98ca5289
RV		 2837 src_addr_width, dst_addr_width,
2838 src_maxburst, dst_maxburst);
2839
2840 return 0;
95e1400f
LW		 2841}
2842
05827630
LW		 2843static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2844 unsigned long arg)
8d318a50 2845{
8d318a50
LW		 2846 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2847
0d0f6b8b 2848 if (d40c->phy_chan == NULL) {
6db5a8ba 2849 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2850 return -EINVAL;
2851 }
2852
8d318a50
LW		 2853 switch (cmd) {
2854 case DMA_TERMINATE_ALL:
1bdae6f4
N		 2855 d40_terminate_all(chan);
2856 return 0;
8d318a50 2857 case DMA_PAUSE:
86eb5fb6 2858 return d40_pause(d40c);
8d318a50 2859 case DMA_RESUME:
86eb5fb6 2860 return d40_resume(d40c);
95e1400f 2861 case DMA_SLAVE_CONFIG:
98ca5289 2862 return d40_set_runtime_config(chan,
95e1400f 2863 (struct dma_slave_config *) arg);
95e1400f
LW		 2864 default:
2865 break;
8d318a50
LW		 2866 }
2867
2868 /* Other commands are unimplemented */
2869 return -ENXIO;
2870}
2871
2872/* Initialization functions */
2873
2874static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2875 struct d40_chan *chans, int offset,
2876 int num_chans)
2877{
2878 int i = 0;
2879 struct d40_chan *d40c;
2880
2881 INIT_LIST_HEAD(&dma->channels);
2882
2883 for (i = offset; i < offset + num_chans; i++) {
2884 d40c = &chans[i];
2885 d40c->base = base;
2886 d40c->chan.device = dma;
2887
8d318a50
LW		 2888 spin_lock_init(&d40c->lock);
2889
2890 d40c->log_num = D40_PHY_CHAN;
2891
4226dd86 2892 INIT_LIST_HEAD(&d40c->done);
8d318a50
LW		 2893 INIT_LIST_HEAD(&d40c->active);
2894 INIT_LIST_HEAD(&d40c->queue);
a8f3067b 2895 INIT_LIST_HEAD(&d40c->pending_queue);
8d318a50 2896 INIT_LIST_HEAD(&d40c->client);
82babbb3 2897 INIT_LIST_HEAD(&d40c->prepare_queue);
8d318a50 2898
8d318a50
LW		 2899 tasklet_init(&d40c->tasklet, dma_tasklet,
2900 (unsigned long) d40c);
2901
2902 list_add_tail(&d40c->chan.device_node,
2903 &dma->channels);
2904 }
2905}
2906
7ad74a7c
RV		 2907static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2908{
2909 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2910 dev->device_prep_slave_sg = d40_prep_slave_sg;
2911
2912 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2913 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2914
2915 /*
2916 * This controller can only access address at even
2917 * 32bit boundaries, i.e. 2^2
2918 */
2919 dev->copy_align = 2;
2920 }
2921
2922 if (dma_has_cap(DMA_SG, dev->cap_mask))
2923 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2924
0c842b55
RV		 2925 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2926 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2927
7ad74a7c
RV		 2928 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2929 dev->device_free_chan_resources = d40_free_chan_resources;
2930 dev->device_issue_pending = d40_issue_pending;
2931 dev->device_tx_status = d40_tx_status;
2932 dev->device_control = d40_control;
2933 dev->dev = base->dev;
2934}
2935
8d318a50
LW		 2936static int __init d40_dmaengine_init(struct d40_base *base,
2937 int num_reserved_chans)
2938{
2939 int err ;
2940
2941 d40_chan_init(base, &base->dma_slave, base->log_chans,
2942 0, base->num_log_chans);
2943
2944 dma_cap_zero(base->dma_slave.cap_mask);
2945 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
0c842b55 2946 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
8d318a50 2947
7ad74a7c 2948 d40_ops_init(base, &base->dma_slave);
8d318a50
LW		 2949
2950 err = dma_async_device_register(&base->dma_slave);
2951
2952 if (err) {
6db5a8ba 2953 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2954 goto failure1;
2955 }
2956
2957 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
a7dacb68 2958 base->num_log_chans, base->num_memcpy_chans);
8d318a50
LW		 2959
2960 dma_cap_zero(base->dma_memcpy.cap_mask);
2961 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
7ad74a7c
RV		 2962 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2963
2964 d40_ops_init(base, &base->dma_memcpy);
8d318a50
LW		 2965
2966 err = dma_async_device_register(&base->dma_memcpy);
2967
2968 if (err) {
6db5a8ba
RV		 2969 d40_err(base->dev,
2970 "Failed to regsiter memcpy only channels\n");
8d318a50
LW		 2971 goto failure2;
2972 }
2973
2974 d40_chan_init(base, &base->dma_both, base->phy_chans,
2975 0, num_reserved_chans);
2976
2977 dma_cap_zero(base->dma_both.cap_mask);
2978 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2979 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
7ad74a7c 2980 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
0c842b55 2981 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
7ad74a7c
RV		 2982
2983 d40_ops_init(base, &base->dma_both);
8d318a50
LW		 2984 err = dma_async_device_register(&base->dma_both);
2985
2986 if (err) {
6db5a8ba
RV		 2987 d40_err(base->dev,
2988 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2989 goto failure3;
2990 }
2991 return 0;
2992failure3:
2993 dma_async_device_unregister(&base->dma_memcpy);
2994failure2:
2995 dma_async_device_unregister(&base->dma_slave);
2996failure1:
2997 return err;
2998}
2999
7fb3e75e
N		 3000/* Suspend resume functionality */
3001#ifdef CONFIG_PM
3002static int dma40_pm_suspend(struct device *dev)
3003{
28c7a19d
N		 3004 struct platform_device *pdev = to_platform_device(dev);
3005 struct d40_base *base = platform_get_drvdata(pdev);
3006 int ret = 0;
7fb3e75e 3007
28c7a19d
N		 3008 if (base->lcpa_regulator)
3009 ret = regulator_disable(base->lcpa_regulator);
3010 return ret;
7fb3e75e
N		 3011}
3012
3013static int dma40_runtime_suspend(struct device *dev)
3014{
3015 struct platform_device *pdev = to_platform_device(dev);
3016 struct d40_base *base = platform_get_drvdata(pdev);
3017
3018 d40_save_restore_registers(base, true);
3019
3020 /* Don't disable/enable clocks for v1 due to HW bugs */
3021 if (base->rev != 1)
3022 writel_relaxed(base->gcc_pwr_off_mask,
3023 base->virtbase + D40_DREG_GCC);
3024
3025 return 0;
3026}
3027
3028static int dma40_runtime_resume(struct device *dev)
3029{
3030 struct platform_device *pdev = to_platform_device(dev);
3031 struct d40_base *base = platform_get_drvdata(pdev);
3032
3033 if (base->initialized)
3034 d40_save_restore_registers(base, false);
3035
3036 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
3037 base->virtbase + D40_DREG_GCC);
3038 return 0;
3039}
3040
28c7a19d
N		 3041static int dma40_resume(struct device *dev)
3042{
3043 struct platform_device *pdev = to_platform_device(dev);
3044 struct d40_base *base = platform_get_drvdata(pdev);
3045 int ret = 0;
3046
3047 if (base->lcpa_regulator)
3048 ret = regulator_enable(base->lcpa_regulator);
3049
3050 return ret;
3051}
7fb3e75e
N		 3052
3053static const struct dev_pm_ops dma40_pm_ops = {
3054 .suspend = dma40_pm_suspend,
3055 .runtime_suspend = dma40_runtime_suspend,
3056 .runtime_resume = dma40_runtime_resume,
28c7a19d 3057 .resume = dma40_resume,
7fb3e75e
N		 3058};
3059#define DMA40_PM_OPS (&dma40_pm_ops)
3060#else
3061#define DMA40_PM_OPS NULL
3062#endif
3063
8d318a50
LW		 3064/* Initialization functions. */
3065
3066static int __init d40_phy_res_init(struct d40_base *base)
3067{
3068 int i;
3069 int num_phy_chans_avail = 0;
3070 u32 val[2];
3071 int odd_even_bit = -2;
7fb3e75e 3072 int gcc = D40_DREG_GCC_ENA;
8d318a50
LW		 3073
3074 val[0] = readl(base->virtbase + D40_DREG_PRSME);
3075 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3076
3077 for (i = 0; i < base->num_phy_chans; i++) {
3078 base->phy_res[i].num = i;
3079 odd_even_bit += 2 * ((i % 2) == 0);
3080 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
3081 /* Mark security only channels as occupied */
3082 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
3083 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 3084 base->phy_res[i].reserved = true;
3085 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3086 D40_DREG_GCC_SRC);
3087 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3088 D40_DREG_GCC_DST);
3089
3090
8d318a50
LW		 3091 } else {
3092 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
3093 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
7fb3e75e 3094 base->phy_res[i].reserved = false;
8d318a50
LW		 3095 num_phy_chans_avail++;
3096 }
3097 spin_lock_init(&base->phy_res[i].lock);
3098 }
6b7acd84
JA		 3099
3100 /* Mark disabled channels as occupied */
3101 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 3102 int chan = base->plat_data->disabled_channels[i];
3103
3104 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
3105 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 3106 base->phy_res[chan].reserved = true;
3107 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3108 D40_DREG_GCC_SRC);
3109 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3110 D40_DREG_GCC_DST);
f57b407c 3111 num_phy_chans_avail--;
6b7acd84
JA		 3112 }
3113
7407048b
FB		 3114 /* Mark soft_lli channels */
3115 for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
3116 int chan = base->plat_data->soft_lli_chans[i];
3117
3118 base->phy_res[chan].use_soft_lli = true;
3119 }
3120
8d318a50
LW		 3121 dev_info(base->dev, "%d of %d physical DMA channels available\n",
3122 num_phy_chans_avail, base->num_phy_chans);
3123
3124 /* Verify settings extended vs standard */
3125 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3126
3127 for (i = 0; i < base->num_phy_chans; i++) {
3128
3129 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
3130 (val[0] & 0x3) != 1)
3131 dev_info(base->dev,
3132 "[%s] INFO: channel %d is misconfigured (%d)\n",
3133 __func__, i, val[0] & 0x3);
3134
3135 val[0] = val[0] >> 2;
3136 }
3137
7fb3e75e
N		 3138 /*
3139 * To keep things simple, Enable all clocks initially.
3140 * The clocks will get managed later post channel allocation.
3141 * The clocks for the event lines on which reserved channels exists
3142 * are not managed here.
3143 */
3144 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3145 base->gcc_pwr_off_mask = gcc;
3146
8d318a50
LW		 3147 return num_phy_chans_avail;
3148}
3149
3150static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3151{
d4adcc01 3152 struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
8d318a50
LW		 3153 struct clk *clk = NULL;
3154 void __iomem *virtbase = NULL;
3155 struct resource *res = NULL;
3156 struct d40_base *base = NULL;
3157 int num_log_chans = 0;
3158 int num_phy_chans;
a7dacb68 3159 int num_memcpy_chans;
b707c658 3160 int clk_ret = -EINVAL;
8d318a50 3161 int i;
f4b89764
LW		 3162 u32 pid;
3163 u32 cid;
3164 u8 rev;
8d318a50
LW		 3165
3166 clk = clk_get(&pdev->dev, NULL);
8d318a50 3167 if (IS_ERR(clk)) {
6db5a8ba 3168 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 3169 goto failure;
3170 }
3171
b707c658
UH		 3172 clk_ret = clk_prepare_enable(clk);
3173 if (clk_ret) {
3174 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
3175 goto failure;
3176 }
8d318a50
LW		 3177
3178 /* Get IO for DMAC base address */
3179 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3180 if (!res)
3181 goto failure;
3182
3183 if (request_mem_region(res->start, resource_size(res),
3184 D40_NAME " I/O base") == NULL)
3185 goto failure;
3186
3187 virtbase = ioremap(res->start, resource_size(res));
3188 if (!virtbase)
3189 goto failure;
3190
f4b89764
LW		 3191 /* This is just a regular AMBA PrimeCell ID actually */
3192 for (pid = 0, i = 0; i < 4; i++)
3193 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3194 & 255) << (i * 8);
3195 for (cid = 0, i = 0; i < 4; i++)
3196 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3197 & 255) << (i * 8);
8d318a50 3198
f4b89764
LW		 3199 if (cid != AMBA_CID) {
3200 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
3201 goto failure;
3202 }
3203 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
6db5a8ba 3204 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
f4b89764
LW		 3205 AMBA_MANF_BITS(pid),
3206 AMBA_VENDOR_ST);
8d318a50
LW		 3207 goto failure;
3208 }
f4b89764
LW		 3209 /*
3210 * HW revision:
3211 * DB8500ed has revision 0
3212 * ? has revision 1
3213 * DB8500v1 has revision 2
3214 * DB8500v2 has revision 3
47db92f4
GB		 3215 * AP9540v1 has revision 4
3216 * DB8540v1 has revision 4
f4b89764
LW		 3217 */
3218 rev = AMBA_REV_BITS(pid);
8b2fe9b6
LJ		 3219 if (rev < 2) {
3220 d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
3221 goto failure;
3222 }
3ae0267f 3223
8d318a50 3224 /* The number of physical channels on this HW */
47db92f4
GB		 3225 if (plat_data->num_of_phy_chans)
3226 num_phy_chans = plat_data->num_of_phy_chans;
3227 else
3228 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
8d318a50 3229
a7dacb68
LJ		 3230 /* The number of channels used for memcpy */
3231 if (plat_data->num_of_memcpy_chans)
3232 num_memcpy_chans = plat_data->num_of_memcpy_chans;
3233 else
3234 num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
3235
db72da92
LJ		 3236 num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
3237
b2abb249 3238 dev_info(&pdev->dev,
3a919d5b
FE		 3239 "hardware rev: %d @ %pa with %d physical and %d logical channels\n",
3240 rev, &res->start, num_phy_chans, num_log_chans);
8d318a50 3241
8d318a50 3242 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
a7dacb68 3243 (num_phy_chans + num_log_chans + num_memcpy_chans) *
8d318a50
LW		 3244 sizeof(struct d40_chan), GFP_KERNEL);
3245
3246 if (base == NULL) {
6db5a8ba 3247 d40_err(&pdev->dev, "Out of memory\n");
8d318a50
LW		 3248 goto failure;
3249 }
3250
3ae0267f 3251 base->rev = rev;
8d318a50 3252 base->clk = clk;
a7dacb68 3253 base->num_memcpy_chans = num_memcpy_chans;
8d318a50
LW		 3254 base->num_phy_chans = num_phy_chans;
3255 base->num_log_chans = num_log_chans;
3256 base->phy_start = res->start;
3257 base->phy_size = resource_size(res);
3258 base->virtbase = virtbase;
3259 base->plat_data = plat_data;
3260 base->dev = &pdev->dev;
3261 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3262 base->log_chans = &base->phy_chans[num_phy_chans];
3263
3cb645dc
TL		 3264 if (base->plat_data->num_of_phy_chans == 14) {
3265 base->gen_dmac.backup = d40_backup_regs_v4b;
3266 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3267 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3268 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3269 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3270 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3271 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3272 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3273 base->gen_dmac.il = il_v4b;
3274 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3275 base->gen_dmac.init_reg = dma_init_reg_v4b;
3276 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3277 } else {
3278 if (base->rev >= 3) {
3279 base->gen_dmac.backup = d40_backup_regs_v4a;
3280 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3281 }
3282 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3283 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3284 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3285 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3286 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3287 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3288 base->gen_dmac.il = il_v4a;
3289 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3290 base->gen_dmac.init_reg = dma_init_reg_v4a;
3291 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3292 }
3293
8d318a50
LW		 3294 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
3295 GFP_KERNEL);
3296 if (!base->phy_res)
3297 goto failure;
3298
3299 base->lookup_phy_chans = kzalloc(num_phy_chans *
3300 sizeof(struct d40_chan *),
3301 GFP_KERNEL);
3302 if (!base->lookup_phy_chans)
3303 goto failure;
3304
8a59fed3
LJ		 3305 base->lookup_log_chans = kzalloc(num_log_chans *
3306 sizeof(struct d40_chan *),
3307 GFP_KERNEL);
3308 if (!base->lookup_log_chans)
3309 goto failure;
698e4732 3310
7fb3e75e
N		 3311 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3312 sizeof(d40_backup_regs_chan),
8d318a50 3313 GFP_KERNEL);
7fb3e75e
N		 3314 if (!base->reg_val_backup_chan)
3315 goto failure;
3316
3317 base->lcla_pool.alloc_map =
3318 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
3319 * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
8d318a50
LW		 3320 if (!base->lcla_pool.alloc_map)
3321 goto failure;
3322
c675b1b4
JA		 3323 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3324 0, SLAB_HWCACHE_ALIGN,
3325 NULL);
3326 if (base->desc_slab == NULL)
3327 goto failure;
3328
8d318a50
LW		 3329 return base;
3330
3331failure:
b707c658
UH		 3332 if (!clk_ret)
3333 clk_disable_unprepare(clk);
3334 if (!IS_ERR(clk))
8d318a50 3335 clk_put(clk);
8d318a50
LW		 3336 if (virtbase)
3337 iounmap(virtbase);
3338 if (res)
3339 release_mem_region(res->start,
3340 resource_size(res));
3341 if (virtbase)
3342 iounmap(virtbase);
3343
3344 if (base) {
3345 kfree(base->lcla_pool.alloc_map);
1bdae6f4 3346 kfree(base->reg_val_backup_chan);
8d318a50
LW		 3347 kfree(base->lookup_log_chans);
3348 kfree(base->lookup_phy_chans);
3349 kfree(base->phy_res);
3350 kfree(base);
3351 }
3352
3353 return NULL;
3354}
3355
3356static void __init d40_hw_init(struct d40_base *base)
3357{
3358
8d318a50
LW		 3359 int i;
3360 u32 prmseo[2] = {0, 0};
3361 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3362 u32 pcmis = 0;
3363 u32 pcicr = 0;
3cb645dc
TL		 3364 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3365 u32 reg_size = base->gen_dmac.init_reg_size;
8d318a50 3366
3cb645dc 3367 for (i = 0; i < reg_size; i++)
8d318a50
LW		 3368 writel(dma_init_reg[i].val,
3369 base->virtbase + dma_init_reg[i].reg);
3370
3371 /* Configure all our dma channels to default settings */
3372 for (i = 0; i < base->num_phy_chans; i++) {
3373
3374 activeo[i % 2] = activeo[i % 2] << 2;
3375
3376 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3377 == D40_ALLOC_PHY) {
3378 activeo[i % 2] |= 3;
3379 continue;
3380 }
3381
3382 /* Enable interrupt # */
3383 pcmis = (pcmis << 1) | 1;
3384
3385 /* Clear interrupt # */
3386 pcicr = (pcicr << 1) | 1;
3387
3388 /* Set channel to physical mode */
3389 prmseo[i % 2] = prmseo[i % 2] << 2;
3390 prmseo[i % 2] |= 1;
3391
3392 }
3393
3394 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3395 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3396 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3397 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3398
3399 /* Write which interrupt to enable */
3cb645dc 3400 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
8d318a50
LW		 3401
3402 /* Write which interrupt to clear */
3cb645dc 3403 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
8d318a50 3404
3cb645dc
TL		 3405 /* These are __initdata and cannot be accessed after init */
3406 base->gen_dmac.init_reg = NULL;
3407 base->gen_dmac.init_reg_size = 0;
8d318a50
LW		 3408}
3409
508849ad
LW		 3410static int __init d40_lcla_allocate(struct d40_base *base)
3411{
026cbc42 3412 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 3413 unsigned long *page_list;
3414 int i, j;
3415 int ret = 0;
3416
3417 /*
3418 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3419 * To full fill this hardware requirement without wasting 256 kb
3420 * we allocate pages until we get an aligned one.
3421 */
3422 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3423 GFP_KERNEL);
3424
3425 if (!page_list) {
3426 ret = -ENOMEM;
3427 goto failure;
3428 }
3429
3430 /* Calculating how many pages that are required */
3431 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3432
3433 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3434 page_list[i] = __get_free_pages(GFP_KERNEL,
3435 base->lcla_pool.pages);
3436 if (!page_list[i]) {
3437
6db5a8ba
RV		 3438 d40_err(base->dev, "Failed to allocate %d pages.\n",
3439 base->lcla_pool.pages);
508849ad
LW		 3440
3441 for (j = 0; j < i; j++)
3442 free_pages(page_list[j], base->lcla_pool.pages);
3443 goto failure;
3444 }
3445
3446 if ((virt_to_phys((void *)page_list[i]) &
3447 (LCLA_ALIGNMENT - 1)) == 0)
3448 break;
3449 }
3450
3451 for (j = 0; j < i; j++)
3452 free_pages(page_list[j], base->lcla_pool.pages);
3453
3454 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3455 base->lcla_pool.base = (void *)page_list[i];
3456 } else {
767a9675
JA		 3457 /*
3458 * After many attempts and no succees with finding the correct
3459 * alignment, try with allocating a big buffer.
3460 */
508849ad
LW		 3461 dev_warn(base->dev,
3462 "[%s] Failed to get %d pages @ 18 bit align.\n",
3463 __func__, base->lcla_pool.pages);
3464 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3465 base->num_phy_chans +
3466 LCLA_ALIGNMENT,
3467 GFP_KERNEL);
3468 if (!base->lcla_pool.base_unaligned) {
3469 ret = -ENOMEM;
3470 goto failure;
3471 }
3472
3473 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3474 LCLA_ALIGNMENT);
3475 }
3476
026cbc42
RV		 3477 pool->dma_addr = dma_map_single(base->dev, pool->base,
3478 SZ_1K * base->num_phy_chans,
3479 DMA_TO_DEVICE);
3480 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3481 pool->dma_addr = 0;
3482 ret = -ENOMEM;
3483 goto failure;
3484 }
3485
508849ad
LW		 3486 writel(virt_to_phys(base->lcla_pool.base),
3487 base->virtbase + D40_DREG_LCLA);
3488failure:
3489 kfree(page_list);
3490 return ret;
3491}
3492
1814a170
LJ		 3493static int __init d40_of_probe(struct platform_device *pdev,
3494 struct device_node *np)
3495{
3496 struct stedma40_platform_data *pdata;
499c2bc3 3497 int num_phy = 0, num_memcpy = 0, num_disabled = 0;
cbbe13ea 3498 const __be32 *list;
1814a170
LJ		 3499
3500 pdata = devm_kzalloc(&pdev->dev,
3501 sizeof(struct stedma40_platform_data),
3502 GFP_KERNEL);
3503 if (!pdata)
3504 return -ENOMEM;
3505
fd59f9e6
LJ		 3506 /* If absent this value will be obtained from h/w. */
3507 of_property_read_u32(np, "dma-channels", &num_phy);
3508 if (num_phy > 0)
3509 pdata->num_of_phy_chans = num_phy;
3510
a7dacb68
LJ		 3511 list = of_get_property(np, "memcpy-channels", &num_memcpy);
3512 num_memcpy /= sizeof(*list);
3513
3514 if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
3515 d40_err(&pdev->dev,
3516 "Invalid number of memcpy channels specified (%d)\n",
3517 num_memcpy);
3518 return -EINVAL;
3519 }
3520 pdata->num_of_memcpy_chans = num_memcpy;
3521
3522 of_property_read_u32_array(np, "memcpy-channels",
3523 dma40_memcpy_channels,
3524 num_memcpy);
3525
499c2bc3
LJ		 3526 list = of_get_property(np, "disabled-channels", &num_disabled);
3527 num_disabled /= sizeof(*list);
3528
5be2190a 3529 if (num_disabled >= STEDMA40_MAX_PHYS || num_disabled < 0) {
499c2bc3
LJ		 3530 d40_err(&pdev->dev,
3531 "Invalid number of disabled channels specified (%d)\n",
3532 num_disabled);
3533 return -EINVAL;
3534 }
3535
3536 of_property_read_u32_array(np, "disabled-channels",
3537 pdata->disabled_channels,
3538 num_disabled);
3539 pdata->disabled_channels[num_disabled] = -1;
3540
1814a170
LJ		 3541 pdev->dev.platform_data = pdata;
3542
3543 return 0;
3544}
3545
8d318a50
LW		 3546static int __init d40_probe(struct platform_device *pdev)
3547{
d4adcc01 3548 struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
1814a170 3549 struct device_node *np = pdev->dev.of_node;
8d318a50 3550 int ret = -ENOENT;
1814a170 3551 struct d40_base *base = NULL;
8d318a50
LW		 3552 struct resource *res = NULL;
3553 int num_reserved_chans;
3554 u32 val;
3555
1814a170
LJ		 3556 if (!plat_data) {
3557 if (np) {
3558 if(d40_of_probe(pdev, np)) {
3559 ret = -ENOMEM;
3560 goto failure;
3561 }
3562 } else {
3563 d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
3564 goto failure;
3565 }
3566 }
8d318a50 3567
1814a170 3568 base = d40_hw_detect_init(pdev);
8d318a50
LW		 3569 if (!base)
3570 goto failure;
3571
3572 num_reserved_chans = d40_phy_res_init(base);
3573
3574 platform_set_drvdata(pdev, base);
3575
3576 spin_lock_init(&base->interrupt_lock);
3577 spin_lock_init(&base->execmd_lock);
3578
3579 /* Get IO for logical channel parameter address */
3580 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3581 if (!res) {
3582 ret = -ENOENT;
6db5a8ba 3583 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 3584 goto failure;
3585 }
3586 base->lcpa_size = resource_size(res);
3587 base->phy_lcpa = res->start;
3588
3589 if (request_mem_region(res->start, resource_size(res),
3590 D40_NAME " I/O lcpa") == NULL) {
3591 ret = -EBUSY;
3a919d5b 3592 d40_err(&pdev->dev, "Failed to request LCPA region %pR\n", res);
8d318a50
LW		 3593 goto failure;
3594 }
3595
3596 /* We make use of ESRAM memory for this. */
3597 val = readl(base->virtbase + D40_DREG_LCPA);
3598 if (res->start != val && val != 0) {
3599 dev_warn(&pdev->dev,
3a919d5b
FE		 3600 "[%s] Mismatch LCPA dma 0x%x, def %pa\n",
3601 __func__, val, &res->start);
8d318a50
LW		 3602 } else
3603 writel(res->start, base->virtbase + D40_DREG_LCPA);
3604
3605 base->lcpa_base = ioremap(res->start, resource_size(res));
3606 if (!base->lcpa_base) {
3607 ret = -ENOMEM;
6db5a8ba 3608 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 3609 goto failure;
3610 }
28c7a19d
N		 3611 /* If lcla has to be located in ESRAM we don't need to allocate */
3612 if (base->plat_data->use_esram_lcla) {
3613 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3614 "lcla_esram");
3615 if (!res) {
3616 ret = -ENOENT;
3617 d40_err(&pdev->dev,
3618 "No \"lcla_esram\" memory resource\n");
3619 goto failure;
3620 }
3621 base->lcla_pool.base = ioremap(res->start,
3622 resource_size(res));
3623 if (!base->lcla_pool.base) {
3624 ret = -ENOMEM;
3625 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3626 goto failure;
3627 }
3628 writel(res->start, base->virtbase + D40_DREG_LCLA);
8d318a50 3629
28c7a19d
N		 3630 } else {
3631 ret = d40_lcla_allocate(base);
3632 if (ret) {
3633 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3634 goto failure;
3635 }
8d318a50
LW		 3636 }
3637
3638 spin_lock_init(&base->lcla_pool.lock);
3639
8d318a50
LW		 3640 base->irq = platform_get_irq(pdev, 0);
3641
3642 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 3643 if (ret) {
6db5a8ba 3644 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 3645 goto failure;
3646 }
3647
7fb3e75e
N		 3648 pm_runtime_irq_safe(base->dev);
3649 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3650 pm_runtime_use_autosuspend(base->dev);
3651 pm_runtime_enable(base->dev);
3652 pm_runtime_resume(base->dev);
28c7a19d
N		 3653
3654 if (base->plat_data->use_esram_lcla) {
3655
3656 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3657 if (IS_ERR(base->lcpa_regulator)) {
3658 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
8581bbcd 3659 ret = PTR_ERR(base->lcpa_regulator);
28c7a19d
N		 3660 base->lcpa_regulator = NULL;
3661 goto failure;
3662 }
3663
3664 ret = regulator_enable(base->lcpa_regulator);
3665 if (ret) {
3666 d40_err(&pdev->dev,
3667 "Failed to enable lcpa_regulator\n");
3668 regulator_put(base->lcpa_regulator);
3669 base->lcpa_regulator = NULL;
3670 goto failure;
3671 }
3672 }
3673
7fb3e75e 3674 base->initialized = true;
8581bbcd
WY		 3675 ret = d40_dmaengine_init(base, num_reserved_chans);
3676 if (ret)
8d318a50
LW		 3677 goto failure;
3678
b96710e5 3679 base->dev->dma_parms = &base->dma_parms;
8581bbcd
WY		 3680 ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3681 if (ret) {
b96710e5
PF		 3682 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3683 goto failure;
3684 }
3685
8d318a50
LW		 3686 d40_hw_init(base);
3687
fa332de5 3688 if (np) {
8581bbcd
WY		 3689 ret = of_dma_controller_register(np, d40_xlate, NULL);
3690 if (ret)
fa332de5
LJ		 3691 dev_err(&pdev->dev,
3692 "could not register of_dma_controller\n");
3693 }
3694
8d318a50
LW		 3695 dev_info(base->dev, "initialized\n");
3696 return 0;
3697
3698failure:
3699 if (base) {
c675b1b4
JA		 3700 if (base->desc_slab)
3701 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 3702 if (base->virtbase)
3703 iounmap(base->virtbase);
026cbc42 3704
28c7a19d
N		 3705 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3706 iounmap(base->lcla_pool.base);
3707 base->lcla_pool.base = NULL;
3708 }
3709
026cbc42
RV		 3710 if (base->lcla_pool.dma_addr)
3711 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3712 SZ_1K * base->num_phy_chans,
3713 DMA_TO_DEVICE);
3714
508849ad
LW		 3715 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3716 free_pages((unsigned long)base->lcla_pool.base,
3717 base->lcla_pool.pages);
767a9675
JA		 3718
3719 kfree(base->lcla_pool.base_unaligned);
3720
8d318a50
LW		 3721 if (base->phy_lcpa)
3722 release_mem_region(base->phy_lcpa,
3723 base->lcpa_size);
3724 if (base->phy_start)
3725 release_mem_region(base->phy_start,
3726 base->phy_size);
3727 if (base->clk) {
da2ac56a 3728 clk_disable_unprepare(base->clk);
8d318a50
LW		 3729 clk_put(base->clk);
3730 }
3731
28c7a19d
N		 3732 if (base->lcpa_regulator) {
3733 regulator_disable(base->lcpa_regulator);
3734 regulator_put(base->lcpa_regulator);
3735 }
3736
8d318a50
LW		 3737 kfree(base->lcla_pool.alloc_map);
3738 kfree(base->lookup_log_chans);
3739 kfree(base->lookup_phy_chans);
3740 kfree(base->phy_res);
3741 kfree(base);
3742 }
3743
6db5a8ba 3744 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 3745 return ret;
3746}
3747
1814a170
LJ		 3748static const struct of_device_id d40_match[] = {
3749 { .compatible = "stericsson,dma40", },
3750 {}
3751};
3752
8d318a50
LW		 3753static struct platform_driver d40_driver = {
3754 .driver = {
3755 .owner = THIS_MODULE,
3756 .name = D40_NAME,
7fb3e75e 3757 .pm = DMA40_PM_OPS,
1814a170 3758 .of_match_table = d40_match,
8d318a50
LW		 3759 },
3760};
3761
cb9ab2d8 3762static int __init stedma40_init(void)
8d318a50
LW		 3763{
3764 return platform_driver_probe(&d40_driver, d40_probe);
3765}
a0eb221a 3766subsys_initcall(stedma40_init);
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