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dma40: remove unnecessary casts
[mirror_ubuntu-hirsute-kernel.git] / drivers / dma / ste_dma40.c
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8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
9#include <linux/kernel.h>
10#include <linux/slab.h>
11#include <linux/dmaengine.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
698e4732 15#include <linux/err.h>
8d318a50
LW		 16
17#include <plat/ste_dma40.h>
18
19#include "ste_dma40_ll.h"
20
21#define D40_NAME "dma40"
22
23#define D40_PHY_CHAN -1
24
25/* For masking out/in 2 bit channel positions */
26#define D40_CHAN_POS(chan) (2 * (chan / 2))
27#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
28
29/* Maximum iterations taken before giving up suspending a channel */
30#define D40_SUSPEND_MAX_IT 500
31
508849ad
LW		 32/* Hardware requirement on LCLA alignment */
33#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 34
35/* Max number of links per event group */
36#define D40_LCLA_LINK_PER_EVENT_GRP 128
37#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
38
508849ad
LW		 39/* Attempts before giving up to trying to get pages that are aligned */
40#define MAX_LCLA_ALLOC_ATTEMPTS 256
41
42/* Bit markings for allocation map */
8d318a50
LW		 43#define D40_ALLOC_FREE (1 << 31)
44#define D40_ALLOC_PHY (1 << 30)
45#define D40_ALLOC_LOG_FREE 0
46
8d318a50 47/* Hardware designer of the block */
3ae0267f 48#define D40_HW_DESIGNER 0x8
8d318a50
LW		 49
50/**
51 * enum 40_command - The different commands and/or statuses.
52 *
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 */
58enum d40_command {
59 D40_DMA_STOP = 0,
60 D40_DMA_RUN = 1,
61 D40_DMA_SUSPEND_REQ = 2,
62 D40_DMA_SUSPENDED = 3
63};
64
65/**
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
67 *
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
b00f938c 71 * @dma_addr: DMA address, if mapped
8d318a50
LW		 72 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
73 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
74 * one buffer to one buffer.
75 */
76struct d40_lli_pool {
77 void *base;
508849ad 78 int size;
b00f938c 79 dma_addr_t dma_addr;
8d318a50 80 /* Space for dst and src, plus an extra for padding */
508849ad 81 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 82};
83
84/**
85 * struct d40_desc - A descriptor is one DMA job.
86 *
87 * @lli_phy: LLI settings for physical channel. Both src and dst=
88 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
89 * lli_len equals one.
90 * @lli_log: Same as above but for logical channels.
91 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 92 * @lli_len: Number of llis of current descriptor.
698e4732
JA		 93 * @lli_current: Number of transfered llis.
94 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 95 * @txd: DMA engine struct. Used for among other things for communication
96 * during a transfer.
97 * @node: List entry.
8d318a50 98 * @is_in_client_list: true if the client owns this descriptor.
aa182ae2 99 * the previous one.
8d318a50
LW		 100 *
101 * This descriptor is used for both logical and physical transfers.
102 */
8d318a50
LW		 103struct d40_desc {
104 /* LLI physical */
105 struct d40_phy_lli_bidir lli_phy;
106 /* LLI logical */
107 struct d40_log_lli_bidir lli_log;
108
109 struct d40_lli_pool lli_pool;
941b77a3 110 int lli_len;
698e4732
JA		 111 int lli_current;
112 int lcla_alloc;
8d318a50
LW		 113
114 struct dma_async_tx_descriptor txd;
115 struct list_head node;
116
8d318a50
LW		 117 bool is_in_client_list;
118};
119
120/**
121 * struct d40_lcla_pool - LCLA pool settings and data.
122 *
508849ad
LW		 123 * @base: The virtual address of LCLA. 18 bit aligned.
124 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
125 * This pointer is only there for clean-up on error.
126 * @pages: The number of pages needed for all physical channels.
127 * Only used later for clean-up on error
8d318a50 128 * @lock: Lock to protect the content in this struct.
698e4732 129 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 130 */
131struct d40_lcla_pool {
132 void *base;
026cbc42 133 dma_addr_t dma_addr;
508849ad
LW		 134 void *base_unaligned;
135 int pages;
8d318a50 136 spinlock_t lock;
698e4732 137 struct d40_desc **alloc_map;
8d318a50
LW		 138};
139
140/**
141 * struct d40_phy_res - struct for handling eventlines mapped to physical
142 * channels.
143 *
144 * @lock: A lock protection this entity.
145 * @num: The physical channel number of this entity.
146 * @allocated_src: Bit mapped to show which src event line's are mapped to
147 * this physical channel. Can also be free or physically allocated.
148 * @allocated_dst: Same as for src but is dst.
149 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 150 * event line number.
8d318a50
LW		 151 */
152struct d40_phy_res {
153 spinlock_t lock;
154 int num;
155 u32 allocated_src;
156 u32 allocated_dst;
157};
158
159struct d40_base;
160
161/**
162 * struct d40_chan - Struct that describes a channel.
163 *
164 * @lock: A spinlock to protect this struct.
165 * @log_num: The logical number, if any of this channel.
166 * @completed: Starts with 1, after first interrupt it is set to dma engine's
167 * current cookie.
168 * @pending_tx: The number of pending transfers. Used between interrupt handler
169 * and tasklet.
170 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 171 * @phy_chan: Pointer to physical channel which this instance runs on. If this
172 * point is NULL, then the channel is not allocated.
8d318a50
LW		 173 * @chan: DMA engine handle.
174 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
175 * transfer and call client callback.
176 * @client: Cliented owned descriptor list.
177 * @active: Active descriptor.
178 * @queue: Queued jobs.
8d318a50 179 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 180 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
187 *
188 * This struct can either "be" a logical or a physical channel.
189 */
190struct d40_chan {
191 spinlock_t lock;
192 int log_num;
193 /* ID of the most recent completed transfer */
194 int completed;
195 int pending_tx;
196 bool busy;
197 struct d40_phy_res *phy_chan;
198 struct dma_chan chan;
199 struct tasklet_struct tasklet;
200 struct list_head client;
201 struct list_head active;
202 struct list_head queue;
8d318a50 203 struct stedma40_chan_cfg dma_cfg;
ce2ca125 204 bool configured;
8d318a50
LW		 205 struct d40_base *base;
206 /* Default register configurations */
207 u32 src_def_cfg;
208 u32 dst_def_cfg;
209 struct d40_def_lcsp log_def;
8d318a50 210 struct d40_log_lli_full *lcpa;
95e1400f
LW		 211 /* Runtime reconfiguration */
212 dma_addr_t runtime_addr;
213 enum dma_data_direction runtime_direction;
8d318a50
LW		 214};
215
216/**
217 * struct d40_base - The big global struct, one for each probe'd instance.
218 *
219 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220 * @execmd_lock: Lock for execute command usage since several channels share
221 * the same physical register.
222 * @dev: The device structure.
223 * @virtbase: The virtual base address of the DMA's register.
f4185592 224 * @rev: silicon revision detected.
8d318a50
LW		 225 * @clk: Pointer to the DMA clock structure.
226 * @phy_start: Physical memory start of the DMA registers.
227 * @phy_size: Size of the DMA register map.
228 * @irq: The IRQ number.
229 * @num_phy_chans: The number of physical channels. Read from HW. This
230 * is the number of available channels for this driver, not counting "Secure
231 * mode" allocated physical channels.
232 * @num_log_chans: The number of logical channels. Calculated from
233 * num_phy_chans.
234 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235 * @dma_slave: dma_device channels that can do only do slave transfers.
236 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
8d318a50
LW		 237 * @log_chans: Room for all possible logical channels in system.
238 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
239 * to log_chans entries.
240 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
241 * to phy_chans entries.
242 * @plat_data: Pointer to provided platform_data which is the driver
243 * configuration.
244 * @phy_res: Vector containing all physical channels.
245 * @lcla_pool: lcla pool settings and data.
246 * @lcpa_base: The virtual mapped address of LCPA.
247 * @phy_lcpa: The physical address of the LCPA.
248 * @lcpa_size: The size of the LCPA area.
c675b1b4 249 * @desc_slab: cache for descriptors.
8d318a50
LW		 250 */
251struct d40_base {
252 spinlock_t interrupt_lock;
253 spinlock_t execmd_lock;
254 struct device *dev;
255 void __iomem *virtbase;
f4185592 256 u8 rev:4;
8d318a50
LW		 257 struct clk *clk;
258 phys_addr_t phy_start;
259 resource_size_t phy_size;
260 int irq;
261 int num_phy_chans;
262 int num_log_chans;
263 struct dma_device dma_both;
264 struct dma_device dma_slave;
265 struct dma_device dma_memcpy;
266 struct d40_chan *phy_chans;
267 struct d40_chan *log_chans;
268 struct d40_chan **lookup_log_chans;
269 struct d40_chan **lookup_phy_chans;
270 struct stedma40_platform_data *plat_data;
271 /* Physical half channels */
272 struct d40_phy_res *phy_res;
273 struct d40_lcla_pool lcla_pool;
274 void *lcpa_base;
275 dma_addr_t phy_lcpa;
276 resource_size_t lcpa_size;
c675b1b4 277 struct kmem_cache *desc_slab;
8d318a50
LW		 278};
279
280/**
281 * struct d40_interrupt_lookup - lookup table for interrupt handler
282 *
283 * @src: Interrupt mask register.
284 * @clr: Interrupt clear register.
285 * @is_error: true if this is an error interrupt.
286 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
287 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
288 */
289struct d40_interrupt_lookup {
290 u32 src;
291 u32 clr;
292 bool is_error;
293 int offset;
294};
295
296/**
297 * struct d40_reg_val - simple lookup struct
298 *
299 * @reg: The register.
300 * @val: The value that belongs to the register in reg.
301 */
302struct d40_reg_val {
303 unsigned int reg;
304 unsigned int val;
305};
306
262d2915
RV		 307static struct device *chan2dev(struct d40_chan *d40c)
308{
309 return &d40c->chan.dev->device;
310}
311
724a8577
RV		 312static bool chan_is_physical(struct d40_chan *chan)
313{
314 return chan->log_num == D40_PHY_CHAN;
315}
316
317static bool chan_is_logical(struct d40_chan *chan)
318{
319 return !chan_is_physical(chan);
320}
321
8ca84687
RV		 322static void __iomem *chan_base(struct d40_chan *chan)
323{
324 return chan->base->virtbase + D40_DREG_PCBASE +
325 chan->phy_chan->num * D40_DREG_PCDELTA;
326}
327
6db5a8ba
RV		 328#define d40_err(dev, format, arg...) \
329 dev_err(dev, "[%s] " format, __func__, ## arg)
330
331#define chan_err(d40c, format, arg...) \
332 d40_err(chan2dev(d40c), format, ## arg)
333
b00f938c 334static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
8d318a50
LW		 335 int lli_len, bool is_log)
336{
337 u32 align;
338 void *base;
339
340 if (is_log)
341 align = sizeof(struct d40_log_lli);
342 else
343 align = sizeof(struct d40_phy_lli);
344
345 if (lli_len == 1) {
346 base = d40d->lli_pool.pre_alloc_lli;
347 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
348 d40d->lli_pool.base = NULL;
349 } else {
594ece4d 350 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 351
352 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
353 d40d->lli_pool.base = base;
354
355 if (d40d->lli_pool.base == NULL)
356 return -ENOMEM;
357 }
358
359 if (is_log) {
d924abad 360 d40d->lli_log.src = PTR_ALIGN(base, align);
594ece4d 361 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 362
363 d40d->lli_pool.dma_addr = 0;
8d318a50 364 } else {
d924abad 365 d40d->lli_phy.src = PTR_ALIGN(base, align);
594ece4d 366 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 367
368 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
369 d40d->lli_phy.src,
370 d40d->lli_pool.size,
371 DMA_TO_DEVICE);
372
373 if (dma_mapping_error(d40c->base->dev,
374 d40d->lli_pool.dma_addr)) {
375 kfree(d40d->lli_pool.base);
376 d40d->lli_pool.base = NULL;
377 d40d->lli_pool.dma_addr = 0;
378 return -ENOMEM;
379 }
8d318a50
LW		 380 }
381
382 return 0;
383}
384
b00f938c 385static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 386{
b00f938c
RV		 387 if (d40d->lli_pool.dma_addr)
388 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
389 d40d->lli_pool.size, DMA_TO_DEVICE);
390
8d318a50
LW		 391 kfree(d40d->lli_pool.base);
392 d40d->lli_pool.base = NULL;
393 d40d->lli_pool.size = 0;
394 d40d->lli_log.src = NULL;
395 d40d->lli_log.dst = NULL;
396 d40d->lli_phy.src = NULL;
397 d40d->lli_phy.dst = NULL;
8d318a50
LW		 398}
399
698e4732
JA		 400static int d40_lcla_alloc_one(struct d40_chan *d40c,
401 struct d40_desc *d40d)
402{
403 unsigned long flags;
404 int i;
405 int ret = -EINVAL;
406 int p;
407
408 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
409
410 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
411
412 /*
413 * Allocate both src and dst at the same time, therefore the half
414 * start on 1 since 0 can't be used since zero is used as end marker.
415 */
416 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
417 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
418 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
419 d40d->lcla_alloc++;
420 ret = i;
421 break;
422 }
423 }
424
425 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
426
427 return ret;
428}
429
430static int d40_lcla_free_all(struct d40_chan *d40c,
431 struct d40_desc *d40d)
432{
433 unsigned long flags;
434 int i;
435 int ret = -EINVAL;
436
724a8577 437 if (chan_is_physical(d40c))
698e4732
JA		 438 return 0;
439
440 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
441
442 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
443 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
444 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
445 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
446 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
447 d40d->lcla_alloc--;
448 if (d40d->lcla_alloc == 0) {
449 ret = 0;
450 break;
451 }
452 }
453 }
454
455 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
456
457 return ret;
458
459}
460
8d318a50
LW		 461static void d40_desc_remove(struct d40_desc *d40d)
462{
463 list_del(&d40d->node);
464}
465
466static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
467{
a2c15fa4 468 struct d40_desc *desc = NULL;
8d318a50
LW		 469
470 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 471 struct d40_desc *d;
472 struct d40_desc *_d;
473
8d318a50
LW		 474 list_for_each_entry_safe(d, _d, &d40c->client, node)
475 if (async_tx_test_ack(&d->txd)) {
b00f938c 476 d40_pool_lli_free(d40c, d);
8d318a50 477 d40_desc_remove(d);
a2c15fa4
RV		 478 desc = d;
479 memset(desc, 0, sizeof(*desc));
c675b1b4 480 break;
8d318a50 481 }
8d318a50 482 }
a2c15fa4
RV		 483
484 if (!desc)
485 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
486
487 if (desc)
488 INIT_LIST_HEAD(&desc->node);
489
490 return desc;
8d318a50
LW		 491}
492
493static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
494{
698e4732 495
b00f938c 496 d40_pool_lli_free(d40c, d40d);
698e4732 497 d40_lcla_free_all(d40c, d40d);
c675b1b4 498 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 499}
500
501static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
502{
503 list_add_tail(&desc->node, &d40c->active);
504}
505
698e4732
JA		 506static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
507{
508 int curr_lcla = -EINVAL, next_lcla;
509
724a8577 510 if (chan_is_physical(d40c)) {
698e4732
JA		 511 d40_phy_lli_write(d40c->base->virtbase,
512 d40c->phy_chan->num,
513 d40d->lli_phy.dst,
514 d40d->lli_phy.src);
515 d40d->lli_current = d40d->lli_len;
516 } else {
517
518 if ((d40d->lli_len - d40d->lli_current) > 1)
519 curr_lcla = d40_lcla_alloc_one(d40c, d40d);
520
521 d40_log_lli_lcpa_write(d40c->lcpa,
522 &d40d->lli_log.dst[d40d->lli_current],
523 &d40d->lli_log.src[d40d->lli_current],
524 curr_lcla);
525
526 d40d->lli_current++;
527 for (; d40d->lli_current < d40d->lli_len; d40d->lli_current++) {
026cbc42
RV		 528 unsigned int lcla_offset = d40c->phy_chan->num * 1024 +
529 8 * curr_lcla * 2;
530 struct d40_lcla_pool *pool = &d40c->base->lcla_pool;
531 struct d40_log_lli *lcla = pool->base + lcla_offset;
698e4732
JA		 532
533 if (d40d->lli_current + 1 < d40d->lli_len)
534 next_lcla = d40_lcla_alloc_one(d40c, d40d);
535 else
536 next_lcla = -EINVAL;
537
698e4732
JA		 538 d40_log_lli_lcla_write(lcla,
539 &d40d->lli_log.dst[d40d->lli_current],
540 &d40d->lli_log.src[d40d->lli_current],
541 next_lcla);
542
026cbc42
RV		 543 dma_sync_single_range_for_device(d40c->base->dev,
544 pool->dma_addr, lcla_offset,
545 2 * sizeof(struct d40_log_lli),
546 DMA_TO_DEVICE);
698e4732
JA		 547
548 curr_lcla = next_lcla;
549
550 if (curr_lcla == -EINVAL) {
551 d40d->lli_current++;
552 break;
553 }
554
555 }
556 }
557}
558
8d318a50
LW		 559static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
560{
561 struct d40_desc *d;
562
563 if (list_empty(&d40c->active))
564 return NULL;
565
566 d = list_first_entry(&d40c->active,
567 struct d40_desc,
568 node);
569 return d;
570}
571
572static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
573{
574 list_add_tail(&desc->node, &d40c->queue);
575}
576
577static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
578{
579 struct d40_desc *d;
580
581 if (list_empty(&d40c->queue))
582 return NULL;
583
584 d = list_first_entry(&d40c->queue,
585 struct d40_desc,
586 node);
587 return d;
588}
589
d49278e3
PF		 590static int d40_psize_2_burst_size(bool is_log, int psize)
591{
592 if (is_log) {
593 if (psize == STEDMA40_PSIZE_LOG_1)
594 return 1;
595 } else {
596 if (psize == STEDMA40_PSIZE_PHY_1)
597 return 1;
598 }
599
600 return 2 << psize;
601}
602
603/*
604 * The dma only supports transmitting packages up to
605 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
606 * dma elements required to send the entire sg list
607 */
608static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
609{
610 int dmalen;
611 u32 max_w = max(data_width1, data_width2);
612 u32 min_w = min(data_width1, data_width2);
613 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
614
615 if (seg_max > STEDMA40_MAX_SEG_SIZE)
616 seg_max -= (1 << max_w);
617
618 if (!IS_ALIGNED(size, 1 << max_w))
619 return -EINVAL;
620
621 if (size <= seg_max)
622 dmalen = 1;
623 else {
624 dmalen = size / seg_max;
625 if (dmalen * seg_max < size)
626 dmalen++;
627 }
628 return dmalen;
629}
630
631static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
632 u32 data_width1, u32 data_width2)
633{
634 struct scatterlist *sg;
635 int i;
636 int len = 0;
637 int ret;
638
639 for_each_sg(sgl, sg, sg_len, i) {
640 ret = d40_size_2_dmalen(sg_dma_len(sg),
641 data_width1, data_width2);
642 if (ret < 0)
643 return ret;
644 len += ret;
645 }
646 return len;
647}
8d318a50 648
d49278e3 649/* Support functions for logical channels */
8d318a50
LW		 650
651static int d40_channel_execute_command(struct d40_chan *d40c,
652 enum d40_command command)
653{
767a9675
JA		 654 u32 status;
655 int i;
8d318a50
LW		 656 void __iomem *active_reg;
657 int ret = 0;
658 unsigned long flags;
1d392a7b 659 u32 wmask;
8d318a50
LW		 660
661 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
662
663 if (d40c->phy_chan->num % 2 == 0)
664 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
665 else
666 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
667
668 if (command == D40_DMA_SUSPEND_REQ) {
669 status = (readl(active_reg) &
670 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
671 D40_CHAN_POS(d40c->phy_chan->num);
672
673 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
674 goto done;
675 }
676
1d392a7b
JA		 677 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
678 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
679 active_reg);
8d318a50
LW		 680
681 if (command == D40_DMA_SUSPEND_REQ) {
682
683 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
684 status = (readl(active_reg) &
685 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
686 D40_CHAN_POS(d40c->phy_chan->num);
687
688 cpu_relax();
689 /*
690 * Reduce the number of bus accesses while
691 * waiting for the DMA to suspend.
692 */
693 udelay(3);
694
695 if (status == D40_DMA_STOP ||
696 status == D40_DMA_SUSPENDED)
697 break;
698 }
699
700 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 701 chan_err(d40c,
702 "unable to suspend the chl %d (log: %d) status %x\n",
703 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 704 status);
705 dump_stack();
706 ret = -EBUSY;
707 }
708
709 }
710done:
711 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
712 return ret;
713}
714
715static void d40_term_all(struct d40_chan *d40c)
716{
717 struct d40_desc *d40d;
8d318a50
LW		 718
719 /* Release active descriptors */
720 while ((d40d = d40_first_active_get(d40c))) {
721 d40_desc_remove(d40d);
8d318a50
LW		 722 d40_desc_free(d40c, d40d);
723 }
724
725 /* Release queued descriptors waiting for transfer */
726 while ((d40d = d40_first_queued(d40c))) {
727 d40_desc_remove(d40d);
8d318a50
LW		 728 d40_desc_free(d40c, d40d);
729 }
730
8d318a50
LW		 731
732 d40c->pending_tx = 0;
733 d40c->busy = false;
734}
735
262d2915
RV		 736static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
737 u32 event, int reg)
738{
8ca84687 739 void __iomem *addr = chan_base(d40c) + reg;
262d2915
RV		 740 int tries;
741
742 if (!enable) {
743 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
744 | ~D40_EVENTLINE_MASK(event), addr);
745 return;
746 }
747
748 /*
749 * The hardware sometimes doesn't register the enable when src and dst
750 * event lines are active on the same logical channel. Retry to ensure
751 * it does. Usually only one retry is sufficient.
752 */
753 tries = 100;
754 while (--tries) {
755 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
756 | ~D40_EVENTLINE_MASK(event), addr);
757
758 if (readl(addr) & D40_EVENTLINE_MASK(event))
759 break;
760 }
761
762 if (tries != 99)
763 dev_dbg(chan2dev(d40c),
764 "[%s] workaround enable S%cLNK (%d tries)\n",
765 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
766 100 - tries);
767
768 WARN_ON(!tries);
769}
770
8d318a50
LW		 771static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
772{
8d318a50
LW		 773 unsigned long flags;
774
8d318a50
LW		 775 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
776
777 /* Enable event line connected to device (or memcpy) */
778 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
779 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
780 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
781
262d2915
RV		 782 __d40_config_set_event(d40c, do_enable, event,
783 D40_CHAN_REG_SSLNK);
8d318a50 784 }
262d2915 785
8d318a50
LW		 786 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
787 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
788
262d2915
RV		 789 __d40_config_set_event(d40c, do_enable, event,
790 D40_CHAN_REG_SDLNK);
8d318a50
LW		 791 }
792
793 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
794}
795
a5ebca47 796static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 797{
8ca84687 798 void __iomem *chanbase = chan_base(d40c);
be8cb7df 799 u32 val;
8d318a50 800
8ca84687
RV		 801 val = readl(chanbase + D40_CHAN_REG_SSLNK);
802 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 803
a5ebca47 804 return val;
8d318a50
LW		 805}
806
20a5b6d0
RV		 807static u32 d40_get_prmo(struct d40_chan *d40c)
808{
809 static const unsigned int phy_map[] = {
810 [STEDMA40_PCHAN_BASIC_MODE]
811 = D40_DREG_PRMO_PCHAN_BASIC,
812 [STEDMA40_PCHAN_MODULO_MODE]
813 = D40_DREG_PRMO_PCHAN_MODULO,
814 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
815 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
816 };
817 static const unsigned int log_map[] = {
818 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
819 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
820 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
821 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
822 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
823 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
824 };
825
724a8577 826 if (chan_is_physical(d40c))
20a5b6d0
RV		 827 return phy_map[d40c->dma_cfg.mode_opt];
828 else
829 return log_map[d40c->dma_cfg.mode_opt];
830}
831
b55912c6 832static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 833{
834 u32 addr_base;
835 u32 var;
8d318a50
LW		 836
837 /* Odd addresses are even addresses + 4 */
838 addr_base = (d40c->phy_chan->num % 2) * 4;
839 /* Setup channel mode to logical or physical */
724a8577 840 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 841 D40_CHAN_POS(d40c->phy_chan->num);
842 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
843
844 /* Setup operational mode option register */
20a5b6d0 845 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 846
847 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
848
724a8577 849 if (chan_is_logical(d40c)) {
8ca84687
RV		 850 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
851 & D40_SREG_ELEM_LOG_LIDX_MASK;
852 void __iomem *chanbase = chan_base(d40c);
853
8d318a50 854 /* Set default config for CFG reg */
8ca84687
RV		 855 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
856 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 857
b55912c6 858 /* Set LIDX for lcla */
8ca84687
RV		 859 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
860 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
8d318a50 861 }
8d318a50
LW		 862}
863
aa182ae2
JA		 864static u32 d40_residue(struct d40_chan *d40c)
865{
866 u32 num_elt;
867
724a8577 868 if (chan_is_logical(d40c))
aa182ae2
JA		 869 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
870 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 871 else {
872 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
873 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
874 >> D40_SREG_ELEM_PHY_ECNT_POS;
875 }
876
aa182ae2
JA		 877 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
878}
879
880static bool d40_tx_is_linked(struct d40_chan *d40c)
881{
882 bool is_link;
883
724a8577 884 if (chan_is_logical(d40c))
aa182ae2
JA		 885 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
886 else
8ca84687
RV		 887 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
888 & D40_SREG_LNK_PHYS_LNK_MASK;
889
aa182ae2
JA		 890 return is_link;
891}
892
893static int d40_pause(struct dma_chan *chan)
894{
895 struct d40_chan *d40c =
896 container_of(chan, struct d40_chan, chan);
897 int res = 0;
898 unsigned long flags;
899
3ac012af
JA		 900 if (!d40c->busy)
901 return 0;
902
aa182ae2
JA		 903 spin_lock_irqsave(&d40c->lock, flags);
904
905 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
906 if (res == 0) {
724a8577 907 if (chan_is_logical(d40c)) {
aa182ae2
JA		 908 d40_config_set_event(d40c, false);
909 /* Resume the other logical channels if any */
910 if (d40_chan_has_events(d40c))
911 res = d40_channel_execute_command(d40c,
912 D40_DMA_RUN);
913 }
914 }
915
916 spin_unlock_irqrestore(&d40c->lock, flags);
917 return res;
918}
919
920static int d40_resume(struct dma_chan *chan)
921{
922 struct d40_chan *d40c =
923 container_of(chan, struct d40_chan, chan);
924 int res = 0;
925 unsigned long flags;
926
3ac012af
JA		 927 if (!d40c->busy)
928 return 0;
929
aa182ae2
JA		 930 spin_lock_irqsave(&d40c->lock, flags);
931
932 if (d40c->base->rev == 0)
724a8577 933 if (chan_is_logical(d40c)) {
aa182ae2
JA		 934 res = d40_channel_execute_command(d40c,
935 D40_DMA_SUSPEND_REQ);
936 goto no_suspend;
937 }
938
939 /* If bytes left to transfer or linked tx resume job */
940 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
941
724a8577 942 if (chan_is_logical(d40c))
aa182ae2
JA		 943 d40_config_set_event(d40c, true);
944
945 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
946 }
947
948no_suspend:
949 spin_unlock_irqrestore(&d40c->lock, flags);
950 return res;
951}
952
8d318a50
LW		 953static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
954{
955 struct d40_chan *d40c = container_of(tx->chan,
956 struct d40_chan,
957 chan);
958 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
959 unsigned long flags;
960
961 spin_lock_irqsave(&d40c->lock, flags);
962
aa182ae2
JA		 963 d40c->chan.cookie++;
964
965 if (d40c->chan.cookie < 0)
966 d40c->chan.cookie = 1;
967
968 d40d->txd.cookie = d40c->chan.cookie;
969
8d318a50
LW		 970 d40_desc_queue(d40c, d40d);
971
972 spin_unlock_irqrestore(&d40c->lock, flags);
973
974 return tx->cookie;
975}
976
977static int d40_start(struct d40_chan *d40c)
978{
f4185592
LW		 979 if (d40c->base->rev == 0) {
980 int err;
981
724a8577 982 if (chan_is_logical(d40c)) {
f4185592
LW		 983 err = d40_channel_execute_command(d40c,
984 D40_DMA_SUSPEND_REQ);
985 if (err)
986 return err;
987 }
988 }
989
724a8577 990 if (chan_is_logical(d40c))
8d318a50 991 d40_config_set_event(d40c, true);
8d318a50 992
0c32269d 993 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 994}
995
996static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
997{
998 struct d40_desc *d40d;
999 int err;
1000
1001 /* Start queued jobs, if any */
1002 d40d = d40_first_queued(d40c);
1003
1004 if (d40d != NULL) {
1005 d40c->busy = true;
1006
1007 /* Remove from queue */
1008 d40_desc_remove(d40d);
1009
1010 /* Add to active queue */
1011 d40_desc_submit(d40c, d40d);
1012
7d83a854
RV		 1013 /* Initiate DMA job */
1014 d40_desc_load(d40c, d40d);
8d318a50 1015
7d83a854
RV		 1016 /* Start dma job */
1017 err = d40_start(d40c);
8d318a50 1018
7d83a854
RV		 1019 if (err)
1020 return NULL;
8d318a50
LW		 1021 }
1022
1023 return d40d;
1024}
1025
1026/* called from interrupt context */
1027static void dma_tc_handle(struct d40_chan *d40c)
1028{
1029 struct d40_desc *d40d;
1030
8d318a50
LW		 1031 /* Get first active entry from list */
1032 d40d = d40_first_active_get(d40c);
1033
1034 if (d40d == NULL)
1035 return;
1036
698e4732 1037 d40_lcla_free_all(d40c, d40d);
8d318a50 1038
698e4732 1039 if (d40d->lli_current < d40d->lli_len) {
8d318a50
LW		 1040 d40_desc_load(d40c, d40d);
1041 /* Start dma job */
1042 (void) d40_start(d40c);
1043 return;
1044 }
1045
1046 if (d40_queue_start(d40c) == NULL)
1047 d40c->busy = false;
1048
1049 d40c->pending_tx++;
1050 tasklet_schedule(&d40c->tasklet);
1051
1052}
1053
1054static void dma_tasklet(unsigned long data)
1055{
1056 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1057 struct d40_desc *d40d;
8d318a50
LW		 1058 unsigned long flags;
1059 dma_async_tx_callback callback;
1060 void *callback_param;
1061
1062 spin_lock_irqsave(&d40c->lock, flags);
1063
1064 /* Get first active entry from list */
767a9675 1065 d40d = d40_first_active_get(d40c);
8d318a50 1066
767a9675 1067 if (d40d == NULL)
8d318a50
LW		 1068 goto err;
1069
767a9675 1070 d40c->completed = d40d->txd.cookie;
8d318a50
LW		 1071
1072 /*
1073 * If terminating a channel pending_tx is set to zero.
1074 * This prevents any finished active jobs to return to the client.
1075 */
1076 if (d40c->pending_tx == 0) {
1077 spin_unlock_irqrestore(&d40c->lock, flags);
1078 return;
1079 }
1080
1081 /* Callback to client */
767a9675
JA		 1082 callback = d40d->txd.callback;
1083 callback_param = d40d->txd.callback_param;
1084
1085 if (async_tx_test_ack(&d40d->txd)) {
b00f938c 1086 d40_pool_lli_free(d40c, d40d);
767a9675
JA		 1087 d40_desc_remove(d40d);
1088 d40_desc_free(d40c, d40d);
8d318a50 1089 } else {
767a9675
JA		 1090 if (!d40d->is_in_client_list) {
1091 d40_desc_remove(d40d);
698e4732 1092 d40_lcla_free_all(d40c, d40d);
767a9675
JA		 1093 list_add_tail(&d40d->node, &d40c->client);
1094 d40d->is_in_client_list = true;
8d318a50
LW		 1095 }
1096 }
1097
1098 d40c->pending_tx--;
1099
1100 if (d40c->pending_tx)
1101 tasklet_schedule(&d40c->tasklet);
1102
1103 spin_unlock_irqrestore(&d40c->lock, flags);
1104
767a9675 1105 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
8d318a50
LW		 1106 callback(callback_param);
1107
1108 return;
1109
1110 err:
1111 /* Rescue manouver if receiving double interrupts */
1112 if (d40c->pending_tx > 0)
1113 d40c->pending_tx--;
1114 spin_unlock_irqrestore(&d40c->lock, flags);
1115}
1116
1117static irqreturn_t d40_handle_interrupt(int irq, void *data)
1118{
1119 static const struct d40_interrupt_lookup il[] = {
1120 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1121 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1122 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1123 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1124 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1125 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1126 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1127 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1128 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1129 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1130 };
1131
1132 int i;
1133 u32 regs[ARRAY_SIZE(il)];
8d318a50
LW		 1134 u32 idx;
1135 u32 row;
1136 long chan = -1;
1137 struct d40_chan *d40c;
1138 unsigned long flags;
1139 struct d40_base *base = data;
1140
1141 spin_lock_irqsave(&base->interrupt_lock, flags);
1142
1143 /* Read interrupt status of both logical and physical channels */
1144 for (i = 0; i < ARRAY_SIZE(il); i++)
1145 regs[i] = readl(base->virtbase + il[i].src);
1146
1147 for (;;) {
1148
1149 chan = find_next_bit((unsigned long *)regs,
1150 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1151
1152 /* No more set bits found? */
1153 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1154 break;
1155
1156 row = chan / BITS_PER_LONG;
1157 idx = chan & (BITS_PER_LONG - 1);
1158
1159 /* ACK interrupt */
1b00348d 1160 writel(1 << idx, base->virtbase + il[row].clr);
8d318a50
LW		 1161
1162 if (il[row].offset == D40_PHY_CHAN)
1163 d40c = base->lookup_phy_chans[idx];
1164 else
1165 d40c = base->lookup_log_chans[il[row].offset + idx];
1166 spin_lock(&d40c->lock);
1167
1168 if (!il[row].is_error)
1169 dma_tc_handle(d40c);
1170 else
6db5a8ba
RV		 1171 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1172 chan, il[row].offset, idx);
8d318a50
LW		 1173
1174 spin_unlock(&d40c->lock);
1175 }
1176
1177 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1178
1179 return IRQ_HANDLED;
1180}
1181
8d318a50
LW		 1182static int d40_validate_conf(struct d40_chan *d40c,
1183 struct stedma40_chan_cfg *conf)
1184{
1185 int res = 0;
1186 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1187 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
38bdbf02 1188 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1189
0747c7ba 1190 if (!conf->dir) {
6db5a8ba 1191 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1192 res = -EINVAL;
1193 }
1194
1195 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1196 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1197 d40c->runtime_addr == 0) {
1198
6db5a8ba
RV		 1199 chan_err(d40c, "Invalid TX channel address (%d)\n",
1200 conf->dst_dev_type);
0747c7ba
LW		 1201 res = -EINVAL;
1202 }
1203
1204 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1205 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1206 d40c->runtime_addr == 0) {
6db5a8ba
RV		 1207 chan_err(d40c, "Invalid RX channel address (%d)\n",
1208 conf->src_dev_type);
0747c7ba
LW		 1209 res = -EINVAL;
1210 }
1211
1212 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
8d318a50 1213 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
6db5a8ba 1214 chan_err(d40c, "Invalid dst\n");
8d318a50
LW		 1215 res = -EINVAL;
1216 }
1217
0747c7ba 1218 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
8d318a50 1219 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
6db5a8ba 1220 chan_err(d40c, "Invalid src\n");
8d318a50
LW		 1221 res = -EINVAL;
1222 }
1223
1224 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1225 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
6db5a8ba 1226 chan_err(d40c, "No event line\n");
8d318a50
LW		 1227 res = -EINVAL;
1228 }
1229
1230 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1231 (src_event_group != dst_event_group)) {
6db5a8ba 1232 chan_err(d40c, "Invalid event group\n");
8d318a50
LW		 1233 res = -EINVAL;
1234 }
1235
1236 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1237 /*
1238 * DMAC HW supports it. Will be added to this driver,
1239 * in case any dma client requires it.
1240 */
6db5a8ba 1241 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1242 res = -EINVAL;
1243 }
1244
d49278e3
PF		 1245 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1246 (1 << conf->src_info.data_width) !=
1247 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1248 (1 << conf->dst_info.data_width)) {
1249 /*
1250 * The DMAC hardware only supports
1251 * src (burst x width) == dst (burst x width)
1252 */
1253
6db5a8ba 1254 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1255 res = -EINVAL;
1256 }
1257
8d318a50
LW		 1258 return res;
1259}
1260
1261static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
4aed79b2 1262 int log_event_line, bool is_log)
8d318a50
LW		 1263{
1264 unsigned long flags;
1265 spin_lock_irqsave(&phy->lock, flags);
4aed79b2 1266 if (!is_log) {
8d318a50
LW		 1267 /* Physical interrupts are masked per physical full channel */
1268 if (phy->allocated_src == D40_ALLOC_FREE &&
1269 phy->allocated_dst == D40_ALLOC_FREE) {
1270 phy->allocated_dst = D40_ALLOC_PHY;
1271 phy->allocated_src = D40_ALLOC_PHY;
1272 goto found;
1273 } else
1274 goto not_found;
1275 }
1276
1277 /* Logical channel */
1278 if (is_src) {
1279 if (phy->allocated_src == D40_ALLOC_PHY)
1280 goto not_found;
1281
1282 if (phy->allocated_src == D40_ALLOC_FREE)
1283 phy->allocated_src = D40_ALLOC_LOG_FREE;
1284
1285 if (!(phy->allocated_src & (1 << log_event_line))) {
1286 phy->allocated_src |= 1 << log_event_line;
1287 goto found;
1288 } else
1289 goto not_found;
1290 } else {
1291 if (phy->allocated_dst == D40_ALLOC_PHY)
1292 goto not_found;
1293
1294 if (phy->allocated_dst == D40_ALLOC_FREE)
1295 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1296
1297 if (!(phy->allocated_dst & (1 << log_event_line))) {
1298 phy->allocated_dst |= 1 << log_event_line;
1299 goto found;
1300 } else
1301 goto not_found;
1302 }
1303
1304not_found:
1305 spin_unlock_irqrestore(&phy->lock, flags);
1306 return false;
1307found:
1308 spin_unlock_irqrestore(&phy->lock, flags);
1309 return true;
1310}
1311
1312static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1313 int log_event_line)
1314{
1315 unsigned long flags;
1316 bool is_free = false;
1317
1318 spin_lock_irqsave(&phy->lock, flags);
1319 if (!log_event_line) {
8d318a50
LW		 1320 phy->allocated_dst = D40_ALLOC_FREE;
1321 phy->allocated_src = D40_ALLOC_FREE;
1322 is_free = true;
1323 goto out;
1324 }
1325
1326 /* Logical channel */
1327 if (is_src) {
1328 phy->allocated_src &= ~(1 << log_event_line);
1329 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1330 phy->allocated_src = D40_ALLOC_FREE;
1331 } else {
1332 phy->allocated_dst &= ~(1 << log_event_line);
1333 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1334 phy->allocated_dst = D40_ALLOC_FREE;
1335 }
1336
1337 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1338 D40_ALLOC_FREE);
1339
1340out:
1341 spin_unlock_irqrestore(&phy->lock, flags);
1342
1343 return is_free;
1344}
1345
1346static int d40_allocate_channel(struct d40_chan *d40c)
1347{
1348 int dev_type;
1349 int event_group;
1350 int event_line;
1351 struct d40_phy_res *phys;
1352 int i;
1353 int j;
1354 int log_num;
1355 bool is_src;
38bdbf02 1356 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1357
1358 phys = d40c->base->phy_res;
1359
1360 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1361 dev_type = d40c->dma_cfg.src_dev_type;
1362 log_num = 2 * dev_type;
1363 is_src = true;
1364 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1365 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1366 /* dst event lines are used for logical memcpy */
1367 dev_type = d40c->dma_cfg.dst_dev_type;
1368 log_num = 2 * dev_type + 1;
1369 is_src = false;
1370 } else
1371 return -EINVAL;
1372
1373 event_group = D40_TYPE_TO_GROUP(dev_type);
1374 event_line = D40_TYPE_TO_EVENT(dev_type);
1375
1376 if (!is_log) {
1377 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1378 /* Find physical half channel */
1379 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1380
4aed79b2
MM		 1381 if (d40_alloc_mask_set(&phys[i], is_src,
1382 0, is_log))
8d318a50
LW		 1383 goto found_phy;
1384 }
1385 } else
1386 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1387 int phy_num = j + event_group * 2;
1388 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1389 if (d40_alloc_mask_set(&phys[i],
1390 is_src,
1391 0,
1392 is_log))
8d318a50
LW		 1393 goto found_phy;
1394 }
1395 }
1396 return -EINVAL;
1397found_phy:
1398 d40c->phy_chan = &phys[i];
1399 d40c->log_num = D40_PHY_CHAN;
1400 goto out;
1401 }
1402 if (dev_type == -1)
1403 return -EINVAL;
1404
1405 /* Find logical channel */
1406 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1407 int phy_num = j + event_group * 2;
1408 /*
1409 * Spread logical channels across all available physical rather
1410 * than pack every logical channel at the first available phy
1411 * channels.
1412 */
1413 if (is_src) {
1414 for (i = phy_num; i < phy_num + 2; i++) {
1415 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1416 event_line, is_log))
8d318a50
LW		 1417 goto found_log;
1418 }
1419 } else {
1420 for (i = phy_num + 1; i >= phy_num; i--) {
1421 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1422 event_line, is_log))
8d318a50
LW		 1423 goto found_log;
1424 }
1425 }
1426 }
1427 return -EINVAL;
1428
1429found_log:
1430 d40c->phy_chan = &phys[i];
1431 d40c->log_num = log_num;
1432out:
1433
1434 if (is_log)
1435 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1436 else
1437 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1438
1439 return 0;
1440
1441}
1442
8d318a50
LW		 1443static int d40_config_memcpy(struct d40_chan *d40c)
1444{
1445 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1446
1447 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1448 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1449 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1450 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1451 memcpy[d40c->chan.chan_id];
1452
1453 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1454 dma_has_cap(DMA_SLAVE, cap)) {
1455 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1456 } else {
6db5a8ba 1457 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 1458 return -EINVAL;
1459 }
1460
1461 return 0;
1462}
1463
1464
1465static int d40_free_dma(struct d40_chan *d40c)
1466{
1467
1468 int res = 0;
d181b3a8 1469 u32 event;
8d318a50
LW		 1470 struct d40_phy_res *phy = d40c->phy_chan;
1471 bool is_src;
a8be8627
PF		 1472 struct d40_desc *d;
1473 struct d40_desc *_d;
1474
8d318a50
LW		 1475
1476 /* Terminate all queued and active transfers */
1477 d40_term_all(d40c);
1478
a8be8627
PF		 1479 /* Release client owned descriptors */
1480 if (!list_empty(&d40c->client))
1481 list_for_each_entry_safe(d, _d, &d40c->client, node) {
b00f938c 1482 d40_pool_lli_free(d40c, d);
a8be8627 1483 d40_desc_remove(d);
a8be8627
PF		 1484 d40_desc_free(d40c, d);
1485 }
1486
8d318a50 1487 if (phy == NULL) {
6db5a8ba 1488 chan_err(d40c, "phy == null\n");
8d318a50
LW		 1489 return -EINVAL;
1490 }
1491
1492 if (phy->allocated_src == D40_ALLOC_FREE &&
1493 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 1494 chan_err(d40c, "channel already free\n");
8d318a50
LW		 1495 return -EINVAL;
1496 }
1497
8d318a50
LW		 1498 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1499 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1500 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8d318a50
LW		 1501 is_src = false;
1502 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1503 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8d318a50
LW		 1504 is_src = true;
1505 } else {
6db5a8ba 1506 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 1507 return -EINVAL;
1508 }
1509
d181b3a8
JA		 1510 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1511 if (res) {
6db5a8ba 1512 chan_err(d40c, "suspend failed\n");
d181b3a8
JA		 1513 return res;
1514 }
1515
724a8577 1516 if (chan_is_logical(d40c)) {
d181b3a8 1517 /* Release logical channel, deactivate the event line */
8d318a50 1518
d181b3a8 1519 d40_config_set_event(d40c, false);
8d318a50
LW		 1520 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1521
1522 /*
1523 * Check if there are more logical allocation
1524 * on this phy channel.
1525 */
1526 if (!d40_alloc_mask_free(phy, is_src, event)) {
1527 /* Resume the other logical channels if any */
1528 if (d40_chan_has_events(d40c)) {
1529 res = d40_channel_execute_command(d40c,
1530 D40_DMA_RUN);
1531 if (res) {
6db5a8ba
RV		 1532 chan_err(d40c,
1533 "Executing RUN command\n");
8d318a50
LW		 1534 return res;
1535 }
1536 }
1537 return 0;
1538 }
d181b3a8
JA		 1539 } else {
1540 (void) d40_alloc_mask_free(phy, is_src, 0);
1541 }
8d318a50
LW		 1542
1543 /* Release physical channel */
1544 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1545 if (res) {
6db5a8ba 1546 chan_err(d40c, "Failed to stop channel\n");
8d318a50
LW		 1547 return res;
1548 }
1549 d40c->phy_chan = NULL;
ce2ca125 1550 d40c->configured = false;
8d318a50
LW		 1551 d40c->base->lookup_phy_chans[phy->num] = NULL;
1552
1553 return 0;
8d318a50
LW		 1554}
1555
a5ebca47
JA		 1556static bool d40_is_paused(struct d40_chan *d40c)
1557{
8ca84687 1558 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 1559 bool is_paused = false;
1560 unsigned long flags;
1561 void __iomem *active_reg;
1562 u32 status;
1563 u32 event;
a5ebca47
JA		 1564
1565 spin_lock_irqsave(&d40c->lock, flags);
1566
724a8577 1567 if (chan_is_physical(d40c)) {
a5ebca47
JA		 1568 if (d40c->phy_chan->num % 2 == 0)
1569 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1570 else
1571 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1572
1573 status = (readl(active_reg) &
1574 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1575 D40_CHAN_POS(d40c->phy_chan->num);
1576 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1577 is_paused = true;
1578
1579 goto _exit;
1580 }
1581
a5ebca47 1582 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
9dbfbd35 1583 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
a5ebca47 1584 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8ca84687 1585 status = readl(chanbase + D40_CHAN_REG_SDLNK);
9dbfbd35 1586 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
a5ebca47 1587 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8ca84687 1588 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 1589 } else {
6db5a8ba 1590 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 1591 goto _exit;
1592 }
9dbfbd35 1593
a5ebca47
JA		 1594 status = (status & D40_EVENTLINE_MASK(event)) >>
1595 D40_EVENTLINE_POS(event);
1596
1597 if (status != D40_DMA_RUN)
1598 is_paused = true;
a5ebca47
JA		 1599_exit:
1600 spin_unlock_irqrestore(&d40c->lock, flags);
1601 return is_paused;
1602
1603}
1604
1605
8d318a50
LW		 1606static u32 stedma40_residue(struct dma_chan *chan)
1607{
1608 struct d40_chan *d40c =
1609 container_of(chan, struct d40_chan, chan);
1610 u32 bytes_left;
1611 unsigned long flags;
1612
1613 spin_lock_irqsave(&d40c->lock, flags);
1614 bytes_left = d40_residue(d40c);
1615 spin_unlock_irqrestore(&d40c->lock, flags);
1616
1617 return bytes_left;
1618}
1619
8d318a50
LW		 1620struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
1621 struct scatterlist *sgl_dst,
1622 struct scatterlist *sgl_src,
1623 unsigned int sgl_len,
2a614340 1624 unsigned long dma_flags)
8d318a50
LW		 1625{
1626 int res;
1627 struct d40_desc *d40d;
1628 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1629 chan);
2a614340 1630 unsigned long flags;
8d318a50 1631
0d0f6b8b 1632 if (d40c->phy_chan == NULL) {
6db5a8ba 1633 chan_err(d40c, "Unallocated channel.\n");
0d0f6b8b
JA		 1634 return ERR_PTR(-EINVAL);
1635 }
1636
2a614340 1637 spin_lock_irqsave(&d40c->lock, flags);
8d318a50
LW		 1638 d40d = d40_desc_get(d40c);
1639
1640 if (d40d == NULL)
1641 goto err;
1642
d49278e3
PF		 1643 d40d->lli_len = d40_sg_2_dmalen(sgl_dst, sgl_len,
1644 d40c->dma_cfg.src_info.data_width,
1645 d40c->dma_cfg.dst_info.data_width);
1646 if (d40d->lli_len < 0) {
6db5a8ba 1647 chan_err(d40c, "Unaligned size\n");
d49278e3
PF		 1648 goto err;
1649 }
1650
698e4732 1651 d40d->lli_current = 0;
2a614340 1652 d40d->txd.flags = dma_flags;
8d318a50 1653
724a8577 1654 if (chan_is_logical(d40c)) {
8d318a50 1655
b00f938c 1656 if (d40_pool_lli_alloc(d40c, d40d, d40d->lli_len, true) < 0) {
6db5a8ba 1657 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 1658 goto err;
1659 }
1660
698e4732 1661 (void) d40_log_sg_to_lli(sgl_src,
8d318a50
LW		 1662 sgl_len,
1663 d40d->lli_log.src,
1664 d40c->log_def.lcsp1,
d49278e3
PF		 1665 d40c->dma_cfg.src_info.data_width,
1666 d40c->dma_cfg.dst_info.data_width);
8d318a50 1667
698e4732 1668 (void) d40_log_sg_to_lli(sgl_dst,
8d318a50
LW		 1669 sgl_len,
1670 d40d->lli_log.dst,
1671 d40c->log_def.lcsp3,
d49278e3
PF		 1672 d40c->dma_cfg.dst_info.data_width,
1673 d40c->dma_cfg.src_info.data_width);
8d318a50 1674 } else {
b00f938c 1675 if (d40_pool_lli_alloc(d40c, d40d, d40d->lli_len, false) < 0) {
6db5a8ba 1676 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 1677 goto err;
1678 }
1679
1680 res = d40_phy_sg_to_lli(sgl_src,
1681 sgl_len,
1682 0,
1683 d40d->lli_phy.src,
aa182ae2 1684 virt_to_phys(d40d->lli_phy.src),
8d318a50
LW		 1685 d40c->src_def_cfg,
1686 d40c->dma_cfg.src_info.data_width,
d49278e3 1687 d40c->dma_cfg.dst_info.data_width,
0246e77b 1688 d40c->dma_cfg.src_info.psize);
8d318a50
LW		 1689
1690 if (res < 0)
1691 goto err;
1692
1693 res = d40_phy_sg_to_lli(sgl_dst,
1694 sgl_len,
1695 0,
1696 d40d->lli_phy.dst,
aa182ae2 1697 virt_to_phys(d40d->lli_phy.dst),
8d318a50
LW		 1698 d40c->dst_def_cfg,
1699 d40c->dma_cfg.dst_info.data_width,
d49278e3 1700 d40c->dma_cfg.src_info.data_width,
0246e77b 1701 d40c->dma_cfg.dst_info.psize);
8d318a50
LW		 1702
1703 if (res < 0)
1704 goto err;
1705
b00f938c
RV		 1706 dma_sync_single_for_device(d40c->base->dev,
1707 d40d->lli_pool.dma_addr,
1708 d40d->lli_pool.size, DMA_TO_DEVICE);
8d318a50
LW		 1709 }
1710
1711 dma_async_tx_descriptor_init(&d40d->txd, chan);
1712
1713 d40d->txd.tx_submit = d40_tx_submit;
1714
2a614340 1715 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1716
1717 return &d40d->txd;
1718err:
819504f4
RV		 1719 if (d40d)
1720 d40_desc_free(d40c, d40d);
2a614340 1721 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1722 return NULL;
1723}
1724EXPORT_SYMBOL(stedma40_memcpy_sg);
1725
1726bool stedma40_filter(struct dma_chan *chan, void *data)
1727{
1728 struct stedma40_chan_cfg *info = data;
1729 struct d40_chan *d40c =
1730 container_of(chan, struct d40_chan, chan);
1731 int err;
1732
1733 if (data) {
1734 err = d40_validate_conf(d40c, info);
1735 if (!err)
1736 d40c->dma_cfg = *info;
1737 } else
1738 err = d40_config_memcpy(d40c);
1739
ce2ca125
RV		 1740 if (!err)
1741 d40c->configured = true;
1742
8d318a50
LW		 1743 return err == 0;
1744}
1745EXPORT_SYMBOL(stedma40_filter);
1746
ac2c0a38
RV		 1747static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
1748{
1749 bool realtime = d40c->dma_cfg.realtime;
1750 bool highprio = d40c->dma_cfg.high_priority;
1751 u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
1752 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
1753 u32 event = D40_TYPE_TO_EVENT(dev_type);
1754 u32 group = D40_TYPE_TO_GROUP(dev_type);
1755 u32 bit = 1 << event;
1756
1757 /* Destination event lines are stored in the upper halfword */
1758 if (!src)
1759 bit <<= 16;
1760
1761 writel(bit, d40c->base->virtbase + prioreg + group * 4);
1762 writel(bit, d40c->base->virtbase + rtreg + group * 4);
1763}
1764
1765static void d40_set_prio_realtime(struct d40_chan *d40c)
1766{
1767 if (d40c->base->rev < 3)
1768 return;
1769
1770 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1771 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1772 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
1773
1774 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
1775 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1776 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
1777}
1778
8d318a50
LW		 1779/* DMA ENGINE functions */
1780static int d40_alloc_chan_resources(struct dma_chan *chan)
1781{
1782 int err;
1783 unsigned long flags;
1784 struct d40_chan *d40c =
1785 container_of(chan, struct d40_chan, chan);
ef1872ec 1786 bool is_free_phy;
8d318a50
LW		 1787 spin_lock_irqsave(&d40c->lock, flags);
1788
1789 d40c->completed = chan->cookie = 1;
1790
ce2ca125
RV		 1791 /* If no dma configuration is set use default configuration (memcpy) */
1792 if (!d40c->configured) {
8d318a50 1793 err = d40_config_memcpy(d40c);
ff0b12ba 1794 if (err) {
6db5a8ba 1795 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 1796 goto fail;
1797 }
8d318a50 1798 }
ef1872ec 1799 is_free_phy = (d40c->phy_chan == NULL);
8d318a50
LW		 1800
1801 err = d40_allocate_channel(d40c);
1802 if (err) {
6db5a8ba 1803 chan_err(d40c, "Failed to allocate channel\n");
ff0b12ba 1804 goto fail;
8d318a50
LW		 1805 }
1806
ef1872ec
LW		 1807 /* Fill in basic CFG register values */
1808 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
724a8577 1809 &d40c->dst_def_cfg, chan_is_logical(d40c));
ef1872ec 1810
ac2c0a38
RV		 1811 d40_set_prio_realtime(d40c);
1812
724a8577 1813 if (chan_is_logical(d40c)) {
ef1872ec
LW		 1814 d40_log_cfg(&d40c->dma_cfg,
1815 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1816
1817 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1818 d40c->lcpa = d40c->base->lcpa_base +
1819 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1820 else
1821 d40c->lcpa = d40c->base->lcpa_base +
1822 d40c->dma_cfg.dst_dev_type *
1823 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1824 }
1825
1826 /*
1827 * Only write channel configuration to the DMA if the physical
1828 * resource is free. In case of multiple logical channels
1829 * on the same physical resource, only the first write is necessary.
1830 */
b55912c6
JA		 1831 if (is_free_phy)
1832 d40_config_write(d40c);
ff0b12ba 1833fail:
8d318a50 1834 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 1835 return err;
8d318a50
LW		 1836}
1837
1838static void d40_free_chan_resources(struct dma_chan *chan)
1839{
1840 struct d40_chan *d40c =
1841 container_of(chan, struct d40_chan, chan);
1842 int err;
1843 unsigned long flags;
1844
0d0f6b8b 1845 if (d40c->phy_chan == NULL) {
6db5a8ba 1846 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 1847 return;
1848 }
1849
1850
8d318a50
LW		 1851 spin_lock_irqsave(&d40c->lock, flags);
1852
1853 err = d40_free_dma(d40c);
1854
1855 if (err)
6db5a8ba 1856 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 1857 spin_unlock_irqrestore(&d40c->lock, flags);
1858}
1859
1860static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1861 dma_addr_t dst,
1862 dma_addr_t src,
1863 size_t size,
2a614340 1864 unsigned long dma_flags)
8d318a50
LW		 1865{
1866 struct d40_desc *d40d;
1867 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1868 chan);
2a614340 1869 unsigned long flags;
8d318a50 1870
0d0f6b8b 1871 if (d40c->phy_chan == NULL) {
6db5a8ba 1872 chan_err(d40c, "Channel is not allocated.\n");
0d0f6b8b
JA		 1873 return ERR_PTR(-EINVAL);
1874 }
1875
2a614340 1876 spin_lock_irqsave(&d40c->lock, flags);
8d318a50
LW		 1877 d40d = d40_desc_get(d40c);
1878
1879 if (d40d == NULL) {
6db5a8ba 1880 chan_err(d40c, "Descriptor is NULL\n");
8d318a50
LW		 1881 goto err;
1882 }
1883
2a614340 1884 d40d->txd.flags = dma_flags;
d49278e3
PF		 1885 d40d->lli_len = d40_size_2_dmalen(size,
1886 d40c->dma_cfg.src_info.data_width,
1887 d40c->dma_cfg.dst_info.data_width);
1888 if (d40d->lli_len < 0) {
6db5a8ba 1889 chan_err(d40c, "Unaligned size\n");
d49278e3
PF		 1890 goto err;
1891 }
1892
8d318a50
LW		 1893
1894 dma_async_tx_descriptor_init(&d40d->txd, chan);
1895
1896 d40d->txd.tx_submit = d40_tx_submit;
1897
724a8577 1898 if (chan_is_logical(d40c)) {
8d318a50 1899
b00f938c 1900 if (d40_pool_lli_alloc(d40c,d40d, d40d->lli_len, true) < 0) {
6db5a8ba 1901 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 1902 goto err;
1903 }
698e4732 1904 d40d->lli_current = 0;
8d318a50 1905
d49278e3
PF		 1906 if (d40_log_buf_to_lli(d40d->lli_log.src,
1907 src,
1908 size,
1909 d40c->log_def.lcsp1,
1910 d40c->dma_cfg.src_info.data_width,
1911 d40c->dma_cfg.dst_info.data_width,
1912 true) == NULL)
1913 goto err;
8d318a50 1914
d49278e3
PF		 1915 if (d40_log_buf_to_lli(d40d->lli_log.dst,
1916 dst,
1917 size,
1918 d40c->log_def.lcsp3,
1919 d40c->dma_cfg.dst_info.data_width,
1920 d40c->dma_cfg.src_info.data_width,
1921 true) == NULL)
1922 goto err;
8d318a50
LW		 1923
1924 } else {
1925
b00f938c 1926 if (d40_pool_lli_alloc(d40c, d40d, d40d->lli_len, false) < 0) {
6db5a8ba 1927 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 1928 goto err;
1929 }
1930
d49278e3 1931 if (d40_phy_buf_to_lli(d40d->lli_phy.src,
8d318a50
LW		 1932 src,
1933 size,
1934 d40c->dma_cfg.src_info.psize,
1935 0,
1936 d40c->src_def_cfg,
1937 true,
1938 d40c->dma_cfg.src_info.data_width,
d49278e3
PF		 1939 d40c->dma_cfg.dst_info.data_width,
1940 false) == NULL)
1941 goto err;
8d318a50 1942
d49278e3 1943 if (d40_phy_buf_to_lli(d40d->lli_phy.dst,
8d318a50
LW		 1944 dst,
1945 size,
1946 d40c->dma_cfg.dst_info.psize,
1947 0,
1948 d40c->dst_def_cfg,
1949 true,
1950 d40c->dma_cfg.dst_info.data_width,
d49278e3
PF		 1951 d40c->dma_cfg.src_info.data_width,
1952 false) == NULL)
1953 goto err;
8d318a50 1954
b00f938c
RV		 1955 dma_sync_single_for_device(d40c->base->dev,
1956 d40d->lli_pool.dma_addr,
1957 d40d->lli_pool.size, DMA_TO_DEVICE);
8d318a50
LW		 1958 }
1959
2a614340 1960 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1961 return &d40d->txd;
1962
8d318a50 1963err:
819504f4
RV		 1964 if (d40d)
1965 d40_desc_free(d40c, d40d);
2a614340 1966 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50
LW		 1967 return NULL;
1968}
1969
0d688662
IS		 1970static struct dma_async_tx_descriptor *
1971d40_prep_sg(struct dma_chan *chan,
1972 struct scatterlist *dst_sg, unsigned int dst_nents,
1973 struct scatterlist *src_sg, unsigned int src_nents,
1974 unsigned long dma_flags)
1975{
1976 if (dst_nents != src_nents)
1977 return NULL;
1978
1979 return stedma40_memcpy_sg(chan, dst_sg, src_sg, dst_nents, dma_flags);
1980}
1981
8d318a50
LW		 1982static int d40_prep_slave_sg_log(struct d40_desc *d40d,
1983 struct d40_chan *d40c,
1984 struct scatterlist *sgl,
1985 unsigned int sg_len,
1986 enum dma_data_direction direction,
2a614340 1987 unsigned long dma_flags)
8d318a50
LW		 1988{
1989 dma_addr_t dev_addr = 0;
1990 int total_size;
8d318a50 1991
d49278e3
PF		 1992 d40d->lli_len = d40_sg_2_dmalen(sgl, sg_len,
1993 d40c->dma_cfg.src_info.data_width,
1994 d40c->dma_cfg.dst_info.data_width);
1995 if (d40d->lli_len < 0) {
6db5a8ba 1996 chan_err(d40c, "Unaligned size\n");
d49278e3
PF		 1997 return -EINVAL;
1998 }
1999
b00f938c 2000 if (d40_pool_lli_alloc(d40c, d40d, d40d->lli_len, true) < 0) {
6db5a8ba 2001 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 2002 return -ENOMEM;
2003 }
2004
698e4732 2005 d40d->lli_current = 0;
8d318a50 2006
2a614340 2007 if (direction == DMA_FROM_DEVICE)
95e1400f
LW		 2008 if (d40c->runtime_addr)
2009 dev_addr = d40c->runtime_addr;
2010 else
2011 dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
2a614340 2012 else if (direction == DMA_TO_DEVICE)
95e1400f
LW		 2013 if (d40c->runtime_addr)
2014 dev_addr = d40c->runtime_addr;
2015 else
2016 dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
2017
2a614340 2018 else
8d318a50 2019 return -EINVAL;
2a614340 2020
698e4732 2021 total_size = d40_log_sg_to_dev(sgl, sg_len,
2a614340
JA		 2022 &d40d->lli_log,
2023 &d40c->log_def,
2024 d40c->dma_cfg.src_info.data_width,
2025 d40c->dma_cfg.dst_info.data_width,
2026 direction,
698e4732 2027 dev_addr);
2a614340 2028
8d318a50
LW		 2029 if (total_size < 0)
2030 return -EINVAL;
2031
2032 return 0;
2033}
2034
2035static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
2036 struct d40_chan *d40c,
2037 struct scatterlist *sgl,
2038 unsigned int sgl_len,
2039 enum dma_data_direction direction,
2a614340 2040 unsigned long dma_flags)
8d318a50
LW		 2041{
2042 dma_addr_t src_dev_addr;
2043 dma_addr_t dst_dev_addr;
2044 int res;
2045
d49278e3
PF		 2046 d40d->lli_len = d40_sg_2_dmalen(sgl, sgl_len,
2047 d40c->dma_cfg.src_info.data_width,
2048 d40c->dma_cfg.dst_info.data_width);
2049 if (d40d->lli_len < 0) {
6db5a8ba 2050 chan_err(d40c, "Unaligned size\n");
d49278e3
PF		 2051 return -EINVAL;
2052 }
2053
b00f938c 2054 if (d40_pool_lli_alloc(d40c, d40d, d40d->lli_len, false) < 0) {
6db5a8ba 2055 chan_err(d40c, "Out of memory\n");
8d318a50
LW		 2056 return -ENOMEM;
2057 }
2058
698e4732 2059 d40d->lli_current = 0;
8d318a50
LW		 2060
2061 if (direction == DMA_FROM_DEVICE) {
2062 dst_dev_addr = 0;
95e1400f
LW		 2063 if (d40c->runtime_addr)
2064 src_dev_addr = d40c->runtime_addr;
2065 else
2066 src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
8d318a50 2067 } else if (direction == DMA_TO_DEVICE) {
95e1400f
LW		 2068 if (d40c->runtime_addr)
2069 dst_dev_addr = d40c->runtime_addr;
2070 else
2071 dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
8d318a50
LW		 2072 src_dev_addr = 0;
2073 } else
2074 return -EINVAL;
2075
2076 res = d40_phy_sg_to_lli(sgl,
2077 sgl_len,
2078 src_dev_addr,
2079 d40d->lli_phy.src,
aa182ae2 2080 virt_to_phys(d40d->lli_phy.src),
8d318a50
LW		 2081 d40c->src_def_cfg,
2082 d40c->dma_cfg.src_info.data_width,
d49278e3 2083 d40c->dma_cfg.dst_info.data_width,
0246e77b 2084 d40c->dma_cfg.src_info.psize);
8d318a50
LW		 2085 if (res < 0)
2086 return res;
2087
2088 res = d40_phy_sg_to_lli(sgl,
2089 sgl_len,
2090 dst_dev_addr,
2091 d40d->lli_phy.dst,
aa182ae2 2092 virt_to_phys(d40d->lli_phy.dst),
8d318a50
LW		 2093 d40c->dst_def_cfg,
2094 d40c->dma_cfg.dst_info.data_width,
d49278e3 2095 d40c->dma_cfg.src_info.data_width,
0246e77b 2096 d40c->dma_cfg.dst_info.psize);
8d318a50
LW		 2097 if (res < 0)
2098 return res;
2099
b00f938c
RV		 2100 dma_sync_single_for_device(d40c->base->dev, d40d->lli_pool.dma_addr,
2101 d40d->lli_pool.size, DMA_TO_DEVICE);
8d318a50
LW		 2102 return 0;
2103}
2104
2105static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2106 struct scatterlist *sgl,
2107 unsigned int sg_len,
2108 enum dma_data_direction direction,
2a614340 2109 unsigned long dma_flags)
8d318a50
LW		 2110{
2111 struct d40_desc *d40d;
2112 struct d40_chan *d40c = container_of(chan, struct d40_chan,
2113 chan);
2a614340 2114 unsigned long flags;
8d318a50
LW		 2115 int err;
2116
0d0f6b8b 2117 if (d40c->phy_chan == NULL) {
6db5a8ba 2118 chan_err(d40c, "Cannot prepare unallocated channel\n");
0d0f6b8b
JA		 2119 return ERR_PTR(-EINVAL);
2120 }
2121
2a614340 2122 spin_lock_irqsave(&d40c->lock, flags);
8d318a50 2123 d40d = d40_desc_get(d40c);
8d318a50
LW		 2124
2125 if (d40d == NULL)
819504f4 2126 goto err;
8d318a50 2127
724a8577 2128 if (chan_is_logical(d40c))
8d318a50 2129 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2a614340 2130 direction, dma_flags);
8d318a50
LW		 2131 else
2132 err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
2a614340 2133 direction, dma_flags);
8d318a50 2134 if (err) {
6db5a8ba 2135 chan_err(d40c, "Failed to prepare %s slave sg job: %d\n",
724a8577 2136 chan_is_logical(d40c) ? "log" : "phy", err);
819504f4 2137 goto err;
8d318a50
LW		 2138 }
2139
2a614340 2140 d40d->txd.flags = dma_flags;
8d318a50
LW		 2141
2142 dma_async_tx_descriptor_init(&d40d->txd, chan);
2143
2144 d40d->txd.tx_submit = d40_tx_submit;
2145
819504f4 2146 spin_unlock_irqrestore(&d40c->lock, flags);
8d318a50 2147 return &d40d->txd;
819504f4
RV		 2148
2149err:
2150 if (d40d)
2151 d40_desc_free(d40c, d40d);
2152 spin_unlock_irqrestore(&d40c->lock, flags);
2153 return NULL;
8d318a50
LW		 2154}
2155
2156static enum dma_status d40_tx_status(struct dma_chan *chan,
2157 dma_cookie_t cookie,
2158 struct dma_tx_state *txstate)
2159{
2160 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2161 dma_cookie_t last_used;
2162 dma_cookie_t last_complete;
2163 int ret;
2164
0d0f6b8b 2165 if (d40c->phy_chan == NULL) {
6db5a8ba 2166 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2167 return -EINVAL;
2168 }
2169
8d318a50
LW		 2170 last_complete = d40c->completed;
2171 last_used = chan->cookie;
2172
a5ebca47
JA		 2173 if (d40_is_paused(d40c))
2174 ret = DMA_PAUSED;
2175 else
2176 ret = dma_async_is_complete(cookie, last_complete, last_used);
8d318a50 2177
a5ebca47
JA		 2178 dma_set_tx_state(txstate, last_complete, last_used,
2179 stedma40_residue(chan));
8d318a50
LW		 2180
2181 return ret;
2182}
2183
2184static void d40_issue_pending(struct dma_chan *chan)
2185{
2186 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2187 unsigned long flags;
2188
0d0f6b8b 2189 if (d40c->phy_chan == NULL) {
6db5a8ba 2190 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2191 return;
2192 }
2193
8d318a50
LW		 2194 spin_lock_irqsave(&d40c->lock, flags);
2195
2196 /* Busy means that pending jobs are already being processed */
2197 if (!d40c->busy)
2198 (void) d40_queue_start(d40c);
2199
2200 spin_unlock_irqrestore(&d40c->lock, flags);
2201}
2202
95e1400f
LW		 2203/* Runtime reconfiguration extension */
2204static void d40_set_runtime_config(struct dma_chan *chan,
2205 struct dma_slave_config *config)
2206{
2207 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2208 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2209 enum dma_slave_buswidth config_addr_width;
2210 dma_addr_t config_addr;
2211 u32 config_maxburst;
2212 enum stedma40_periph_data_width addr_width;
2213 int psize;
2214
2215 if (config->direction == DMA_FROM_DEVICE) {
2216 dma_addr_t dev_addr_rx =
2217 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2218
2219 config_addr = config->src_addr;
2220 if (dev_addr_rx)
2221 dev_dbg(d40c->base->dev,
2222 "channel has a pre-wired RX address %08x "
2223 "overriding with %08x\n",
2224 dev_addr_rx, config_addr);
2225 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2226 dev_dbg(d40c->base->dev,
2227 "channel was not configured for peripheral "
2228 "to memory transfer (%d) overriding\n",
2229 cfg->dir);
2230 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2231
2232 config_addr_width = config->src_addr_width;
2233 config_maxburst = config->src_maxburst;
2234
2235 } else if (config->direction == DMA_TO_DEVICE) {
2236 dma_addr_t dev_addr_tx =
2237 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2238
2239 config_addr = config->dst_addr;
2240 if (dev_addr_tx)
2241 dev_dbg(d40c->base->dev,
2242 "channel has a pre-wired TX address %08x "
2243 "overriding with %08x\n",
2244 dev_addr_tx, config_addr);
2245 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2246 dev_dbg(d40c->base->dev,
2247 "channel was not configured for memory "
2248 "to peripheral transfer (%d) overriding\n",
2249 cfg->dir);
2250 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2251
2252 config_addr_width = config->dst_addr_width;
2253 config_maxburst = config->dst_maxburst;
2254
2255 } else {
2256 dev_err(d40c->base->dev,
2257 "unrecognized channel direction %d\n",
2258 config->direction);
2259 return;
2260 }
2261
2262 switch (config_addr_width) {
2263 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2264 addr_width = STEDMA40_BYTE_WIDTH;
2265 break;
2266 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2267 addr_width = STEDMA40_HALFWORD_WIDTH;
2268 break;
2269 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2270 addr_width = STEDMA40_WORD_WIDTH;
2271 break;
2272 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2273 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2274 break;
2275 default:
2276 dev_err(d40c->base->dev,
2277 "illegal peripheral address width "
2278 "requested (%d)\n",
2279 config->src_addr_width);
2280 return;
2281 }
2282
724a8577 2283 if (chan_is_logical(d40c)) {
a59670a4
PF		 2284 if (config_maxburst >= 16)
2285 psize = STEDMA40_PSIZE_LOG_16;
2286 else if (config_maxburst >= 8)
2287 psize = STEDMA40_PSIZE_LOG_8;
2288 else if (config_maxburst >= 4)
2289 psize = STEDMA40_PSIZE_LOG_4;
2290 else
2291 psize = STEDMA40_PSIZE_LOG_1;
2292 } else {
2293 if (config_maxburst >= 16)
2294 psize = STEDMA40_PSIZE_PHY_16;
2295 else if (config_maxburst >= 8)
2296 psize = STEDMA40_PSIZE_PHY_8;
2297 else if (config_maxburst >= 4)
2298 psize = STEDMA40_PSIZE_PHY_4;
d49278e3
PF		 2299 else if (config_maxburst >= 2)
2300 psize = STEDMA40_PSIZE_PHY_2;
a59670a4
PF		 2301 else
2302 psize = STEDMA40_PSIZE_PHY_1;
2303 }
95e1400f
LW		 2304
2305 /* Set up all the endpoint configs */
2306 cfg->src_info.data_width = addr_width;
2307 cfg->src_info.psize = psize;
51f5d744 2308 cfg->src_info.big_endian = false;
95e1400f
LW		 2309 cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2310 cfg->dst_info.data_width = addr_width;
2311 cfg->dst_info.psize = psize;
51f5d744 2312 cfg->dst_info.big_endian = false;
95e1400f
LW		 2313 cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2314
a59670a4 2315 /* Fill in register values */
724a8577 2316 if (chan_is_logical(d40c))
a59670a4
PF		 2317 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2318 else
2319 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2320 &d40c->dst_def_cfg, false);
2321
95e1400f
LW		 2322 /* These settings will take precedence later */
2323 d40c->runtime_addr = config_addr;
2324 d40c->runtime_direction = config->direction;
2325 dev_dbg(d40c->base->dev,
2326 "configured channel %s for %s, data width %d, "
2327 "maxburst %d bytes, LE, no flow control\n",
2328 dma_chan_name(chan),
2329 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2330 config_addr_width,
2331 config_maxburst);
2332}
2333
05827630
LW		 2334static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2335 unsigned long arg)
8d318a50
LW		 2336{
2337 unsigned long flags;
2338 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2339
0d0f6b8b 2340 if (d40c->phy_chan == NULL) {
6db5a8ba 2341 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2342 return -EINVAL;
2343 }
2344
8d318a50
LW		 2345 switch (cmd) {
2346 case DMA_TERMINATE_ALL:
2347 spin_lock_irqsave(&d40c->lock, flags);
2348 d40_term_all(d40c);
2349 spin_unlock_irqrestore(&d40c->lock, flags);
2350 return 0;
2351 case DMA_PAUSE:
2352 return d40_pause(chan);
2353 case DMA_RESUME:
2354 return d40_resume(chan);
95e1400f
LW		 2355 case DMA_SLAVE_CONFIG:
2356 d40_set_runtime_config(chan,
2357 (struct dma_slave_config *) arg);
2358 return 0;
2359 default:
2360 break;
8d318a50
LW		 2361 }
2362
2363 /* Other commands are unimplemented */
2364 return -ENXIO;
2365}
2366
2367/* Initialization functions */
2368
2369static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2370 struct d40_chan *chans, int offset,
2371 int num_chans)
2372{
2373 int i = 0;
2374 struct d40_chan *d40c;
2375
2376 INIT_LIST_HEAD(&dma->channels);
2377
2378 for (i = offset; i < offset + num_chans; i++) {
2379 d40c = &chans[i];
2380 d40c->base = base;
2381 d40c->chan.device = dma;
2382
8d318a50
LW		 2383 spin_lock_init(&d40c->lock);
2384
2385 d40c->log_num = D40_PHY_CHAN;
2386
8d318a50
LW		 2387 INIT_LIST_HEAD(&d40c->active);
2388 INIT_LIST_HEAD(&d40c->queue);
2389 INIT_LIST_HEAD(&d40c->client);
2390
8d318a50
LW		 2391 tasklet_init(&d40c->tasklet, dma_tasklet,
2392 (unsigned long) d40c);
2393
2394 list_add_tail(&d40c->chan.device_node,
2395 &dma->channels);
2396 }
2397}
2398
2399static int __init d40_dmaengine_init(struct d40_base *base,
2400 int num_reserved_chans)
2401{
2402 int err ;
2403
2404 d40_chan_init(base, &base->dma_slave, base->log_chans,
2405 0, base->num_log_chans);
2406
2407 dma_cap_zero(base->dma_slave.cap_mask);
2408 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2409
2410 base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2411 base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2412 base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
0d688662 2413 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
8d318a50
LW		 2414 base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2415 base->dma_slave.device_tx_status = d40_tx_status;
2416 base->dma_slave.device_issue_pending = d40_issue_pending;
2417 base->dma_slave.device_control = d40_control;
2418 base->dma_slave.dev = base->dev;
2419
2420 err = dma_async_device_register(&base->dma_slave);
2421
2422 if (err) {
6db5a8ba 2423 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2424 goto failure1;
2425 }
2426
2427 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2428 base->num_log_chans, base->plat_data->memcpy_len);
2429
2430 dma_cap_zero(base->dma_memcpy.cap_mask);
2431 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
0d688662 2432 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
8d318a50
LW		 2433
2434 base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2435 base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2436 base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
0d688662 2437 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
8d318a50
LW		 2438 base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2439 base->dma_memcpy.device_tx_status = d40_tx_status;
2440 base->dma_memcpy.device_issue_pending = d40_issue_pending;
2441 base->dma_memcpy.device_control = d40_control;
2442 base->dma_memcpy.dev = base->dev;
2443 /*
2444 * This controller can only access address at even
2445 * 32bit boundaries, i.e. 2^2
2446 */
2447 base->dma_memcpy.copy_align = 2;
2448
2449 err = dma_async_device_register(&base->dma_memcpy);
2450
2451 if (err) {
6db5a8ba
RV		 2452 d40_err(base->dev,
2453 "Failed to regsiter memcpy only channels\n");
8d318a50
LW		 2454 goto failure2;
2455 }
2456
2457 d40_chan_init(base, &base->dma_both, base->phy_chans,
2458 0, num_reserved_chans);
2459
2460 dma_cap_zero(base->dma_both.cap_mask);
2461 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2462 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
0d688662 2463 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
8d318a50
LW		 2464
2465 base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2466 base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2467 base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
0d688662 2468 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
8d318a50
LW		 2469 base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2470 base->dma_both.device_tx_status = d40_tx_status;
2471 base->dma_both.device_issue_pending = d40_issue_pending;
2472 base->dma_both.device_control = d40_control;
2473 base->dma_both.dev = base->dev;
2474 base->dma_both.copy_align = 2;
2475 err = dma_async_device_register(&base->dma_both);
2476
2477 if (err) {
6db5a8ba
RV		 2478 d40_err(base->dev,
2479 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2480 goto failure3;
2481 }
2482 return 0;
2483failure3:
2484 dma_async_device_unregister(&base->dma_memcpy);
2485failure2:
2486 dma_async_device_unregister(&base->dma_slave);
2487failure1:
2488 return err;
2489}
2490
2491/* Initialization functions. */
2492
2493static int __init d40_phy_res_init(struct d40_base *base)
2494{
2495 int i;
2496 int num_phy_chans_avail = 0;
2497 u32 val[2];
2498 int odd_even_bit = -2;
2499
2500 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2501 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2502
2503 for (i = 0; i < base->num_phy_chans; i++) {
2504 base->phy_res[i].num = i;
2505 odd_even_bit += 2 * ((i % 2) == 0);
2506 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2507 /* Mark security only channels as occupied */
2508 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2509 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2510 } else {
2511 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2512 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2513 num_phy_chans_avail++;
2514 }
2515 spin_lock_init(&base->phy_res[i].lock);
2516 }
6b7acd84
JA		 2517
2518 /* Mark disabled channels as occupied */
2519 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 2520 int chan = base->plat_data->disabled_channels[i];
2521
2522 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2523 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2524 num_phy_chans_avail--;
6b7acd84
JA		 2525 }
2526
8d318a50
LW		 2527 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2528 num_phy_chans_avail, base->num_phy_chans);
2529
2530 /* Verify settings extended vs standard */
2531 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2532
2533 for (i = 0; i < base->num_phy_chans; i++) {
2534
2535 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2536 (val[0] & 0x3) != 1)
2537 dev_info(base->dev,
2538 "[%s] INFO: channel %d is misconfigured (%d)\n",
2539 __func__, i, val[0] & 0x3);
2540
2541 val[0] = val[0] >> 2;
2542 }
2543
2544 return num_phy_chans_avail;
2545}
2546
2547static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2548{
2549 static const struct d40_reg_val dma_id_regs[] = {
2550 /* Peripheral Id */
2551 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2552 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2553 /*
2554 * D40_DREG_PERIPHID2 Depends on HW revision:
4d594900 2555 * DB8500ed has 0x0008,
8d318a50 2556 * ? has 0x0018,
4d594900
RV		 2557 * DB8500v1 has 0x0028
2558 * DB8500v2 has 0x0038
8d318a50
LW		 2559 */
2560 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2561
2562 /* PCell Id */
2563 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2564 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2565 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2566 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2567 };
2568 struct stedma40_platform_data *plat_data;
2569 struct clk *clk = NULL;
2570 void __iomem *virtbase = NULL;
2571 struct resource *res = NULL;
2572 struct d40_base *base = NULL;
2573 int num_log_chans = 0;
2574 int num_phy_chans;
2575 int i;
f4185592 2576 u32 val;
3ae0267f 2577 u32 rev;
8d318a50
LW		 2578
2579 clk = clk_get(&pdev->dev, NULL);
2580
2581 if (IS_ERR(clk)) {
6db5a8ba 2582 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 2583 goto failure;
2584 }
2585
2586 clk_enable(clk);
2587
2588 /* Get IO for DMAC base address */
2589 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2590 if (!res)
2591 goto failure;
2592
2593 if (request_mem_region(res->start, resource_size(res),
2594 D40_NAME " I/O base") == NULL)
2595 goto failure;
2596
2597 virtbase = ioremap(res->start, resource_size(res));
2598 if (!virtbase)
2599 goto failure;
2600
2601 /* HW version check */
2602 for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2603 if (dma_id_regs[i].val !=
2604 readl(virtbase + dma_id_regs[i].reg)) {
6db5a8ba
RV		 2605 d40_err(&pdev->dev,
2606 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
8d318a50
LW		 2607 dma_id_regs[i].val,
2608 dma_id_regs[i].reg,
2609 readl(virtbase + dma_id_regs[i].reg));
2610 goto failure;
2611 }
2612 }
2613
3ae0267f 2614 /* Get silicon revision and designer */
f4185592 2615 val = readl(virtbase + D40_DREG_PERIPHID2);
8d318a50 2616
3ae0267f
JA		 2617 if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2618 D40_HW_DESIGNER) {
6db5a8ba
RV		 2619 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
2620 val & D40_DREG_PERIPHID2_DESIGNER_MASK,
3ae0267f 2621 D40_HW_DESIGNER);
8d318a50
LW		 2622 goto failure;
2623 }
2624
3ae0267f
JA		 2625 rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2626 D40_DREG_PERIPHID2_REV_POS;
2627
8d318a50
LW		 2628 /* The number of physical channels on this HW */
2629 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2630
2631 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
3ae0267f 2632 rev, res->start);
8d318a50
LW		 2633
2634 plat_data = pdev->dev.platform_data;
2635
2636 /* Count the number of logical channels in use */
2637 for (i = 0; i < plat_data->dev_len; i++)
2638 if (plat_data->dev_rx[i] != 0)
2639 num_log_chans++;
2640
2641 for (i = 0; i < plat_data->dev_len; i++)
2642 if (plat_data->dev_tx[i] != 0)
2643 num_log_chans++;
2644
2645 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2646 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2647 sizeof(struct d40_chan), GFP_KERNEL);
2648
2649 if (base == NULL) {
6db5a8ba 2650 d40_err(&pdev->dev, "Out of memory\n");
8d318a50
LW		 2651 goto failure;
2652 }
2653
3ae0267f 2654 base->rev = rev;
8d318a50
LW		 2655 base->clk = clk;
2656 base->num_phy_chans = num_phy_chans;
2657 base->num_log_chans = num_log_chans;
2658 base->phy_start = res->start;
2659 base->phy_size = resource_size(res);
2660 base->virtbase = virtbase;
2661 base->plat_data = plat_data;
2662 base->dev = &pdev->dev;
2663 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2664 base->log_chans = &base->phy_chans[num_phy_chans];
2665
2666 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2667 GFP_KERNEL);
2668 if (!base->phy_res)
2669 goto failure;
2670
2671 base->lookup_phy_chans = kzalloc(num_phy_chans *
2672 sizeof(struct d40_chan *),
2673 GFP_KERNEL);
2674 if (!base->lookup_phy_chans)
2675 goto failure;
2676
2677 if (num_log_chans + plat_data->memcpy_len) {
2678 /*
2679 * The max number of logical channels are event lines for all
2680 * src devices and dst devices
2681 */
2682 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2683 sizeof(struct d40_chan *),
2684 GFP_KERNEL);
2685 if (!base->lookup_log_chans)
2686 goto failure;
2687 }
698e4732
JA		 2688
2689 base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
2690 sizeof(struct d40_desc *) *
2691 D40_LCLA_LINK_PER_EVENT_GRP,
8d318a50
LW		 2692 GFP_KERNEL);
2693 if (!base->lcla_pool.alloc_map)
2694 goto failure;
2695
c675b1b4
JA		 2696 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2697 0, SLAB_HWCACHE_ALIGN,
2698 NULL);
2699 if (base->desc_slab == NULL)
2700 goto failure;
2701
8d318a50
LW		 2702 return base;
2703
2704failure:
c6134c96 2705 if (!IS_ERR(clk)) {
8d318a50
LW		 2706 clk_disable(clk);
2707 clk_put(clk);
2708 }
2709 if (virtbase)
2710 iounmap(virtbase);
2711 if (res)
2712 release_mem_region(res->start,
2713 resource_size(res));
2714 if (virtbase)
2715 iounmap(virtbase);
2716
2717 if (base) {
2718 kfree(base->lcla_pool.alloc_map);
2719 kfree(base->lookup_log_chans);
2720 kfree(base->lookup_phy_chans);
2721 kfree(base->phy_res);
2722 kfree(base);
2723 }
2724
2725 return NULL;
2726}
2727
2728static void __init d40_hw_init(struct d40_base *base)
2729{
2730
2731 static const struct d40_reg_val dma_init_reg[] = {
2732 /* Clock every part of the DMA block from start */
2733 { .reg = D40_DREG_GCC, .val = 0x0000ff01},
2734
2735 /* Interrupts on all logical channels */
2736 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2737 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2738 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2739 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2740 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2741 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2742 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2743 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2744 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2745 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2746 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2747 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2748 };
2749 int i;
2750 u32 prmseo[2] = {0, 0};
2751 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2752 u32 pcmis = 0;
2753 u32 pcicr = 0;
2754
2755 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2756 writel(dma_init_reg[i].val,
2757 base->virtbase + dma_init_reg[i].reg);
2758
2759 /* Configure all our dma channels to default settings */
2760 for (i = 0; i < base->num_phy_chans; i++) {
2761
2762 activeo[i % 2] = activeo[i % 2] << 2;
2763
2764 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2765 == D40_ALLOC_PHY) {
2766 activeo[i % 2] |= 3;
2767 continue;
2768 }
2769
2770 /* Enable interrupt # */
2771 pcmis = (pcmis << 1) | 1;
2772
2773 /* Clear interrupt # */
2774 pcicr = (pcicr << 1) | 1;
2775
2776 /* Set channel to physical mode */
2777 prmseo[i % 2] = prmseo[i % 2] << 2;
2778 prmseo[i % 2] |= 1;
2779
2780 }
2781
2782 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2783 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2784 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2785 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2786
2787 /* Write which interrupt to enable */
2788 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2789
2790 /* Write which interrupt to clear */
2791 writel(pcicr, base->virtbase + D40_DREG_PCICR);
2792
2793}
2794
508849ad
LW		 2795static int __init d40_lcla_allocate(struct d40_base *base)
2796{
026cbc42 2797 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 2798 unsigned long *page_list;
2799 int i, j;
2800 int ret = 0;
2801
2802 /*
2803 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2804 * To full fill this hardware requirement without wasting 256 kb
2805 * we allocate pages until we get an aligned one.
2806 */
2807 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2808 GFP_KERNEL);
2809
2810 if (!page_list) {
2811 ret = -ENOMEM;
2812 goto failure;
2813 }
2814
2815 /* Calculating how many pages that are required */
2816 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2817
2818 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2819 page_list[i] = __get_free_pages(GFP_KERNEL,
2820 base->lcla_pool.pages);
2821 if (!page_list[i]) {
2822
6db5a8ba
RV		 2823 d40_err(base->dev, "Failed to allocate %d pages.\n",
2824 base->lcla_pool.pages);
508849ad
LW		 2825
2826 for (j = 0; j < i; j++)
2827 free_pages(page_list[j], base->lcla_pool.pages);
2828 goto failure;
2829 }
2830
2831 if ((virt_to_phys((void *)page_list[i]) &
2832 (LCLA_ALIGNMENT - 1)) == 0)
2833 break;
2834 }
2835
2836 for (j = 0; j < i; j++)
2837 free_pages(page_list[j], base->lcla_pool.pages);
2838
2839 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2840 base->lcla_pool.base = (void *)page_list[i];
2841 } else {
767a9675
JA		 2842 /*
2843 * After many attempts and no succees with finding the correct
2844 * alignment, try with allocating a big buffer.
2845 */
508849ad
LW		 2846 dev_warn(base->dev,
2847 "[%s] Failed to get %d pages @ 18 bit align.\n",
2848 __func__, base->lcla_pool.pages);
2849 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2850 base->num_phy_chans +
2851 LCLA_ALIGNMENT,
2852 GFP_KERNEL);
2853 if (!base->lcla_pool.base_unaligned) {
2854 ret = -ENOMEM;
2855 goto failure;
2856 }
2857
2858 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2859 LCLA_ALIGNMENT);
2860 }
2861
026cbc42
RV		 2862 pool->dma_addr = dma_map_single(base->dev, pool->base,
2863 SZ_1K * base->num_phy_chans,
2864 DMA_TO_DEVICE);
2865 if (dma_mapping_error(base->dev, pool->dma_addr)) {
2866 pool->dma_addr = 0;
2867 ret = -ENOMEM;
2868 goto failure;
2869 }
2870
508849ad
LW		 2871 writel(virt_to_phys(base->lcla_pool.base),
2872 base->virtbase + D40_DREG_LCLA);
2873failure:
2874 kfree(page_list);
2875 return ret;
2876}
2877
8d318a50
LW		 2878static int __init d40_probe(struct platform_device *pdev)
2879{
2880 int err;
2881 int ret = -ENOENT;
2882 struct d40_base *base;
2883 struct resource *res = NULL;
2884 int num_reserved_chans;
2885 u32 val;
2886
2887 base = d40_hw_detect_init(pdev);
2888
2889 if (!base)
2890 goto failure;
2891
2892 num_reserved_chans = d40_phy_res_init(base);
2893
2894 platform_set_drvdata(pdev, base);
2895
2896 spin_lock_init(&base->interrupt_lock);
2897 spin_lock_init(&base->execmd_lock);
2898
2899 /* Get IO for logical channel parameter address */
2900 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2901 if (!res) {
2902 ret = -ENOENT;
6db5a8ba 2903 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 2904 goto failure;
2905 }
2906 base->lcpa_size = resource_size(res);
2907 base->phy_lcpa = res->start;
2908
2909 if (request_mem_region(res->start, resource_size(res),
2910 D40_NAME " I/O lcpa") == NULL) {
2911 ret = -EBUSY;
6db5a8ba
RV		 2912 d40_err(&pdev->dev,
2913 "Failed to request LCPA region 0x%x-0x%x\n",
2914 res->start, res->end);
8d318a50
LW		 2915 goto failure;
2916 }
2917
2918 /* We make use of ESRAM memory for this. */
2919 val = readl(base->virtbase + D40_DREG_LCPA);
2920 if (res->start != val && val != 0) {
2921 dev_warn(&pdev->dev,
2922 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2923 __func__, val, res->start);
2924 } else
2925 writel(res->start, base->virtbase + D40_DREG_LCPA);
2926
2927 base->lcpa_base = ioremap(res->start, resource_size(res));
2928 if (!base->lcpa_base) {
2929 ret = -ENOMEM;
6db5a8ba 2930 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 2931 goto failure;
2932 }
8d318a50 2933
508849ad
LW		 2934 ret = d40_lcla_allocate(base);
2935 if (ret) {
6db5a8ba 2936 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
8d318a50
LW		 2937 goto failure;
2938 }
2939
2940 spin_lock_init(&base->lcla_pool.lock);
2941
8d318a50
LW		 2942 base->irq = platform_get_irq(pdev, 0);
2943
2944 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 2945 if (ret) {
6db5a8ba 2946 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 2947 goto failure;
2948 }
2949
2950 err = d40_dmaengine_init(base, num_reserved_chans);
2951 if (err)
2952 goto failure;
2953
2954 d40_hw_init(base);
2955
2956 dev_info(base->dev, "initialized\n");
2957 return 0;
2958
2959failure:
2960 if (base) {
c675b1b4
JA		 2961 if (base->desc_slab)
2962 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 2963 if (base->virtbase)
2964 iounmap(base->virtbase);
026cbc42
RV		 2965
2966 if (base->lcla_pool.dma_addr)
2967 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
2968 SZ_1K * base->num_phy_chans,
2969 DMA_TO_DEVICE);
2970
508849ad
LW		 2971 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2972 free_pages((unsigned long)base->lcla_pool.base,
2973 base->lcla_pool.pages);
767a9675
JA		 2974
2975 kfree(base->lcla_pool.base_unaligned);
2976
8d318a50
LW		 2977 if (base->phy_lcpa)
2978 release_mem_region(base->phy_lcpa,
2979 base->lcpa_size);
2980 if (base->phy_start)
2981 release_mem_region(base->phy_start,
2982 base->phy_size);
2983 if (base->clk) {
2984 clk_disable(base->clk);
2985 clk_put(base->clk);
2986 }
2987
2988 kfree(base->lcla_pool.alloc_map);
2989 kfree(base->lookup_log_chans);
2990 kfree(base->lookup_phy_chans);
2991 kfree(base->phy_res);
2992 kfree(base);
2993 }
2994
6db5a8ba 2995 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 2996 return ret;
2997}
2998
2999static struct platform_driver d40_driver = {
3000 .driver = {
3001 .owner = THIS_MODULE,
3002 .name = D40_NAME,
3003 },
3004};
3005
cb9ab2d8 3006static int __init stedma40_init(void)
8d318a50
LW		 3007{
3008 return platform_driver_probe(&d40_driver, d40_probe);
3009}
3010arch_initcall(stedma40_init);
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