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dma40: combine duplicated code in log_sg_to_dev
[mirror_ubuntu-hirsute-kernel.git] / drivers / dma / ste_dma40.c
CommitLineData
8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
9#include <linux/kernel.h>
10#include <linux/slab.h>
11#include <linux/dmaengine.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
698e4732 15#include <linux/err.h>
8d318a50
LW		 16
17#include <plat/ste_dma40.h>
18
19#include "ste_dma40_ll.h"
20
21#define D40_NAME "dma40"
22
23#define D40_PHY_CHAN -1
24
25/* For masking out/in 2 bit channel positions */
26#define D40_CHAN_POS(chan) (2 * (chan / 2))
27#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
28
29/* Maximum iterations taken before giving up suspending a channel */
30#define D40_SUSPEND_MAX_IT 500
31
508849ad
LW		 32/* Hardware requirement on LCLA alignment */
33#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 34
35/* Max number of links per event group */
36#define D40_LCLA_LINK_PER_EVENT_GRP 128
37#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
38
508849ad
LW		 39/* Attempts before giving up to trying to get pages that are aligned */
40#define MAX_LCLA_ALLOC_ATTEMPTS 256
41
42/* Bit markings for allocation map */
8d318a50
LW		 43#define D40_ALLOC_FREE (1 << 31)
44#define D40_ALLOC_PHY (1 << 30)
45#define D40_ALLOC_LOG_FREE 0
46
8d318a50 47/* Hardware designer of the block */
3ae0267f 48#define D40_HW_DESIGNER 0x8
8d318a50
LW		 49
50/**
51 * enum 40_command - The different commands and/or statuses.
52 *
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 */
58enum d40_command {
59 D40_DMA_STOP = 0,
60 D40_DMA_RUN = 1,
61 D40_DMA_SUSPEND_REQ = 2,
62 D40_DMA_SUSPENDED = 3
63};
64
65/**
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
67 *
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
b00f938c 71 * @dma_addr: DMA address, if mapped
8d318a50
LW		 72 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
73 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
74 * one buffer to one buffer.
75 */
76struct d40_lli_pool {
77 void *base;
508849ad 78 int size;
b00f938c 79 dma_addr_t dma_addr;
8d318a50 80 /* Space for dst and src, plus an extra for padding */
508849ad 81 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 82};
83
84/**
85 * struct d40_desc - A descriptor is one DMA job.
86 *
87 * @lli_phy: LLI settings for physical channel. Both src and dst=
88 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
89 * lli_len equals one.
90 * @lli_log: Same as above but for logical channels.
91 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 92 * @lli_len: Number of llis of current descriptor.
698e4732
JA		 93 * @lli_current: Number of transfered llis.
94 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 95 * @txd: DMA engine struct. Used for among other things for communication
96 * during a transfer.
97 * @node: List entry.
8d318a50 98 * @is_in_client_list: true if the client owns this descriptor.
aa182ae2 99 * the previous one.
8d318a50
LW		 100 *
101 * This descriptor is used for both logical and physical transfers.
102 */
8d318a50
LW		 103struct d40_desc {
104 /* LLI physical */
105 struct d40_phy_lli_bidir lli_phy;
106 /* LLI logical */
107 struct d40_log_lli_bidir lli_log;
108
109 struct d40_lli_pool lli_pool;
941b77a3 110 int lli_len;
698e4732
JA		 111 int lli_current;
112 int lcla_alloc;
8d318a50
LW		 113
114 struct dma_async_tx_descriptor txd;
115 struct list_head node;
116
8d318a50
LW		 117 bool is_in_client_list;
118};
119
120/**
121 * struct d40_lcla_pool - LCLA pool settings and data.
122 *
508849ad
LW		 123 * @base: The virtual address of LCLA. 18 bit aligned.
124 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
125 * This pointer is only there for clean-up on error.
126 * @pages: The number of pages needed for all physical channels.
127 * Only used later for clean-up on error
8d318a50 128 * @lock: Lock to protect the content in this struct.
698e4732 129 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 130 */
131struct d40_lcla_pool {
132 void *base;
026cbc42 133 dma_addr_t dma_addr;
508849ad
LW		 134 void *base_unaligned;
135 int pages;
8d318a50 136 spinlock_t lock;
698e4732 137 struct d40_desc **alloc_map;
8d318a50
LW		 138};
139
140/**
141 * struct d40_phy_res - struct for handling eventlines mapped to physical
142 * channels.
143 *
144 * @lock: A lock protection this entity.
145 * @num: The physical channel number of this entity.
146 * @allocated_src: Bit mapped to show which src event line's are mapped to
147 * this physical channel. Can also be free or physically allocated.
148 * @allocated_dst: Same as for src but is dst.
149 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 150 * event line number.
8d318a50
LW		 151 */
152struct d40_phy_res {
153 spinlock_t lock;
154 int num;
155 u32 allocated_src;
156 u32 allocated_dst;
157};
158
159struct d40_base;
160
161/**
162 * struct d40_chan - Struct that describes a channel.
163 *
164 * @lock: A spinlock to protect this struct.
165 * @log_num: The logical number, if any of this channel.
166 * @completed: Starts with 1, after first interrupt it is set to dma engine's
167 * current cookie.
168 * @pending_tx: The number of pending transfers. Used between interrupt handler
169 * and tasklet.
170 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 171 * @phy_chan: Pointer to physical channel which this instance runs on. If this
172 * point is NULL, then the channel is not allocated.
8d318a50
LW		 173 * @chan: DMA engine handle.
174 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
175 * transfer and call client callback.
176 * @client: Cliented owned descriptor list.
177 * @active: Active descriptor.
178 * @queue: Queued jobs.
8d318a50 179 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 180 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
187 *
188 * This struct can either "be" a logical or a physical channel.
189 */
190struct d40_chan {
191 spinlock_t lock;
192 int log_num;
193 /* ID of the most recent completed transfer */
194 int completed;
195 int pending_tx;
196 bool busy;
197 struct d40_phy_res *phy_chan;
198 struct dma_chan chan;
199 struct tasklet_struct tasklet;
200 struct list_head client;
201 struct list_head active;
202 struct list_head queue;
8d318a50 203 struct stedma40_chan_cfg dma_cfg;
ce2ca125 204 bool configured;
8d318a50
LW		 205 struct d40_base *base;
206 /* Default register configurations */
207 u32 src_def_cfg;
208 u32 dst_def_cfg;
209 struct d40_def_lcsp log_def;
8d318a50 210 struct d40_log_lli_full *lcpa;
95e1400f
LW		 211 /* Runtime reconfiguration */
212 dma_addr_t runtime_addr;
213 enum dma_data_direction runtime_direction;
8d318a50
LW		 214};
215
216/**
217 * struct d40_base - The big global struct, one for each probe'd instance.
218 *
219 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220 * @execmd_lock: Lock for execute command usage since several channels share
221 * the same physical register.
222 * @dev: The device structure.
223 * @virtbase: The virtual base address of the DMA's register.
f4185592 224 * @rev: silicon revision detected.
8d318a50
LW		 225 * @clk: Pointer to the DMA clock structure.
226 * @phy_start: Physical memory start of the DMA registers.
227 * @phy_size: Size of the DMA register map.
228 * @irq: The IRQ number.
229 * @num_phy_chans: The number of physical channels. Read from HW. This
230 * is the number of available channels for this driver, not counting "Secure
231 * mode" allocated physical channels.
232 * @num_log_chans: The number of logical channels. Calculated from
233 * num_phy_chans.
234 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235 * @dma_slave: dma_device channels that can do only do slave transfers.
236 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
8d318a50
LW		 237 * @log_chans: Room for all possible logical channels in system.
238 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
239 * to log_chans entries.
240 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
241 * to phy_chans entries.
242 * @plat_data: Pointer to provided platform_data which is the driver
243 * configuration.
244 * @phy_res: Vector containing all physical channels.
245 * @lcla_pool: lcla pool settings and data.
246 * @lcpa_base: The virtual mapped address of LCPA.
247 * @phy_lcpa: The physical address of the LCPA.
248 * @lcpa_size: The size of the LCPA area.
c675b1b4 249 * @desc_slab: cache for descriptors.
8d318a50
LW		 250 */
251struct d40_base {
252 spinlock_t interrupt_lock;
253 spinlock_t execmd_lock;
254 struct device *dev;
255 void __iomem *virtbase;
f4185592 256 u8 rev:4;
8d318a50
LW		 257 struct clk *clk;
258 phys_addr_t phy_start;
259 resource_size_t phy_size;
260 int irq;
261 int num_phy_chans;
262 int num_log_chans;
263 struct dma_device dma_both;
264 struct dma_device dma_slave;
265 struct dma_device dma_memcpy;
266 struct d40_chan *phy_chans;
267 struct d40_chan *log_chans;
268 struct d40_chan **lookup_log_chans;
269 struct d40_chan **lookup_phy_chans;
270 struct stedma40_platform_data *plat_data;
271 /* Physical half channels */
272 struct d40_phy_res *phy_res;
273 struct d40_lcla_pool lcla_pool;
274 void *lcpa_base;
275 dma_addr_t phy_lcpa;
276 resource_size_t lcpa_size;
c675b1b4 277 struct kmem_cache *desc_slab;
8d318a50
LW		 278};
279
280/**
281 * struct d40_interrupt_lookup - lookup table for interrupt handler
282 *
283 * @src: Interrupt mask register.
284 * @clr: Interrupt clear register.
285 * @is_error: true if this is an error interrupt.
286 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
287 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
288 */
289struct d40_interrupt_lookup {
290 u32 src;
291 u32 clr;
292 bool is_error;
293 int offset;
294};
295
296/**
297 * struct d40_reg_val - simple lookup struct
298 *
299 * @reg: The register.
300 * @val: The value that belongs to the register in reg.
301 */
302struct d40_reg_val {
303 unsigned int reg;
304 unsigned int val;
305};
306
262d2915
RV		 307static struct device *chan2dev(struct d40_chan *d40c)
308{
309 return &d40c->chan.dev->device;
310}
311
724a8577
RV		 312static bool chan_is_physical(struct d40_chan *chan)
313{
314 return chan->log_num == D40_PHY_CHAN;
315}
316
317static bool chan_is_logical(struct d40_chan *chan)
318{
319 return !chan_is_physical(chan);
320}
321
8ca84687
RV		 322static void __iomem *chan_base(struct d40_chan *chan)
323{
324 return chan->base->virtbase + D40_DREG_PCBASE +
325 chan->phy_chan->num * D40_DREG_PCDELTA;
326}
327
6db5a8ba
RV		 328#define d40_err(dev, format, arg...) \
329 dev_err(dev, "[%s] " format, __func__, ## arg)
330
331#define chan_err(d40c, format, arg...) \
332 d40_err(chan2dev(d40c), format, ## arg)
333
b00f938c 334static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
dbd88788 335 int lli_len)
8d318a50 336{
dbd88788 337 bool is_log = chan_is_logical(d40c);
8d318a50
LW		 338 u32 align;
339 void *base;
340
341 if (is_log)
342 align = sizeof(struct d40_log_lli);
343 else
344 align = sizeof(struct d40_phy_lli);
345
346 if (lli_len == 1) {
347 base = d40d->lli_pool.pre_alloc_lli;
348 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
349 d40d->lli_pool.base = NULL;
350 } else {
594ece4d 351 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 352
353 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
354 d40d->lli_pool.base = base;
355
356 if (d40d->lli_pool.base == NULL)
357 return -ENOMEM;
358 }
359
360 if (is_log) {
d924abad 361 d40d->lli_log.src = PTR_ALIGN(base, align);
594ece4d 362 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 363
364 d40d->lli_pool.dma_addr = 0;
8d318a50 365 } else {
d924abad 366 d40d->lli_phy.src = PTR_ALIGN(base, align);
594ece4d 367 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 368
369 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
370 d40d->lli_phy.src,
371 d40d->lli_pool.size,
372 DMA_TO_DEVICE);
373
374 if (dma_mapping_error(d40c->base->dev,
375 d40d->lli_pool.dma_addr)) {
376 kfree(d40d->lli_pool.base);
377 d40d->lli_pool.base = NULL;
378 d40d->lli_pool.dma_addr = 0;
379 return -ENOMEM;
380 }
8d318a50
LW		 381 }
382
383 return 0;
384}
385
b00f938c 386static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 387{
b00f938c
RV		 388 if (d40d->lli_pool.dma_addr)
389 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
390 d40d->lli_pool.size, DMA_TO_DEVICE);
391
8d318a50
LW		 392 kfree(d40d->lli_pool.base);
393 d40d->lli_pool.base = NULL;
394 d40d->lli_pool.size = 0;
395 d40d->lli_log.src = NULL;
396 d40d->lli_log.dst = NULL;
397 d40d->lli_phy.src = NULL;
398 d40d->lli_phy.dst = NULL;
8d318a50
LW		 399}
400
698e4732
JA		 401static int d40_lcla_alloc_one(struct d40_chan *d40c,
402 struct d40_desc *d40d)
403{
404 unsigned long flags;
405 int i;
406 int ret = -EINVAL;
407 int p;
408
409 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
410
411 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
412
413 /*
414 * Allocate both src and dst at the same time, therefore the half
415 * start on 1 since 0 can't be used since zero is used as end marker.
416 */
417 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
418 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
419 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
420 d40d->lcla_alloc++;
421 ret = i;
422 break;
423 }
424 }
425
426 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
427
428 return ret;
429}
430
431static int d40_lcla_free_all(struct d40_chan *d40c,
432 struct d40_desc *d40d)
433{
434 unsigned long flags;
435 int i;
436 int ret = -EINVAL;
437
724a8577 438 if (chan_is_physical(d40c))
698e4732
JA		 439 return 0;
440
441 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
442
443 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
444 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
445 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
446 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
447 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
448 d40d->lcla_alloc--;
449 if (d40d->lcla_alloc == 0) {
450 ret = 0;
451 break;
452 }
453 }
454 }
455
456 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
457
458 return ret;
459
460}
461
8d318a50
LW		 462static void d40_desc_remove(struct d40_desc *d40d)
463{
464 list_del(&d40d->node);
465}
466
467static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
468{
a2c15fa4 469 struct d40_desc *desc = NULL;
8d318a50
LW		 470
471 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 472 struct d40_desc *d;
473 struct d40_desc *_d;
474
8d318a50
LW		 475 list_for_each_entry_safe(d, _d, &d40c->client, node)
476 if (async_tx_test_ack(&d->txd)) {
b00f938c 477 d40_pool_lli_free(d40c, d);
8d318a50 478 d40_desc_remove(d);
a2c15fa4
RV		 479 desc = d;
480 memset(desc, 0, sizeof(*desc));
c675b1b4 481 break;
8d318a50 482 }
8d318a50 483 }
a2c15fa4
RV		 484
485 if (!desc)
486 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
487
488 if (desc)
489 INIT_LIST_HEAD(&desc->node);
490
491 return desc;
8d318a50
LW		 492}
493
494static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
495{
698e4732 496
b00f938c 497 d40_pool_lli_free(d40c, d40d);
698e4732 498 d40_lcla_free_all(d40c, d40d);
c675b1b4 499 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 500}
501
502static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
503{
504 list_add_tail(&desc->node, &d40c->active);
505}
506
1c4b0927
RV		 507static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
508{
509 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
510 struct d40_phy_lli *lli_src = desc->lli_phy.src;
511 void __iomem *base = chan_base(chan);
512
513 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
514 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
515 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
516 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
517
518 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
519 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
520 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
521 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
522}
523
698e4732
JA		 524static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
525{
526 int curr_lcla = -EINVAL, next_lcla;
527
724a8577 528 if (chan_is_physical(d40c)) {
1c4b0927 529 d40_phy_lli_load(d40c, d40d);
698e4732
JA		 530 d40d->lli_current = d40d->lli_len;
531 } else {
532
533 if ((d40d->lli_len - d40d->lli_current) > 1)
534 curr_lcla = d40_lcla_alloc_one(d40c, d40d);
535
536 d40_log_lli_lcpa_write(d40c->lcpa,
537 &d40d->lli_log.dst[d40d->lli_current],
538 &d40d->lli_log.src[d40d->lli_current],
539 curr_lcla);
540
541 d40d->lli_current++;
542 for (; d40d->lli_current < d40d->lli_len; d40d->lli_current++) {
026cbc42
RV		 543 unsigned int lcla_offset = d40c->phy_chan->num * 1024 +
544 8 * curr_lcla * 2;
545 struct d40_lcla_pool *pool = &d40c->base->lcla_pool;
546 struct d40_log_lli *lcla = pool->base + lcla_offset;
698e4732
JA		 547
548 if (d40d->lli_current + 1 < d40d->lli_len)
549 next_lcla = d40_lcla_alloc_one(d40c, d40d);
550 else
551 next_lcla = -EINVAL;
552
698e4732
JA		 553 d40_log_lli_lcla_write(lcla,
554 &d40d->lli_log.dst[d40d->lli_current],
555 &d40d->lli_log.src[d40d->lli_current],
556 next_lcla);
557
026cbc42
RV		 558 dma_sync_single_range_for_device(d40c->base->dev,
559 pool->dma_addr, lcla_offset,
560 2 * sizeof(struct d40_log_lli),
561 DMA_TO_DEVICE);
698e4732
JA		 562
563 curr_lcla = next_lcla;
564
565 if (curr_lcla == -EINVAL) {
566 d40d->lli_current++;
567 break;
568 }
569
570 }
571 }
572}
573
8d318a50
LW		 574static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
575{
576 struct d40_desc *d;
577
578 if (list_empty(&d40c->active))
579 return NULL;
580
581 d = list_first_entry(&d40c->active,
582 struct d40_desc,
583 node);
584 return d;
585}
586
587static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
588{
589 list_add_tail(&desc->node, &d40c->queue);
590}
591
592static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
593{
594 struct d40_desc *d;
595
596 if (list_empty(&d40c->queue))
597 return NULL;
598
599 d = list_first_entry(&d40c->queue,
600 struct d40_desc,
601 node);
602 return d;
603}
604
d49278e3
PF		 605static int d40_psize_2_burst_size(bool is_log, int psize)
606{
607 if (is_log) {
608 if (psize == STEDMA40_PSIZE_LOG_1)
609 return 1;
610 } else {
611 if (psize == STEDMA40_PSIZE_PHY_1)
612 return 1;
613 }
614
615 return 2 << psize;
616}
617
618/*
619 * The dma only supports transmitting packages up to
620 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
621 * dma elements required to send the entire sg list
622 */
623static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
624{
625 int dmalen;
626 u32 max_w = max(data_width1, data_width2);
627 u32 min_w = min(data_width1, data_width2);
628 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
629
630 if (seg_max > STEDMA40_MAX_SEG_SIZE)
631 seg_max -= (1 << max_w);
632
633 if (!IS_ALIGNED(size, 1 << max_w))
634 return -EINVAL;
635
636 if (size <= seg_max)
637 dmalen = 1;
638 else {
639 dmalen = size / seg_max;
640 if (dmalen * seg_max < size)
641 dmalen++;
642 }
643 return dmalen;
644}
645
646static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
647 u32 data_width1, u32 data_width2)
648{
649 struct scatterlist *sg;
650 int i;
651 int len = 0;
652 int ret;
653
654 for_each_sg(sgl, sg, sg_len, i) {
655 ret = d40_size_2_dmalen(sg_dma_len(sg),
656 data_width1, data_width2);
657 if (ret < 0)
658 return ret;
659 len += ret;
660 }
661 return len;
662}
8d318a50 663
d49278e3 664/* Support functions for logical channels */
8d318a50
LW		 665
666static int d40_channel_execute_command(struct d40_chan *d40c,
667 enum d40_command command)
668{
767a9675
JA		 669 u32 status;
670 int i;
8d318a50
LW		 671 void __iomem *active_reg;
672 int ret = 0;
673 unsigned long flags;
1d392a7b 674 u32 wmask;
8d318a50
LW		 675
676 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
677
678 if (d40c->phy_chan->num % 2 == 0)
679 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
680 else
681 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
682
683 if (command == D40_DMA_SUSPEND_REQ) {
684 status = (readl(active_reg) &
685 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
686 D40_CHAN_POS(d40c->phy_chan->num);
687
688 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
689 goto done;
690 }
691
1d392a7b
JA		 692 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
693 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
694 active_reg);
8d318a50
LW		 695
696 if (command == D40_DMA_SUSPEND_REQ) {
697
698 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
699 status = (readl(active_reg) &
700 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
701 D40_CHAN_POS(d40c->phy_chan->num);
702
703 cpu_relax();
704 /*
705 * Reduce the number of bus accesses while
706 * waiting for the DMA to suspend.
707 */
708 udelay(3);
709
710 if (status == D40_DMA_STOP ||
711 status == D40_DMA_SUSPENDED)
712 break;
713 }
714
715 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 716 chan_err(d40c,
717 "unable to suspend the chl %d (log: %d) status %x\n",
718 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 719 status);
720 dump_stack();
721 ret = -EBUSY;
722 }
723
724 }
725done:
726 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
727 return ret;
728}
729
730static void d40_term_all(struct d40_chan *d40c)
731{
732 struct d40_desc *d40d;
8d318a50
LW		 733
734 /* Release active descriptors */
735 while ((d40d = d40_first_active_get(d40c))) {
736 d40_desc_remove(d40d);
8d318a50
LW		 737 d40_desc_free(d40c, d40d);
738 }
739
740 /* Release queued descriptors waiting for transfer */
741 while ((d40d = d40_first_queued(d40c))) {
742 d40_desc_remove(d40d);
8d318a50
LW		 743 d40_desc_free(d40c, d40d);
744 }
745
8d318a50
LW		 746
747 d40c->pending_tx = 0;
748 d40c->busy = false;
749}
750
262d2915
RV		 751static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
752 u32 event, int reg)
753{
8ca84687 754 void __iomem *addr = chan_base(d40c) + reg;
262d2915
RV		 755 int tries;
756
757 if (!enable) {
758 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
759 | ~D40_EVENTLINE_MASK(event), addr);
760 return;
761 }
762
763 /*
764 * The hardware sometimes doesn't register the enable when src and dst
765 * event lines are active on the same logical channel. Retry to ensure
766 * it does. Usually only one retry is sufficient.
767 */
768 tries = 100;
769 while (--tries) {
770 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
771 | ~D40_EVENTLINE_MASK(event), addr);
772
773 if (readl(addr) & D40_EVENTLINE_MASK(event))
774 break;
775 }
776
777 if (tries != 99)
778 dev_dbg(chan2dev(d40c),
779 "[%s] workaround enable S%cLNK (%d tries)\n",
780 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
781 100 - tries);
782
783 WARN_ON(!tries);
784}
785
8d318a50
LW		 786static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
787{
8d318a50
LW		 788 unsigned long flags;
789
8d318a50
LW		 790 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
791
792 /* Enable event line connected to device (or memcpy) */
793 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
794 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
795 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
796
262d2915
RV		 797 __d40_config_set_event(d40c, do_enable, event,
798 D40_CHAN_REG_SSLNK);
8d318a50 799 }
262d2915 800
8d318a50
LW		 801 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
802 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
803
262d2915
RV		 804 __d40_config_set_event(d40c, do_enable, event,
805 D40_CHAN_REG_SDLNK);
8d318a50
LW		 806 }
807
808 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
809}
810
a5ebca47 811static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 812{
8ca84687 813 void __iomem *chanbase = chan_base(d40c);
be8cb7df 814 u32 val;
8d318a50 815
8ca84687
RV		 816 val = readl(chanbase + D40_CHAN_REG_SSLNK);
817 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 818
a5ebca47 819 return val;
8d318a50
LW		 820}
821
20a5b6d0
RV		 822static u32 d40_get_prmo(struct d40_chan *d40c)
823{
824 static const unsigned int phy_map[] = {
825 [STEDMA40_PCHAN_BASIC_MODE]
826 = D40_DREG_PRMO_PCHAN_BASIC,
827 [STEDMA40_PCHAN_MODULO_MODE]
828 = D40_DREG_PRMO_PCHAN_MODULO,
829 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
830 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
831 };
832 static const unsigned int log_map[] = {
833 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
834 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
835 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
836 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
837 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
838 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
839 };
840
724a8577 841 if (chan_is_physical(d40c))
20a5b6d0
RV		 842 return phy_map[d40c->dma_cfg.mode_opt];
843 else
844 return log_map[d40c->dma_cfg.mode_opt];
845}
846
b55912c6 847static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 848{
849 u32 addr_base;
850 u32 var;
8d318a50
LW		 851
852 /* Odd addresses are even addresses + 4 */
853 addr_base = (d40c->phy_chan->num % 2) * 4;
854 /* Setup channel mode to logical or physical */
724a8577 855 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 856 D40_CHAN_POS(d40c->phy_chan->num);
857 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
858
859 /* Setup operational mode option register */
20a5b6d0 860 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 861
862 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
863
724a8577 864 if (chan_is_logical(d40c)) {
8ca84687
RV		 865 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
866 & D40_SREG_ELEM_LOG_LIDX_MASK;
867 void __iomem *chanbase = chan_base(d40c);
868
8d318a50 869 /* Set default config for CFG reg */
8ca84687
RV		 870 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
871 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 872
b55912c6 873 /* Set LIDX for lcla */
8ca84687
RV		 874 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
875 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
8d318a50 876 }
8d318a50
LW		 877}
878
aa182ae2
JA		 879static u32 d40_residue(struct d40_chan *d40c)
880{
881 u32 num_elt;
882
724a8577 883 if (chan_is_logical(d40c))
aa182ae2
JA		 884 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
885 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 886 else {
887 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
888 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
889 >> D40_SREG_ELEM_PHY_ECNT_POS;
890 }
891
aa182ae2
JA		 892 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
893}
894
895static bool d40_tx_is_linked(struct d40_chan *d40c)
896{
897 bool is_link;
898
724a8577 899 if (chan_is_logical(d40c))
aa182ae2
JA		 900 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
901 else
8ca84687
RV		 902 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
903 & D40_SREG_LNK_PHYS_LNK_MASK;
904
aa182ae2
JA		 905 return is_link;
906}
907
908static int d40_pause(struct dma_chan *chan)
909{
910 struct d40_chan *d40c =
911 container_of(chan, struct d40_chan, chan);
912 int res = 0;
913 unsigned long flags;
914
3ac012af
JA		 915 if (!d40c->busy)
916 return 0;
917
aa182ae2
JA		 918 spin_lock_irqsave(&d40c->lock, flags);
919
920 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
921 if (res == 0) {
724a8577 922 if (chan_is_logical(d40c)) {
aa182ae2
JA		 923 d40_config_set_event(d40c, false);
924 /* Resume the other logical channels if any */
925 if (d40_chan_has_events(d40c))
926 res = d40_channel_execute_command(d40c,
927 D40_DMA_RUN);
928 }
929 }
930
931 spin_unlock_irqrestore(&d40c->lock, flags);
932 return res;
933}
934
935static int d40_resume(struct dma_chan *chan)
936{
937 struct d40_chan *d40c =
938 container_of(chan, struct d40_chan, chan);
939 int res = 0;
940 unsigned long flags;
941
3ac012af
JA		 942 if (!d40c->busy)
943 return 0;
944
aa182ae2
JA		 945 spin_lock_irqsave(&d40c->lock, flags);
946
947 if (d40c->base->rev == 0)
724a8577 948 if (chan_is_logical(d40c)) {
aa182ae2
JA		 949 res = d40_channel_execute_command(d40c,
950 D40_DMA_SUSPEND_REQ);
951 goto no_suspend;
952 }
953
954 /* If bytes left to transfer or linked tx resume job */
955 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
956
724a8577 957 if (chan_is_logical(d40c))
aa182ae2
JA		 958 d40_config_set_event(d40c, true);
959
960 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
961 }
962
963no_suspend:
964 spin_unlock_irqrestore(&d40c->lock, flags);
965 return res;
966}
967
8d318a50
LW		 968static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
969{
970 struct d40_chan *d40c = container_of(tx->chan,
971 struct d40_chan,
972 chan);
973 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
974 unsigned long flags;
975
976 spin_lock_irqsave(&d40c->lock, flags);
977
aa182ae2
JA		 978 d40c->chan.cookie++;
979
980 if (d40c->chan.cookie < 0)
981 d40c->chan.cookie = 1;
982
983 d40d->txd.cookie = d40c->chan.cookie;
984
8d318a50
LW		 985 d40_desc_queue(d40c, d40d);
986
987 spin_unlock_irqrestore(&d40c->lock, flags);
988
989 return tx->cookie;
990}
991
992static int d40_start(struct d40_chan *d40c)
993{
f4185592
LW		 994 if (d40c->base->rev == 0) {
995 int err;
996
724a8577 997 if (chan_is_logical(d40c)) {
f4185592
LW		 998 err = d40_channel_execute_command(d40c,
999 D40_DMA_SUSPEND_REQ);
1000 if (err)
1001 return err;
1002 }
1003 }
1004
724a8577 1005 if (chan_is_logical(d40c))
8d318a50 1006 d40_config_set_event(d40c, true);
8d318a50 1007
0c32269d 1008 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 1009}
1010
1011static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1012{
1013 struct d40_desc *d40d;
1014 int err;
1015
1016 /* Start queued jobs, if any */
1017 d40d = d40_first_queued(d40c);
1018
1019 if (d40d != NULL) {
1020 d40c->busy = true;
1021
1022 /* Remove from queue */
1023 d40_desc_remove(d40d);
1024
1025 /* Add to active queue */
1026 d40_desc_submit(d40c, d40d);
1027
7d83a854
RV		 1028 /* Initiate DMA job */
1029 d40_desc_load(d40c, d40d);
8d318a50 1030
7d83a854
RV		 1031 /* Start dma job */
1032 err = d40_start(d40c);
8d318a50 1033
7d83a854
RV		 1034 if (err)
1035 return NULL;
8d318a50
LW		 1036 }
1037
1038 return d40d;
1039}
1040
1041/* called from interrupt context */
1042static void dma_tc_handle(struct d40_chan *d40c)
1043{
1044 struct d40_desc *d40d;
1045
8d318a50
LW		 1046 /* Get first active entry from list */
1047 d40d = d40_first_active_get(d40c);
1048
1049 if (d40d == NULL)
1050 return;
1051
698e4732 1052 d40_lcla_free_all(d40c, d40d);
8d318a50 1053
698e4732 1054 if (d40d->lli_current < d40d->lli_len) {
8d318a50
LW		 1055 d40_desc_load(d40c, d40d);
1056 /* Start dma job */
1057 (void) d40_start(d40c);
1058 return;
1059 }
1060
1061 if (d40_queue_start(d40c) == NULL)
1062 d40c->busy = false;
1063
1064 d40c->pending_tx++;
1065 tasklet_schedule(&d40c->tasklet);
1066
1067}
1068
1069static void dma_tasklet(unsigned long data)
1070{
1071 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1072 struct d40_desc *d40d;
8d318a50
LW		 1073 unsigned long flags;
1074 dma_async_tx_callback callback;
1075 void *callback_param;
1076
1077 spin_lock_irqsave(&d40c->lock, flags);
1078
1079 /* Get first active entry from list */
767a9675 1080 d40d = d40_first_active_get(d40c);
8d318a50 1081
767a9675 1082 if (d40d == NULL)
8d318a50
LW		 1083 goto err;
1084
767a9675 1085 d40c->completed = d40d->txd.cookie;
8d318a50
LW		 1086
1087 /*
1088 * If terminating a channel pending_tx is set to zero.
1089 * This prevents any finished active jobs to return to the client.
1090 */
1091 if (d40c->pending_tx == 0) {
1092 spin_unlock_irqrestore(&d40c->lock, flags);
1093 return;
1094 }
1095
1096 /* Callback to client */
767a9675
JA		 1097 callback = d40d->txd.callback;
1098 callback_param = d40d->txd.callback_param;
1099
1100 if (async_tx_test_ack(&d40d->txd)) {
b00f938c 1101 d40_pool_lli_free(d40c, d40d);
767a9675
JA		 1102 d40_desc_remove(d40d);
1103 d40_desc_free(d40c, d40d);
8d318a50 1104 } else {
767a9675
JA		 1105 if (!d40d->is_in_client_list) {
1106 d40_desc_remove(d40d);
698e4732 1107 d40_lcla_free_all(d40c, d40d);
767a9675
JA		 1108 list_add_tail(&d40d->node, &d40c->client);
1109 d40d->is_in_client_list = true;
8d318a50
LW		 1110 }
1111 }
1112
1113 d40c->pending_tx--;
1114
1115 if (d40c->pending_tx)
1116 tasklet_schedule(&d40c->tasklet);
1117
1118 spin_unlock_irqrestore(&d40c->lock, flags);
1119
767a9675 1120 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
8d318a50
LW		 1121 callback(callback_param);
1122
1123 return;
1124
1125 err:
1126 /* Rescue manouver if receiving double interrupts */
1127 if (d40c->pending_tx > 0)
1128 d40c->pending_tx--;
1129 spin_unlock_irqrestore(&d40c->lock, flags);
1130}
1131
1132static irqreturn_t d40_handle_interrupt(int irq, void *data)
1133{
1134 static const struct d40_interrupt_lookup il[] = {
1135 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1136 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1137 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1138 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1139 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1140 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1141 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1142 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1143 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1144 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1145 };
1146
1147 int i;
1148 u32 regs[ARRAY_SIZE(il)];
8d318a50
LW		 1149 u32 idx;
1150 u32 row;
1151 long chan = -1;
1152 struct d40_chan *d40c;
1153 unsigned long flags;
1154 struct d40_base *base = data;
1155
1156 spin_lock_irqsave(&base->interrupt_lock, flags);
1157
1158 /* Read interrupt status of both logical and physical channels */
1159 for (i = 0; i < ARRAY_SIZE(il); i++)
1160 regs[i] = readl(base->virtbase + il[i].src);
1161
1162 for (;;) {
1163
1164 chan = find_next_bit((unsigned long *)regs,
1165 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1166
1167 /* No more set bits found? */
1168 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1169 break;
1170
1171 row = chan / BITS_PER_LONG;
1172 idx = chan & (BITS_PER_LONG - 1);
1173
1174 /* ACK interrupt */
1b00348d 1175 writel(1 << idx, base->virtbase + il[row].clr);
8d318a50
LW		 1176
1177 if (il[row].offset == D40_PHY_CHAN)
1178 d40c = base->lookup_phy_chans[idx];
1179 else
1180 d40c = base->lookup_log_chans[il[row].offset + idx];
1181 spin_lock(&d40c->lock);
1182
1183 if (!il[row].is_error)
1184 dma_tc_handle(d40c);
1185 else
6db5a8ba
RV		 1186 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1187 chan, il[row].offset, idx);
8d318a50
LW		 1188
1189 spin_unlock(&d40c->lock);
1190 }
1191
1192 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1193
1194 return IRQ_HANDLED;
1195}
1196
8d318a50
LW		 1197static int d40_validate_conf(struct d40_chan *d40c,
1198 struct stedma40_chan_cfg *conf)
1199{
1200 int res = 0;
1201 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1202 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
38bdbf02 1203 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1204
0747c7ba 1205 if (!conf->dir) {
6db5a8ba 1206 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1207 res = -EINVAL;
1208 }
1209
1210 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1211 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1212 d40c->runtime_addr == 0) {
1213
6db5a8ba
RV		 1214 chan_err(d40c, "Invalid TX channel address (%d)\n",
1215 conf->dst_dev_type);
0747c7ba
LW		 1216 res = -EINVAL;
1217 }
1218
1219 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1220 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1221 d40c->runtime_addr == 0) {
6db5a8ba
RV		 1222 chan_err(d40c, "Invalid RX channel address (%d)\n",
1223 conf->src_dev_type);
0747c7ba
LW		 1224 res = -EINVAL;
1225 }
1226
1227 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
8d318a50 1228 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
6db5a8ba 1229 chan_err(d40c, "Invalid dst\n");
8d318a50
LW		 1230 res = -EINVAL;
1231 }
1232
0747c7ba 1233 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
8d318a50 1234 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
6db5a8ba 1235 chan_err(d40c, "Invalid src\n");
8d318a50
LW		 1236 res = -EINVAL;
1237 }
1238
1239 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1240 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
6db5a8ba 1241 chan_err(d40c, "No event line\n");
8d318a50
LW		 1242 res = -EINVAL;
1243 }
1244
1245 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1246 (src_event_group != dst_event_group)) {
6db5a8ba 1247 chan_err(d40c, "Invalid event group\n");
8d318a50
LW		 1248 res = -EINVAL;
1249 }
1250
1251 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1252 /*
1253 * DMAC HW supports it. Will be added to this driver,
1254 * in case any dma client requires it.
1255 */
6db5a8ba 1256 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1257 res = -EINVAL;
1258 }
1259
d49278e3
PF		 1260 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1261 (1 << conf->src_info.data_width) !=
1262 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1263 (1 << conf->dst_info.data_width)) {
1264 /*
1265 * The DMAC hardware only supports
1266 * src (burst x width) == dst (burst x width)
1267 */
1268
6db5a8ba 1269 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1270 res = -EINVAL;
1271 }
1272
8d318a50
LW		 1273 return res;
1274}
1275
1276static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
4aed79b2 1277 int log_event_line, bool is_log)
8d318a50
LW		 1278{
1279 unsigned long flags;
1280 spin_lock_irqsave(&phy->lock, flags);
4aed79b2 1281 if (!is_log) {
8d318a50
LW		 1282 /* Physical interrupts are masked per physical full channel */
1283 if (phy->allocated_src == D40_ALLOC_FREE &&
1284 phy->allocated_dst == D40_ALLOC_FREE) {
1285 phy->allocated_dst = D40_ALLOC_PHY;
1286 phy->allocated_src = D40_ALLOC_PHY;
1287 goto found;
1288 } else
1289 goto not_found;
1290 }
1291
1292 /* Logical channel */
1293 if (is_src) {
1294 if (phy->allocated_src == D40_ALLOC_PHY)
1295 goto not_found;
1296
1297 if (phy->allocated_src == D40_ALLOC_FREE)
1298 phy->allocated_src = D40_ALLOC_LOG_FREE;
1299
1300 if (!(phy->allocated_src & (1 << log_event_line))) {
1301 phy->allocated_src |= 1 << log_event_line;
1302 goto found;
1303 } else
1304 goto not_found;
1305 } else {
1306 if (phy->allocated_dst == D40_ALLOC_PHY)
1307 goto not_found;
1308
1309 if (phy->allocated_dst == D40_ALLOC_FREE)
1310 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1311
1312 if (!(phy->allocated_dst & (1 << log_event_line))) {
1313 phy->allocated_dst |= 1 << log_event_line;
1314 goto found;
1315 } else
1316 goto not_found;
1317 }
1318
1319not_found:
1320 spin_unlock_irqrestore(&phy->lock, flags);
1321 return false;
1322found:
1323 spin_unlock_irqrestore(&phy->lock, flags);
1324 return true;
1325}
1326
1327static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1328 int log_event_line)
1329{
1330 unsigned long flags;
1331 bool is_free = false;
1332
1333 spin_lock_irqsave(&phy->lock, flags);
1334 if (!log_event_line) {
8d318a50
LW		 1335 phy->allocated_dst = D40_ALLOC_FREE;
1336 phy->allocated_src = D40_ALLOC_FREE;
1337 is_free = true;
1338 goto out;
1339 }
1340
1341 /* Logical channel */
1342 if (is_src) {
1343 phy->allocated_src &= ~(1 << log_event_line);
1344 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1345 phy->allocated_src = D40_ALLOC_FREE;
1346 } else {
1347 phy->allocated_dst &= ~(1 << log_event_line);
1348 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1349 phy->allocated_dst = D40_ALLOC_FREE;
1350 }
1351
1352 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1353 D40_ALLOC_FREE);
1354
1355out:
1356 spin_unlock_irqrestore(&phy->lock, flags);
1357
1358 return is_free;
1359}
1360
1361static int d40_allocate_channel(struct d40_chan *d40c)
1362{
1363 int dev_type;
1364 int event_group;
1365 int event_line;
1366 struct d40_phy_res *phys;
1367 int i;
1368 int j;
1369 int log_num;
1370 bool is_src;
38bdbf02 1371 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1372
1373 phys = d40c->base->phy_res;
1374
1375 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1376 dev_type = d40c->dma_cfg.src_dev_type;
1377 log_num = 2 * dev_type;
1378 is_src = true;
1379 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1380 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1381 /* dst event lines are used for logical memcpy */
1382 dev_type = d40c->dma_cfg.dst_dev_type;
1383 log_num = 2 * dev_type + 1;
1384 is_src = false;
1385 } else
1386 return -EINVAL;
1387
1388 event_group = D40_TYPE_TO_GROUP(dev_type);
1389 event_line = D40_TYPE_TO_EVENT(dev_type);
1390
1391 if (!is_log) {
1392 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1393 /* Find physical half channel */
1394 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1395
4aed79b2
MM		 1396 if (d40_alloc_mask_set(&phys[i], is_src,
1397 0, is_log))
8d318a50
LW		 1398 goto found_phy;
1399 }
1400 } else
1401 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1402 int phy_num = j + event_group * 2;
1403 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1404 if (d40_alloc_mask_set(&phys[i],
1405 is_src,
1406 0,
1407 is_log))
8d318a50
LW		 1408 goto found_phy;
1409 }
1410 }
1411 return -EINVAL;
1412found_phy:
1413 d40c->phy_chan = &phys[i];
1414 d40c->log_num = D40_PHY_CHAN;
1415 goto out;
1416 }
1417 if (dev_type == -1)
1418 return -EINVAL;
1419
1420 /* Find logical channel */
1421 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1422 int phy_num = j + event_group * 2;
1423 /*
1424 * Spread logical channels across all available physical rather
1425 * than pack every logical channel at the first available phy
1426 * channels.
1427 */
1428 if (is_src) {
1429 for (i = phy_num; i < phy_num + 2; i++) {
1430 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1431 event_line, is_log))
8d318a50
LW		 1432 goto found_log;
1433 }
1434 } else {
1435 for (i = phy_num + 1; i >= phy_num; i--) {
1436 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1437 event_line, is_log))
8d318a50
LW		 1438 goto found_log;
1439 }
1440 }
1441 }
1442 return -EINVAL;
1443
1444found_log:
1445 d40c->phy_chan = &phys[i];
1446 d40c->log_num = log_num;
1447out:
1448
1449 if (is_log)
1450 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1451 else
1452 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1453
1454 return 0;
1455
1456}
1457
8d318a50
LW		 1458static int d40_config_memcpy(struct d40_chan *d40c)
1459{
1460 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1461
1462 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1463 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1464 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1465 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1466 memcpy[d40c->chan.chan_id];
1467
1468 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1469 dma_has_cap(DMA_SLAVE, cap)) {
1470 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1471 } else {
6db5a8ba 1472 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 1473 return -EINVAL;
1474 }
1475
1476 return 0;
1477}
1478
1479
1480static int d40_free_dma(struct d40_chan *d40c)
1481{
1482
1483 int res = 0;
d181b3a8 1484 u32 event;
8d318a50
LW		 1485 struct d40_phy_res *phy = d40c->phy_chan;
1486 bool is_src;
a8be8627
PF		 1487 struct d40_desc *d;
1488 struct d40_desc *_d;
1489
8d318a50
LW		 1490
1491 /* Terminate all queued and active transfers */
1492 d40_term_all(d40c);
1493
a8be8627
PF		 1494 /* Release client owned descriptors */
1495 if (!list_empty(&d40c->client))
1496 list_for_each_entry_safe(d, _d, &d40c->client, node) {
b00f938c 1497 d40_pool_lli_free(d40c, d);
a8be8627 1498 d40_desc_remove(d);
a8be8627
PF		 1499 d40_desc_free(d40c, d);
1500 }
1501
8d318a50 1502 if (phy == NULL) {
6db5a8ba 1503 chan_err(d40c, "phy == null\n");
8d318a50
LW		 1504 return -EINVAL;
1505 }
1506
1507 if (phy->allocated_src == D40_ALLOC_FREE &&
1508 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 1509 chan_err(d40c, "channel already free\n");
8d318a50
LW		 1510 return -EINVAL;
1511 }
1512
8d318a50
LW		 1513 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1514 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1515 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8d318a50
LW		 1516 is_src = false;
1517 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1518 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8d318a50
LW		 1519 is_src = true;
1520 } else {
6db5a8ba 1521 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 1522 return -EINVAL;
1523 }
1524
d181b3a8
JA		 1525 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1526 if (res) {
6db5a8ba 1527 chan_err(d40c, "suspend failed\n");
d181b3a8
JA		 1528 return res;
1529 }
1530
724a8577 1531 if (chan_is_logical(d40c)) {
d181b3a8 1532 /* Release logical channel, deactivate the event line */
8d318a50 1533
d181b3a8 1534 d40_config_set_event(d40c, false);
8d318a50
LW		 1535 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1536
1537 /*
1538 * Check if there are more logical allocation
1539 * on this phy channel.
1540 */
1541 if (!d40_alloc_mask_free(phy, is_src, event)) {
1542 /* Resume the other logical channels if any */
1543 if (d40_chan_has_events(d40c)) {
1544 res = d40_channel_execute_command(d40c,
1545 D40_DMA_RUN);
1546 if (res) {
6db5a8ba
RV		 1547 chan_err(d40c,
1548 "Executing RUN command\n");
8d318a50
LW		 1549 return res;
1550 }
1551 }
1552 return 0;
1553 }
d181b3a8
JA		 1554 } else {
1555 (void) d40_alloc_mask_free(phy, is_src, 0);
1556 }
8d318a50
LW		 1557
1558 /* Release physical channel */
1559 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1560 if (res) {
6db5a8ba 1561 chan_err(d40c, "Failed to stop channel\n");
8d318a50
LW		 1562 return res;
1563 }
1564 d40c->phy_chan = NULL;
ce2ca125 1565 d40c->configured = false;
8d318a50
LW		 1566 d40c->base->lookup_phy_chans[phy->num] = NULL;
1567
1568 return 0;
8d318a50
LW		 1569}
1570
a5ebca47
JA		 1571static bool d40_is_paused(struct d40_chan *d40c)
1572{
8ca84687 1573 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 1574 bool is_paused = false;
1575 unsigned long flags;
1576 void __iomem *active_reg;
1577 u32 status;
1578 u32 event;
a5ebca47
JA		 1579
1580 spin_lock_irqsave(&d40c->lock, flags);
1581
724a8577 1582 if (chan_is_physical(d40c)) {
a5ebca47
JA		 1583 if (d40c->phy_chan->num % 2 == 0)
1584 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1585 else
1586 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1587
1588 status = (readl(active_reg) &
1589 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1590 D40_CHAN_POS(d40c->phy_chan->num);
1591 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1592 is_paused = true;
1593
1594 goto _exit;
1595 }
1596
a5ebca47 1597 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
9dbfbd35 1598 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
a5ebca47 1599 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8ca84687 1600 status = readl(chanbase + D40_CHAN_REG_SDLNK);
9dbfbd35 1601 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
a5ebca47 1602 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8ca84687 1603 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 1604 } else {
6db5a8ba 1605 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 1606 goto _exit;
1607 }
9dbfbd35 1608
a5ebca47
JA		 1609 status = (status & D40_EVENTLINE_MASK(event)) >>
1610 D40_EVENTLINE_POS(event);
1611
1612 if (status != D40_DMA_RUN)
1613 is_paused = true;
a5ebca47
JA		 1614_exit:
1615 spin_unlock_irqrestore(&d40c->lock, flags);
1616 return is_paused;
1617
1618}
1619
1620
8d318a50
LW		 1621static u32 stedma40_residue(struct dma_chan *chan)
1622{
1623 struct d40_chan *d40c =
1624 container_of(chan, struct d40_chan, chan);
1625 u32 bytes_left;
1626 unsigned long flags;
1627
1628 spin_lock_irqsave(&d40c->lock, flags);
1629 bytes_left = d40_residue(d40c);
1630 spin_unlock_irqrestore(&d40c->lock, flags);
1631
1632 return bytes_left;
1633}
1634
3e3a0763
RV		 1635static int
1636d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
1637 struct scatterlist *sg_src, struct scatterlist *sg_dst,
1638 unsigned int sg_len, enum dma_data_direction direction,
1639 dma_addr_t dev_addr)
1640{
1641 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1642 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1643 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
1644
1645 if (direction == DMA_NONE) {
1646 /* memcpy */
1647 (void) d40_log_sg_to_lli(sg_src, sg_len,
1648 desc->lli_log.src,
1649 chan->log_def.lcsp1,
1650 src_info->data_width,
1651 dst_info->data_width);
1652
1653 (void) d40_log_sg_to_lli(sg_dst, sg_len,
1654 desc->lli_log.dst,
1655 chan->log_def.lcsp3,
1656 dst_info->data_width,
1657 src_info->data_width);
1658 } else {
1659 unsigned int total_size;
1660
1661 total_size = d40_log_sg_to_dev(sg_src, sg_len,
1662 &desc->lli_log,
1663 &chan->log_def,
1664 src_info->data_width,
1665 dst_info->data_width,
1666 direction, dev_addr);
1667 if (total_size < 0)
1668 return -EINVAL;
1669 }
1670
1671 return 0;
1672}
1673
1674static int
1675d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
1676 struct scatterlist *sg_src, struct scatterlist *sg_dst,
1677 unsigned int sg_len, enum dma_data_direction direction,
1678 dma_addr_t dev_addr)
1679{
1680 dma_addr_t src_dev_addr = direction == DMA_FROM_DEVICE ? dev_addr : 0;
1681 dma_addr_t dst_dev_addr = direction == DMA_TO_DEVICE ? dev_addr : 0;
1682 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1683 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1684 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
1685 int ret;
1686
1687 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
1688 desc->lli_phy.src,
1689 virt_to_phys(desc->lli_phy.src),
1690 chan->src_def_cfg,
1691 src_info->data_width,
1692 dst_info->data_width,
1693 src_info->psize);
1694
1695 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
1696 desc->lli_phy.dst,
1697 virt_to_phys(desc->lli_phy.dst),
1698 chan->dst_def_cfg,
1699 dst_info->data_width,
1700 src_info->data_width,
1701 dst_info->psize);
1702
1703 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
1704 desc->lli_pool.size, DMA_TO_DEVICE);
1705
1706 return ret < 0 ? ret : 0;
1707}
1708
1709
5f81158f
RV		 1710static struct d40_desc *
1711d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
1712 unsigned int sg_len, unsigned long dma_flags)
1713{
1714 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1715 struct d40_desc *desc;
dbd88788 1716 int ret;
5f81158f
RV		 1717
1718 desc = d40_desc_get(chan);
1719 if (!desc)
1720 return NULL;
1721
1722 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
1723 cfg->dst_info.data_width);
1724 if (desc->lli_len < 0) {
1725 chan_err(chan, "Unaligned size\n");
dbd88788
RV		 1726 goto err;
1727 }
5f81158f 1728
dbd88788
RV		 1729 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
1730 if (ret < 0) {
1731 chan_err(chan, "Could not allocate lli\n");
1732 goto err;
5f81158f
RV		 1733 }
1734
dbd88788 1735
5f81158f
RV		 1736 desc->lli_current = 0;
1737 desc->txd.flags = dma_flags;
1738 desc->txd.tx_submit = d40_tx_submit;
1739
1740 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
1741
1742 return desc;
dbd88788
RV		 1743
1744err:
1745 d40_desc_free(chan, desc);
1746 return NULL;
5f81158f
RV		 1747}
1748
cade1d30
RV		 1749static dma_addr_t
1750d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
8d318a50 1751{
cade1d30
RV		 1752 struct stedma40_platform_data *plat = chan->base->plat_data;
1753 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1754 dma_addr_t addr;
1755
1756 if (chan->runtime_addr)
1757 return chan->runtime_addr;
1758
1759 if (direction == DMA_FROM_DEVICE)
1760 addr = plat->dev_rx[cfg->src_dev_type];
1761 else if (direction == DMA_TO_DEVICE)
1762 addr = plat->dev_tx[cfg->dst_dev_type];
1763
1764 return addr;
1765}
1766
1767static struct dma_async_tx_descriptor *
1768d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
1769 struct scatterlist *sg_dst, unsigned int sg_len,
1770 enum dma_data_direction direction, unsigned long dma_flags)
1771{
1772 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
1773 dma_addr_t dev_addr = 0;
1774 struct d40_desc *desc;
2a614340 1775 unsigned long flags;
cade1d30 1776 int ret;
8d318a50 1777
cade1d30
RV		 1778 if (!chan->phy_chan) {
1779 chan_err(chan, "Cannot prepare unallocated channel\n");
1780 return NULL;
0d0f6b8b
JA		 1781 }
1782
cade1d30 1783 spin_lock_irqsave(&chan->lock, flags);
8d318a50 1784
cade1d30
RV		 1785 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
1786 if (desc == NULL)
8d318a50
LW		 1787 goto err;
1788
cade1d30
RV		 1789 if (direction != DMA_NONE)
1790 dev_addr = d40_get_dev_addr(chan, direction);
1791
1792 if (chan_is_logical(chan))
1793 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
1794 sg_len, direction, dev_addr);
1795 else
1796 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
1797 sg_len, direction, dev_addr);
1798
1799 if (ret) {
1800 chan_err(chan, "Failed to prepare %s sg job: %d\n",
1801 chan_is_logical(chan) ? "log" : "phy", ret);
1802 goto err;
8d318a50
LW		 1803 }
1804
cade1d30
RV		 1805 spin_unlock_irqrestore(&chan->lock, flags);
1806
1807 return &desc->txd;
8d318a50 1808
8d318a50 1809err:
cade1d30
RV		 1810 if (desc)
1811 d40_desc_free(chan, desc);
1812 spin_unlock_irqrestore(&chan->lock, flags);
8d318a50
LW		 1813 return NULL;
1814}
8d318a50
LW		 1815
1816bool stedma40_filter(struct dma_chan *chan, void *data)
1817{
1818 struct stedma40_chan_cfg *info = data;
1819 struct d40_chan *d40c =
1820 container_of(chan, struct d40_chan, chan);
1821 int err;
1822
1823 if (data) {
1824 err = d40_validate_conf(d40c, info);
1825 if (!err)
1826 d40c->dma_cfg = *info;
1827 } else
1828 err = d40_config_memcpy(d40c);
1829
ce2ca125
RV		 1830 if (!err)
1831 d40c->configured = true;
1832
8d318a50
LW		 1833 return err == 0;
1834}
1835EXPORT_SYMBOL(stedma40_filter);
1836
ac2c0a38
RV		 1837static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
1838{
1839 bool realtime = d40c->dma_cfg.realtime;
1840 bool highprio = d40c->dma_cfg.high_priority;
1841 u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
1842 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
1843 u32 event = D40_TYPE_TO_EVENT(dev_type);
1844 u32 group = D40_TYPE_TO_GROUP(dev_type);
1845 u32 bit = 1 << event;
1846
1847 /* Destination event lines are stored in the upper halfword */
1848 if (!src)
1849 bit <<= 16;
1850
1851 writel(bit, d40c->base->virtbase + prioreg + group * 4);
1852 writel(bit, d40c->base->virtbase + rtreg + group * 4);
1853}
1854
1855static void d40_set_prio_realtime(struct d40_chan *d40c)
1856{
1857 if (d40c->base->rev < 3)
1858 return;
1859
1860 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1861 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1862 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
1863
1864 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
1865 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1866 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
1867}
1868
8d318a50
LW		 1869/* DMA ENGINE functions */
1870static int d40_alloc_chan_resources(struct dma_chan *chan)
1871{
1872 int err;
1873 unsigned long flags;
1874 struct d40_chan *d40c =
1875 container_of(chan, struct d40_chan, chan);
ef1872ec 1876 bool is_free_phy;
8d318a50
LW		 1877 spin_lock_irqsave(&d40c->lock, flags);
1878
1879 d40c->completed = chan->cookie = 1;
1880
ce2ca125
RV		 1881 /* If no dma configuration is set use default configuration (memcpy) */
1882 if (!d40c->configured) {
8d318a50 1883 err = d40_config_memcpy(d40c);
ff0b12ba 1884 if (err) {
6db5a8ba 1885 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 1886 goto fail;
1887 }
8d318a50 1888 }
ef1872ec 1889 is_free_phy = (d40c->phy_chan == NULL);
8d318a50
LW		 1890
1891 err = d40_allocate_channel(d40c);
1892 if (err) {
6db5a8ba 1893 chan_err(d40c, "Failed to allocate channel\n");
ff0b12ba 1894 goto fail;
8d318a50
LW		 1895 }
1896
ef1872ec
LW		 1897 /* Fill in basic CFG register values */
1898 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
724a8577 1899 &d40c->dst_def_cfg, chan_is_logical(d40c));
ef1872ec 1900
ac2c0a38
RV		 1901 d40_set_prio_realtime(d40c);
1902
724a8577 1903 if (chan_is_logical(d40c)) {
ef1872ec
LW		 1904 d40_log_cfg(&d40c->dma_cfg,
1905 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1906
1907 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1908 d40c->lcpa = d40c->base->lcpa_base +
1909 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1910 else
1911 d40c->lcpa = d40c->base->lcpa_base +
1912 d40c->dma_cfg.dst_dev_type *
1913 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1914 }
1915
1916 /*
1917 * Only write channel configuration to the DMA if the physical
1918 * resource is free. In case of multiple logical channels
1919 * on the same physical resource, only the first write is necessary.
1920 */
b55912c6
JA		 1921 if (is_free_phy)
1922 d40_config_write(d40c);
ff0b12ba 1923fail:
8d318a50 1924 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 1925 return err;
8d318a50
LW		 1926}
1927
1928static void d40_free_chan_resources(struct dma_chan *chan)
1929{
1930 struct d40_chan *d40c =
1931 container_of(chan, struct d40_chan, chan);
1932 int err;
1933 unsigned long flags;
1934
0d0f6b8b 1935 if (d40c->phy_chan == NULL) {
6db5a8ba 1936 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 1937 return;
1938 }
1939
1940
8d318a50
LW		 1941 spin_lock_irqsave(&d40c->lock, flags);
1942
1943 err = d40_free_dma(d40c);
1944
1945 if (err)
6db5a8ba 1946 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 1947 spin_unlock_irqrestore(&d40c->lock, flags);
1948}
1949
1950static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1951 dma_addr_t dst,
1952 dma_addr_t src,
1953 size_t size,
2a614340 1954 unsigned long dma_flags)
8d318a50 1955{
95944c6e
RV		 1956 struct scatterlist dst_sg;
1957 struct scatterlist src_sg;
8d318a50 1958
95944c6e
RV		 1959 sg_init_table(&dst_sg, 1);
1960 sg_init_table(&src_sg, 1);
8d318a50 1961
95944c6e
RV		 1962 sg_dma_address(&dst_sg) = dst;
1963 sg_dma_address(&src_sg) = src;
8d318a50 1964
95944c6e
RV		 1965 sg_dma_len(&dst_sg) = size;
1966 sg_dma_len(&src_sg) = size;
8d318a50 1967
cade1d30 1968 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
8d318a50
LW		 1969}
1970
0d688662 1971static struct dma_async_tx_descriptor *
cade1d30
RV		 1972d40_prep_memcpy_sg(struct dma_chan *chan,
1973 struct scatterlist *dst_sg, unsigned int dst_nents,
1974 struct scatterlist *src_sg, unsigned int src_nents,
1975 unsigned long dma_flags)
0d688662
IS		 1976{
1977 if (dst_nents != src_nents)
1978 return NULL;
1979
cade1d30 1980 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
00ac0341
RV		 1981}
1982
8d318a50
LW		 1983static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
1984 struct scatterlist *sgl,
1985 unsigned int sg_len,
1986 enum dma_data_direction direction,
2a614340 1987 unsigned long dma_flags)
8d318a50 1988{
00ac0341
RV		 1989 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE)
1990 return NULL;
1991
cade1d30 1992 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
8d318a50
LW		 1993}
1994
1995static enum dma_status d40_tx_status(struct dma_chan *chan,
1996 dma_cookie_t cookie,
1997 struct dma_tx_state *txstate)
1998{
1999 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2000 dma_cookie_t last_used;
2001 dma_cookie_t last_complete;
2002 int ret;
2003
0d0f6b8b 2004 if (d40c->phy_chan == NULL) {
6db5a8ba 2005 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2006 return -EINVAL;
2007 }
2008
8d318a50
LW		 2009 last_complete = d40c->completed;
2010 last_used = chan->cookie;
2011
a5ebca47
JA		 2012 if (d40_is_paused(d40c))
2013 ret = DMA_PAUSED;
2014 else
2015 ret = dma_async_is_complete(cookie, last_complete, last_used);
8d318a50 2016
a5ebca47
JA		 2017 dma_set_tx_state(txstate, last_complete, last_used,
2018 stedma40_residue(chan));
8d318a50
LW		 2019
2020 return ret;
2021}
2022
2023static void d40_issue_pending(struct dma_chan *chan)
2024{
2025 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2026 unsigned long flags;
2027
0d0f6b8b 2028 if (d40c->phy_chan == NULL) {
6db5a8ba 2029 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2030 return;
2031 }
2032
8d318a50
LW		 2033 spin_lock_irqsave(&d40c->lock, flags);
2034
2035 /* Busy means that pending jobs are already being processed */
2036 if (!d40c->busy)
2037 (void) d40_queue_start(d40c);
2038
2039 spin_unlock_irqrestore(&d40c->lock, flags);
2040}
2041
95e1400f
LW		 2042/* Runtime reconfiguration extension */
2043static void d40_set_runtime_config(struct dma_chan *chan,
2044 struct dma_slave_config *config)
2045{
2046 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2047 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2048 enum dma_slave_buswidth config_addr_width;
2049 dma_addr_t config_addr;
2050 u32 config_maxburst;
2051 enum stedma40_periph_data_width addr_width;
2052 int psize;
2053
2054 if (config->direction == DMA_FROM_DEVICE) {
2055 dma_addr_t dev_addr_rx =
2056 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2057
2058 config_addr = config->src_addr;
2059 if (dev_addr_rx)
2060 dev_dbg(d40c->base->dev,
2061 "channel has a pre-wired RX address %08x "
2062 "overriding with %08x\n",
2063 dev_addr_rx, config_addr);
2064 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2065 dev_dbg(d40c->base->dev,
2066 "channel was not configured for peripheral "
2067 "to memory transfer (%d) overriding\n",
2068 cfg->dir);
2069 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2070
2071 config_addr_width = config->src_addr_width;
2072 config_maxburst = config->src_maxburst;
2073
2074 } else if (config->direction == DMA_TO_DEVICE) {
2075 dma_addr_t dev_addr_tx =
2076 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2077
2078 config_addr = config->dst_addr;
2079 if (dev_addr_tx)
2080 dev_dbg(d40c->base->dev,
2081 "channel has a pre-wired TX address %08x "
2082 "overriding with %08x\n",
2083 dev_addr_tx, config_addr);
2084 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2085 dev_dbg(d40c->base->dev,
2086 "channel was not configured for memory "
2087 "to peripheral transfer (%d) overriding\n",
2088 cfg->dir);
2089 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2090
2091 config_addr_width = config->dst_addr_width;
2092 config_maxburst = config->dst_maxburst;
2093
2094 } else {
2095 dev_err(d40c->base->dev,
2096 "unrecognized channel direction %d\n",
2097 config->direction);
2098 return;
2099 }
2100
2101 switch (config_addr_width) {
2102 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2103 addr_width = STEDMA40_BYTE_WIDTH;
2104 break;
2105 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2106 addr_width = STEDMA40_HALFWORD_WIDTH;
2107 break;
2108 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2109 addr_width = STEDMA40_WORD_WIDTH;
2110 break;
2111 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2112 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2113 break;
2114 default:
2115 dev_err(d40c->base->dev,
2116 "illegal peripheral address width "
2117 "requested (%d)\n",
2118 config->src_addr_width);
2119 return;
2120 }
2121
724a8577 2122 if (chan_is_logical(d40c)) {
a59670a4
PF		 2123 if (config_maxburst >= 16)
2124 psize = STEDMA40_PSIZE_LOG_16;
2125 else if (config_maxburst >= 8)
2126 psize = STEDMA40_PSIZE_LOG_8;
2127 else if (config_maxburst >= 4)
2128 psize = STEDMA40_PSIZE_LOG_4;
2129 else
2130 psize = STEDMA40_PSIZE_LOG_1;
2131 } else {
2132 if (config_maxburst >= 16)
2133 psize = STEDMA40_PSIZE_PHY_16;
2134 else if (config_maxburst >= 8)
2135 psize = STEDMA40_PSIZE_PHY_8;
2136 else if (config_maxburst >= 4)
2137 psize = STEDMA40_PSIZE_PHY_4;
d49278e3
PF		 2138 else if (config_maxburst >= 2)
2139 psize = STEDMA40_PSIZE_PHY_2;
a59670a4
PF		 2140 else
2141 psize = STEDMA40_PSIZE_PHY_1;
2142 }
95e1400f
LW		 2143
2144 /* Set up all the endpoint configs */
2145 cfg->src_info.data_width = addr_width;
2146 cfg->src_info.psize = psize;
51f5d744 2147 cfg->src_info.big_endian = false;
95e1400f
LW		 2148 cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2149 cfg->dst_info.data_width = addr_width;
2150 cfg->dst_info.psize = psize;
51f5d744 2151 cfg->dst_info.big_endian = false;
95e1400f
LW		 2152 cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2153
a59670a4 2154 /* Fill in register values */
724a8577 2155 if (chan_is_logical(d40c))
a59670a4
PF		 2156 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2157 else
2158 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2159 &d40c->dst_def_cfg, false);
2160
95e1400f
LW		 2161 /* These settings will take precedence later */
2162 d40c->runtime_addr = config_addr;
2163 d40c->runtime_direction = config->direction;
2164 dev_dbg(d40c->base->dev,
2165 "configured channel %s for %s, data width %d, "
2166 "maxburst %d bytes, LE, no flow control\n",
2167 dma_chan_name(chan),
2168 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2169 config_addr_width,
2170 config_maxburst);
2171}
2172
05827630
LW		 2173static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2174 unsigned long arg)
8d318a50
LW		 2175{
2176 unsigned long flags;
2177 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2178
0d0f6b8b 2179 if (d40c->phy_chan == NULL) {
6db5a8ba 2180 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2181 return -EINVAL;
2182 }
2183
8d318a50
LW		 2184 switch (cmd) {
2185 case DMA_TERMINATE_ALL:
2186 spin_lock_irqsave(&d40c->lock, flags);
2187 d40_term_all(d40c);
2188 spin_unlock_irqrestore(&d40c->lock, flags);
2189 return 0;
2190 case DMA_PAUSE:
2191 return d40_pause(chan);
2192 case DMA_RESUME:
2193 return d40_resume(chan);
95e1400f
LW		 2194 case DMA_SLAVE_CONFIG:
2195 d40_set_runtime_config(chan,
2196 (struct dma_slave_config *) arg);
2197 return 0;
2198 default:
2199 break;
8d318a50
LW		 2200 }
2201
2202 /* Other commands are unimplemented */
2203 return -ENXIO;
2204}
2205
2206/* Initialization functions */
2207
2208static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2209 struct d40_chan *chans, int offset,
2210 int num_chans)
2211{
2212 int i = 0;
2213 struct d40_chan *d40c;
2214
2215 INIT_LIST_HEAD(&dma->channels);
2216
2217 for (i = offset; i < offset + num_chans; i++) {
2218 d40c = &chans[i];
2219 d40c->base = base;
2220 d40c->chan.device = dma;
2221
8d318a50
LW		 2222 spin_lock_init(&d40c->lock);
2223
2224 d40c->log_num = D40_PHY_CHAN;
2225
8d318a50
LW		 2226 INIT_LIST_HEAD(&d40c->active);
2227 INIT_LIST_HEAD(&d40c->queue);
2228 INIT_LIST_HEAD(&d40c->client);
2229
8d318a50
LW		 2230 tasklet_init(&d40c->tasklet, dma_tasklet,
2231 (unsigned long) d40c);
2232
2233 list_add_tail(&d40c->chan.device_node,
2234 &dma->channels);
2235 }
2236}
2237
2238static int __init d40_dmaengine_init(struct d40_base *base,
2239 int num_reserved_chans)
2240{
2241 int err ;
2242
2243 d40_chan_init(base, &base->dma_slave, base->log_chans,
2244 0, base->num_log_chans);
2245
2246 dma_cap_zero(base->dma_slave.cap_mask);
2247 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2248
2249 base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2250 base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2251 base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
cade1d30 2252 base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
8d318a50
LW		 2253 base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2254 base->dma_slave.device_tx_status = d40_tx_status;
2255 base->dma_slave.device_issue_pending = d40_issue_pending;
2256 base->dma_slave.device_control = d40_control;
2257 base->dma_slave.dev = base->dev;
2258
2259 err = dma_async_device_register(&base->dma_slave);
2260
2261 if (err) {
6db5a8ba 2262 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2263 goto failure1;
2264 }
2265
2266 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2267 base->num_log_chans, base->plat_data->memcpy_len);
2268
2269 dma_cap_zero(base->dma_memcpy.cap_mask);
2270 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
0d688662 2271 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
8d318a50
LW		 2272
2273 base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2274 base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2275 base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
cade1d30 2276 base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
8d318a50
LW		 2277 base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2278 base->dma_memcpy.device_tx_status = d40_tx_status;
2279 base->dma_memcpy.device_issue_pending = d40_issue_pending;
2280 base->dma_memcpy.device_control = d40_control;
2281 base->dma_memcpy.dev = base->dev;
2282 /*
2283 * This controller can only access address at even
2284 * 32bit boundaries, i.e. 2^2
2285 */
2286 base->dma_memcpy.copy_align = 2;
2287
2288 err = dma_async_device_register(&base->dma_memcpy);
2289
2290 if (err) {
6db5a8ba
RV		 2291 d40_err(base->dev,
2292 "Failed to regsiter memcpy only channels\n");
8d318a50
LW		 2293 goto failure2;
2294 }
2295
2296 d40_chan_init(base, &base->dma_both, base->phy_chans,
2297 0, num_reserved_chans);
2298
2299 dma_cap_zero(base->dma_both.cap_mask);
2300 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2301 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
0d688662 2302 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
8d318a50
LW		 2303
2304 base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2305 base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2306 base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
cade1d30 2307 base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
8d318a50
LW		 2308 base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2309 base->dma_both.device_tx_status = d40_tx_status;
2310 base->dma_both.device_issue_pending = d40_issue_pending;
2311 base->dma_both.device_control = d40_control;
2312 base->dma_both.dev = base->dev;
2313 base->dma_both.copy_align = 2;
2314 err = dma_async_device_register(&base->dma_both);
2315
2316 if (err) {
6db5a8ba
RV		 2317 d40_err(base->dev,
2318 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2319 goto failure3;
2320 }
2321 return 0;
2322failure3:
2323 dma_async_device_unregister(&base->dma_memcpy);
2324failure2:
2325 dma_async_device_unregister(&base->dma_slave);
2326failure1:
2327 return err;
2328}
2329
2330/* Initialization functions. */
2331
2332static int __init d40_phy_res_init(struct d40_base *base)
2333{
2334 int i;
2335 int num_phy_chans_avail = 0;
2336 u32 val[2];
2337 int odd_even_bit = -2;
2338
2339 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2340 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2341
2342 for (i = 0; i < base->num_phy_chans; i++) {
2343 base->phy_res[i].num = i;
2344 odd_even_bit += 2 * ((i % 2) == 0);
2345 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2346 /* Mark security only channels as occupied */
2347 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2348 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2349 } else {
2350 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2351 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2352 num_phy_chans_avail++;
2353 }
2354 spin_lock_init(&base->phy_res[i].lock);
2355 }
6b7acd84
JA		 2356
2357 /* Mark disabled channels as occupied */
2358 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 2359 int chan = base->plat_data->disabled_channels[i];
2360
2361 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2362 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2363 num_phy_chans_avail--;
6b7acd84
JA		 2364 }
2365
8d318a50
LW		 2366 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2367 num_phy_chans_avail, base->num_phy_chans);
2368
2369 /* Verify settings extended vs standard */
2370 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2371
2372 for (i = 0; i < base->num_phy_chans; i++) {
2373
2374 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2375 (val[0] & 0x3) != 1)
2376 dev_info(base->dev,
2377 "[%s] INFO: channel %d is misconfigured (%d)\n",
2378 __func__, i, val[0] & 0x3);
2379
2380 val[0] = val[0] >> 2;
2381 }
2382
2383 return num_phy_chans_avail;
2384}
2385
2386static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2387{
2388 static const struct d40_reg_val dma_id_regs[] = {
2389 /* Peripheral Id */
2390 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2391 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2392 /*
2393 * D40_DREG_PERIPHID2 Depends on HW revision:
4d594900 2394 * DB8500ed has 0x0008,
8d318a50 2395 * ? has 0x0018,
4d594900
RV		 2396 * DB8500v1 has 0x0028
2397 * DB8500v2 has 0x0038
8d318a50
LW		 2398 */
2399 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2400
2401 /* PCell Id */
2402 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2403 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2404 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2405 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2406 };
2407 struct stedma40_platform_data *plat_data;
2408 struct clk *clk = NULL;
2409 void __iomem *virtbase = NULL;
2410 struct resource *res = NULL;
2411 struct d40_base *base = NULL;
2412 int num_log_chans = 0;
2413 int num_phy_chans;
2414 int i;
f4185592 2415 u32 val;
3ae0267f 2416 u32 rev;
8d318a50
LW		 2417
2418 clk = clk_get(&pdev->dev, NULL);
2419
2420 if (IS_ERR(clk)) {
6db5a8ba 2421 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 2422 goto failure;
2423 }
2424
2425 clk_enable(clk);
2426
2427 /* Get IO for DMAC base address */
2428 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2429 if (!res)
2430 goto failure;
2431
2432 if (request_mem_region(res->start, resource_size(res),
2433 D40_NAME " I/O base") == NULL)
2434 goto failure;
2435
2436 virtbase = ioremap(res->start, resource_size(res));
2437 if (!virtbase)
2438 goto failure;
2439
2440 /* HW version check */
2441 for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2442 if (dma_id_regs[i].val !=
2443 readl(virtbase + dma_id_regs[i].reg)) {
6db5a8ba
RV		 2444 d40_err(&pdev->dev,
2445 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
8d318a50
LW		 2446 dma_id_regs[i].val,
2447 dma_id_regs[i].reg,
2448 readl(virtbase + dma_id_regs[i].reg));
2449 goto failure;
2450 }
2451 }
2452
3ae0267f 2453 /* Get silicon revision and designer */
f4185592 2454 val = readl(virtbase + D40_DREG_PERIPHID2);
8d318a50 2455
3ae0267f
JA		 2456 if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2457 D40_HW_DESIGNER) {
6db5a8ba
RV		 2458 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
2459 val & D40_DREG_PERIPHID2_DESIGNER_MASK,
3ae0267f 2460 D40_HW_DESIGNER);
8d318a50
LW		 2461 goto failure;
2462 }
2463
3ae0267f
JA		 2464 rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2465 D40_DREG_PERIPHID2_REV_POS;
2466
8d318a50
LW		 2467 /* The number of physical channels on this HW */
2468 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2469
2470 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
3ae0267f 2471 rev, res->start);
8d318a50
LW		 2472
2473 plat_data = pdev->dev.platform_data;
2474
2475 /* Count the number of logical channels in use */
2476 for (i = 0; i < plat_data->dev_len; i++)
2477 if (plat_data->dev_rx[i] != 0)
2478 num_log_chans++;
2479
2480 for (i = 0; i < plat_data->dev_len; i++)
2481 if (plat_data->dev_tx[i] != 0)
2482 num_log_chans++;
2483
2484 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2485 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2486 sizeof(struct d40_chan), GFP_KERNEL);
2487
2488 if (base == NULL) {
6db5a8ba 2489 d40_err(&pdev->dev, "Out of memory\n");
8d318a50
LW		 2490 goto failure;
2491 }
2492
3ae0267f 2493 base->rev = rev;
8d318a50
LW		 2494 base->clk = clk;
2495 base->num_phy_chans = num_phy_chans;
2496 base->num_log_chans = num_log_chans;
2497 base->phy_start = res->start;
2498 base->phy_size = resource_size(res);
2499 base->virtbase = virtbase;
2500 base->plat_data = plat_data;
2501 base->dev = &pdev->dev;
2502 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2503 base->log_chans = &base->phy_chans[num_phy_chans];
2504
2505 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2506 GFP_KERNEL);
2507 if (!base->phy_res)
2508 goto failure;
2509
2510 base->lookup_phy_chans = kzalloc(num_phy_chans *
2511 sizeof(struct d40_chan *),
2512 GFP_KERNEL);
2513 if (!base->lookup_phy_chans)
2514 goto failure;
2515
2516 if (num_log_chans + plat_data->memcpy_len) {
2517 /*
2518 * The max number of logical channels are event lines for all
2519 * src devices and dst devices
2520 */
2521 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2522 sizeof(struct d40_chan *),
2523 GFP_KERNEL);
2524 if (!base->lookup_log_chans)
2525 goto failure;
2526 }
698e4732
JA		 2527
2528 base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
2529 sizeof(struct d40_desc *) *
2530 D40_LCLA_LINK_PER_EVENT_GRP,
8d318a50
LW		 2531 GFP_KERNEL);
2532 if (!base->lcla_pool.alloc_map)
2533 goto failure;
2534
c675b1b4
JA		 2535 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2536 0, SLAB_HWCACHE_ALIGN,
2537 NULL);
2538 if (base->desc_slab == NULL)
2539 goto failure;
2540
8d318a50
LW		 2541 return base;
2542
2543failure:
c6134c96 2544 if (!IS_ERR(clk)) {
8d318a50
LW		 2545 clk_disable(clk);
2546 clk_put(clk);
2547 }
2548 if (virtbase)
2549 iounmap(virtbase);
2550 if (res)
2551 release_mem_region(res->start,
2552 resource_size(res));
2553 if (virtbase)
2554 iounmap(virtbase);
2555
2556 if (base) {
2557 kfree(base->lcla_pool.alloc_map);
2558 kfree(base->lookup_log_chans);
2559 kfree(base->lookup_phy_chans);
2560 kfree(base->phy_res);
2561 kfree(base);
2562 }
2563
2564 return NULL;
2565}
2566
2567static void __init d40_hw_init(struct d40_base *base)
2568{
2569
2570 static const struct d40_reg_val dma_init_reg[] = {
2571 /* Clock every part of the DMA block from start */
2572 { .reg = D40_DREG_GCC, .val = 0x0000ff01},
2573
2574 /* Interrupts on all logical channels */
2575 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2576 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2577 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2578 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2579 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2580 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2581 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2582 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2583 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2584 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2585 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2586 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2587 };
2588 int i;
2589 u32 prmseo[2] = {0, 0};
2590 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2591 u32 pcmis = 0;
2592 u32 pcicr = 0;
2593
2594 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2595 writel(dma_init_reg[i].val,
2596 base->virtbase + dma_init_reg[i].reg);
2597
2598 /* Configure all our dma channels to default settings */
2599 for (i = 0; i < base->num_phy_chans; i++) {
2600
2601 activeo[i % 2] = activeo[i % 2] << 2;
2602
2603 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2604 == D40_ALLOC_PHY) {
2605 activeo[i % 2] |= 3;
2606 continue;
2607 }
2608
2609 /* Enable interrupt # */
2610 pcmis = (pcmis << 1) | 1;
2611
2612 /* Clear interrupt # */
2613 pcicr = (pcicr << 1) | 1;
2614
2615 /* Set channel to physical mode */
2616 prmseo[i % 2] = prmseo[i % 2] << 2;
2617 prmseo[i % 2] |= 1;
2618
2619 }
2620
2621 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2622 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2623 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2624 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2625
2626 /* Write which interrupt to enable */
2627 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2628
2629 /* Write which interrupt to clear */
2630 writel(pcicr, base->virtbase + D40_DREG_PCICR);
2631
2632}
2633
508849ad
LW		 2634static int __init d40_lcla_allocate(struct d40_base *base)
2635{
026cbc42 2636 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 2637 unsigned long *page_list;
2638 int i, j;
2639 int ret = 0;
2640
2641 /*
2642 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2643 * To full fill this hardware requirement without wasting 256 kb
2644 * we allocate pages until we get an aligned one.
2645 */
2646 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2647 GFP_KERNEL);
2648
2649 if (!page_list) {
2650 ret = -ENOMEM;
2651 goto failure;
2652 }
2653
2654 /* Calculating how many pages that are required */
2655 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2656
2657 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2658 page_list[i] = __get_free_pages(GFP_KERNEL,
2659 base->lcla_pool.pages);
2660 if (!page_list[i]) {
2661
6db5a8ba
RV		 2662 d40_err(base->dev, "Failed to allocate %d pages.\n",
2663 base->lcla_pool.pages);
508849ad
LW		 2664
2665 for (j = 0; j < i; j++)
2666 free_pages(page_list[j], base->lcla_pool.pages);
2667 goto failure;
2668 }
2669
2670 if ((virt_to_phys((void *)page_list[i]) &
2671 (LCLA_ALIGNMENT - 1)) == 0)
2672 break;
2673 }
2674
2675 for (j = 0; j < i; j++)
2676 free_pages(page_list[j], base->lcla_pool.pages);
2677
2678 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2679 base->lcla_pool.base = (void *)page_list[i];
2680 } else {
767a9675
JA		 2681 /*
2682 * After many attempts and no succees with finding the correct
2683 * alignment, try with allocating a big buffer.
2684 */
508849ad
LW		 2685 dev_warn(base->dev,
2686 "[%s] Failed to get %d pages @ 18 bit align.\n",
2687 __func__, base->lcla_pool.pages);
2688 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2689 base->num_phy_chans +
2690 LCLA_ALIGNMENT,
2691 GFP_KERNEL);
2692 if (!base->lcla_pool.base_unaligned) {
2693 ret = -ENOMEM;
2694 goto failure;
2695 }
2696
2697 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2698 LCLA_ALIGNMENT);
2699 }
2700
026cbc42
RV		 2701 pool->dma_addr = dma_map_single(base->dev, pool->base,
2702 SZ_1K * base->num_phy_chans,
2703 DMA_TO_DEVICE);
2704 if (dma_mapping_error(base->dev, pool->dma_addr)) {
2705 pool->dma_addr = 0;
2706 ret = -ENOMEM;
2707 goto failure;
2708 }
2709
508849ad
LW		 2710 writel(virt_to_phys(base->lcla_pool.base),
2711 base->virtbase + D40_DREG_LCLA);
2712failure:
2713 kfree(page_list);
2714 return ret;
2715}
2716
8d318a50
LW		 2717static int __init d40_probe(struct platform_device *pdev)
2718{
2719 int err;
2720 int ret = -ENOENT;
2721 struct d40_base *base;
2722 struct resource *res = NULL;
2723 int num_reserved_chans;
2724 u32 val;
2725
2726 base = d40_hw_detect_init(pdev);
2727
2728 if (!base)
2729 goto failure;
2730
2731 num_reserved_chans = d40_phy_res_init(base);
2732
2733 platform_set_drvdata(pdev, base);
2734
2735 spin_lock_init(&base->interrupt_lock);
2736 spin_lock_init(&base->execmd_lock);
2737
2738 /* Get IO for logical channel parameter address */
2739 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2740 if (!res) {
2741 ret = -ENOENT;
6db5a8ba 2742 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 2743 goto failure;
2744 }
2745 base->lcpa_size = resource_size(res);
2746 base->phy_lcpa = res->start;
2747
2748 if (request_mem_region(res->start, resource_size(res),
2749 D40_NAME " I/O lcpa") == NULL) {
2750 ret = -EBUSY;
6db5a8ba
RV		 2751 d40_err(&pdev->dev,
2752 "Failed to request LCPA region 0x%x-0x%x\n",
2753 res->start, res->end);
8d318a50
LW		 2754 goto failure;
2755 }
2756
2757 /* We make use of ESRAM memory for this. */
2758 val = readl(base->virtbase + D40_DREG_LCPA);
2759 if (res->start != val && val != 0) {
2760 dev_warn(&pdev->dev,
2761 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2762 __func__, val, res->start);
2763 } else
2764 writel(res->start, base->virtbase + D40_DREG_LCPA);
2765
2766 base->lcpa_base = ioremap(res->start, resource_size(res));
2767 if (!base->lcpa_base) {
2768 ret = -ENOMEM;
6db5a8ba 2769 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 2770 goto failure;
2771 }
8d318a50 2772
508849ad
LW		 2773 ret = d40_lcla_allocate(base);
2774 if (ret) {
6db5a8ba 2775 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
8d318a50
LW		 2776 goto failure;
2777 }
2778
2779 spin_lock_init(&base->lcla_pool.lock);
2780
8d318a50
LW		 2781 base->irq = platform_get_irq(pdev, 0);
2782
2783 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 2784 if (ret) {
6db5a8ba 2785 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 2786 goto failure;
2787 }
2788
2789 err = d40_dmaengine_init(base, num_reserved_chans);
2790 if (err)
2791 goto failure;
2792
2793 d40_hw_init(base);
2794
2795 dev_info(base->dev, "initialized\n");
2796 return 0;
2797
2798failure:
2799 if (base) {
c675b1b4
JA		 2800 if (base->desc_slab)
2801 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 2802 if (base->virtbase)
2803 iounmap(base->virtbase);
026cbc42
RV		 2804
2805 if (base->lcla_pool.dma_addr)
2806 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
2807 SZ_1K * base->num_phy_chans,
2808 DMA_TO_DEVICE);
2809
508849ad
LW		 2810 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2811 free_pages((unsigned long)base->lcla_pool.base,
2812 base->lcla_pool.pages);
767a9675
JA		 2813
2814 kfree(base->lcla_pool.base_unaligned);
2815
8d318a50
LW		 2816 if (base->phy_lcpa)
2817 release_mem_region(base->phy_lcpa,
2818 base->lcpa_size);
2819 if (base->phy_start)
2820 release_mem_region(base->phy_start,
2821 base->phy_size);
2822 if (base->clk) {
2823 clk_disable(base->clk);
2824 clk_put(base->clk);
2825 }
2826
2827 kfree(base->lcla_pool.alloc_map);
2828 kfree(base->lookup_log_chans);
2829 kfree(base->lookup_phy_chans);
2830 kfree(base->phy_res);
2831 kfree(base);
2832 }
2833
6db5a8ba 2834 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 2835 return ret;
2836}
2837
2838static struct platform_driver d40_driver = {
2839 .driver = {
2840 .owner = THIS_MODULE,
2841 .name = D40_NAME,
2842 },
2843};
2844
cb9ab2d8 2845static int __init stedma40_init(void)
8d318a50
LW		 2846{
2847 return platform_driver_probe(&d40_driver, d40_probe);
2848}
2849arch_initcall(stedma40_init);
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