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dma40: extract lcla code into separate function
[mirror_ubuntu-hirsute-kernel.git] / drivers / dma / ste_dma40.c
CommitLineData
8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
9#include <linux/kernel.h>
10#include <linux/slab.h>
11#include <linux/dmaengine.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
698e4732 15#include <linux/err.h>
8d318a50
LW		 16
17#include <plat/ste_dma40.h>
18
19#include "ste_dma40_ll.h"
20
21#define D40_NAME "dma40"
22
23#define D40_PHY_CHAN -1
24
25/* For masking out/in 2 bit channel positions */
26#define D40_CHAN_POS(chan) (2 * (chan / 2))
27#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
28
29/* Maximum iterations taken before giving up suspending a channel */
30#define D40_SUSPEND_MAX_IT 500
31
508849ad
LW		 32/* Hardware requirement on LCLA alignment */
33#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 34
35/* Max number of links per event group */
36#define D40_LCLA_LINK_PER_EVENT_GRP 128
37#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
38
508849ad
LW		 39/* Attempts before giving up to trying to get pages that are aligned */
40#define MAX_LCLA_ALLOC_ATTEMPTS 256
41
42/* Bit markings for allocation map */
8d318a50
LW		 43#define D40_ALLOC_FREE (1 << 31)
44#define D40_ALLOC_PHY (1 << 30)
45#define D40_ALLOC_LOG_FREE 0
46
8d318a50 47/* Hardware designer of the block */
3ae0267f 48#define D40_HW_DESIGNER 0x8
8d318a50
LW		 49
50/**
51 * enum 40_command - The different commands and/or statuses.
52 *
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 */
58enum d40_command {
59 D40_DMA_STOP = 0,
60 D40_DMA_RUN = 1,
61 D40_DMA_SUSPEND_REQ = 2,
62 D40_DMA_SUSPENDED = 3
63};
64
65/**
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
67 *
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
b00f938c 71 * @dma_addr: DMA address, if mapped
8d318a50
LW		 72 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
73 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
74 * one buffer to one buffer.
75 */
76struct d40_lli_pool {
77 void *base;
508849ad 78 int size;
b00f938c 79 dma_addr_t dma_addr;
8d318a50 80 /* Space for dst and src, plus an extra for padding */
508849ad 81 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 82};
83
84/**
85 * struct d40_desc - A descriptor is one DMA job.
86 *
87 * @lli_phy: LLI settings for physical channel. Both src and dst=
88 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
89 * lli_len equals one.
90 * @lli_log: Same as above but for logical channels.
91 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 92 * @lli_len: Number of llis of current descriptor.
698e4732
JA		 93 * @lli_current: Number of transfered llis.
94 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 95 * @txd: DMA engine struct. Used for among other things for communication
96 * during a transfer.
97 * @node: List entry.
8d318a50 98 * @is_in_client_list: true if the client owns this descriptor.
aa182ae2 99 * the previous one.
8d318a50
LW		 100 *
101 * This descriptor is used for both logical and physical transfers.
102 */
8d318a50
LW		 103struct d40_desc {
104 /* LLI physical */
105 struct d40_phy_lli_bidir lli_phy;
106 /* LLI logical */
107 struct d40_log_lli_bidir lli_log;
108
109 struct d40_lli_pool lli_pool;
941b77a3 110 int lli_len;
698e4732
JA		 111 int lli_current;
112 int lcla_alloc;
8d318a50
LW		 113
114 struct dma_async_tx_descriptor txd;
115 struct list_head node;
116
8d318a50
LW		 117 bool is_in_client_list;
118};
119
120/**
121 * struct d40_lcla_pool - LCLA pool settings and data.
122 *
508849ad
LW		 123 * @base: The virtual address of LCLA. 18 bit aligned.
124 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
125 * This pointer is only there for clean-up on error.
126 * @pages: The number of pages needed for all physical channels.
127 * Only used later for clean-up on error
8d318a50 128 * @lock: Lock to protect the content in this struct.
698e4732 129 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 130 */
131struct d40_lcla_pool {
132 void *base;
026cbc42 133 dma_addr_t dma_addr;
508849ad
LW		 134 void *base_unaligned;
135 int pages;
8d318a50 136 spinlock_t lock;
698e4732 137 struct d40_desc **alloc_map;
8d318a50
LW		 138};
139
140/**
141 * struct d40_phy_res - struct for handling eventlines mapped to physical
142 * channels.
143 *
144 * @lock: A lock protection this entity.
145 * @num: The physical channel number of this entity.
146 * @allocated_src: Bit mapped to show which src event line's are mapped to
147 * this physical channel. Can also be free or physically allocated.
148 * @allocated_dst: Same as for src but is dst.
149 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 150 * event line number.
8d318a50
LW		 151 */
152struct d40_phy_res {
153 spinlock_t lock;
154 int num;
155 u32 allocated_src;
156 u32 allocated_dst;
157};
158
159struct d40_base;
160
161/**
162 * struct d40_chan - Struct that describes a channel.
163 *
164 * @lock: A spinlock to protect this struct.
165 * @log_num: The logical number, if any of this channel.
166 * @completed: Starts with 1, after first interrupt it is set to dma engine's
167 * current cookie.
168 * @pending_tx: The number of pending transfers. Used between interrupt handler
169 * and tasklet.
170 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 171 * @phy_chan: Pointer to physical channel which this instance runs on. If this
172 * point is NULL, then the channel is not allocated.
8d318a50
LW		 173 * @chan: DMA engine handle.
174 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
175 * transfer and call client callback.
176 * @client: Cliented owned descriptor list.
177 * @active: Active descriptor.
178 * @queue: Queued jobs.
8d318a50 179 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 180 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
187 *
188 * This struct can either "be" a logical or a physical channel.
189 */
190struct d40_chan {
191 spinlock_t lock;
192 int log_num;
193 /* ID of the most recent completed transfer */
194 int completed;
195 int pending_tx;
196 bool busy;
197 struct d40_phy_res *phy_chan;
198 struct dma_chan chan;
199 struct tasklet_struct tasklet;
200 struct list_head client;
201 struct list_head active;
202 struct list_head queue;
8d318a50 203 struct stedma40_chan_cfg dma_cfg;
ce2ca125 204 bool configured;
8d318a50
LW		 205 struct d40_base *base;
206 /* Default register configurations */
207 u32 src_def_cfg;
208 u32 dst_def_cfg;
209 struct d40_def_lcsp log_def;
8d318a50 210 struct d40_log_lli_full *lcpa;
95e1400f
LW		 211 /* Runtime reconfiguration */
212 dma_addr_t runtime_addr;
213 enum dma_data_direction runtime_direction;
8d318a50
LW		 214};
215
216/**
217 * struct d40_base - The big global struct, one for each probe'd instance.
218 *
219 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220 * @execmd_lock: Lock for execute command usage since several channels share
221 * the same physical register.
222 * @dev: The device structure.
223 * @virtbase: The virtual base address of the DMA's register.
f4185592 224 * @rev: silicon revision detected.
8d318a50
LW		 225 * @clk: Pointer to the DMA clock structure.
226 * @phy_start: Physical memory start of the DMA registers.
227 * @phy_size: Size of the DMA register map.
228 * @irq: The IRQ number.
229 * @num_phy_chans: The number of physical channels. Read from HW. This
230 * is the number of available channels for this driver, not counting "Secure
231 * mode" allocated physical channels.
232 * @num_log_chans: The number of logical channels. Calculated from
233 * num_phy_chans.
234 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235 * @dma_slave: dma_device channels that can do only do slave transfers.
236 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
8d318a50
LW		 237 * @log_chans: Room for all possible logical channels in system.
238 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
239 * to log_chans entries.
240 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
241 * to phy_chans entries.
242 * @plat_data: Pointer to provided platform_data which is the driver
243 * configuration.
244 * @phy_res: Vector containing all physical channels.
245 * @lcla_pool: lcla pool settings and data.
246 * @lcpa_base: The virtual mapped address of LCPA.
247 * @phy_lcpa: The physical address of the LCPA.
248 * @lcpa_size: The size of the LCPA area.
c675b1b4 249 * @desc_slab: cache for descriptors.
8d318a50
LW		 250 */
251struct d40_base {
252 spinlock_t interrupt_lock;
253 spinlock_t execmd_lock;
254 struct device *dev;
255 void __iomem *virtbase;
f4185592 256 u8 rev:4;
8d318a50
LW		 257 struct clk *clk;
258 phys_addr_t phy_start;
259 resource_size_t phy_size;
260 int irq;
261 int num_phy_chans;
262 int num_log_chans;
263 struct dma_device dma_both;
264 struct dma_device dma_slave;
265 struct dma_device dma_memcpy;
266 struct d40_chan *phy_chans;
267 struct d40_chan *log_chans;
268 struct d40_chan **lookup_log_chans;
269 struct d40_chan **lookup_phy_chans;
270 struct stedma40_platform_data *plat_data;
271 /* Physical half channels */
272 struct d40_phy_res *phy_res;
273 struct d40_lcla_pool lcla_pool;
274 void *lcpa_base;
275 dma_addr_t phy_lcpa;
276 resource_size_t lcpa_size;
c675b1b4 277 struct kmem_cache *desc_slab;
8d318a50
LW		 278};
279
280/**
281 * struct d40_interrupt_lookup - lookup table for interrupt handler
282 *
283 * @src: Interrupt mask register.
284 * @clr: Interrupt clear register.
285 * @is_error: true if this is an error interrupt.
286 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
287 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
288 */
289struct d40_interrupt_lookup {
290 u32 src;
291 u32 clr;
292 bool is_error;
293 int offset;
294};
295
296/**
297 * struct d40_reg_val - simple lookup struct
298 *
299 * @reg: The register.
300 * @val: The value that belongs to the register in reg.
301 */
302struct d40_reg_val {
303 unsigned int reg;
304 unsigned int val;
305};
306
262d2915
RV		 307static struct device *chan2dev(struct d40_chan *d40c)
308{
309 return &d40c->chan.dev->device;
310}
311
724a8577
RV		 312static bool chan_is_physical(struct d40_chan *chan)
313{
314 return chan->log_num == D40_PHY_CHAN;
315}
316
317static bool chan_is_logical(struct d40_chan *chan)
318{
319 return !chan_is_physical(chan);
320}
321
8ca84687
RV		 322static void __iomem *chan_base(struct d40_chan *chan)
323{
324 return chan->base->virtbase + D40_DREG_PCBASE +
325 chan->phy_chan->num * D40_DREG_PCDELTA;
326}
327
6db5a8ba
RV		 328#define d40_err(dev, format, arg...) \
329 dev_err(dev, "[%s] " format, __func__, ## arg)
330
331#define chan_err(d40c, format, arg...) \
332 d40_err(chan2dev(d40c), format, ## arg)
333
b00f938c 334static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
dbd88788 335 int lli_len)
8d318a50 336{
dbd88788 337 bool is_log = chan_is_logical(d40c);
8d318a50
LW		 338 u32 align;
339 void *base;
340
341 if (is_log)
342 align = sizeof(struct d40_log_lli);
343 else
344 align = sizeof(struct d40_phy_lli);
345
346 if (lli_len == 1) {
347 base = d40d->lli_pool.pre_alloc_lli;
348 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
349 d40d->lli_pool.base = NULL;
350 } else {
594ece4d 351 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 352
353 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
354 d40d->lli_pool.base = base;
355
356 if (d40d->lli_pool.base == NULL)
357 return -ENOMEM;
358 }
359
360 if (is_log) {
d924abad 361 d40d->lli_log.src = PTR_ALIGN(base, align);
594ece4d 362 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 363
364 d40d->lli_pool.dma_addr = 0;
8d318a50 365 } else {
d924abad 366 d40d->lli_phy.src = PTR_ALIGN(base, align);
594ece4d 367 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 368
369 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
370 d40d->lli_phy.src,
371 d40d->lli_pool.size,
372 DMA_TO_DEVICE);
373
374 if (dma_mapping_error(d40c->base->dev,
375 d40d->lli_pool.dma_addr)) {
376 kfree(d40d->lli_pool.base);
377 d40d->lli_pool.base = NULL;
378 d40d->lli_pool.dma_addr = 0;
379 return -ENOMEM;
380 }
8d318a50
LW		 381 }
382
383 return 0;
384}
385
b00f938c 386static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 387{
b00f938c
RV		 388 if (d40d->lli_pool.dma_addr)
389 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
390 d40d->lli_pool.size, DMA_TO_DEVICE);
391
8d318a50
LW		 392 kfree(d40d->lli_pool.base);
393 d40d->lli_pool.base = NULL;
394 d40d->lli_pool.size = 0;
395 d40d->lli_log.src = NULL;
396 d40d->lli_log.dst = NULL;
397 d40d->lli_phy.src = NULL;
398 d40d->lli_phy.dst = NULL;
8d318a50
LW		 399}
400
698e4732
JA		 401static int d40_lcla_alloc_one(struct d40_chan *d40c,
402 struct d40_desc *d40d)
403{
404 unsigned long flags;
405 int i;
406 int ret = -EINVAL;
407 int p;
408
409 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
410
411 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
412
413 /*
414 * Allocate both src and dst at the same time, therefore the half
415 * start on 1 since 0 can't be used since zero is used as end marker.
416 */
417 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
418 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
419 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
420 d40d->lcla_alloc++;
421 ret = i;
422 break;
423 }
424 }
425
426 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
427
428 return ret;
429}
430
431static int d40_lcla_free_all(struct d40_chan *d40c,
432 struct d40_desc *d40d)
433{
434 unsigned long flags;
435 int i;
436 int ret = -EINVAL;
437
724a8577 438 if (chan_is_physical(d40c))
698e4732
JA		 439 return 0;
440
441 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
442
443 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
444 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
445 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
446 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
447 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
448 d40d->lcla_alloc--;
449 if (d40d->lcla_alloc == 0) {
450 ret = 0;
451 break;
452 }
453 }
454 }
455
456 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
457
458 return ret;
459
460}
461
8d318a50
LW		 462static void d40_desc_remove(struct d40_desc *d40d)
463{
464 list_del(&d40d->node);
465}
466
467static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
468{
a2c15fa4 469 struct d40_desc *desc = NULL;
8d318a50
LW		 470
471 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 472 struct d40_desc *d;
473 struct d40_desc *_d;
474
8d318a50
LW		 475 list_for_each_entry_safe(d, _d, &d40c->client, node)
476 if (async_tx_test_ack(&d->txd)) {
b00f938c 477 d40_pool_lli_free(d40c, d);
8d318a50 478 d40_desc_remove(d);
a2c15fa4
RV		 479 desc = d;
480 memset(desc, 0, sizeof(*desc));
c675b1b4 481 break;
8d318a50 482 }
8d318a50 483 }
a2c15fa4
RV		 484
485 if (!desc)
486 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
487
488 if (desc)
489 INIT_LIST_HEAD(&desc->node);
490
491 return desc;
8d318a50
LW		 492}
493
494static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
495{
698e4732 496
b00f938c 497 d40_pool_lli_free(d40c, d40d);
698e4732 498 d40_lcla_free_all(d40c, d40d);
c675b1b4 499 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 500}
501
502static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
503{
504 list_add_tail(&desc->node, &d40c->active);
505}
506
1c4b0927
RV		 507static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
508{
509 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
510 struct d40_phy_lli *lli_src = desc->lli_phy.src;
511 void __iomem *base = chan_base(chan);
512
513 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
514 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
515 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
516 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
517
518 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
519 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
520 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
521 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
522}
523
e65889c7 524static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
698e4732 525{
e65889c7
RV		 526 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
527 struct d40_log_lli_bidir *lli = &desc->lli_log;
528 int lli_current = desc->lli_current;
529 int lli_len = desc->lli_len;
530 int curr_lcla = -EINVAL;
531
532 if (lli_len - lli_current > 1)
533 curr_lcla = d40_lcla_alloc_one(chan, desc);
534
535 d40_log_lli_lcpa_write(chan->lcpa,
536 &lli->dst[lli_current],
537 &lli->src[lli_current],
538 curr_lcla);
539
540 lli_current++;
541 for (; lli_current < lli_len; lli_current++) {
542 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
543 8 * curr_lcla * 2;
544 struct d40_log_lli *lcla = pool->base + lcla_offset;
545 int next_lcla;
546
547 if (lli_current + 1 < lli_len)
548 next_lcla = d40_lcla_alloc_one(chan, desc);
549 else
550 next_lcla = -EINVAL;
551
552 d40_log_lli_lcla_write(lcla,
553 &lli->dst[lli_current],
554 &lli->src[lli_current],
555 next_lcla);
556
557 dma_sync_single_range_for_device(chan->base->dev,
558 pool->dma_addr, lcla_offset,
559 2 * sizeof(struct d40_log_lli),
560 DMA_TO_DEVICE);
561
562 curr_lcla = next_lcla;
563
564 if (curr_lcla == -EINVAL) {
565 lli_current++;
566 break;
567 }
568 }
569
570 desc->lli_current = lli_current;
571}
698e4732 572
e65889c7
RV		 573static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
574{
724a8577 575 if (chan_is_physical(d40c)) {
1c4b0927 576 d40_phy_lli_load(d40c, d40d);
698e4732 577 d40d->lli_current = d40d->lli_len;
e65889c7
RV		 578 } else
579 d40_log_lli_to_lcxa(d40c, d40d);
698e4732
JA		 580}
581
8d318a50
LW		 582static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
583{
584 struct d40_desc *d;
585
586 if (list_empty(&d40c->active))
587 return NULL;
588
589 d = list_first_entry(&d40c->active,
590 struct d40_desc,
591 node);
592 return d;
593}
594
595static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
596{
597 list_add_tail(&desc->node, &d40c->queue);
598}
599
600static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
601{
602 struct d40_desc *d;
603
604 if (list_empty(&d40c->queue))
605 return NULL;
606
607 d = list_first_entry(&d40c->queue,
608 struct d40_desc,
609 node);
610 return d;
611}
612
d49278e3
PF		 613static int d40_psize_2_burst_size(bool is_log, int psize)
614{
615 if (is_log) {
616 if (psize == STEDMA40_PSIZE_LOG_1)
617 return 1;
618 } else {
619 if (psize == STEDMA40_PSIZE_PHY_1)
620 return 1;
621 }
622
623 return 2 << psize;
624}
625
626/*
627 * The dma only supports transmitting packages up to
628 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
629 * dma elements required to send the entire sg list
630 */
631static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
632{
633 int dmalen;
634 u32 max_w = max(data_width1, data_width2);
635 u32 min_w = min(data_width1, data_width2);
636 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
637
638 if (seg_max > STEDMA40_MAX_SEG_SIZE)
639 seg_max -= (1 << max_w);
640
641 if (!IS_ALIGNED(size, 1 << max_w))
642 return -EINVAL;
643
644 if (size <= seg_max)
645 dmalen = 1;
646 else {
647 dmalen = size / seg_max;
648 if (dmalen * seg_max < size)
649 dmalen++;
650 }
651 return dmalen;
652}
653
654static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
655 u32 data_width1, u32 data_width2)
656{
657 struct scatterlist *sg;
658 int i;
659 int len = 0;
660 int ret;
661
662 for_each_sg(sgl, sg, sg_len, i) {
663 ret = d40_size_2_dmalen(sg_dma_len(sg),
664 data_width1, data_width2);
665 if (ret < 0)
666 return ret;
667 len += ret;
668 }
669 return len;
670}
8d318a50 671
d49278e3 672/* Support functions for logical channels */
8d318a50
LW		 673
674static int d40_channel_execute_command(struct d40_chan *d40c,
675 enum d40_command command)
676{
767a9675
JA		 677 u32 status;
678 int i;
8d318a50
LW		 679 void __iomem *active_reg;
680 int ret = 0;
681 unsigned long flags;
1d392a7b 682 u32 wmask;
8d318a50
LW		 683
684 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
685
686 if (d40c->phy_chan->num % 2 == 0)
687 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
688 else
689 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
690
691 if (command == D40_DMA_SUSPEND_REQ) {
692 status = (readl(active_reg) &
693 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
694 D40_CHAN_POS(d40c->phy_chan->num);
695
696 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
697 goto done;
698 }
699
1d392a7b
JA		 700 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
701 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
702 active_reg);
8d318a50
LW		 703
704 if (command == D40_DMA_SUSPEND_REQ) {
705
706 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
707 status = (readl(active_reg) &
708 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
709 D40_CHAN_POS(d40c->phy_chan->num);
710
711 cpu_relax();
712 /*
713 * Reduce the number of bus accesses while
714 * waiting for the DMA to suspend.
715 */
716 udelay(3);
717
718 if (status == D40_DMA_STOP ||
719 status == D40_DMA_SUSPENDED)
720 break;
721 }
722
723 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 724 chan_err(d40c,
725 "unable to suspend the chl %d (log: %d) status %x\n",
726 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 727 status);
728 dump_stack();
729 ret = -EBUSY;
730 }
731
732 }
733done:
734 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
735 return ret;
736}
737
738static void d40_term_all(struct d40_chan *d40c)
739{
740 struct d40_desc *d40d;
8d318a50
LW		 741
742 /* Release active descriptors */
743 while ((d40d = d40_first_active_get(d40c))) {
744 d40_desc_remove(d40d);
8d318a50
LW		 745 d40_desc_free(d40c, d40d);
746 }
747
748 /* Release queued descriptors waiting for transfer */
749 while ((d40d = d40_first_queued(d40c))) {
750 d40_desc_remove(d40d);
8d318a50
LW		 751 d40_desc_free(d40c, d40d);
752 }
753
8d318a50
LW		 754
755 d40c->pending_tx = 0;
756 d40c->busy = false;
757}
758
262d2915
RV		 759static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
760 u32 event, int reg)
761{
8ca84687 762 void __iomem *addr = chan_base(d40c) + reg;
262d2915
RV		 763 int tries;
764
765 if (!enable) {
766 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
767 | ~D40_EVENTLINE_MASK(event), addr);
768 return;
769 }
770
771 /*
772 * The hardware sometimes doesn't register the enable when src and dst
773 * event lines are active on the same logical channel. Retry to ensure
774 * it does. Usually only one retry is sufficient.
775 */
776 tries = 100;
777 while (--tries) {
778 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
779 | ~D40_EVENTLINE_MASK(event), addr);
780
781 if (readl(addr) & D40_EVENTLINE_MASK(event))
782 break;
783 }
784
785 if (tries != 99)
786 dev_dbg(chan2dev(d40c),
787 "[%s] workaround enable S%cLNK (%d tries)\n",
788 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
789 100 - tries);
790
791 WARN_ON(!tries);
792}
793
8d318a50
LW		 794static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
795{
8d318a50
LW		 796 unsigned long flags;
797
8d318a50
LW		 798 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
799
800 /* Enable event line connected to device (or memcpy) */
801 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
802 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
803 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
804
262d2915
RV		 805 __d40_config_set_event(d40c, do_enable, event,
806 D40_CHAN_REG_SSLNK);
8d318a50 807 }
262d2915 808
8d318a50
LW		 809 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
810 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
811
262d2915
RV		 812 __d40_config_set_event(d40c, do_enable, event,
813 D40_CHAN_REG_SDLNK);
8d318a50
LW		 814 }
815
816 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
817}
818
a5ebca47 819static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 820{
8ca84687 821 void __iomem *chanbase = chan_base(d40c);
be8cb7df 822 u32 val;
8d318a50 823
8ca84687
RV		 824 val = readl(chanbase + D40_CHAN_REG_SSLNK);
825 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 826
a5ebca47 827 return val;
8d318a50
LW		 828}
829
20a5b6d0
RV		 830static u32 d40_get_prmo(struct d40_chan *d40c)
831{
832 static const unsigned int phy_map[] = {
833 [STEDMA40_PCHAN_BASIC_MODE]
834 = D40_DREG_PRMO_PCHAN_BASIC,
835 [STEDMA40_PCHAN_MODULO_MODE]
836 = D40_DREG_PRMO_PCHAN_MODULO,
837 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
838 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
839 };
840 static const unsigned int log_map[] = {
841 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
842 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
843 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
844 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
845 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
846 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
847 };
848
724a8577 849 if (chan_is_physical(d40c))
20a5b6d0
RV		 850 return phy_map[d40c->dma_cfg.mode_opt];
851 else
852 return log_map[d40c->dma_cfg.mode_opt];
853}
854
b55912c6 855static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 856{
857 u32 addr_base;
858 u32 var;
8d318a50
LW		 859
860 /* Odd addresses are even addresses + 4 */
861 addr_base = (d40c->phy_chan->num % 2) * 4;
862 /* Setup channel mode to logical or physical */
724a8577 863 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 864 D40_CHAN_POS(d40c->phy_chan->num);
865 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
866
867 /* Setup operational mode option register */
20a5b6d0 868 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 869
870 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
871
724a8577 872 if (chan_is_logical(d40c)) {
8ca84687
RV		 873 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
874 & D40_SREG_ELEM_LOG_LIDX_MASK;
875 void __iomem *chanbase = chan_base(d40c);
876
8d318a50 877 /* Set default config for CFG reg */
8ca84687
RV		 878 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
879 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 880
b55912c6 881 /* Set LIDX for lcla */
8ca84687
RV		 882 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
883 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
8d318a50 884 }
8d318a50
LW		 885}
886
aa182ae2
JA		 887static u32 d40_residue(struct d40_chan *d40c)
888{
889 u32 num_elt;
890
724a8577 891 if (chan_is_logical(d40c))
aa182ae2
JA		 892 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
893 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 894 else {
895 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
896 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
897 >> D40_SREG_ELEM_PHY_ECNT_POS;
898 }
899
aa182ae2
JA		 900 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
901}
902
903static bool d40_tx_is_linked(struct d40_chan *d40c)
904{
905 bool is_link;
906
724a8577 907 if (chan_is_logical(d40c))
aa182ae2
JA		 908 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
909 else
8ca84687
RV		 910 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
911 & D40_SREG_LNK_PHYS_LNK_MASK;
912
aa182ae2
JA		 913 return is_link;
914}
915
916static int d40_pause(struct dma_chan *chan)
917{
918 struct d40_chan *d40c =
919 container_of(chan, struct d40_chan, chan);
920 int res = 0;
921 unsigned long flags;
922
3ac012af
JA		 923 if (!d40c->busy)
924 return 0;
925
aa182ae2
JA		 926 spin_lock_irqsave(&d40c->lock, flags);
927
928 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
929 if (res == 0) {
724a8577 930 if (chan_is_logical(d40c)) {
aa182ae2
JA		 931 d40_config_set_event(d40c, false);
932 /* Resume the other logical channels if any */
933 if (d40_chan_has_events(d40c))
934 res = d40_channel_execute_command(d40c,
935 D40_DMA_RUN);
936 }
937 }
938
939 spin_unlock_irqrestore(&d40c->lock, flags);
940 return res;
941}
942
943static int d40_resume(struct dma_chan *chan)
944{
945 struct d40_chan *d40c =
946 container_of(chan, struct d40_chan, chan);
947 int res = 0;
948 unsigned long flags;
949
3ac012af
JA		 950 if (!d40c->busy)
951 return 0;
952
aa182ae2
JA		 953 spin_lock_irqsave(&d40c->lock, flags);
954
955 if (d40c->base->rev == 0)
724a8577 956 if (chan_is_logical(d40c)) {
aa182ae2
JA		 957 res = d40_channel_execute_command(d40c,
958 D40_DMA_SUSPEND_REQ);
959 goto no_suspend;
960 }
961
962 /* If bytes left to transfer or linked tx resume job */
963 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
964
724a8577 965 if (chan_is_logical(d40c))
aa182ae2
JA		 966 d40_config_set_event(d40c, true);
967
968 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
969 }
970
971no_suspend:
972 spin_unlock_irqrestore(&d40c->lock, flags);
973 return res;
974}
975
8d318a50
LW		 976static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
977{
978 struct d40_chan *d40c = container_of(tx->chan,
979 struct d40_chan,
980 chan);
981 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
982 unsigned long flags;
983
984 spin_lock_irqsave(&d40c->lock, flags);
985
aa182ae2
JA		 986 d40c->chan.cookie++;
987
988 if (d40c->chan.cookie < 0)
989 d40c->chan.cookie = 1;
990
991 d40d->txd.cookie = d40c->chan.cookie;
992
8d318a50
LW		 993 d40_desc_queue(d40c, d40d);
994
995 spin_unlock_irqrestore(&d40c->lock, flags);
996
997 return tx->cookie;
998}
999
1000static int d40_start(struct d40_chan *d40c)
1001{
f4185592
LW		 1002 if (d40c->base->rev == 0) {
1003 int err;
1004
724a8577 1005 if (chan_is_logical(d40c)) {
f4185592
LW		 1006 err = d40_channel_execute_command(d40c,
1007 D40_DMA_SUSPEND_REQ);
1008 if (err)
1009 return err;
1010 }
1011 }
1012
724a8577 1013 if (chan_is_logical(d40c))
8d318a50 1014 d40_config_set_event(d40c, true);
8d318a50 1015
0c32269d 1016 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 1017}
1018
1019static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1020{
1021 struct d40_desc *d40d;
1022 int err;
1023
1024 /* Start queued jobs, if any */
1025 d40d = d40_first_queued(d40c);
1026
1027 if (d40d != NULL) {
1028 d40c->busy = true;
1029
1030 /* Remove from queue */
1031 d40_desc_remove(d40d);
1032
1033 /* Add to active queue */
1034 d40_desc_submit(d40c, d40d);
1035
7d83a854
RV		 1036 /* Initiate DMA job */
1037 d40_desc_load(d40c, d40d);
8d318a50 1038
7d83a854
RV		 1039 /* Start dma job */
1040 err = d40_start(d40c);
8d318a50 1041
7d83a854
RV		 1042 if (err)
1043 return NULL;
8d318a50
LW		 1044 }
1045
1046 return d40d;
1047}
1048
1049/* called from interrupt context */
1050static void dma_tc_handle(struct d40_chan *d40c)
1051{
1052 struct d40_desc *d40d;
1053
8d318a50
LW		 1054 /* Get first active entry from list */
1055 d40d = d40_first_active_get(d40c);
1056
1057 if (d40d == NULL)
1058 return;
1059
698e4732 1060 d40_lcla_free_all(d40c, d40d);
8d318a50 1061
698e4732 1062 if (d40d->lli_current < d40d->lli_len) {
8d318a50
LW		 1063 d40_desc_load(d40c, d40d);
1064 /* Start dma job */
1065 (void) d40_start(d40c);
1066 return;
1067 }
1068
1069 if (d40_queue_start(d40c) == NULL)
1070 d40c->busy = false;
1071
1072 d40c->pending_tx++;
1073 tasklet_schedule(&d40c->tasklet);
1074
1075}
1076
1077static void dma_tasklet(unsigned long data)
1078{
1079 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1080 struct d40_desc *d40d;
8d318a50
LW		 1081 unsigned long flags;
1082 dma_async_tx_callback callback;
1083 void *callback_param;
1084
1085 spin_lock_irqsave(&d40c->lock, flags);
1086
1087 /* Get first active entry from list */
767a9675 1088 d40d = d40_first_active_get(d40c);
8d318a50 1089
767a9675 1090 if (d40d == NULL)
8d318a50
LW		 1091 goto err;
1092
767a9675 1093 d40c->completed = d40d->txd.cookie;
8d318a50
LW		 1094
1095 /*
1096 * If terminating a channel pending_tx is set to zero.
1097 * This prevents any finished active jobs to return to the client.
1098 */
1099 if (d40c->pending_tx == 0) {
1100 spin_unlock_irqrestore(&d40c->lock, flags);
1101 return;
1102 }
1103
1104 /* Callback to client */
767a9675
JA		 1105 callback = d40d->txd.callback;
1106 callback_param = d40d->txd.callback_param;
1107
1108 if (async_tx_test_ack(&d40d->txd)) {
b00f938c 1109 d40_pool_lli_free(d40c, d40d);
767a9675
JA		 1110 d40_desc_remove(d40d);
1111 d40_desc_free(d40c, d40d);
8d318a50 1112 } else {
767a9675
JA		 1113 if (!d40d->is_in_client_list) {
1114 d40_desc_remove(d40d);
698e4732 1115 d40_lcla_free_all(d40c, d40d);
767a9675
JA		 1116 list_add_tail(&d40d->node, &d40c->client);
1117 d40d->is_in_client_list = true;
8d318a50
LW		 1118 }
1119 }
1120
1121 d40c->pending_tx--;
1122
1123 if (d40c->pending_tx)
1124 tasklet_schedule(&d40c->tasklet);
1125
1126 spin_unlock_irqrestore(&d40c->lock, flags);
1127
767a9675 1128 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
8d318a50
LW		 1129 callback(callback_param);
1130
1131 return;
1132
1133 err:
1134 /* Rescue manouver if receiving double interrupts */
1135 if (d40c->pending_tx > 0)
1136 d40c->pending_tx--;
1137 spin_unlock_irqrestore(&d40c->lock, flags);
1138}
1139
1140static irqreturn_t d40_handle_interrupt(int irq, void *data)
1141{
1142 static const struct d40_interrupt_lookup il[] = {
1143 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1144 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1145 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1146 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1147 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1148 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1149 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1150 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1151 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1152 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1153 };
1154
1155 int i;
1156 u32 regs[ARRAY_SIZE(il)];
8d318a50
LW		 1157 u32 idx;
1158 u32 row;
1159 long chan = -1;
1160 struct d40_chan *d40c;
1161 unsigned long flags;
1162 struct d40_base *base = data;
1163
1164 spin_lock_irqsave(&base->interrupt_lock, flags);
1165
1166 /* Read interrupt status of both logical and physical channels */
1167 for (i = 0; i < ARRAY_SIZE(il); i++)
1168 regs[i] = readl(base->virtbase + il[i].src);
1169
1170 for (;;) {
1171
1172 chan = find_next_bit((unsigned long *)regs,
1173 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1174
1175 /* No more set bits found? */
1176 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1177 break;
1178
1179 row = chan / BITS_PER_LONG;
1180 idx = chan & (BITS_PER_LONG - 1);
1181
1182 /* ACK interrupt */
1b00348d 1183 writel(1 << idx, base->virtbase + il[row].clr);
8d318a50
LW		 1184
1185 if (il[row].offset == D40_PHY_CHAN)
1186 d40c = base->lookup_phy_chans[idx];
1187 else
1188 d40c = base->lookup_log_chans[il[row].offset + idx];
1189 spin_lock(&d40c->lock);
1190
1191 if (!il[row].is_error)
1192 dma_tc_handle(d40c);
1193 else
6db5a8ba
RV		 1194 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1195 chan, il[row].offset, idx);
8d318a50
LW		 1196
1197 spin_unlock(&d40c->lock);
1198 }
1199
1200 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1201
1202 return IRQ_HANDLED;
1203}
1204
8d318a50
LW		 1205static int d40_validate_conf(struct d40_chan *d40c,
1206 struct stedma40_chan_cfg *conf)
1207{
1208 int res = 0;
1209 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1210 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
38bdbf02 1211 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1212
0747c7ba 1213 if (!conf->dir) {
6db5a8ba 1214 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1215 res = -EINVAL;
1216 }
1217
1218 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1219 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1220 d40c->runtime_addr == 0) {
1221
6db5a8ba
RV		 1222 chan_err(d40c, "Invalid TX channel address (%d)\n",
1223 conf->dst_dev_type);
0747c7ba
LW		 1224 res = -EINVAL;
1225 }
1226
1227 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1228 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1229 d40c->runtime_addr == 0) {
6db5a8ba
RV		 1230 chan_err(d40c, "Invalid RX channel address (%d)\n",
1231 conf->src_dev_type);
0747c7ba
LW		 1232 res = -EINVAL;
1233 }
1234
1235 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
8d318a50 1236 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
6db5a8ba 1237 chan_err(d40c, "Invalid dst\n");
8d318a50
LW		 1238 res = -EINVAL;
1239 }
1240
0747c7ba 1241 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
8d318a50 1242 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
6db5a8ba 1243 chan_err(d40c, "Invalid src\n");
8d318a50
LW		 1244 res = -EINVAL;
1245 }
1246
1247 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1248 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
6db5a8ba 1249 chan_err(d40c, "No event line\n");
8d318a50
LW		 1250 res = -EINVAL;
1251 }
1252
1253 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1254 (src_event_group != dst_event_group)) {
6db5a8ba 1255 chan_err(d40c, "Invalid event group\n");
8d318a50
LW		 1256 res = -EINVAL;
1257 }
1258
1259 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1260 /*
1261 * DMAC HW supports it. Will be added to this driver,
1262 * in case any dma client requires it.
1263 */
6db5a8ba 1264 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1265 res = -EINVAL;
1266 }
1267
d49278e3
PF		 1268 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1269 (1 << conf->src_info.data_width) !=
1270 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1271 (1 << conf->dst_info.data_width)) {
1272 /*
1273 * The DMAC hardware only supports
1274 * src (burst x width) == dst (burst x width)
1275 */
1276
6db5a8ba 1277 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1278 res = -EINVAL;
1279 }
1280
8d318a50
LW		 1281 return res;
1282}
1283
1284static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
4aed79b2 1285 int log_event_line, bool is_log)
8d318a50
LW		 1286{
1287 unsigned long flags;
1288 spin_lock_irqsave(&phy->lock, flags);
4aed79b2 1289 if (!is_log) {
8d318a50
LW		 1290 /* Physical interrupts are masked per physical full channel */
1291 if (phy->allocated_src == D40_ALLOC_FREE &&
1292 phy->allocated_dst == D40_ALLOC_FREE) {
1293 phy->allocated_dst = D40_ALLOC_PHY;
1294 phy->allocated_src = D40_ALLOC_PHY;
1295 goto found;
1296 } else
1297 goto not_found;
1298 }
1299
1300 /* Logical channel */
1301 if (is_src) {
1302 if (phy->allocated_src == D40_ALLOC_PHY)
1303 goto not_found;
1304
1305 if (phy->allocated_src == D40_ALLOC_FREE)
1306 phy->allocated_src = D40_ALLOC_LOG_FREE;
1307
1308 if (!(phy->allocated_src & (1 << log_event_line))) {
1309 phy->allocated_src |= 1 << log_event_line;
1310 goto found;
1311 } else
1312 goto not_found;
1313 } else {
1314 if (phy->allocated_dst == D40_ALLOC_PHY)
1315 goto not_found;
1316
1317 if (phy->allocated_dst == D40_ALLOC_FREE)
1318 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1319
1320 if (!(phy->allocated_dst & (1 << log_event_line))) {
1321 phy->allocated_dst |= 1 << log_event_line;
1322 goto found;
1323 } else
1324 goto not_found;
1325 }
1326
1327not_found:
1328 spin_unlock_irqrestore(&phy->lock, flags);
1329 return false;
1330found:
1331 spin_unlock_irqrestore(&phy->lock, flags);
1332 return true;
1333}
1334
1335static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1336 int log_event_line)
1337{
1338 unsigned long flags;
1339 bool is_free = false;
1340
1341 spin_lock_irqsave(&phy->lock, flags);
1342 if (!log_event_line) {
8d318a50
LW		 1343 phy->allocated_dst = D40_ALLOC_FREE;
1344 phy->allocated_src = D40_ALLOC_FREE;
1345 is_free = true;
1346 goto out;
1347 }
1348
1349 /* Logical channel */
1350 if (is_src) {
1351 phy->allocated_src &= ~(1 << log_event_line);
1352 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1353 phy->allocated_src = D40_ALLOC_FREE;
1354 } else {
1355 phy->allocated_dst &= ~(1 << log_event_line);
1356 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1357 phy->allocated_dst = D40_ALLOC_FREE;
1358 }
1359
1360 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1361 D40_ALLOC_FREE);
1362
1363out:
1364 spin_unlock_irqrestore(&phy->lock, flags);
1365
1366 return is_free;
1367}
1368
1369static int d40_allocate_channel(struct d40_chan *d40c)
1370{
1371 int dev_type;
1372 int event_group;
1373 int event_line;
1374 struct d40_phy_res *phys;
1375 int i;
1376 int j;
1377 int log_num;
1378 bool is_src;
38bdbf02 1379 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1380
1381 phys = d40c->base->phy_res;
1382
1383 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1384 dev_type = d40c->dma_cfg.src_dev_type;
1385 log_num = 2 * dev_type;
1386 is_src = true;
1387 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1388 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1389 /* dst event lines are used for logical memcpy */
1390 dev_type = d40c->dma_cfg.dst_dev_type;
1391 log_num = 2 * dev_type + 1;
1392 is_src = false;
1393 } else
1394 return -EINVAL;
1395
1396 event_group = D40_TYPE_TO_GROUP(dev_type);
1397 event_line = D40_TYPE_TO_EVENT(dev_type);
1398
1399 if (!is_log) {
1400 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1401 /* Find physical half channel */
1402 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1403
4aed79b2
MM		 1404 if (d40_alloc_mask_set(&phys[i], is_src,
1405 0, is_log))
8d318a50
LW		 1406 goto found_phy;
1407 }
1408 } else
1409 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1410 int phy_num = j + event_group * 2;
1411 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1412 if (d40_alloc_mask_set(&phys[i],
1413 is_src,
1414 0,
1415 is_log))
8d318a50
LW		 1416 goto found_phy;
1417 }
1418 }
1419 return -EINVAL;
1420found_phy:
1421 d40c->phy_chan = &phys[i];
1422 d40c->log_num = D40_PHY_CHAN;
1423 goto out;
1424 }
1425 if (dev_type == -1)
1426 return -EINVAL;
1427
1428 /* Find logical channel */
1429 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1430 int phy_num = j + event_group * 2;
1431 /*
1432 * Spread logical channels across all available physical rather
1433 * than pack every logical channel at the first available phy
1434 * channels.
1435 */
1436 if (is_src) {
1437 for (i = phy_num; i < phy_num + 2; i++) {
1438 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1439 event_line, is_log))
8d318a50
LW		 1440 goto found_log;
1441 }
1442 } else {
1443 for (i = phy_num + 1; i >= phy_num; i--) {
1444 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1445 event_line, is_log))
8d318a50
LW		 1446 goto found_log;
1447 }
1448 }
1449 }
1450 return -EINVAL;
1451
1452found_log:
1453 d40c->phy_chan = &phys[i];
1454 d40c->log_num = log_num;
1455out:
1456
1457 if (is_log)
1458 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1459 else
1460 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1461
1462 return 0;
1463
1464}
1465
8d318a50
LW		 1466static int d40_config_memcpy(struct d40_chan *d40c)
1467{
1468 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1469
1470 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1471 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1472 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1473 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1474 memcpy[d40c->chan.chan_id];
1475
1476 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1477 dma_has_cap(DMA_SLAVE, cap)) {
1478 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1479 } else {
6db5a8ba 1480 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 1481 return -EINVAL;
1482 }
1483
1484 return 0;
1485}
1486
1487
1488static int d40_free_dma(struct d40_chan *d40c)
1489{
1490
1491 int res = 0;
d181b3a8 1492 u32 event;
8d318a50
LW		 1493 struct d40_phy_res *phy = d40c->phy_chan;
1494 bool is_src;
a8be8627
PF		 1495 struct d40_desc *d;
1496 struct d40_desc *_d;
1497
8d318a50
LW		 1498
1499 /* Terminate all queued and active transfers */
1500 d40_term_all(d40c);
1501
a8be8627
PF		 1502 /* Release client owned descriptors */
1503 if (!list_empty(&d40c->client))
1504 list_for_each_entry_safe(d, _d, &d40c->client, node) {
b00f938c 1505 d40_pool_lli_free(d40c, d);
a8be8627 1506 d40_desc_remove(d);
a8be8627
PF		 1507 d40_desc_free(d40c, d);
1508 }
1509
8d318a50 1510 if (phy == NULL) {
6db5a8ba 1511 chan_err(d40c, "phy == null\n");
8d318a50
LW		 1512 return -EINVAL;
1513 }
1514
1515 if (phy->allocated_src == D40_ALLOC_FREE &&
1516 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 1517 chan_err(d40c, "channel already free\n");
8d318a50
LW		 1518 return -EINVAL;
1519 }
1520
8d318a50
LW		 1521 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1522 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1523 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8d318a50
LW		 1524 is_src = false;
1525 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1526 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8d318a50
LW		 1527 is_src = true;
1528 } else {
6db5a8ba 1529 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 1530 return -EINVAL;
1531 }
1532
d181b3a8
JA		 1533 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1534 if (res) {
6db5a8ba 1535 chan_err(d40c, "suspend failed\n");
d181b3a8
JA		 1536 return res;
1537 }
1538
724a8577 1539 if (chan_is_logical(d40c)) {
d181b3a8 1540 /* Release logical channel, deactivate the event line */
8d318a50 1541
d181b3a8 1542 d40_config_set_event(d40c, false);
8d318a50
LW		 1543 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1544
1545 /*
1546 * Check if there are more logical allocation
1547 * on this phy channel.
1548 */
1549 if (!d40_alloc_mask_free(phy, is_src, event)) {
1550 /* Resume the other logical channels if any */
1551 if (d40_chan_has_events(d40c)) {
1552 res = d40_channel_execute_command(d40c,
1553 D40_DMA_RUN);
1554 if (res) {
6db5a8ba
RV		 1555 chan_err(d40c,
1556 "Executing RUN command\n");
8d318a50
LW		 1557 return res;
1558 }
1559 }
1560 return 0;
1561 }
d181b3a8
JA		 1562 } else {
1563 (void) d40_alloc_mask_free(phy, is_src, 0);
1564 }
8d318a50
LW		 1565
1566 /* Release physical channel */
1567 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1568 if (res) {
6db5a8ba 1569 chan_err(d40c, "Failed to stop channel\n");
8d318a50
LW		 1570 return res;
1571 }
1572 d40c->phy_chan = NULL;
ce2ca125 1573 d40c->configured = false;
8d318a50
LW		 1574 d40c->base->lookup_phy_chans[phy->num] = NULL;
1575
1576 return 0;
8d318a50
LW		 1577}
1578
a5ebca47
JA		 1579static bool d40_is_paused(struct d40_chan *d40c)
1580{
8ca84687 1581 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 1582 bool is_paused = false;
1583 unsigned long flags;
1584 void __iomem *active_reg;
1585 u32 status;
1586 u32 event;
a5ebca47
JA		 1587
1588 spin_lock_irqsave(&d40c->lock, flags);
1589
724a8577 1590 if (chan_is_physical(d40c)) {
a5ebca47
JA		 1591 if (d40c->phy_chan->num % 2 == 0)
1592 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1593 else
1594 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1595
1596 status = (readl(active_reg) &
1597 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1598 D40_CHAN_POS(d40c->phy_chan->num);
1599 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1600 is_paused = true;
1601
1602 goto _exit;
1603 }
1604
a5ebca47 1605 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
9dbfbd35 1606 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
a5ebca47 1607 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8ca84687 1608 status = readl(chanbase + D40_CHAN_REG_SDLNK);
9dbfbd35 1609 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
a5ebca47 1610 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8ca84687 1611 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 1612 } else {
6db5a8ba 1613 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 1614 goto _exit;
1615 }
9dbfbd35 1616
a5ebca47
JA		 1617 status = (status & D40_EVENTLINE_MASK(event)) >>
1618 D40_EVENTLINE_POS(event);
1619
1620 if (status != D40_DMA_RUN)
1621 is_paused = true;
a5ebca47
JA		 1622_exit:
1623 spin_unlock_irqrestore(&d40c->lock, flags);
1624 return is_paused;
1625
1626}
1627
1628
8d318a50
LW		 1629static u32 stedma40_residue(struct dma_chan *chan)
1630{
1631 struct d40_chan *d40c =
1632 container_of(chan, struct d40_chan, chan);
1633 u32 bytes_left;
1634 unsigned long flags;
1635
1636 spin_lock_irqsave(&d40c->lock, flags);
1637 bytes_left = d40_residue(d40c);
1638 spin_unlock_irqrestore(&d40c->lock, flags);
1639
1640 return bytes_left;
1641}
1642
3e3a0763
RV		 1643static int
1644d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
1645 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 1646 unsigned int sg_len, dma_addr_t src_dev_addr,
1647 dma_addr_t dst_dev_addr)
3e3a0763
RV		 1648{
1649 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1650 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1651 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
5ed04b85 1652 int ret;
3e3a0763 1653
5ed04b85
RV		 1654 ret = d40_log_sg_to_lli(sg_src, sg_len,
1655 src_dev_addr,
1656 desc->lli_log.src,
1657 chan->log_def.lcsp1,
1658 src_info->data_width,
1659 dst_info->data_width);
1660
1661 ret = d40_log_sg_to_lli(sg_dst, sg_len,
1662 dst_dev_addr,
1663 desc->lli_log.dst,
1664 chan->log_def.lcsp3,
1665 dst_info->data_width,
1666 src_info->data_width);
1667
1668 return ret < 0 ? ret : 0;
3e3a0763
RV		 1669}
1670
1671static int
1672d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
1673 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 1674 unsigned int sg_len, dma_addr_t src_dev_addr,
1675 dma_addr_t dst_dev_addr)
3e3a0763 1676{
3e3a0763
RV		 1677 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1678 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1679 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
1680 int ret;
1681
1682 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
1683 desc->lli_phy.src,
1684 virt_to_phys(desc->lli_phy.src),
1685 chan->src_def_cfg,
cc31b6f7 1686 src_info, dst_info);
3e3a0763
RV		 1687
1688 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
1689 desc->lli_phy.dst,
1690 virt_to_phys(desc->lli_phy.dst),
1691 chan->dst_def_cfg,
cc31b6f7 1692 dst_info, src_info);
3e3a0763
RV		 1693
1694 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
1695 desc->lli_pool.size, DMA_TO_DEVICE);
1696
1697 return ret < 0 ? ret : 0;
1698}
1699
1700
5f81158f
RV		 1701static struct d40_desc *
1702d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
1703 unsigned int sg_len, unsigned long dma_flags)
1704{
1705 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1706 struct d40_desc *desc;
dbd88788 1707 int ret;
5f81158f
RV		 1708
1709 desc = d40_desc_get(chan);
1710 if (!desc)
1711 return NULL;
1712
1713 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
1714 cfg->dst_info.data_width);
1715 if (desc->lli_len < 0) {
1716 chan_err(chan, "Unaligned size\n");
dbd88788
RV		 1717 goto err;
1718 }
5f81158f 1719
dbd88788
RV		 1720 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
1721 if (ret < 0) {
1722 chan_err(chan, "Could not allocate lli\n");
1723 goto err;
5f81158f
RV		 1724 }
1725
dbd88788 1726
5f81158f
RV		 1727 desc->lli_current = 0;
1728 desc->txd.flags = dma_flags;
1729 desc->txd.tx_submit = d40_tx_submit;
1730
1731 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
1732
1733 return desc;
dbd88788
RV		 1734
1735err:
1736 d40_desc_free(chan, desc);
1737 return NULL;
5f81158f
RV		 1738}
1739
cade1d30
RV		 1740static dma_addr_t
1741d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
8d318a50 1742{
cade1d30
RV		 1743 struct stedma40_platform_data *plat = chan->base->plat_data;
1744 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1745 dma_addr_t addr;
1746
1747 if (chan->runtime_addr)
1748 return chan->runtime_addr;
1749
1750 if (direction == DMA_FROM_DEVICE)
1751 addr = plat->dev_rx[cfg->src_dev_type];
1752 else if (direction == DMA_TO_DEVICE)
1753 addr = plat->dev_tx[cfg->dst_dev_type];
1754
1755 return addr;
1756}
1757
1758static struct dma_async_tx_descriptor *
1759d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
1760 struct scatterlist *sg_dst, unsigned int sg_len,
1761 enum dma_data_direction direction, unsigned long dma_flags)
1762{
1763 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
822c5676
RV		 1764 dma_addr_t src_dev_addr = 0;
1765 dma_addr_t dst_dev_addr = 0;
cade1d30 1766 struct d40_desc *desc;
2a614340 1767 unsigned long flags;
cade1d30 1768 int ret;
8d318a50 1769
cade1d30
RV		 1770 if (!chan->phy_chan) {
1771 chan_err(chan, "Cannot prepare unallocated channel\n");
1772 return NULL;
0d0f6b8b
JA		 1773 }
1774
cade1d30 1775 spin_lock_irqsave(&chan->lock, flags);
8d318a50 1776
cade1d30
RV		 1777 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
1778 if (desc == NULL)
8d318a50
LW		 1779 goto err;
1780
822c5676
RV		 1781 if (direction != DMA_NONE) {
1782 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
1783
1784 if (direction == DMA_FROM_DEVICE)
1785 src_dev_addr = dev_addr;
1786 else if (direction == DMA_TO_DEVICE)
1787 dst_dev_addr = dev_addr;
1788 }
cade1d30
RV		 1789
1790 if (chan_is_logical(chan))
1791 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
822c5676 1792 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 1793 else
1794 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
822c5676 1795 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 1796
1797 if (ret) {
1798 chan_err(chan, "Failed to prepare %s sg job: %d\n",
1799 chan_is_logical(chan) ? "log" : "phy", ret);
1800 goto err;
8d318a50
LW		 1801 }
1802
cade1d30
RV		 1803 spin_unlock_irqrestore(&chan->lock, flags);
1804
1805 return &desc->txd;
8d318a50 1806
8d318a50 1807err:
cade1d30
RV		 1808 if (desc)
1809 d40_desc_free(chan, desc);
1810 spin_unlock_irqrestore(&chan->lock, flags);
8d318a50
LW		 1811 return NULL;
1812}
8d318a50
LW		 1813
1814bool stedma40_filter(struct dma_chan *chan, void *data)
1815{
1816 struct stedma40_chan_cfg *info = data;
1817 struct d40_chan *d40c =
1818 container_of(chan, struct d40_chan, chan);
1819 int err;
1820
1821 if (data) {
1822 err = d40_validate_conf(d40c, info);
1823 if (!err)
1824 d40c->dma_cfg = *info;
1825 } else
1826 err = d40_config_memcpy(d40c);
1827
ce2ca125
RV		 1828 if (!err)
1829 d40c->configured = true;
1830
8d318a50
LW		 1831 return err == 0;
1832}
1833EXPORT_SYMBOL(stedma40_filter);
1834
ac2c0a38
RV		 1835static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
1836{
1837 bool realtime = d40c->dma_cfg.realtime;
1838 bool highprio = d40c->dma_cfg.high_priority;
1839 u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
1840 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
1841 u32 event = D40_TYPE_TO_EVENT(dev_type);
1842 u32 group = D40_TYPE_TO_GROUP(dev_type);
1843 u32 bit = 1 << event;
1844
1845 /* Destination event lines are stored in the upper halfword */
1846 if (!src)
1847 bit <<= 16;
1848
1849 writel(bit, d40c->base->virtbase + prioreg + group * 4);
1850 writel(bit, d40c->base->virtbase + rtreg + group * 4);
1851}
1852
1853static void d40_set_prio_realtime(struct d40_chan *d40c)
1854{
1855 if (d40c->base->rev < 3)
1856 return;
1857
1858 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1859 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1860 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
1861
1862 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
1863 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1864 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
1865}
1866
8d318a50
LW		 1867/* DMA ENGINE functions */
1868static int d40_alloc_chan_resources(struct dma_chan *chan)
1869{
1870 int err;
1871 unsigned long flags;
1872 struct d40_chan *d40c =
1873 container_of(chan, struct d40_chan, chan);
ef1872ec 1874 bool is_free_phy;
8d318a50
LW		 1875 spin_lock_irqsave(&d40c->lock, flags);
1876
1877 d40c->completed = chan->cookie = 1;
1878
ce2ca125
RV		 1879 /* If no dma configuration is set use default configuration (memcpy) */
1880 if (!d40c->configured) {
8d318a50 1881 err = d40_config_memcpy(d40c);
ff0b12ba 1882 if (err) {
6db5a8ba 1883 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 1884 goto fail;
1885 }
8d318a50 1886 }
ef1872ec 1887 is_free_phy = (d40c->phy_chan == NULL);
8d318a50
LW		 1888
1889 err = d40_allocate_channel(d40c);
1890 if (err) {
6db5a8ba 1891 chan_err(d40c, "Failed to allocate channel\n");
ff0b12ba 1892 goto fail;
8d318a50
LW		 1893 }
1894
ef1872ec
LW		 1895 /* Fill in basic CFG register values */
1896 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
724a8577 1897 &d40c->dst_def_cfg, chan_is_logical(d40c));
ef1872ec 1898
ac2c0a38
RV		 1899 d40_set_prio_realtime(d40c);
1900
724a8577 1901 if (chan_is_logical(d40c)) {
ef1872ec
LW		 1902 d40_log_cfg(&d40c->dma_cfg,
1903 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1904
1905 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1906 d40c->lcpa = d40c->base->lcpa_base +
1907 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1908 else
1909 d40c->lcpa = d40c->base->lcpa_base +
1910 d40c->dma_cfg.dst_dev_type *
1911 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1912 }
1913
1914 /*
1915 * Only write channel configuration to the DMA if the physical
1916 * resource is free. In case of multiple logical channels
1917 * on the same physical resource, only the first write is necessary.
1918 */
b55912c6
JA		 1919 if (is_free_phy)
1920 d40_config_write(d40c);
ff0b12ba 1921fail:
8d318a50 1922 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 1923 return err;
8d318a50
LW		 1924}
1925
1926static void d40_free_chan_resources(struct dma_chan *chan)
1927{
1928 struct d40_chan *d40c =
1929 container_of(chan, struct d40_chan, chan);
1930 int err;
1931 unsigned long flags;
1932
0d0f6b8b 1933 if (d40c->phy_chan == NULL) {
6db5a8ba 1934 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 1935 return;
1936 }
1937
1938
8d318a50
LW		 1939 spin_lock_irqsave(&d40c->lock, flags);
1940
1941 err = d40_free_dma(d40c);
1942
1943 if (err)
6db5a8ba 1944 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 1945 spin_unlock_irqrestore(&d40c->lock, flags);
1946}
1947
1948static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1949 dma_addr_t dst,
1950 dma_addr_t src,
1951 size_t size,
2a614340 1952 unsigned long dma_flags)
8d318a50 1953{
95944c6e
RV		 1954 struct scatterlist dst_sg;
1955 struct scatterlist src_sg;
8d318a50 1956
95944c6e
RV		 1957 sg_init_table(&dst_sg, 1);
1958 sg_init_table(&src_sg, 1);
8d318a50 1959
95944c6e
RV		 1960 sg_dma_address(&dst_sg) = dst;
1961 sg_dma_address(&src_sg) = src;
8d318a50 1962
95944c6e
RV		 1963 sg_dma_len(&dst_sg) = size;
1964 sg_dma_len(&src_sg) = size;
8d318a50 1965
cade1d30 1966 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
8d318a50
LW		 1967}
1968
0d688662 1969static struct dma_async_tx_descriptor *
cade1d30
RV		 1970d40_prep_memcpy_sg(struct dma_chan *chan,
1971 struct scatterlist *dst_sg, unsigned int dst_nents,
1972 struct scatterlist *src_sg, unsigned int src_nents,
1973 unsigned long dma_flags)
0d688662
IS		 1974{
1975 if (dst_nents != src_nents)
1976 return NULL;
1977
cade1d30 1978 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
00ac0341
RV		 1979}
1980
8d318a50
LW		 1981static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
1982 struct scatterlist *sgl,
1983 unsigned int sg_len,
1984 enum dma_data_direction direction,
2a614340 1985 unsigned long dma_flags)
8d318a50 1986{
00ac0341
RV		 1987 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE)
1988 return NULL;
1989
cade1d30 1990 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
8d318a50
LW		 1991}
1992
1993static enum dma_status d40_tx_status(struct dma_chan *chan,
1994 dma_cookie_t cookie,
1995 struct dma_tx_state *txstate)
1996{
1997 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
1998 dma_cookie_t last_used;
1999 dma_cookie_t last_complete;
2000 int ret;
2001
0d0f6b8b 2002 if (d40c->phy_chan == NULL) {
6db5a8ba 2003 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2004 return -EINVAL;
2005 }
2006
8d318a50
LW		 2007 last_complete = d40c->completed;
2008 last_used = chan->cookie;
2009
a5ebca47
JA		 2010 if (d40_is_paused(d40c))
2011 ret = DMA_PAUSED;
2012 else
2013 ret = dma_async_is_complete(cookie, last_complete, last_used);
8d318a50 2014
a5ebca47
JA		 2015 dma_set_tx_state(txstate, last_complete, last_used,
2016 stedma40_residue(chan));
8d318a50
LW		 2017
2018 return ret;
2019}
2020
2021static void d40_issue_pending(struct dma_chan *chan)
2022{
2023 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2024 unsigned long flags;
2025
0d0f6b8b 2026 if (d40c->phy_chan == NULL) {
6db5a8ba 2027 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2028 return;
2029 }
2030
8d318a50
LW		 2031 spin_lock_irqsave(&d40c->lock, flags);
2032
2033 /* Busy means that pending jobs are already being processed */
2034 if (!d40c->busy)
2035 (void) d40_queue_start(d40c);
2036
2037 spin_unlock_irqrestore(&d40c->lock, flags);
2038}
2039
95e1400f
LW		 2040/* Runtime reconfiguration extension */
2041static void d40_set_runtime_config(struct dma_chan *chan,
2042 struct dma_slave_config *config)
2043{
2044 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2045 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2046 enum dma_slave_buswidth config_addr_width;
2047 dma_addr_t config_addr;
2048 u32 config_maxburst;
2049 enum stedma40_periph_data_width addr_width;
2050 int psize;
2051
2052 if (config->direction == DMA_FROM_DEVICE) {
2053 dma_addr_t dev_addr_rx =
2054 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2055
2056 config_addr = config->src_addr;
2057 if (dev_addr_rx)
2058 dev_dbg(d40c->base->dev,
2059 "channel has a pre-wired RX address %08x "
2060 "overriding with %08x\n",
2061 dev_addr_rx, config_addr);
2062 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2063 dev_dbg(d40c->base->dev,
2064 "channel was not configured for peripheral "
2065 "to memory transfer (%d) overriding\n",
2066 cfg->dir);
2067 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2068
2069 config_addr_width = config->src_addr_width;
2070 config_maxburst = config->src_maxburst;
2071
2072 } else if (config->direction == DMA_TO_DEVICE) {
2073 dma_addr_t dev_addr_tx =
2074 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2075
2076 config_addr = config->dst_addr;
2077 if (dev_addr_tx)
2078 dev_dbg(d40c->base->dev,
2079 "channel has a pre-wired TX address %08x "
2080 "overriding with %08x\n",
2081 dev_addr_tx, config_addr);
2082 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2083 dev_dbg(d40c->base->dev,
2084 "channel was not configured for memory "
2085 "to peripheral transfer (%d) overriding\n",
2086 cfg->dir);
2087 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2088
2089 config_addr_width = config->dst_addr_width;
2090 config_maxburst = config->dst_maxburst;
2091
2092 } else {
2093 dev_err(d40c->base->dev,
2094 "unrecognized channel direction %d\n",
2095 config->direction);
2096 return;
2097 }
2098
2099 switch (config_addr_width) {
2100 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2101 addr_width = STEDMA40_BYTE_WIDTH;
2102 break;
2103 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2104 addr_width = STEDMA40_HALFWORD_WIDTH;
2105 break;
2106 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2107 addr_width = STEDMA40_WORD_WIDTH;
2108 break;
2109 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2110 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2111 break;
2112 default:
2113 dev_err(d40c->base->dev,
2114 "illegal peripheral address width "
2115 "requested (%d)\n",
2116 config->src_addr_width);
2117 return;
2118 }
2119
724a8577 2120 if (chan_is_logical(d40c)) {
a59670a4
PF		 2121 if (config_maxburst >= 16)
2122 psize = STEDMA40_PSIZE_LOG_16;
2123 else if (config_maxburst >= 8)
2124 psize = STEDMA40_PSIZE_LOG_8;
2125 else if (config_maxburst >= 4)
2126 psize = STEDMA40_PSIZE_LOG_4;
2127 else
2128 psize = STEDMA40_PSIZE_LOG_1;
2129 } else {
2130 if (config_maxburst >= 16)
2131 psize = STEDMA40_PSIZE_PHY_16;
2132 else if (config_maxburst >= 8)
2133 psize = STEDMA40_PSIZE_PHY_8;
2134 else if (config_maxburst >= 4)
2135 psize = STEDMA40_PSIZE_PHY_4;
d49278e3
PF		 2136 else if (config_maxburst >= 2)
2137 psize = STEDMA40_PSIZE_PHY_2;
a59670a4
PF		 2138 else
2139 psize = STEDMA40_PSIZE_PHY_1;
2140 }
95e1400f
LW		 2141
2142 /* Set up all the endpoint configs */
2143 cfg->src_info.data_width = addr_width;
2144 cfg->src_info.psize = psize;
51f5d744 2145 cfg->src_info.big_endian = false;
95e1400f
LW		 2146 cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2147 cfg->dst_info.data_width = addr_width;
2148 cfg->dst_info.psize = psize;
51f5d744 2149 cfg->dst_info.big_endian = false;
95e1400f
LW		 2150 cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2151
a59670a4 2152 /* Fill in register values */
724a8577 2153 if (chan_is_logical(d40c))
a59670a4
PF		 2154 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2155 else
2156 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2157 &d40c->dst_def_cfg, false);
2158
95e1400f
LW		 2159 /* These settings will take precedence later */
2160 d40c->runtime_addr = config_addr;
2161 d40c->runtime_direction = config->direction;
2162 dev_dbg(d40c->base->dev,
2163 "configured channel %s for %s, data width %d, "
2164 "maxburst %d bytes, LE, no flow control\n",
2165 dma_chan_name(chan),
2166 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2167 config_addr_width,
2168 config_maxburst);
2169}
2170
05827630
LW		 2171static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2172 unsigned long arg)
8d318a50
LW		 2173{
2174 unsigned long flags;
2175 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2176
0d0f6b8b 2177 if (d40c->phy_chan == NULL) {
6db5a8ba 2178 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2179 return -EINVAL;
2180 }
2181
8d318a50
LW		 2182 switch (cmd) {
2183 case DMA_TERMINATE_ALL:
2184 spin_lock_irqsave(&d40c->lock, flags);
2185 d40_term_all(d40c);
2186 spin_unlock_irqrestore(&d40c->lock, flags);
2187 return 0;
2188 case DMA_PAUSE:
2189 return d40_pause(chan);
2190 case DMA_RESUME:
2191 return d40_resume(chan);
95e1400f
LW		 2192 case DMA_SLAVE_CONFIG:
2193 d40_set_runtime_config(chan,
2194 (struct dma_slave_config *) arg);
2195 return 0;
2196 default:
2197 break;
8d318a50
LW		 2198 }
2199
2200 /* Other commands are unimplemented */
2201 return -ENXIO;
2202}
2203
2204/* Initialization functions */
2205
2206static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2207 struct d40_chan *chans, int offset,
2208 int num_chans)
2209{
2210 int i = 0;
2211 struct d40_chan *d40c;
2212
2213 INIT_LIST_HEAD(&dma->channels);
2214
2215 for (i = offset; i < offset + num_chans; i++) {
2216 d40c = &chans[i];
2217 d40c->base = base;
2218 d40c->chan.device = dma;
2219
8d318a50
LW		 2220 spin_lock_init(&d40c->lock);
2221
2222 d40c->log_num = D40_PHY_CHAN;
2223
8d318a50
LW		 2224 INIT_LIST_HEAD(&d40c->active);
2225 INIT_LIST_HEAD(&d40c->queue);
2226 INIT_LIST_HEAD(&d40c->client);
2227
8d318a50
LW		 2228 tasklet_init(&d40c->tasklet, dma_tasklet,
2229 (unsigned long) d40c);
2230
2231 list_add_tail(&d40c->chan.device_node,
2232 &dma->channels);
2233 }
2234}
2235
2236static int __init d40_dmaengine_init(struct d40_base *base,
2237 int num_reserved_chans)
2238{
2239 int err ;
2240
2241 d40_chan_init(base, &base->dma_slave, base->log_chans,
2242 0, base->num_log_chans);
2243
2244 dma_cap_zero(base->dma_slave.cap_mask);
2245 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2246
2247 base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2248 base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2249 base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
cade1d30 2250 base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
8d318a50
LW		 2251 base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2252 base->dma_slave.device_tx_status = d40_tx_status;
2253 base->dma_slave.device_issue_pending = d40_issue_pending;
2254 base->dma_slave.device_control = d40_control;
2255 base->dma_slave.dev = base->dev;
2256
2257 err = dma_async_device_register(&base->dma_slave);
2258
2259 if (err) {
6db5a8ba 2260 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2261 goto failure1;
2262 }
2263
2264 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2265 base->num_log_chans, base->plat_data->memcpy_len);
2266
2267 dma_cap_zero(base->dma_memcpy.cap_mask);
2268 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
0d688662 2269 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
8d318a50
LW		 2270
2271 base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2272 base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2273 base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
cade1d30 2274 base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
8d318a50
LW		 2275 base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2276 base->dma_memcpy.device_tx_status = d40_tx_status;
2277 base->dma_memcpy.device_issue_pending = d40_issue_pending;
2278 base->dma_memcpy.device_control = d40_control;
2279 base->dma_memcpy.dev = base->dev;
2280 /*
2281 * This controller can only access address at even
2282 * 32bit boundaries, i.e. 2^2
2283 */
2284 base->dma_memcpy.copy_align = 2;
2285
2286 err = dma_async_device_register(&base->dma_memcpy);
2287
2288 if (err) {
6db5a8ba
RV		 2289 d40_err(base->dev,
2290 "Failed to regsiter memcpy only channels\n");
8d318a50
LW		 2291 goto failure2;
2292 }
2293
2294 d40_chan_init(base, &base->dma_both, base->phy_chans,
2295 0, num_reserved_chans);
2296
2297 dma_cap_zero(base->dma_both.cap_mask);
2298 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2299 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
0d688662 2300 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
8d318a50
LW		 2301
2302 base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2303 base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2304 base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
cade1d30 2305 base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
8d318a50
LW		 2306 base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2307 base->dma_both.device_tx_status = d40_tx_status;
2308 base->dma_both.device_issue_pending = d40_issue_pending;
2309 base->dma_both.device_control = d40_control;
2310 base->dma_both.dev = base->dev;
2311 base->dma_both.copy_align = 2;
2312 err = dma_async_device_register(&base->dma_both);
2313
2314 if (err) {
6db5a8ba
RV		 2315 d40_err(base->dev,
2316 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2317 goto failure3;
2318 }
2319 return 0;
2320failure3:
2321 dma_async_device_unregister(&base->dma_memcpy);
2322failure2:
2323 dma_async_device_unregister(&base->dma_slave);
2324failure1:
2325 return err;
2326}
2327
2328/* Initialization functions. */
2329
2330static int __init d40_phy_res_init(struct d40_base *base)
2331{
2332 int i;
2333 int num_phy_chans_avail = 0;
2334 u32 val[2];
2335 int odd_even_bit = -2;
2336
2337 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2338 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2339
2340 for (i = 0; i < base->num_phy_chans; i++) {
2341 base->phy_res[i].num = i;
2342 odd_even_bit += 2 * ((i % 2) == 0);
2343 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2344 /* Mark security only channels as occupied */
2345 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2346 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2347 } else {
2348 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2349 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2350 num_phy_chans_avail++;
2351 }
2352 spin_lock_init(&base->phy_res[i].lock);
2353 }
6b7acd84
JA		 2354
2355 /* Mark disabled channels as occupied */
2356 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 2357 int chan = base->plat_data->disabled_channels[i];
2358
2359 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2360 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2361 num_phy_chans_avail--;
6b7acd84
JA		 2362 }
2363
8d318a50
LW		 2364 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2365 num_phy_chans_avail, base->num_phy_chans);
2366
2367 /* Verify settings extended vs standard */
2368 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2369
2370 for (i = 0; i < base->num_phy_chans; i++) {
2371
2372 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2373 (val[0] & 0x3) != 1)
2374 dev_info(base->dev,
2375 "[%s] INFO: channel %d is misconfigured (%d)\n",
2376 __func__, i, val[0] & 0x3);
2377
2378 val[0] = val[0] >> 2;
2379 }
2380
2381 return num_phy_chans_avail;
2382}
2383
2384static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2385{
2386 static const struct d40_reg_val dma_id_regs[] = {
2387 /* Peripheral Id */
2388 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2389 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2390 /*
2391 * D40_DREG_PERIPHID2 Depends on HW revision:
4d594900 2392 * DB8500ed has 0x0008,
8d318a50 2393 * ? has 0x0018,
4d594900
RV		 2394 * DB8500v1 has 0x0028
2395 * DB8500v2 has 0x0038
8d318a50
LW		 2396 */
2397 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2398
2399 /* PCell Id */
2400 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2401 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2402 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2403 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2404 };
2405 struct stedma40_platform_data *plat_data;
2406 struct clk *clk = NULL;
2407 void __iomem *virtbase = NULL;
2408 struct resource *res = NULL;
2409 struct d40_base *base = NULL;
2410 int num_log_chans = 0;
2411 int num_phy_chans;
2412 int i;
f4185592 2413 u32 val;
3ae0267f 2414 u32 rev;
8d318a50
LW		 2415
2416 clk = clk_get(&pdev->dev, NULL);
2417
2418 if (IS_ERR(clk)) {
6db5a8ba 2419 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 2420 goto failure;
2421 }
2422
2423 clk_enable(clk);
2424
2425 /* Get IO for DMAC base address */
2426 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2427 if (!res)
2428 goto failure;
2429
2430 if (request_mem_region(res->start, resource_size(res),
2431 D40_NAME " I/O base") == NULL)
2432 goto failure;
2433
2434 virtbase = ioremap(res->start, resource_size(res));
2435 if (!virtbase)
2436 goto failure;
2437
2438 /* HW version check */
2439 for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2440 if (dma_id_regs[i].val !=
2441 readl(virtbase + dma_id_regs[i].reg)) {
6db5a8ba
RV		 2442 d40_err(&pdev->dev,
2443 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
8d318a50
LW		 2444 dma_id_regs[i].val,
2445 dma_id_regs[i].reg,
2446 readl(virtbase + dma_id_regs[i].reg));
2447 goto failure;
2448 }
2449 }
2450
3ae0267f 2451 /* Get silicon revision and designer */
f4185592 2452 val = readl(virtbase + D40_DREG_PERIPHID2);
8d318a50 2453
3ae0267f
JA		 2454 if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2455 D40_HW_DESIGNER) {
6db5a8ba
RV		 2456 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
2457 val & D40_DREG_PERIPHID2_DESIGNER_MASK,
3ae0267f 2458 D40_HW_DESIGNER);
8d318a50
LW		 2459 goto failure;
2460 }
2461
3ae0267f
JA		 2462 rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2463 D40_DREG_PERIPHID2_REV_POS;
2464
8d318a50
LW		 2465 /* The number of physical channels on this HW */
2466 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2467
2468 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
3ae0267f 2469 rev, res->start);
8d318a50
LW		 2470
2471 plat_data = pdev->dev.platform_data;
2472
2473 /* Count the number of logical channels in use */
2474 for (i = 0; i < plat_data->dev_len; i++)
2475 if (plat_data->dev_rx[i] != 0)
2476 num_log_chans++;
2477
2478 for (i = 0; i < plat_data->dev_len; i++)
2479 if (plat_data->dev_tx[i] != 0)
2480 num_log_chans++;
2481
2482 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2483 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2484 sizeof(struct d40_chan), GFP_KERNEL);
2485
2486 if (base == NULL) {
6db5a8ba 2487 d40_err(&pdev->dev, "Out of memory\n");
8d318a50
LW		 2488 goto failure;
2489 }
2490
3ae0267f 2491 base->rev = rev;
8d318a50
LW		 2492 base->clk = clk;
2493 base->num_phy_chans = num_phy_chans;
2494 base->num_log_chans = num_log_chans;
2495 base->phy_start = res->start;
2496 base->phy_size = resource_size(res);
2497 base->virtbase = virtbase;
2498 base->plat_data = plat_data;
2499 base->dev = &pdev->dev;
2500 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2501 base->log_chans = &base->phy_chans[num_phy_chans];
2502
2503 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2504 GFP_KERNEL);
2505 if (!base->phy_res)
2506 goto failure;
2507
2508 base->lookup_phy_chans = kzalloc(num_phy_chans *
2509 sizeof(struct d40_chan *),
2510 GFP_KERNEL);
2511 if (!base->lookup_phy_chans)
2512 goto failure;
2513
2514 if (num_log_chans + plat_data->memcpy_len) {
2515 /*
2516 * The max number of logical channels are event lines for all
2517 * src devices and dst devices
2518 */
2519 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2520 sizeof(struct d40_chan *),
2521 GFP_KERNEL);
2522 if (!base->lookup_log_chans)
2523 goto failure;
2524 }
698e4732
JA		 2525
2526 base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
2527 sizeof(struct d40_desc *) *
2528 D40_LCLA_LINK_PER_EVENT_GRP,
8d318a50
LW		 2529 GFP_KERNEL);
2530 if (!base->lcla_pool.alloc_map)
2531 goto failure;
2532
c675b1b4
JA		 2533 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2534 0, SLAB_HWCACHE_ALIGN,
2535 NULL);
2536 if (base->desc_slab == NULL)
2537 goto failure;
2538
8d318a50
LW		 2539 return base;
2540
2541failure:
c6134c96 2542 if (!IS_ERR(clk)) {
8d318a50
LW		 2543 clk_disable(clk);
2544 clk_put(clk);
2545 }
2546 if (virtbase)
2547 iounmap(virtbase);
2548 if (res)
2549 release_mem_region(res->start,
2550 resource_size(res));
2551 if (virtbase)
2552 iounmap(virtbase);
2553
2554 if (base) {
2555 kfree(base->lcla_pool.alloc_map);
2556 kfree(base->lookup_log_chans);
2557 kfree(base->lookup_phy_chans);
2558 kfree(base->phy_res);
2559 kfree(base);
2560 }
2561
2562 return NULL;
2563}
2564
2565static void __init d40_hw_init(struct d40_base *base)
2566{
2567
2568 static const struct d40_reg_val dma_init_reg[] = {
2569 /* Clock every part of the DMA block from start */
2570 { .reg = D40_DREG_GCC, .val = 0x0000ff01},
2571
2572 /* Interrupts on all logical channels */
2573 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2574 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2575 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2576 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2577 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2578 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2579 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2580 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2581 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2582 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2583 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2584 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2585 };
2586 int i;
2587 u32 prmseo[2] = {0, 0};
2588 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2589 u32 pcmis = 0;
2590 u32 pcicr = 0;
2591
2592 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2593 writel(dma_init_reg[i].val,
2594 base->virtbase + dma_init_reg[i].reg);
2595
2596 /* Configure all our dma channels to default settings */
2597 for (i = 0; i < base->num_phy_chans; i++) {
2598
2599 activeo[i % 2] = activeo[i % 2] << 2;
2600
2601 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2602 == D40_ALLOC_PHY) {
2603 activeo[i % 2] |= 3;
2604 continue;
2605 }
2606
2607 /* Enable interrupt # */
2608 pcmis = (pcmis << 1) | 1;
2609
2610 /* Clear interrupt # */
2611 pcicr = (pcicr << 1) | 1;
2612
2613 /* Set channel to physical mode */
2614 prmseo[i % 2] = prmseo[i % 2] << 2;
2615 prmseo[i % 2] |= 1;
2616
2617 }
2618
2619 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2620 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2621 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2622 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2623
2624 /* Write which interrupt to enable */
2625 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2626
2627 /* Write which interrupt to clear */
2628 writel(pcicr, base->virtbase + D40_DREG_PCICR);
2629
2630}
2631
508849ad
LW		 2632static int __init d40_lcla_allocate(struct d40_base *base)
2633{
026cbc42 2634 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 2635 unsigned long *page_list;
2636 int i, j;
2637 int ret = 0;
2638
2639 /*
2640 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2641 * To full fill this hardware requirement without wasting 256 kb
2642 * we allocate pages until we get an aligned one.
2643 */
2644 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2645 GFP_KERNEL);
2646
2647 if (!page_list) {
2648 ret = -ENOMEM;
2649 goto failure;
2650 }
2651
2652 /* Calculating how many pages that are required */
2653 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2654
2655 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2656 page_list[i] = __get_free_pages(GFP_KERNEL,
2657 base->lcla_pool.pages);
2658 if (!page_list[i]) {
2659
6db5a8ba
RV		 2660 d40_err(base->dev, "Failed to allocate %d pages.\n",
2661 base->lcla_pool.pages);
508849ad
LW		 2662
2663 for (j = 0; j < i; j++)
2664 free_pages(page_list[j], base->lcla_pool.pages);
2665 goto failure;
2666 }
2667
2668 if ((virt_to_phys((void *)page_list[i]) &
2669 (LCLA_ALIGNMENT - 1)) == 0)
2670 break;
2671 }
2672
2673 for (j = 0; j < i; j++)
2674 free_pages(page_list[j], base->lcla_pool.pages);
2675
2676 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2677 base->lcla_pool.base = (void *)page_list[i];
2678 } else {
767a9675
JA		 2679 /*
2680 * After many attempts and no succees with finding the correct
2681 * alignment, try with allocating a big buffer.
2682 */
508849ad
LW		 2683 dev_warn(base->dev,
2684 "[%s] Failed to get %d pages @ 18 bit align.\n",
2685 __func__, base->lcla_pool.pages);
2686 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2687 base->num_phy_chans +
2688 LCLA_ALIGNMENT,
2689 GFP_KERNEL);
2690 if (!base->lcla_pool.base_unaligned) {
2691 ret = -ENOMEM;
2692 goto failure;
2693 }
2694
2695 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2696 LCLA_ALIGNMENT);
2697 }
2698
026cbc42
RV		 2699 pool->dma_addr = dma_map_single(base->dev, pool->base,
2700 SZ_1K * base->num_phy_chans,
2701 DMA_TO_DEVICE);
2702 if (dma_mapping_error(base->dev, pool->dma_addr)) {
2703 pool->dma_addr = 0;
2704 ret = -ENOMEM;
2705 goto failure;
2706 }
2707
508849ad
LW		 2708 writel(virt_to_phys(base->lcla_pool.base),
2709 base->virtbase + D40_DREG_LCLA);
2710failure:
2711 kfree(page_list);
2712 return ret;
2713}
2714
8d318a50
LW		 2715static int __init d40_probe(struct platform_device *pdev)
2716{
2717 int err;
2718 int ret = -ENOENT;
2719 struct d40_base *base;
2720 struct resource *res = NULL;
2721 int num_reserved_chans;
2722 u32 val;
2723
2724 base = d40_hw_detect_init(pdev);
2725
2726 if (!base)
2727 goto failure;
2728
2729 num_reserved_chans = d40_phy_res_init(base);
2730
2731 platform_set_drvdata(pdev, base);
2732
2733 spin_lock_init(&base->interrupt_lock);
2734 spin_lock_init(&base->execmd_lock);
2735
2736 /* Get IO for logical channel parameter address */
2737 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2738 if (!res) {
2739 ret = -ENOENT;
6db5a8ba 2740 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 2741 goto failure;
2742 }
2743 base->lcpa_size = resource_size(res);
2744 base->phy_lcpa = res->start;
2745
2746 if (request_mem_region(res->start, resource_size(res),
2747 D40_NAME " I/O lcpa") == NULL) {
2748 ret = -EBUSY;
6db5a8ba
RV		 2749 d40_err(&pdev->dev,
2750 "Failed to request LCPA region 0x%x-0x%x\n",
2751 res->start, res->end);
8d318a50
LW		 2752 goto failure;
2753 }
2754
2755 /* We make use of ESRAM memory for this. */
2756 val = readl(base->virtbase + D40_DREG_LCPA);
2757 if (res->start != val && val != 0) {
2758 dev_warn(&pdev->dev,
2759 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2760 __func__, val, res->start);
2761 } else
2762 writel(res->start, base->virtbase + D40_DREG_LCPA);
2763
2764 base->lcpa_base = ioremap(res->start, resource_size(res));
2765 if (!base->lcpa_base) {
2766 ret = -ENOMEM;
6db5a8ba 2767 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 2768 goto failure;
2769 }
8d318a50 2770
508849ad
LW		 2771 ret = d40_lcla_allocate(base);
2772 if (ret) {
6db5a8ba 2773 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
8d318a50
LW		 2774 goto failure;
2775 }
2776
2777 spin_lock_init(&base->lcla_pool.lock);
2778
8d318a50
LW		 2779 base->irq = platform_get_irq(pdev, 0);
2780
2781 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 2782 if (ret) {
6db5a8ba 2783 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 2784 goto failure;
2785 }
2786
2787 err = d40_dmaengine_init(base, num_reserved_chans);
2788 if (err)
2789 goto failure;
2790
2791 d40_hw_init(base);
2792
2793 dev_info(base->dev, "initialized\n");
2794 return 0;
2795
2796failure:
2797 if (base) {
c675b1b4
JA		 2798 if (base->desc_slab)
2799 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 2800 if (base->virtbase)
2801 iounmap(base->virtbase);
026cbc42
RV		 2802
2803 if (base->lcla_pool.dma_addr)
2804 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
2805 SZ_1K * base->num_phy_chans,
2806 DMA_TO_DEVICE);
2807
508849ad
LW		 2808 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2809 free_pages((unsigned long)base->lcla_pool.base,
2810 base->lcla_pool.pages);
767a9675
JA		 2811
2812 kfree(base->lcla_pool.base_unaligned);
2813
8d318a50
LW		 2814 if (base->phy_lcpa)
2815 release_mem_region(base->phy_lcpa,
2816 base->lcpa_size);
2817 if (base->phy_start)
2818 release_mem_region(base->phy_start,
2819 base->phy_size);
2820 if (base->clk) {
2821 clk_disable(base->clk);
2822 clk_put(base->clk);
2823 }
2824
2825 kfree(base->lcla_pool.alloc_map);
2826 kfree(base->lookup_log_chans);
2827 kfree(base->lookup_phy_chans);
2828 kfree(base->phy_res);
2829 kfree(base);
2830 }
2831
6db5a8ba 2832 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 2833 return ret;
2834}
2835
2836static struct platform_driver d40_driver = {
2837 .driver = {
2838 .owner = THIS_MODULE,
2839 .name = D40_NAME,
2840 },
2841};
2842
cb9ab2d8 2843static int __init stedma40_init(void)
8d318a50
LW		 2844{
2845 return platform_driver_probe(&d40_driver, d40_probe);
2846}
2847arch_initcall(stedma40_init);
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