]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/dma/stm32-dma.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
dmaengine: stm32-dma: check FIFO error interrupt enable
[mirror_ubuntu-hirsute-kernel.git] / drivers / dma / stm32-dma.c
CommitLineData
d8b46839
CM		 1/*
2 * Driver for STM32 DMA controller
3 *
4 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
5 *
6 * Copyright (C) M'boumba Cedric Madianga 2015
7 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
a2b6103b 8 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
d8b46839
CM		 9 *
10 * License terms: GNU General Public License (GPL), version 2
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dmaengine.h>
16#include <linux/dma-mapping.h>
17#include <linux/err.h>
18#include <linux/init.h>
19#include <linux/jiffies.h>
20#include <linux/list.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_dma.h>
25#include <linux/platform_device.h>
26#include <linux/reset.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29
30#include "virt-dma.h"
31
32#define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */
33#define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */
34#define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */
35#define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */
36#define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */
c2d86b1c 37#define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */
d8b46839
CM		 38#define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
39#define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
40#define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
9df3bd55
PYM		 41#define STM32_DMA_MASKI (STM32_DMA_TCI \
42 | STM32_DMA_TEI \
43 | STM32_DMA_DMEI \
44 | STM32_DMA_FEI)
d8b46839
CM		 45
46/* DMA Stream x Configuration Register */
47#define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
48#define STM32_DMA_SCR_REQ(n) ((n & 0x7) << 25)
49#define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23)
50#define STM32_DMA_SCR_MBURST(n) ((n & 0x3) << 23)
51#define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21)
52#define STM32_DMA_SCR_PBURST(n) ((n & 0x3) << 21)
53#define STM32_DMA_SCR_PL_MASK GENMASK(17, 16)
54#define STM32_DMA_SCR_PL(n) ((n & 0x3) << 16)
55#define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13)
56#define STM32_DMA_SCR_MSIZE(n) ((n & 0x3) << 13)
57#define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11)
58#define STM32_DMA_SCR_PSIZE(n) ((n & 0x3) << 11)
59#define STM32_DMA_SCR_PSIZE_GET(n) ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)
60#define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6)
61#define STM32_DMA_SCR_DIR(n) ((n & 0x3) << 6)
62#define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */
63#define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */
64#define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */
65#define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */
66#define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */
67#define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */
68#define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */
249d5531
PYM		 69#define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable
70 */
d8b46839
CM		 71#define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */
72#define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */
73#define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */
74#define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \
75 | STM32_DMA_SCR_MINC \
76 | STM32_DMA_SCR_PINCOS \
77 | STM32_DMA_SCR_PL_MASK)
78#define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \
79 | STM32_DMA_SCR_TEIE \
80 | STM32_DMA_SCR_DMEIE)
81
82/* DMA Stream x number of data register */
83#define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x))
84
85/* DMA stream peripheral address register */
86#define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x))
87
88/* DMA stream x memory 0 address register */
89#define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x))
90
91/* DMA stream x memory 1 address register */
92#define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x))
93
94/* DMA stream x FIFO control register */
95#define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x))
96#define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0)
97#define STM32_DMA_SFCR_FTH(n) (n & STM32_DMA_SFCR_FTH_MASK)
98#define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */
99#define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */
100#define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \
101 | STM32_DMA_SFCR_DMDIS)
102
103/* DMA direction */
104#define STM32_DMA_DEV_TO_MEM 0x00
105#define STM32_DMA_MEM_TO_DEV 0x01
106#define STM32_DMA_MEM_TO_MEM 0x02
107
108/* DMA priority level */
109#define STM32_DMA_PRIORITY_LOW 0x00
110#define STM32_DMA_PRIORITY_MEDIUM 0x01
111#define STM32_DMA_PRIORITY_HIGH 0x02
112#define STM32_DMA_PRIORITY_VERY_HIGH 0x03
113
114/* DMA FIFO threshold selection */
115#define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00
116#define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01
117#define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02
118#define STM32_DMA_FIFO_THRESHOLD_FULL 0x03
119
120#define STM32_DMA_MAX_DATA_ITEMS 0xffff
80a76952
PYM		 121/*
122 * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
123 * gather at boundary. Thus it's safer to round down this value on FIFO
124 * size (16 Bytes)
125 */
126#define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \
127 ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
d8b46839
CM		 128#define STM32_DMA_MAX_CHANNELS 0x08
129#define STM32_DMA_MAX_REQUEST_ID 0x08
130#define STM32_DMA_MAX_DATA_PARAM 0x03
a2b6103b
PYM		 131#define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */
132#define STM32_DMA_MIN_BURST 4
276b0046 133#define STM32_DMA_MAX_BURST 16
d8b46839 134
951f44cb
PYM		 135/* DMA Features */
136#define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0)
137#define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
138
d8b46839
CM		 139enum stm32_dma_width {
140 STM32_DMA_BYTE,
141 STM32_DMA_HALF_WORD,
142 STM32_DMA_WORD,
143};
144
145enum stm32_dma_burst_size {
146 STM32_DMA_BURST_SINGLE,
147 STM32_DMA_BURST_INCR4,
148 STM32_DMA_BURST_INCR8,
149 STM32_DMA_BURST_INCR16,
150};
151
951f44cb
PYM		 152/**
153 * struct stm32_dma_cfg - STM32 DMA custom configuration
154 * @channel_id: channel ID
155 * @request_line: DMA request
156 * @stream_config: 32bit mask specifying the DMA channel configuration
157 * @features: 32bit mask specifying the DMA Feature list
158 */
d8b46839
CM		 159struct stm32_dma_cfg {
160 u32 channel_id;
161 u32 request_line;
162 u32 stream_config;
951f44cb 163 u32 features;
d8b46839
CM		 164};
165
166struct stm32_dma_chan_reg {
167 u32 dma_lisr;
168 u32 dma_hisr;
169 u32 dma_lifcr;
170 u32 dma_hifcr;
171 u32 dma_scr;
172 u32 dma_sndtr;
173 u32 dma_spar;
174 u32 dma_sm0ar;
175 u32 dma_sm1ar;
176 u32 dma_sfcr;
177};
178
179struct stm32_dma_sg_req {
180 u32 len;
181 struct stm32_dma_chan_reg chan_reg;
182};
183
184struct stm32_dma_desc {
185 struct virt_dma_desc vdesc;
186 bool cyclic;
187 u32 num_sgs;
188 struct stm32_dma_sg_req sg_req[];
189};
190
191struct stm32_dma_chan {
192 struct virt_dma_chan vchan;
193 bool config_init;
194 bool busy;
195 u32 id;
196 u32 irq;
197 struct stm32_dma_desc *desc;
198 u32 next_sg;
199 struct dma_slave_config dma_sconfig;
200 struct stm32_dma_chan_reg chan_reg;
951f44cb 201 u32 threshold;
a2b6103b
PYM		 202 u32 mem_burst;
203 u32 mem_width;
d8b46839
CM		 204};
205
206struct stm32_dma_device {
207 struct dma_device ddev;
208 void __iomem *base;
209 struct clk *clk;
210 struct reset_control *rst;
211 bool mem2mem;
212 struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];
213};
214
215static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)
216{
217 return container_of(chan->vchan.chan.device, struct stm32_dma_device,
218 ddev);
219}
220
221static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c)
222{
223 return container_of(c, struct stm32_dma_chan, vchan.chan);
224}
225
226static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc)
227{
228 return container_of(vdesc, struct stm32_dma_desc, vdesc);
229}
230
231static struct device *chan2dev(struct stm32_dma_chan *chan)
232{
233 return &chan->vchan.chan.dev->device;
234}
235
236static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
237{
238 return readl_relaxed(dmadev->base + reg);
239}
240
241static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
242{
243 writel_relaxed(val, dmadev->base + reg);
244}
245
246static struct stm32_dma_desc *stm32_dma_alloc_desc(u32 num_sgs)
247{
248 return kzalloc(sizeof(struct stm32_dma_desc) +
249 sizeof(struct stm32_dma_sg_req) * num_sgs, GFP_NOWAIT);
250}
251
252static int stm32_dma_get_width(struct stm32_dma_chan *chan,
253 enum dma_slave_buswidth width)
254{
255 switch (width) {
256 case DMA_SLAVE_BUSWIDTH_1_BYTE:
257 return STM32_DMA_BYTE;
258 case DMA_SLAVE_BUSWIDTH_2_BYTES:
259 return STM32_DMA_HALF_WORD;
260 case DMA_SLAVE_BUSWIDTH_4_BYTES:
261 return STM32_DMA_WORD;
262 default:
263 dev_err(chan2dev(chan), "Dma bus width not supported\n");
264 return -EINVAL;
265 }
266}
267
a2b6103b
PYM		 268static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len,
269 u32 threshold)
270{
271 enum dma_slave_buswidth max_width;
272
273 if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL)
274 max_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
275 else
276 max_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
277
278 while ((buf_len < max_width || buf_len % max_width) &&
279 max_width > DMA_SLAVE_BUSWIDTH_1_BYTE)
280 max_width = max_width >> 1;
281
282 return max_width;
283}
284
285static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold,
286 enum dma_slave_buswidth width)
287{
288 u32 remaining;
289
290 if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) {
291 if (burst != 0) {
292 /*
293 * If number of beats fit in several whole bursts
294 * this configuration is allowed.
295 */
296 remaining = ((STM32_DMA_FIFO_SIZE / width) *
297 (threshold + 1) / 4) % burst;
298
299 if (remaining == 0)
300 return true;
301 } else {
302 return true;
303 }
304 }
305
306 return false;
307}
308
309static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold)
310{
cc832dc8
PYM		 311 /*
312 * Buffer or period length has to be aligned on FIFO depth.
313 * Otherwise bytes may be stuck within FIFO at buffer or period
314 * length.
315 */
316 return ((buf_len % ((threshold + 1) * 4)) == 0);
a2b6103b
PYM		 317}
318
319static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold,
320 enum dma_slave_buswidth width)
321{
322 u32 best_burst = max_burst;
323
324 if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold))
325 return 0;
326
327 while ((buf_len < best_burst * width && best_burst > 1) ||
328 !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold,
329 width)) {
330 if (best_burst > STM32_DMA_MIN_BURST)
331 best_burst = best_burst >> 1;
332 else
333 best_burst = 0;
334 }
335
336 return best_burst;
337}
338
d8b46839
CM		 339static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
340{
341 switch (maxburst) {
342 case 0:
343 case 1:
344 return STM32_DMA_BURST_SINGLE;
345 case 4:
346 return STM32_DMA_BURST_INCR4;
347 case 8:
348 return STM32_DMA_BURST_INCR8;
349 case 16:
350 return STM32_DMA_BURST_INCR16;
351 default:
352 dev_err(chan2dev(chan), "Dma burst size not supported\n");
353 return -EINVAL;
354 }
355}
356
357static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,
a2b6103b 358 u32 src_burst, u32 dst_burst)
d8b46839
CM		 359{
360 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
361 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
362
a2b6103b 363 if (!src_burst && !dst_burst) {
d8b46839
CM		 364 /* Using direct mode */
365 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
366 } else {
367 /* Using FIFO mode */
368 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
369 }
370}
371
372static int stm32_dma_slave_config(struct dma_chan *c,
373 struct dma_slave_config *config)
374{
375 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
376
377 memcpy(&chan->dma_sconfig, config, sizeof(*config));
378
379 chan->config_init = true;
380
381 return 0;
382}
383
384static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
385{
386 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
387 u32 flags, dma_isr;
388
389 /*
390 * Read "flags" from DMA_xISR register corresponding to the selected
391 * DMA channel at the correct bit offset inside that register.
392 *
393 * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
394 * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
395 */
396
397 if (chan->id & 4)
398 dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR);
399 else
400 dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR);
401
402 flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
403
9df3bd55 404 return flags & STM32_DMA_MASKI;
d8b46839
CM		 405}
406
407static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
408{
409 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
410 u32 dma_ifcr;
411
412 /*
413 * Write "flags" to the DMA_xIFCR register corresponding to the selected
414 * DMA channel at the correct bit offset inside that register.
415 *
416 * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
417 * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
418 */
9df3bd55 419 flags &= STM32_DMA_MASKI;
d8b46839
CM		 420 dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
421
422 if (chan->id & 4)
423 stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr);
424 else
425 stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr);
426}
427
428static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)
429{
430 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
431 unsigned long timeout = jiffies + msecs_to_jiffies(5000);
432 u32 dma_scr, id;
433
434 id = chan->id;
435 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
436
437 if (dma_scr & STM32_DMA_SCR_EN) {
438 dma_scr &= ~STM32_DMA_SCR_EN;
439 stm32_dma_write(dmadev, STM32_DMA_SCR(id), dma_scr);
440
441 do {
442 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
443 dma_scr &= STM32_DMA_SCR_EN;
444 if (!dma_scr)
445 break;
446
447 if (time_after_eq(jiffies, timeout)) {
448 dev_err(chan2dev(chan), "%s: timeout!\n",
449 __func__);
450 return -EBUSY;
451 }
452 cond_resched();
453 } while (1);
454 }
455
456 return 0;
457}
458
459static void stm32_dma_stop(struct stm32_dma_chan *chan)
460{
461 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
462 u32 dma_scr, dma_sfcr, status;
463 int ret;
464
465 /* Disable interrupts */
466 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
467 dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;
468 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
469 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
470 dma_sfcr &= ~STM32_DMA_SFCR_FEIE;
471 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
472
473 /* Disable DMA */
474 ret = stm32_dma_disable_chan(chan);
475 if (ret < 0)
476 return;
477
478 /* Clear interrupt status if it is there */
479 status = stm32_dma_irq_status(chan);
480 if (status) {
481 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",
482 __func__, status);
483 stm32_dma_irq_clear(chan, status);
484 }
485
486 chan->busy = false;
487}
488
489static int stm32_dma_terminate_all(struct dma_chan *c)
490{
491 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
492 unsigned long flags;
493 LIST_HEAD(head);
494
495 spin_lock_irqsave(&chan->vchan.lock, flags);
496
497 if (chan->busy) {
498 stm32_dma_stop(chan);
499 chan->desc = NULL;
500 }
501
502 vchan_get_all_descriptors(&chan->vchan, &head);
503 spin_unlock_irqrestore(&chan->vchan.lock, flags);
504 vchan_dma_desc_free_list(&chan->vchan, &head);
505
506 return 0;
507}
508
dc808675
CM		 509static void stm32_dma_synchronize(struct dma_chan *c)
510{
511 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
512
513 vchan_synchronize(&chan->vchan);
514}
515
d8b46839
CM		 516static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
517{
518 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
519 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
520 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
521 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
522 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
523 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
524 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
525
526 dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr);
527 dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr);
528 dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar);
529 dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);
530 dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);
531 dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr);
532}
533
e57cb3b3
PYM		 534static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
535
8d1b76f0 536static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
d8b46839
CM		 537{
538 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
539 struct virt_dma_desc *vdesc;
540 struct stm32_dma_sg_req *sg_req;
541 struct stm32_dma_chan_reg *reg;
542 u32 status;
543 int ret;
544
545 ret = stm32_dma_disable_chan(chan);
546 if (ret < 0)
8d1b76f0 547 return;
d8b46839
CM		 548
549 if (!chan->desc) {
550 vdesc = vchan_next_desc(&chan->vchan);
551 if (!vdesc)
8d1b76f0 552 return;
d8b46839
CM		 553
554 chan->desc = to_stm32_dma_desc(vdesc);
555 chan->next_sg = 0;
556 }
557
558 if (chan->next_sg == chan->desc->num_sgs)
559 chan->next_sg = 0;
560
561 sg_req = &chan->desc->sg_req[chan->next_sg];
562 reg = &sg_req->chan_reg;
563
564 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
565 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
566 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
567 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
568 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
569 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
570
571 chan->next_sg++;
572
573 /* Clear interrupt status if it is there */
574 status = stm32_dma_irq_status(chan);
575 if (status)
576 stm32_dma_irq_clear(chan, status);
577
e57cb3b3
PYM		 578 if (chan->desc->cyclic)
579 stm32_dma_configure_next_sg(chan);
580
d8b46839
CM		 581 stm32_dma_dump_reg(chan);
582
583 /* Start DMA */
584 reg->dma_scr |= STM32_DMA_SCR_EN;
585 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
586
587 chan->busy = true;
588
90ec93cb 589 dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);
d8b46839
CM		 590}
591
592static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
593{
594 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
595 struct stm32_dma_sg_req *sg_req;
596 u32 dma_scr, dma_sm0ar, dma_sm1ar, id;
597
598 id = chan->id;
599 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
600
601 if (dma_scr & STM32_DMA_SCR_DBM) {
602 if (chan->next_sg == chan->desc->num_sgs)
603 chan->next_sg = 0;
604
605 sg_req = &chan->desc->sg_req[chan->next_sg];
606
607 if (dma_scr & STM32_DMA_SCR_CT) {
608 dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
609 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
610 dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
611 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
612 } else {
613 dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
614 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
615 dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
616 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
617 }
d8b46839
CM		 618 }
619}
620
621static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
622{
623 if (chan->desc) {
624 if (chan->desc->cyclic) {
625 vchan_cyclic_callback(&chan->desc->vdesc);
2b12c558 626 chan->next_sg++;
d8b46839
CM		 627 stm32_dma_configure_next_sg(chan);
628 } else {
629 chan->busy = false;
630 if (chan->next_sg == chan->desc->num_sgs) {
631 list_del(&chan->desc->vdesc.node);
632 vchan_cookie_complete(&chan->desc->vdesc);
633 chan->desc = NULL;
634 }
635 stm32_dma_start_transfer(chan);
636 }
637 }
638}
639
640static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
641{
642 struct stm32_dma_chan *chan = devid;
643 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
ca4c72c0 644 u32 status, scr, sfcr;
d8b46839
CM		 645
646 spin_lock(&chan->vchan.lock);
647
648 status = stm32_dma_irq_status(chan);
649 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
ca4c72c0 650 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
d8b46839 651
c2d86b1c 652 if (status & STM32_DMA_TCI) {
d8b46839 653 stm32_dma_irq_clear(chan, STM32_DMA_TCI);
c2d86b1c
PYM		 654 if (scr & STM32_DMA_SCR_TCIE)
655 stm32_dma_handle_chan_done(chan);
656 status &= ~STM32_DMA_TCI;
657 }
658 if (status & STM32_DMA_HTI) {
659 stm32_dma_irq_clear(chan, STM32_DMA_HTI);
660 status &= ~STM32_DMA_HTI;
661 }
662 if (status & STM32_DMA_FEI) {
663 stm32_dma_irq_clear(chan, STM32_DMA_FEI);
664 status &= ~STM32_DMA_FEI;
ca4c72c0
PYM		 665 if (sfcr & STM32_DMA_SFCR_FEIE) {
666 if (!(scr & STM32_DMA_SCR_EN))
667 dev_err(chan2dev(chan), "FIFO Error\n");
668 else
669 dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
670 }
c2d86b1c
PYM		 671 }
672 if (status) {
d8b46839
CM		 673 stm32_dma_irq_clear(chan, status);
674 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
c2d86b1c
PYM		 675 if (!(scr & STM32_DMA_SCR_EN))
676 dev_err(chan2dev(chan), "chan disabled by HW\n");
d8b46839
CM		 677 }
678
679 spin_unlock(&chan->vchan.lock);
680
681 return IRQ_HANDLED;
682}
683
684static void stm32_dma_issue_pending(struct dma_chan *c)
685{
686 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
687 unsigned long flags;
d8b46839
CM		 688
689 spin_lock_irqsave(&chan->vchan.lock, flags);
8d1b76f0 690 if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
90ec93cb 691 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);
8d1b76f0 692 stm32_dma_start_transfer(chan);
e57cb3b3 693
d8b46839
CM		 694 }
695 spin_unlock_irqrestore(&chan->vchan.lock, flags);
696}
697
698static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
699 enum dma_transfer_direction direction,
a2b6103b
PYM		 700 enum dma_slave_buswidth *buswidth,
701 u32 buf_len)
d8b46839
CM		 702{
703 enum dma_slave_buswidth src_addr_width, dst_addr_width;
704 int src_bus_width, dst_bus_width;
705 int src_burst_size, dst_burst_size;
a2b6103b
PYM		 706 u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
707 u32 dma_scr, threshold;
d8b46839
CM		 708
709 src_addr_width = chan->dma_sconfig.src_addr_width;
710 dst_addr_width = chan->dma_sconfig.dst_addr_width;
711 src_maxburst = chan->dma_sconfig.src_maxburst;
712 dst_maxburst = chan->dma_sconfig.dst_maxburst;
a2b6103b 713 threshold = chan->threshold;
d8b46839
CM		 714
715 switch (direction) {
716 case DMA_MEM_TO_DEV:
a2b6103b 717 /* Set device data size */
d8b46839
CM		 718 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
719 if (dst_bus_width < 0)
720 return dst_bus_width;
721
a2b6103b
PYM		 722 /* Set device burst size */
723 dst_best_burst = stm32_dma_get_best_burst(buf_len,
724 dst_maxburst,
725 threshold,
726 dst_addr_width);
727
728 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
d8b46839
CM		 729 if (dst_burst_size < 0)
730 return dst_burst_size;
731
a2b6103b
PYM		 732 /* Set memory data size */
733 src_addr_width = stm32_dma_get_max_width(buf_len, threshold);
734 chan->mem_width = src_addr_width;
d8b46839
CM		 735 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
736 if (src_bus_width < 0)
737 return src_bus_width;
738
a2b6103b
PYM		 739 /* Set memory burst size */
740 src_maxburst = STM32_DMA_MAX_BURST;
741 src_best_burst = stm32_dma_get_best_burst(buf_len,
742 src_maxburst,
743 threshold,
744 src_addr_width);
745 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
d8b46839
CM		 746 if (src_burst_size < 0)
747 return src_burst_size;
748
749 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) |
750 STM32_DMA_SCR_PSIZE(dst_bus_width) |
751 STM32_DMA_SCR_MSIZE(src_bus_width) |
752 STM32_DMA_SCR_PBURST(dst_burst_size) |
753 STM32_DMA_SCR_MBURST(src_burst_size);
754
a2b6103b
PYM		 755 /* Set FIFO threshold */
756 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
757 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
758
759 /* Set peripheral address */
d8b46839
CM		 760 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
761 *buswidth = dst_addr_width;
762 break;
763
764 case DMA_DEV_TO_MEM:
a2b6103b 765 /* Set device data size */
d8b46839
CM		 766 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
767 if (src_bus_width < 0)
768 return src_bus_width;
769
a2b6103b
PYM		 770 /* Set device burst size */
771 src_best_burst = stm32_dma_get_best_burst(buf_len,
772 src_maxburst,
773 threshold,
774 src_addr_width);
775 chan->mem_burst = src_best_burst;
776 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
d8b46839
CM		 777 if (src_burst_size < 0)
778 return src_burst_size;
779
a2b6103b
PYM		 780 /* Set memory data size */
781 dst_addr_width = stm32_dma_get_max_width(buf_len, threshold);
782 chan->mem_width = dst_addr_width;
d8b46839
CM		 783 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
784 if (dst_bus_width < 0)
785 return dst_bus_width;
786
a2b6103b
PYM		 787 /* Set memory burst size */
788 dst_maxburst = STM32_DMA_MAX_BURST;
789 dst_best_burst = stm32_dma_get_best_burst(buf_len,
790 dst_maxburst,
791 threshold,
792 dst_addr_width);
793 chan->mem_burst = dst_best_burst;
794 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
d8b46839
CM		 795 if (dst_burst_size < 0)
796 return dst_burst_size;
797
798 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) |
799 STM32_DMA_SCR_PSIZE(src_bus_width) |
800 STM32_DMA_SCR_MSIZE(dst_bus_width) |
801 STM32_DMA_SCR_PBURST(src_burst_size) |
802 STM32_DMA_SCR_MBURST(dst_burst_size);
803
a2b6103b
PYM		 804 /* Set FIFO threshold */
805 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
806 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
807
808 /* Set peripheral address */
d8b46839
CM		 809 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
810 *buswidth = chan->dma_sconfig.src_addr_width;
811 break;
812
813 default:
814 dev_err(chan2dev(chan), "Dma direction is not supported\n");
815 return -EINVAL;
816 }
817
a2b6103b 818 stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst);
d8b46839 819
a2b6103b 820 /* Set DMA control register */
d8b46839
CM		 821 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
822 STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK |
823 STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK);
824 chan->chan_reg.dma_scr |= dma_scr;
825
826 return 0;
827}
828
829static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs)
830{
831 memset(regs, 0, sizeof(struct stm32_dma_chan_reg));
832}
833
834static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
835 struct dma_chan *c, struct scatterlist *sgl,
836 u32 sg_len, enum dma_transfer_direction direction,
837 unsigned long flags, void *context)
838{
839 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
840 struct stm32_dma_desc *desc;
841 struct scatterlist *sg;
842 enum dma_slave_buswidth buswidth;
843 u32 nb_data_items;
844 int i, ret;
845
846 if (!chan->config_init) {
847 dev_err(chan2dev(chan), "dma channel is not configured\n");
848 return NULL;
849 }
850
851 if (sg_len < 1) {
852 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);
853 return NULL;
854 }
855
856 desc = stm32_dma_alloc_desc(sg_len);
857 if (!desc)
858 return NULL;
859
d8b46839
CM		 860 /* Set peripheral flow controller */
861 if (chan->dma_sconfig.device_fc)
862 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
863 else
864 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
865
866 for_each_sg(sgl, sg, sg_len, i) {
a2b6103b
PYM		 867 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
868 sg_dma_len(sg));
869 if (ret < 0)
870 goto err;
871
d8b46839
CM		 872 desc->sg_req[i].len = sg_dma_len(sg);
873
874 nb_data_items = desc->sg_req[i].len / buswidth;
80a76952 875 if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
d8b46839
CM		 876 dev_err(chan2dev(chan), "nb items not supported\n");
877 goto err;
878 }
879
880 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
881 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
882 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
883 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
884 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
885 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
886 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
887 }
888
889 desc->num_sgs = sg_len;
890 desc->cyclic = false;
891
892 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
893
894err:
895 kfree(desc);
896 return NULL;
897}
898
899static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
900 struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
901 size_t period_len, enum dma_transfer_direction direction,
902 unsigned long flags)
903{
904 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
905 struct stm32_dma_desc *desc;
906 enum dma_slave_buswidth buswidth;
907 u32 num_periods, nb_data_items;
908 int i, ret;
909
910 if (!buf_len || !period_len) {
911 dev_err(chan2dev(chan), "Invalid buffer/period len\n");
912 return NULL;
913 }
914
915 if (!chan->config_init) {
916 dev_err(chan2dev(chan), "dma channel is not configured\n");
917 return NULL;
918 }
919
920 if (buf_len % period_len) {
921 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");
922 return NULL;
923 }
924
925 /*
926 * We allow to take more number of requests till DMA is
927 * not started. The driver will loop over all requests.
928 * Once DMA is started then new requests can be queued only after
929 * terminating the DMA.
930 */
931 if (chan->busy) {
932 dev_err(chan2dev(chan), "Request not allowed when dma busy\n");
933 return NULL;
934 }
935
a2b6103b 936 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len);
d8b46839
CM		 937 if (ret < 0)
938 return NULL;
939
940 nb_data_items = period_len / buswidth;
80a76952 941 if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
d8b46839
CM		 942 dev_err(chan2dev(chan), "number of items not supported\n");
943 return NULL;
944 }
945
946 /* Enable Circular mode or double buffer mode */
947 if (buf_len == period_len)
948 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
949 else
950 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
951
952 /* Clear periph ctrl if client set it */
953 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
954
955 num_periods = buf_len / period_len;
956
957 desc = stm32_dma_alloc_desc(num_periods);
958 if (!desc)
959 return NULL;
960
961 for (i = 0; i < num_periods; i++) {
962 desc->sg_req[i].len = period_len;
963
964 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
965 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
966 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
967 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
968 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
969 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
970 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
971 buf_addr += period_len;
972 }
973
974 desc->num_sgs = num_periods;
975 desc->cyclic = true;
976
977 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
978}
979
980static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
981 struct dma_chan *c, dma_addr_t dest,
982 dma_addr_t src, size_t len, unsigned long flags)
983{
984 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
a2b6103b 985 enum dma_slave_buswidth max_width;
d8b46839
CM		 986 struct stm32_dma_desc *desc;
987 size_t xfer_count, offset;
a2b6103b 988 u32 num_sgs, best_burst, dma_burst, threshold;
d8b46839
CM		 989 int i;
990
80a76952 991 num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
d8b46839
CM		 992 desc = stm32_dma_alloc_desc(num_sgs);
993 if (!desc)
994 return NULL;
995
a2b6103b
PYM		 996 threshold = chan->threshold;
997
d8b46839
CM		 998 for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
999 xfer_count = min_t(size_t, len - offset,
80a76952 1000 STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
d8b46839 1001
a2b6103b
PYM		 1002 /* Compute best burst size */
1003 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1004 best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,
1005 threshold, max_width);
1006 dma_burst = stm32_dma_get_burst(chan, best_burst);
d8b46839
CM		 1007
1008 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1009 desc->sg_req[i].chan_reg.dma_scr =
1010 STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) |
a2b6103b
PYM		 1011 STM32_DMA_SCR_PBURST(dma_burst) |
1012 STM32_DMA_SCR_MBURST(dma_burst) |
d8b46839
CM		 1013 STM32_DMA_SCR_MINC |
1014 STM32_DMA_SCR_PINC |
1015 STM32_DMA_SCR_TCIE |
1016 STM32_DMA_SCR_TEIE;
a2b6103b
PYM		 1017 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
1018 desc->sg_req[i].chan_reg.dma_sfcr |=
1019 STM32_DMA_SFCR_FTH(threshold);
d8b46839
CM		 1020 desc->sg_req[i].chan_reg.dma_spar = src + offset;
1021 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
1022 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
a2b6103b 1023 desc->sg_req[i].len = xfer_count;
d8b46839
CM		 1024 }
1025
1026 desc->num_sgs = num_sgs;
1027 desc->cyclic = false;
1028
1029 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1030}
1031
2b12c558
CM		 1032static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
1033{
1034 u32 dma_scr, width, ndtr;
1035 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1036
1037 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
1038 width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
1039 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
1040
1041 return ndtr << width;
1042}
1043
d8b46839
CM		 1044static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
1045 struct stm32_dma_desc *desc,
1046 u32 next_sg)
1047{
a2b6103b 1048 u32 modulo, burst_size;
2b12c558 1049 u32 residue = 0;
d8b46839
CM		 1050 int i;
1051
2b12c558
CM		 1052 /*
1053 * In cyclic mode, for the last period, residue = remaining bytes from
1054 * NDTR
1055 */
a2b6103b
PYM		 1056 if (chan->desc->cyclic && next_sg == 0) {
1057 residue = stm32_dma_get_remaining_bytes(chan);
1058 goto end;
1059 }
d8b46839 1060
2b12c558
CM		 1061 /*
1062 * For all other periods in cyclic mode, and in sg mode,
1063 * residue = remaining bytes from NDTR + remaining periods/sg to be
1064 * transferred
1065 */
d8b46839
CM		 1066 for (i = next_sg; i < desc->num_sgs; i++)
1067 residue += desc->sg_req[i].len;
2b12c558 1068 residue += stm32_dma_get_remaining_bytes(chan);
d8b46839 1069
a2b6103b
PYM		 1070end:
1071 if (!chan->mem_burst)
1072 return residue;
1073
1074 burst_size = chan->mem_burst * chan->mem_width;
1075 modulo = residue % burst_size;
1076 if (modulo)
1077 residue = residue - modulo + burst_size;
1078
d8b46839
CM		 1079 return residue;
1080}
1081
1082static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
1083 dma_cookie_t cookie,
1084 struct dma_tx_state *state)
1085{
1086 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1087 struct virt_dma_desc *vdesc;
1088 enum dma_status status;
1089 unsigned long flags;
57b5a321 1090 u32 residue = 0;
d8b46839
CM		 1091
1092 status = dma_cookie_status(c, cookie, state);
249d5531 1093 if (status == DMA_COMPLETE || !state)
d8b46839
CM		 1094 return status;
1095
1096 spin_lock_irqsave(&chan->vchan.lock, flags);
1097 vdesc = vchan_find_desc(&chan->vchan, cookie);
57b5a321 1098 if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
d8b46839
CM		 1099 residue = stm32_dma_desc_residue(chan, chan->desc,
1100 chan->next_sg);
57b5a321 1101 else if (vdesc)
d8b46839
CM		 1102 residue = stm32_dma_desc_residue(chan,
1103 to_stm32_dma_desc(vdesc), 0);
d8b46839
CM		 1104 dma_set_residue(state, residue);
1105
1106 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1107
1108 return status;
1109}
1110
1111static int stm32_dma_alloc_chan_resources(struct dma_chan *c)
1112{
1113 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1114 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1115 int ret;
1116
1117 chan->config_init = false;
1118 ret = clk_prepare_enable(dmadev->clk);
1119 if (ret < 0) {
1120 dev_err(chan2dev(chan), "clk_prepare_enable failed: %d\n", ret);
1121 return ret;
1122 }
1123
1124 ret = stm32_dma_disable_chan(chan);
1125 if (ret < 0)
1126 clk_disable_unprepare(dmadev->clk);
1127
1128 return ret;
1129}
1130
1131static void stm32_dma_free_chan_resources(struct dma_chan *c)
1132{
1133 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1134 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1135 unsigned long flags;
1136
1137 dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);
1138
1139 if (chan->busy) {
1140 spin_lock_irqsave(&chan->vchan.lock, flags);
1141 stm32_dma_stop(chan);
1142 chan->desc = NULL;
1143 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1144 }
1145
1146 clk_disable_unprepare(dmadev->clk);
1147
1148 vchan_free_chan_resources(to_virt_chan(c));
1149}
1150
1151static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
1152{
1153 kfree(container_of(vdesc, struct stm32_dma_desc, vdesc));
1154}
1155
e97adb49 1156static void stm32_dma_set_config(struct stm32_dma_chan *chan,
249d5531 1157 struct stm32_dma_cfg *cfg)
d8b46839
CM		 1158{
1159 stm32_dma_clear_reg(&chan->chan_reg);
1160
1161 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
1162 chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);
1163
1164 /* Enable Interrupts */
1165 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
1166
951f44cb 1167 chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
d8b46839
CM		 1168}
1169
1170static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
1171 struct of_dma *ofdma)
1172{
1173 struct stm32_dma_device *dmadev = ofdma->of_dma_data;
5df4eb45 1174 struct device *dev = dmadev->ddev.dev;
d8b46839
CM		 1175 struct stm32_dma_cfg cfg;
1176 struct stm32_dma_chan *chan;
1177 struct dma_chan *c;
1178
5df4eb45
CM		 1179 if (dma_spec->args_count < 4) {
1180 dev_err(dev, "Bad number of cells\n");
d8b46839 1181 return NULL;
5df4eb45 1182 }
d8b46839
CM		 1183
1184 cfg.channel_id = dma_spec->args[0];
1185 cfg.request_line = dma_spec->args[1];
1186 cfg.stream_config = dma_spec->args[2];
951f44cb 1187 cfg.features = dma_spec->args[3];
d8b46839 1188
249d5531
PYM		 1189 if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS ||
1190 cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) {
5df4eb45 1191 dev_err(dev, "Bad channel and/or request id\n");
d8b46839 1192 return NULL;
5df4eb45 1193 }
d8b46839 1194
d8b46839
CM		 1195 chan = &dmadev->chan[cfg.channel_id];
1196
1197 c = dma_get_slave_channel(&chan->vchan.chan);
5df4eb45 1198 if (!c) {
041cf7e0 1199 dev_err(dev, "No more channels available\n");
5df4eb45
CM		 1200 return NULL;
1201 }
1202
1203 stm32_dma_set_config(chan, &cfg);
d8b46839
CM		 1204
1205 return c;
1206}
1207
1208static const struct of_device_id stm32_dma_of_match[] = {
1209 { .compatible = "st,stm32-dma", },
1210 { /* sentinel */ },
1211};
1212MODULE_DEVICE_TABLE(of, stm32_dma_of_match);
1213
1214static int stm32_dma_probe(struct platform_device *pdev)
1215{
1216 struct stm32_dma_chan *chan;
1217 struct stm32_dma_device *dmadev;
1218 struct dma_device *dd;
1219 const struct of_device_id *match;
1220 struct resource *res;
1221 int i, ret;
1222
1223 match = of_match_device(stm32_dma_of_match, &pdev->dev);
1224 if (!match) {
1225 dev_err(&pdev->dev, "Error: No device match found\n");
1226 return -ENODEV;
1227 }
1228
1229 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
1230 if (!dmadev)
1231 return -ENOMEM;
1232
1233 dd = &dmadev->ddev;
1234
1235 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1236 dmadev->base = devm_ioremap_resource(&pdev->dev, res);
1237 if (IS_ERR(dmadev->base))
1238 return PTR_ERR(dmadev->base);
1239
1240 dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1241 if (IS_ERR(dmadev->clk)) {
1242 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1243 return PTR_ERR(dmadev->clk);
1244 }
1245
1246 dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
1247 "st,mem2mem");
1248
1249 dmadev->rst = devm_reset_control_get(&pdev->dev, NULL);
1250 if (!IS_ERR(dmadev->rst)) {
1251 reset_control_assert(dmadev->rst);
1252 udelay(2);
1253 reset_control_deassert(dmadev->rst);
1254 }
1255
1256 dma_cap_set(DMA_SLAVE, dd->cap_mask);
1257 dma_cap_set(DMA_PRIVATE, dd->cap_mask);
1258 dma_cap_set(DMA_CYCLIC, dd->cap_mask);
1259 dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources;
1260 dd->device_free_chan_resources = stm32_dma_free_chan_resources;
1261 dd->device_tx_status = stm32_dma_tx_status;
1262 dd->device_issue_pending = stm32_dma_issue_pending;
1263 dd->device_prep_slave_sg = stm32_dma_prep_slave_sg;
1264 dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic;
1265 dd->device_config = stm32_dma_slave_config;
1266 dd->device_terminate_all = stm32_dma_terminate_all;
dc808675 1267 dd->device_synchronize = stm32_dma_synchronize;
d8b46839
CM		 1268 dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1269 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1270 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1271 dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1272 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1273 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1274 dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1275 dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
276b0046 1276 dd->max_burst = STM32_DMA_MAX_BURST;
d8b46839
CM		 1277 dd->dev = &pdev->dev;
1278 INIT_LIST_HEAD(&dd->channels);
1279
1280 if (dmadev->mem2mem) {
1281 dma_cap_set(DMA_MEMCPY, dd->cap_mask);
1282 dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy;
1283 dd->directions |= BIT(DMA_MEM_TO_MEM);
1284 }
1285
1286 for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1287 chan = &dmadev->chan[i];
1288 chan->id = i;
1289 chan->vchan.desc_free = stm32_dma_desc_free;
1290 vchan_init(&chan->vchan, dd);
1291 }
1292
1293 ret = dma_async_device_register(dd);
1294 if (ret)
1295 return ret;
1296
1297 for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1298 chan = &dmadev->chan[i];
1299 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1300 if (!res) {
1301 ret = -EINVAL;
1302 dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1303 goto err_unregister;
1304 }
1305 chan->irq = res->start;
1306 ret = devm_request_irq(&pdev->dev, chan->irq,
1307 stm32_dma_chan_irq, 0,
1308 dev_name(chan2dev(chan)), chan);
1309 if (ret) {
1310 dev_err(&pdev->dev,
1311 "request_irq failed with err %d channel %d\n",
1312 ret, i);
1313 goto err_unregister;
1314 }
1315 }
1316
1317 ret = of_dma_controller_register(pdev->dev.of_node,
1318 stm32_dma_of_xlate, dmadev);
1319 if (ret < 0) {
1320 dev_err(&pdev->dev,
1321 "STM32 DMA DMA OF registration failed %d\n", ret);
1322 goto err_unregister;
1323 }
1324
1325 platform_set_drvdata(pdev, dmadev);
1326
1327 dev_info(&pdev->dev, "STM32 DMA driver registered\n");
1328
1329 return 0;
1330
1331err_unregister:
1332 dma_async_device_unregister(dd);
1333
1334 return ret;
1335}
1336
1337static struct platform_driver stm32_dma_driver = {
1338 .driver = {
1339 .name = "stm32-dma",
1340 .of_match_table = stm32_dma_of_match,
1341 },
1342};
1343
1344static int __init stm32_dma_init(void)
1345{
1346 return platform_driver_probe(&stm32_dma_driver, stm32_dma_probe);
1347}
1348subsys_initcall(stm32_dma_init);
Ubuntu Hirsute Linux kernel mirror