[mirror_ubuntu-kernels.git] / drivers / dma / stm32-dmamux.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *
 * Copyright (C) STMicroelectronics SA 2017
 * Author(s): M'boumba Cedric Madianga <cedric.madianga@gmail.com>
 *            Pierre-Yves Mordret <pierre-yves.mordret@st.com>
 *
 * DMA Router driver for STM32 DMA MUX
 *
 * Based on TI DMA Crossbar driver
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_dma.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define STM32_DMAMUX_CCR(x)		(0x4 * (x))
#define STM32_DMAMUX_MAX_DMA_REQUESTS	32
#define STM32_DMAMUX_MAX_REQUESTS	255

struct stm32_dmamux {
	u32 master;
	u32 request;
	u32 chan_id;
};

struct stm32_dmamux_data {
	struct dma_router dmarouter;
	struct clk *clk;
	void __iomem *iomem;
	u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
	u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
	spinlock_t lock; /* Protects register access */
	unsigned long *dma_inuse; /* Used DMA channel */
	u32 ccr[STM32_DMAMUX_MAX_DMA_REQUESTS]; /* Used to backup CCR register
						 * in suspend
						 */
	u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
			 *  [0] holds number of DMA Masters.
			 *  To be kept at very end end of this structure
			 */
};

static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg)
{
	return readl_relaxed(iomem + reg);
}

static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)
{
	writel_relaxed(val, iomem + reg);
}

static void stm32_dmamux_free(struct device *dev, void *route_data)
{
	struct stm32_dmamux_data *dmamux = dev_get_drvdata(dev);
	struct stm32_dmamux *mux = route_data;
	unsigned long flags;

	/* Clear dma request */
	spin_lock_irqsave(&dmamux->lock, flags);

	stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);
	clear_bit(mux->chan_id, dmamux->dma_inuse);

	pm_runtime_put_sync(dev);

	spin_unlock_irqrestore(&dmamux->lock, flags);

	dev_dbg(dev, "Unmapping DMAMUX(%u) to DMA%u(%u)\n",
		mux->request, mux->master, mux->chan_id);

	kfree(mux);
}

static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,
					 struct of_dma *ofdma)
{
	struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
	struct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);
	struct stm32_dmamux *mux;
	u32 i, min, max;
	int ret;
	unsigned long flags;

	if (dma_spec->args_count != 3) {
		dev_err(&pdev->dev, "invalid number of dma mux args\n");
		return ERR_PTR(-EINVAL);
	}

	if (dma_spec->args[0] > dmamux->dmamux_requests) {
		dev_err(&pdev->dev, "invalid mux request number: %d\n",
			dma_spec->args[0]);
		return ERR_PTR(-EINVAL);
	}

	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
	if (!mux)
		return ERR_PTR(-ENOMEM);

	spin_lock_irqsave(&dmamux->lock, flags);
	mux->chan_id = find_first_zero_bit(dmamux->dma_inuse,
					   dmamux->dma_requests);

	if (mux->chan_id == dmamux->dma_requests) {
		spin_unlock_irqrestore(&dmamux->lock, flags);
		dev_err(&pdev->dev, "Run out of free DMA requests\n");
		ret = -ENOMEM;
		goto error_chan_id;
	}
	set_bit(mux->chan_id, dmamux->dma_inuse);
	spin_unlock_irqrestore(&dmamux->lock, flags);

	/* Look for DMA Master */
	for (i = 1, min = 0, max = dmamux->dma_reqs[i];
	     i <= dmamux->dma_reqs[0];
	     min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])
		if (mux->chan_id < max)
			break;
	mux->master = i - 1;

	/* The of_node_put() will be done in of_dma_router_xlate function */
	dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", i - 1);
	if (!dma_spec->np) {
		dev_err(&pdev->dev, "can't get dma master\n");
		ret = -EINVAL;
		goto error;
	}

	/* Set dma request */
	spin_lock_irqsave(&dmamux->lock, flags);
	ret = pm_runtime_resume_and_get(&pdev->dev);
	if (ret < 0) {
		spin_unlock_irqrestore(&dmamux->lock, flags);
		goto error;
	}
	spin_unlock_irqrestore(&dmamux->lock, flags);

	mux->request = dma_spec->args[0];

	/*  craft DMA spec */
	dma_spec->args[3] = dma_spec->args[2];
	dma_spec->args[2] = dma_spec->args[1];
	dma_spec->args[1] = 0;
	dma_spec->args[0] = mux->chan_id - min;
	dma_spec->args_count = 4;

	stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id),
			   mux->request);
	dev_dbg(&pdev->dev, "Mapping DMAMUX(%u) to DMA%u(%u)\n",
		mux->request, mux->master, mux->chan_id);

	return mux;

error:
	clear_bit(mux->chan_id, dmamux->dma_inuse);

error_chan_id:
	kfree(mux);
	return ERR_PTR(ret);
}

static const struct of_device_id stm32_stm32dma_master_match[] __maybe_unused = {
	{ .compatible = "st,stm32-dma", },
	{},
};

static int stm32_dmamux_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	const struct of_device_id *match;
	struct device_node *dma_node;
	struct stm32_dmamux_data *stm32_dmamux;
	struct resource *res;
	void __iomem *iomem;
	struct reset_control *rst;
	int i, count, ret;
	u32 dma_req;

	if (!node)
		return -ENODEV;

	count = device_property_count_u32(&pdev->dev, "dma-masters");
	if (count < 0) {
		dev_err(&pdev->dev, "Can't get DMA master(s) node\n");
		return -ENODEV;
	}

	stm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) +
				    sizeof(u32) * (count + 1), GFP_KERNEL);
	if (!stm32_dmamux)
		return -ENOMEM;

	dma_req = 0;
	for (i = 1; i <= count; i++) {
		dma_node = of_parse_phandle(node, "dma-masters", i - 1);

		match = of_match_node(stm32_stm32dma_master_match, dma_node);
		if (!match) {
			dev_err(&pdev->dev, "DMA master is not supported\n");
			of_node_put(dma_node);
			return -EINVAL;
		}

		if (of_property_read_u32(dma_node, "dma-requests",
					 &stm32_dmamux->dma_reqs[i])) {
			dev_info(&pdev->dev,
				 "Missing MUX output information, using %u.\n",
				 STM32_DMAMUX_MAX_DMA_REQUESTS);
			stm32_dmamux->dma_reqs[i] =
				STM32_DMAMUX_MAX_DMA_REQUESTS;
		}
		dma_req += stm32_dmamux->dma_reqs[i];
		of_node_put(dma_node);
	}

	if (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) {
		dev_err(&pdev->dev, "Too many DMA Master Requests to manage\n");
		return -ENODEV;
	}

	stm32_dmamux->dma_requests = dma_req;
	stm32_dmamux->dma_reqs[0] = count;
	stm32_dmamux->dma_inuse = devm_kcalloc(&pdev->dev,
					       BITS_TO_LONGS(dma_req),
					       sizeof(unsigned long),
					       GFP_KERNEL);
	if (!stm32_dmamux->dma_inuse)
		return -ENOMEM;

	if (device_property_read_u32(&pdev->dev, "dma-requests",
				     &stm32_dmamux->dmamux_requests)) {
		stm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS;
		dev_warn(&pdev->dev, "DMAMUX defaulting on %u requests\n",
			 stm32_dmamux->dmamux_requests);
	}
	pm_runtime_get_noresume(&pdev->dev);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	iomem = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(iomem))
		return PTR_ERR(iomem);

	spin_lock_init(&stm32_dmamux->lock);

	stm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(stm32_dmamux->clk))
		return dev_err_probe(&pdev->dev, PTR_ERR(stm32_dmamux->clk),
				     "Missing clock controller\n");

	ret = clk_prepare_enable(stm32_dmamux->clk);
	if (ret < 0) {
		dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
		return ret;
	}

	rst = devm_reset_control_get(&pdev->dev, NULL);
	if (IS_ERR(rst)) {
		ret = PTR_ERR(rst);
		if (ret == -EPROBE_DEFER)
			goto err_clk;
	} else {
		reset_control_assert(rst);
		udelay(2);
		reset_control_deassert(rst);
	}

	stm32_dmamux->iomem = iomem;
	stm32_dmamux->dmarouter.dev = &pdev->dev;
	stm32_dmamux->dmarouter.route_free = stm32_dmamux_free;

	platform_set_drvdata(pdev, stm32_dmamux);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

	pm_runtime_get_noresume(&pdev->dev);

	/* Reset the dmamux */
	for (i = 0; i < stm32_dmamux->dma_requests; i++)
		stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0);

	pm_runtime_put(&pdev->dev);

	ret = of_dma_router_register(node, stm32_dmamux_route_allocate,
				     &stm32_dmamux->dmarouter);
	if (ret)
		goto err_clk;

	return 0;

err_clk:
	clk_disable_unprepare(stm32_dmamux->clk);

	return ret;
}

#ifdef CONFIG_PM
static int stm32_dmamux_runtime_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);

	clk_disable_unprepare(stm32_dmamux->clk);

	return 0;
}

static int stm32_dmamux_runtime_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
	int ret;

	ret = clk_prepare_enable(stm32_dmamux->clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to prepare_enable clock\n");
		return ret;
	}

	return 0;
}
#endif

#ifdef CONFIG_PM_SLEEP
static int stm32_dmamux_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
	int i, ret;

	ret = pm_runtime_resume_and_get(dev);
	if (ret < 0)
		return ret;

	for (i = 0; i < stm32_dmamux->dma_requests; i++)
		stm32_dmamux->ccr[i] = stm32_dmamux_read(stm32_dmamux->iomem,
							 STM32_DMAMUX_CCR(i));

	pm_runtime_put_sync(dev);

	pm_runtime_force_suspend(dev);

	return 0;
}

static int stm32_dmamux_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
	int i, ret;

	ret = pm_runtime_force_resume(dev);
	if (ret < 0)
		return ret;

	ret = pm_runtime_resume_and_get(dev);
	if (ret < 0)
		return ret;

	for (i = 0; i < stm32_dmamux->dma_requests; i++)
		stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i),
				   stm32_dmamux->ccr[i]);

	pm_runtime_put_sync(dev);

	return 0;
}
#endif

static const struct dev_pm_ops stm32_dmamux_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(stm32_dmamux_suspend, stm32_dmamux_resume)
	SET_RUNTIME_PM_OPS(stm32_dmamux_runtime_suspend,
			   stm32_dmamux_runtime_resume, NULL)
};

static const struct of_device_id stm32_dmamux_match[] = {
	{ .compatible = "st,stm32h7-dmamux" },
	{},
};

static struct platform_driver stm32_dmamux_driver = {
	.probe	= stm32_dmamux_probe,
	.driver = {
		.name = "stm32-dmamux",
		.of_match_table = stm32_dmamux_match,
		.pm = &stm32_dmamux_pm_ops,
	},
};

static int __init stm32_dmamux_init(void)
{
	return platform_driver_register(&stm32_dmamux_driver);
}
arch_initcall(stm32_dmamux_init);

MODULE_DESCRIPTION("DMA Router driver for STM32 DMA MUX");
MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
MODULE_AUTHOR("Pierre-Yves Mordret <pierre-yves.mordret@st.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
df7e762d PYM	2	/*
	3	*
	4	* Copyright (C) STMicroelectronics SA 2017
	5	* Author(s): M'boumba Cedric Madianga <cedric.madianga@gmail.com>
	6	* Pierre-Yves Mordret <pierre-yves.mordret@st.com>
	7	*
df7e762d PYM	8	* DMA Router driver for STM32 DMA MUX
	9	*
	10	* Based on TI DMA Crossbar driver
df7e762d PYM	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/delay.h>
	15	#include <linux/err.h>
	16	#include <linux/init.h>
	17	#include <linux/module.h>
	18	#include <linux/of_device.h>
	19	#include <linux/of_dma.h>
4f3ceca2	20	#include <linux/pm_runtime.h>
df7e762d PYM	21	#include <linux/reset.h>
	22	#include <linux/slab.h>
	23	#include <linux/spinlock.h>
	24
	25	#define STM32_DMAMUX_CCR(x) (0x4 * (x))
	26	#define STM32_DMAMUX_MAX_DMA_REQUESTS 32
	27	#define STM32_DMAMUX_MAX_REQUESTS 255
	28
	29	struct stm32_dmamux {
	30	u32 master;
	31	u32 request;
	32	u32 chan_id;
	33	};
	34
	35	struct stm32_dmamux_data {
	36	struct dma_router dmarouter;
	37	struct clk *clk;
df7e762d PYM	38	void __iomem *iomem;
	39	u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
	40	u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
	41	spinlock_t lock; /* Protects register access */
	42	unsigned long dma_inuse; / Used DMA channel */
f65c2e14 PYM	43	u32 ccr[STM32_DMAMUX_MAX_DMA_REQUESTS]; /* Used to backup CCR register
	44	* in suspend
	45	*/
df7e762d PYM	46	u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
	47	* [0] holds number of DMA Masters.
	48	* To be kept at very end end of this structure
	49	*/
	50	};
	51
	52	static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg)
	53	{
	54	return readl_relaxed(iomem + reg);
	55	}
	56
	57	static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)
	58	{
	59	writel_relaxed(val, iomem + reg);
	60	}
	61
	62	static void stm32_dmamux_free(struct device dev, void route_data)
	63	{
	64	struct stm32_dmamux_data *dmamux = dev_get_drvdata(dev);
	65	struct stm32_dmamux *mux = route_data;
	66	unsigned long flags;
	67
	68	/* Clear dma request */
	69	spin_lock_irqsave(&dmamux->lock, flags);
	70
	71	stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);
	72	clear_bit(mux->chan_id, dmamux->dma_inuse);
	73
4f3ceca2	74	pm_runtime_put_sync(dev);
df7e762d PYM	75
	76	spin_unlock_irqrestore(&dmamux->lock, flags);
	77
	78	dev_dbg(dev, "Unmapping DMAMUX(%u) to DMA%u(%u)\n",
	79	mux->request, mux->master, mux->chan_id);
	80
	81	kfree(mux);
	82	}
	83
	84	static void stm32_dmamux_route_allocate(struct of_phandle_args dma_spec,
	85	struct of_dma *ofdma)
	86	{
	87	struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
	88	struct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);
	89	struct stm32_dmamux *mux;
	90	u32 i, min, max;
	91	int ret;
	92	unsigned long flags;
	93
	94	if (dma_spec->args_count != 3) {
	95	dev_err(&pdev->dev, "invalid number of dma mux args\n");
	96	return ERR_PTR(-EINVAL);
	97	}
	98
	99	if (dma_spec->args[0] > dmamux->dmamux_requests) {
	100	dev_err(&pdev->dev, "invalid mux request number: %d\n",
	101	dma_spec->args[0]);
	102	return ERR_PTR(-EINVAL);
	103	}
	104
	105	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
	106	if (!mux)
	107	return ERR_PTR(-ENOMEM);
	108
	109	spin_lock_irqsave(&dmamux->lock, flags);
	110	mux->chan_id = find_first_zero_bit(dmamux->dma_inuse,
	111	dmamux->dma_requests);
df7e762d PYM	112
df7e762d PYM	113	if (mux->chan_id == dmamux->dma_requests) {
3e4543bf	114	spin_unlock_irqrestore(&dmamux->lock, flags);
df7e762d PYM	115	dev_err(&pdev->dev, "Run out of free DMA requests\n");
df7e762d PYM	116	ret = -ENOMEM;
3e4543bf	117	goto error_chan_id;
df7e762d	118	}
3e4543bf PYM	119	set_bit(mux->chan_id, dmamux->dma_inuse);
3e4543bf PYM	120	spin_unlock_irqrestore(&dmamux->lock, flags);
df7e762d PYM	121
	122	/* Look for DMA Master */
	123	for (i = 1, min = 0, max = dmamux->dma_reqs[i];
	124	i <= dmamux->dma_reqs[0];
	125	min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])
	126	if (mux->chan_id < max)
	127	break;
	128	mux->master = i - 1;
	129
	130	/* The of_node_put() will be done in of_dma_router_xlate function */
	131	dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", i - 1);
	132	if (!dma_spec->np) {
	133	dev_err(&pdev->dev, "can't get dma master\n");
	134	ret = -EINVAL;
	135	goto error;
	136	}
	137
	138	/* Set dma request */
	139	spin_lock_irqsave(&dmamux->lock, flags);
baa16371	140	ret = pm_runtime_resume_and_get(&pdev->dev);
4f3ceca2 PYM	141	if (ret < 0) {
	142	spin_unlock_irqrestore(&dmamux->lock, flags);
	143	goto error;
df7e762d PYM	144	}
	145	spin_unlock_irqrestore(&dmamux->lock, flags);
	146
	147	mux->request = dma_spec->args[0];
	148
	149	/* craft DMA spec */
	150	dma_spec->args[3] = dma_spec->args[2];
	151	dma_spec->args[2] = dma_spec->args[1];
	152	dma_spec->args[1] = 0;
	153	dma_spec->args[0] = mux->chan_id - min;
	154	dma_spec->args_count = 4;
	155
	156	stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id),
	157	mux->request);
	158	dev_dbg(&pdev->dev, "Mapping DMAMUX(%u) to DMA%u(%u)\n",
	159	mux->request, mux->master, mux->chan_id);
	160
	161	return mux;
	162
	163	error:
	164	clear_bit(mux->chan_id, dmamux->dma_inuse);
3e4543bf PYM	165
3e4543bf PYM	166	error_chan_id:
df7e762d PYM	167	kfree(mux);
	168	return ERR_PTR(ret);
	169	}
	170
25d39b59	171	static const struct of_device_id stm32_stm32dma_master_match[] __maybe_unused = {
df7e762d PYM	172	{ .compatible = "st,stm32-dma", },
	173	{},
	174	};
	175
	176	static int stm32_dmamux_probe(struct platform_device *pdev)
	177	{
	178	struct device_node *node = pdev->dev.of_node;
	179	const struct of_device_id *match;
	180	struct device_node *dma_node;
	181	struct stm32_dmamux_data *stm32_dmamux;
	182	struct resource *res;
	183	void __iomem *iomem;
d04d2f62	184	struct reset_control *rst;
df7e762d PYM	185	int i, count, ret;
	186	u32 dma_req;
	187
	188	if (!node)
	189	return -ENODEV;
	190
2cb114c4	191	count = device_property_count_u32(&pdev->dev, "dma-masters");
df7e762d PYM	192	if (count < 0) {
	193	dev_err(&pdev->dev, "Can't get DMA master(s) node\n");
	194	return -ENODEV;
	195	}
	196
	197	stm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) +
	198	sizeof(u32) * (count + 1), GFP_KERNEL);
	199	if (!stm32_dmamux)
	200	return -ENOMEM;
	201
	202	dma_req = 0;
	203	for (i = 1; i <= count; i++) {
	204	dma_node = of_parse_phandle(node, "dma-masters", i - 1);
	205
	206	match = of_match_node(stm32_stm32dma_master_match, dma_node);
	207	if (!match) {
	208	dev_err(&pdev->dev, "DMA master is not supported\n");
	209	of_node_put(dma_node);
	210	return -EINVAL;
	211	}
	212
	213	if (of_property_read_u32(dma_node, "dma-requests",
	214	&stm32_dmamux->dma_reqs[i])) {
	215	dev_info(&pdev->dev,
	216	"Missing MUX output information, using %u.\n",
	217	STM32_DMAMUX_MAX_DMA_REQUESTS);
	218	stm32_dmamux->dma_reqs[i] =
	219	STM32_DMAMUX_MAX_DMA_REQUESTS;
	220	}
	221	dma_req += stm32_dmamux->dma_reqs[i];
	222	of_node_put(dma_node);
	223	}
	224
	225	if (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) {
	226	dev_err(&pdev->dev, "Too many DMA Master Requests to manage\n");
	227	return -ENODEV;
	228	}
	229
	230	stm32_dmamux->dma_requests = dma_req;
	231	stm32_dmamux->dma_reqs[0] = count;
	232	stm32_dmamux->dma_inuse = devm_kcalloc(&pdev->dev,
	233	BITS_TO_LONGS(dma_req),
	234	sizeof(unsigned long),
	235	GFP_KERNEL);
	236	if (!stm32_dmamux->dma_inuse)
	237	return -ENOMEM;
	238
	239	if (device_property_read_u32(&pdev->dev, "dma-requests",
	240	&stm32_dmamux->dmamux_requests)) {
	241	stm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS;
	242	dev_warn(&pdev->dev, "DMAMUX defaulting on %u requests\n",
	243	stm32_dmamux->dmamux_requests);
	244	}
4f3ceca2	245	pm_runtime_get_noresume(&pdev->dev);
df7e762d PYM	246
df7e762d PYM	247	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
df7e762d	248	iomem = devm_ioremap_resource(&pdev->dev, res);
4219ff33 DC	249	if (IS_ERR(iomem))
4219ff33 DC	250	return PTR_ERR(iomem);
df7e762d PYM	251
	252	spin_lock_init(&stm32_dmamux->lock);
	253
	254	stm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL);
1c966e1d KK	255	if (IS_ERR(stm32_dmamux->clk))
	256	return dev_err_probe(&pdev->dev, PTR_ERR(stm32_dmamux->clk),
	257	"Missing clock controller\n");
df7e762d	258
57e9f366 EC	259	ret = clk_prepare_enable(stm32_dmamux->clk);
	260	if (ret < 0) {
	261	dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
	262	return ret;
	263	}
	264
d04d2f62	265	rst = devm_reset_control_get(&pdev->dev, NULL);
6cc70897 EC	266	if (IS_ERR(rst)) {
	267	ret = PTR_ERR(rst);
	268	if (ret == -EPROBE_DEFER)
	269	goto err_clk;
	270	} else {
d04d2f62	271	reset_control_assert(rst);
df7e762d	272	udelay(2);
d04d2f62	273	reset_control_deassert(rst);
df7e762d PYM	274	}
	275
	276	stm32_dmamux->iomem = iomem;
	277	stm32_dmamux->dmarouter.dev = &pdev->dev;
	278	stm32_dmamux->dmarouter.route_free = stm32_dmamux_free;
	279
	280	platform_set_drvdata(pdev, stm32_dmamux);
4f3ceca2 PYM	281	pm_runtime_set_active(&pdev->dev);
4f3ceca2 PYM	282	pm_runtime_enable(&pdev->dev);
df7e762d	283
4f3ceca2 PYM	284	pm_runtime_get_noresume(&pdev->dev);
4f3ceca2 PYM	285
df7e762d PYM	286	/* Reset the dmamux */
	287	for (i = 0; i < stm32_dmamux->dma_requests; i++)
	288	stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0);
	289
4f3ceca2	290	pm_runtime_put(&pdev->dev);
df7e762d	291
57e9f366	292	ret = of_dma_router_register(node, stm32_dmamux_route_allocate,
df7e762d	293	&stm32_dmamux->dmarouter);
57e9f366	294	if (ret)
6cc70897 EC	295	goto err_clk;
	296
	297	return 0;
	298
	299	err_clk:
	300	clk_disable_unprepare(stm32_dmamux->clk);
57e9f366 EC	301
57e9f366 EC	302	return ret;
df7e762d PYM	303	}
df7e762d PYM	304
4f3ceca2 PYM	305	#ifdef CONFIG_PM
	306	static int stm32_dmamux_runtime_suspend(struct device *dev)
	307	{
7b11ef96	308	struct platform_device *pdev = to_platform_device(dev);
4f3ceca2 PYM	309	struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
	310
	311	clk_disable_unprepare(stm32_dmamux->clk);
	312
	313	return 0;
	314	}
	315
	316	static int stm32_dmamux_runtime_resume(struct device *dev)
	317	{
7b11ef96	318	struct platform_device *pdev = to_platform_device(dev);
4f3ceca2 PYM	319	struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
	320	int ret;
	321
	322	ret = clk_prepare_enable(stm32_dmamux->clk);
	323	if (ret) {
	324	dev_err(&pdev->dev, "failed to prepare_enable clock\n");
	325	return ret;
	326	}
	327
	328	return 0;
	329	}
	330	#endif
	331
f65c2e14 PYM	332	#ifdef CONFIG_PM_SLEEP
	333	static int stm32_dmamux_suspend(struct device *dev)
	334	{
	335	struct platform_device *pdev = to_platform_device(dev);
	336	struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
	337	int i, ret;
	338
baa16371	339	ret = pm_runtime_resume_and_get(dev);
f65c2e14 PYM	340	if (ret < 0)
	341	return ret;
	342
	343	for (i = 0; i < stm32_dmamux->dma_requests; i++)
	344	stm32_dmamux->ccr[i] = stm32_dmamux_read(stm32_dmamux->iomem,
	345	STM32_DMAMUX_CCR(i));
	346
	347	pm_runtime_put_sync(dev);
	348
	349	pm_runtime_force_suspend(dev);
	350
	351	return 0;
	352	}
	353
	354	static int stm32_dmamux_resume(struct device *dev)
	355	{
	356	struct platform_device *pdev = to_platform_device(dev);
	357	struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
	358	int i, ret;
	359
	360	ret = pm_runtime_force_resume(dev);
	361	if (ret < 0)
	362	return ret;
	363
baa16371	364	ret = pm_runtime_resume_and_get(dev);
f65c2e14 PYM	365	if (ret < 0)
	366	return ret;
	367
	368	for (i = 0; i < stm32_dmamux->dma_requests; i++)
	369	stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i),
	370	stm32_dmamux->ccr[i]);
	371
	372	pm_runtime_put_sync(dev);
	373
	374	return 0;
	375	}
	376	#endif
	377
4f3ceca2	378	static const struct dev_pm_ops stm32_dmamux_pm_ops = {
f65c2e14	379	SET_SYSTEM_SLEEP_PM_OPS(stm32_dmamux_suspend, stm32_dmamux_resume)
4f3ceca2 PYM	380	SET_RUNTIME_PM_OPS(stm32_dmamux_runtime_suspend,
	381	stm32_dmamux_runtime_resume, NULL)
	382	};
	383
df7e762d PYM	384	static const struct of_device_id stm32_dmamux_match[] = {
	385	{ .compatible = "st,stm32h7-dmamux" },
	386	{},
	387	};
	388
	389	static struct platform_driver stm32_dmamux_driver = {
	390	.probe = stm32_dmamux_probe,
	391	.driver = {
	392	.name = "stm32-dmamux",
	393	.of_match_table = stm32_dmamux_match,
4f3ceca2	394	.pm = &stm32_dmamux_pm_ops,
df7e762d PYM	395	},
	396	};
	397
	398	static int __init stm32_dmamux_init(void)
	399	{
	400	return platform_driver_register(&stm32_dmamux_driver);
	401	}
	402	arch_initcall(stm32_dmamux_init);
	403
	404	MODULE_DESCRIPTION("DMA Router driver for STM32 DMA MUX");
	405	MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
	406	MODULE_AUTHOR("Pierre-Yves Mordret <pierre-yves.mordret@st.com>");
	407	MODULE_LICENSE("GPL v2");