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55585930 MR |
1 | /* |
2 | * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd | |
3 | * Author: Sugar <shuge@allwinnertech.com> | |
4 | * | |
5 | * Copyright (C) 2014 Maxime Ripard | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dmapool.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of_dma.h> | |
25a37c2f | 21 | #include <linux/of_device.h> |
55585930 MR |
22 | #include <linux/platform_device.h> |
23 | #include <linux/reset.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/types.h> | |
26 | ||
27 | #include "virt-dma.h" | |
28 | ||
55585930 MR |
29 | /* |
30 | * Common registers | |
31 | */ | |
32 | #define DMA_IRQ_EN(x) ((x) * 0x04) | |
33 | #define DMA_IRQ_HALF BIT(0) | |
34 | #define DMA_IRQ_PKG BIT(1) | |
35 | #define DMA_IRQ_QUEUE BIT(2) | |
36 | ||
37 | #define DMA_IRQ_CHAN_NR 8 | |
38 | #define DMA_IRQ_CHAN_WIDTH 4 | |
39 | ||
40 | ||
41 | #define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10) | |
42 | ||
43 | #define DMA_STAT 0x30 | |
44 | ||
45 | /* | |
46 | * Channels specific registers | |
47 | */ | |
48 | #define DMA_CHAN_ENABLE 0x00 | |
49 | #define DMA_CHAN_ENABLE_START BIT(0) | |
50 | #define DMA_CHAN_ENABLE_STOP 0 | |
51 | ||
52 | #define DMA_CHAN_PAUSE 0x04 | |
53 | #define DMA_CHAN_PAUSE_PAUSE BIT(1) | |
54 | #define DMA_CHAN_PAUSE_RESUME 0 | |
55 | ||
56 | #define DMA_CHAN_LLI_ADDR 0x08 | |
57 | ||
58 | #define DMA_CHAN_CUR_CFG 0x0c | |
59 | #define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f) | |
60 | #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) | |
61 | #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) | |
62 | #define DMA_CHAN_CFG_SRC_BURST(x) (((x) & 0x3) << 7) | |
63 | #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) | |
64 | ||
65 | #define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) | |
66 | #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) | |
67 | #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) | |
68 | #define DMA_CHAN_CFG_DST_BURST(x) (DMA_CHAN_CFG_SRC_BURST(x) << 16) | |
69 | #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) | |
70 | ||
71 | #define DMA_CHAN_CUR_SRC 0x10 | |
72 | ||
73 | #define DMA_CHAN_CUR_DST 0x14 | |
74 | ||
75 | #define DMA_CHAN_CUR_CNT 0x18 | |
76 | ||
77 | #define DMA_CHAN_CUR_PARA 0x1c | |
78 | ||
79 | ||
80 | /* | |
81 | * Various hardware related defines | |
82 | */ | |
83 | #define LLI_LAST_ITEM 0xfffff800 | |
84 | #define NORMAL_WAIT 8 | |
85 | #define DRQ_SDRAM 1 | |
86 | ||
25a37c2f CYT |
87 | /* |
88 | * Hardware channels / ports representation | |
89 | * | |
90 | * The hardware is used in several SoCs, with differing numbers | |
91 | * of channels and endpoints. This structure ties those numbers | |
92 | * to a certain compatible string. | |
93 | */ | |
94 | struct sun6i_dma_config { | |
95 | u32 nr_max_channels; | |
96 | u32 nr_max_requests; | |
97 | u32 nr_max_vchans; | |
98 | }; | |
99 | ||
55585930 MR |
100 | /* |
101 | * Hardware representation of the LLI | |
102 | * | |
103 | * The hardware will be fed the physical address of this structure, | |
104 | * and read its content in order to start the transfer. | |
105 | */ | |
106 | struct sun6i_dma_lli { | |
107 | u32 cfg; | |
108 | u32 src; | |
109 | u32 dst; | |
110 | u32 len; | |
111 | u32 para; | |
112 | u32 p_lli_next; | |
113 | ||
114 | /* | |
115 | * This field is not used by the DMA controller, but will be | |
116 | * used by the CPU to go through the list (mostly for dumping | |
117 | * or freeing it). | |
118 | */ | |
119 | struct sun6i_dma_lli *v_lli_next; | |
120 | }; | |
121 | ||
122 | ||
123 | struct sun6i_desc { | |
124 | struct virt_dma_desc vd; | |
125 | dma_addr_t p_lli; | |
126 | struct sun6i_dma_lli *v_lli; | |
127 | }; | |
128 | ||
129 | struct sun6i_pchan { | |
130 | u32 idx; | |
131 | void __iomem *base; | |
132 | struct sun6i_vchan *vchan; | |
133 | struct sun6i_desc *desc; | |
134 | struct sun6i_desc *done; | |
135 | }; | |
136 | ||
137 | struct sun6i_vchan { | |
138 | struct virt_dma_chan vc; | |
139 | struct list_head node; | |
140 | struct dma_slave_config cfg; | |
141 | struct sun6i_pchan *phy; | |
142 | u8 port; | |
143 | }; | |
144 | ||
145 | struct sun6i_dma_dev { | |
146 | struct dma_device slave; | |
147 | void __iomem *base; | |
148 | struct clk *clk; | |
149 | int irq; | |
150 | spinlock_t lock; | |
151 | struct reset_control *rstc; | |
152 | struct tasklet_struct task; | |
153 | atomic_t tasklet_shutdown; | |
154 | struct list_head pending; | |
155 | struct dma_pool *pool; | |
156 | struct sun6i_pchan *pchans; | |
157 | struct sun6i_vchan *vchans; | |
25a37c2f | 158 | const struct sun6i_dma_config *cfg; |
55585930 MR |
159 | }; |
160 | ||
161 | static struct device *chan2dev(struct dma_chan *chan) | |
162 | { | |
163 | return &chan->dev->device; | |
164 | } | |
165 | ||
166 | static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d) | |
167 | { | |
168 | return container_of(d, struct sun6i_dma_dev, slave); | |
169 | } | |
170 | ||
171 | static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan) | |
172 | { | |
173 | return container_of(chan, struct sun6i_vchan, vc.chan); | |
174 | } | |
175 | ||
176 | static inline struct sun6i_desc * | |
177 | to_sun6i_desc(struct dma_async_tx_descriptor *tx) | |
178 | { | |
179 | return container_of(tx, struct sun6i_desc, vd.tx); | |
180 | } | |
181 | ||
182 | static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) | |
183 | { | |
184 | dev_dbg(sdev->slave.dev, "Common register:\n" | |
185 | "\tmask0(%04x): 0x%08x\n" | |
186 | "\tmask1(%04x): 0x%08x\n" | |
187 | "\tpend0(%04x): 0x%08x\n" | |
188 | "\tpend1(%04x): 0x%08x\n" | |
189 | "\tstats(%04x): 0x%08x\n", | |
190 | DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)), | |
191 | DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)), | |
192 | DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)), | |
193 | DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)), | |
194 | DMA_STAT, readl(sdev->base + DMA_STAT)); | |
195 | } | |
196 | ||
197 | static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev, | |
198 | struct sun6i_pchan *pchan) | |
199 | { | |
42c0d54e | 200 | phys_addr_t reg = virt_to_phys(pchan->base); |
55585930 MR |
201 | |
202 | dev_dbg(sdev->slave.dev, "Chan %d reg: %pa\n" | |
203 | "\t___en(%04x): \t0x%08x\n" | |
204 | "\tpause(%04x): \t0x%08x\n" | |
205 | "\tstart(%04x): \t0x%08x\n" | |
206 | "\t__cfg(%04x): \t0x%08x\n" | |
207 | "\t__src(%04x): \t0x%08x\n" | |
208 | "\t__dst(%04x): \t0x%08x\n" | |
209 | "\tcount(%04x): \t0x%08x\n" | |
210 | "\t_para(%04x): \t0x%08x\n\n", | |
211 | pchan->idx, ®, | |
212 | DMA_CHAN_ENABLE, | |
213 | readl(pchan->base + DMA_CHAN_ENABLE), | |
214 | DMA_CHAN_PAUSE, | |
215 | readl(pchan->base + DMA_CHAN_PAUSE), | |
216 | DMA_CHAN_LLI_ADDR, | |
217 | readl(pchan->base + DMA_CHAN_LLI_ADDR), | |
218 | DMA_CHAN_CUR_CFG, | |
219 | readl(pchan->base + DMA_CHAN_CUR_CFG), | |
220 | DMA_CHAN_CUR_SRC, | |
221 | readl(pchan->base + DMA_CHAN_CUR_SRC), | |
222 | DMA_CHAN_CUR_DST, | |
223 | readl(pchan->base + DMA_CHAN_CUR_DST), | |
224 | DMA_CHAN_CUR_CNT, | |
225 | readl(pchan->base + DMA_CHAN_CUR_CNT), | |
226 | DMA_CHAN_CUR_PARA, | |
227 | readl(pchan->base + DMA_CHAN_CUR_PARA)); | |
228 | } | |
229 | ||
230 | static inline int convert_burst(u32 maxburst, u8 *burst) | |
231 | { | |
232 | switch (maxburst) { | |
233 | case 1: | |
234 | *burst = 0; | |
235 | break; | |
236 | case 8: | |
237 | *burst = 2; | |
238 | break; | |
239 | default: | |
240 | return -EINVAL; | |
241 | } | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static inline int convert_buswidth(enum dma_slave_buswidth addr_width, u8 *width) | |
247 | { | |
92e4a3bf MR |
248 | if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) || |
249 | (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
55585930 | 250 | return -EINVAL; |
55585930 | 251 | |
92e4a3bf | 252 | *width = addr_width >> 1; |
55585930 MR |
253 | return 0; |
254 | } | |
255 | ||
256 | static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev, | |
257 | struct sun6i_dma_lli *next, | |
258 | dma_addr_t next_phy, | |
259 | struct sun6i_desc *txd) | |
260 | { | |
261 | if ((!prev && !txd) || !next) | |
262 | return NULL; | |
263 | ||
264 | if (!prev) { | |
265 | txd->p_lli = next_phy; | |
266 | txd->v_lli = next; | |
267 | } else { | |
268 | prev->p_lli_next = next_phy; | |
269 | prev->v_lli_next = next; | |
270 | } | |
271 | ||
272 | next->p_lli_next = LLI_LAST_ITEM; | |
273 | next->v_lli_next = NULL; | |
274 | ||
275 | return next; | |
276 | } | |
277 | ||
278 | static inline int sun6i_dma_cfg_lli(struct sun6i_dma_lli *lli, | |
279 | dma_addr_t src, | |
280 | dma_addr_t dst, u32 len, | |
281 | struct dma_slave_config *config) | |
282 | { | |
283 | u8 src_width, dst_width, src_burst, dst_burst; | |
284 | int ret; | |
285 | ||
286 | if (!config) | |
287 | return -EINVAL; | |
288 | ||
289 | ret = convert_burst(config->src_maxburst, &src_burst); | |
290 | if (ret) | |
291 | return ret; | |
292 | ||
293 | ret = convert_burst(config->dst_maxburst, &dst_burst); | |
294 | if (ret) | |
295 | return ret; | |
296 | ||
297 | ret = convert_buswidth(config->src_addr_width, &src_width); | |
298 | if (ret) | |
299 | return ret; | |
300 | ||
301 | ret = convert_buswidth(config->dst_addr_width, &dst_width); | |
302 | if (ret) | |
303 | return ret; | |
304 | ||
305 | lli->cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) | | |
306 | DMA_CHAN_CFG_SRC_WIDTH(src_width) | | |
307 | DMA_CHAN_CFG_DST_BURST(dst_burst) | | |
308 | DMA_CHAN_CFG_DST_WIDTH(dst_width); | |
309 | ||
310 | lli->src = src; | |
311 | lli->dst = dst; | |
312 | lli->len = len; | |
313 | lli->para = NORMAL_WAIT; | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
318 | static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan, | |
319 | struct sun6i_dma_lli *lli) | |
320 | { | |
42c0d54e | 321 | phys_addr_t p_lli = virt_to_phys(lli); |
55585930 MR |
322 | |
323 | dev_dbg(chan2dev(&vchan->vc.chan), | |
324 | "\n\tdesc: p - %pa v - 0x%p\n" | |
325 | "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n" | |
326 | "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n", | |
327 | &p_lli, lli, | |
328 | lli->cfg, lli->src, lli->dst, | |
329 | lli->len, lli->para, lli->p_lli_next); | |
330 | } | |
331 | ||
332 | static void sun6i_dma_free_desc(struct virt_dma_desc *vd) | |
333 | { | |
334 | struct sun6i_desc *txd = to_sun6i_desc(&vd->tx); | |
335 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device); | |
336 | struct sun6i_dma_lli *v_lli, *v_next; | |
337 | dma_addr_t p_lli, p_next; | |
338 | ||
339 | if (unlikely(!txd)) | |
340 | return; | |
341 | ||
342 | p_lli = txd->p_lli; | |
343 | v_lli = txd->v_lli; | |
344 | ||
345 | while (v_lli) { | |
346 | v_next = v_lli->v_lli_next; | |
347 | p_next = v_lli->p_lli_next; | |
348 | ||
349 | dma_pool_free(sdev->pool, v_lli, p_lli); | |
350 | ||
351 | v_lli = v_next; | |
352 | p_lli = p_next; | |
353 | } | |
354 | ||
355 | kfree(txd); | |
356 | } | |
357 | ||
358 | static int sun6i_dma_terminate_all(struct sun6i_vchan *vchan) | |
359 | { | |
360 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device); | |
361 | struct sun6i_pchan *pchan = vchan->phy; | |
362 | unsigned long flags; | |
363 | LIST_HEAD(head); | |
364 | ||
365 | spin_lock(&sdev->lock); | |
366 | list_del_init(&vchan->node); | |
367 | spin_unlock(&sdev->lock); | |
368 | ||
369 | spin_lock_irqsave(&vchan->vc.lock, flags); | |
370 | ||
371 | vchan_get_all_descriptors(&vchan->vc, &head); | |
372 | ||
373 | if (pchan) { | |
374 | writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE); | |
375 | writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE); | |
376 | ||
377 | vchan->phy = NULL; | |
378 | pchan->vchan = NULL; | |
379 | pchan->desc = NULL; | |
380 | pchan->done = NULL; | |
381 | } | |
382 | ||
383 | spin_unlock_irqrestore(&vchan->vc.lock, flags); | |
384 | ||
385 | vchan_dma_desc_free_list(&vchan->vc, &head); | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) | |
391 | { | |
392 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device); | |
393 | struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc); | |
394 | struct sun6i_pchan *pchan = vchan->phy; | |
395 | u32 irq_val, irq_reg, irq_offset; | |
396 | ||
397 | if (!pchan) | |
398 | return -EAGAIN; | |
399 | ||
400 | if (!desc) { | |
401 | pchan->desc = NULL; | |
402 | pchan->done = NULL; | |
403 | return -EAGAIN; | |
404 | } | |
405 | ||
406 | list_del(&desc->node); | |
407 | ||
408 | pchan->desc = to_sun6i_desc(&desc->tx); | |
409 | pchan->done = NULL; | |
410 | ||
411 | sun6i_dma_dump_lli(vchan, pchan->desc->v_lli); | |
412 | ||
413 | irq_reg = pchan->idx / DMA_IRQ_CHAN_NR; | |
414 | irq_offset = pchan->idx % DMA_IRQ_CHAN_NR; | |
415 | ||
416 | irq_val = readl(sdev->base + DMA_IRQ_EN(irq_offset)); | |
417 | irq_val |= DMA_IRQ_QUEUE << (irq_offset * DMA_IRQ_CHAN_WIDTH); | |
418 | writel(irq_val, sdev->base + DMA_IRQ_EN(irq_offset)); | |
419 | ||
420 | writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR); | |
421 | writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE); | |
422 | ||
423 | sun6i_dma_dump_com_regs(sdev); | |
424 | sun6i_dma_dump_chan_regs(sdev, pchan); | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
429 | static void sun6i_dma_tasklet(unsigned long data) | |
430 | { | |
431 | struct sun6i_dma_dev *sdev = (struct sun6i_dma_dev *)data; | |
25a37c2f | 432 | const struct sun6i_dma_config *cfg = sdev->cfg; |
55585930 MR |
433 | struct sun6i_vchan *vchan; |
434 | struct sun6i_pchan *pchan; | |
435 | unsigned int pchan_alloc = 0; | |
436 | unsigned int pchan_idx; | |
437 | ||
438 | list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) { | |
439 | spin_lock_irq(&vchan->vc.lock); | |
440 | ||
441 | pchan = vchan->phy; | |
442 | ||
443 | if (pchan && pchan->done) { | |
444 | if (sun6i_dma_start_desc(vchan)) { | |
445 | /* | |
446 | * No current txd associated with this channel | |
447 | */ | |
448 | dev_dbg(sdev->slave.dev, "pchan %u: free\n", | |
449 | pchan->idx); | |
450 | ||
451 | /* Mark this channel free */ | |
452 | vchan->phy = NULL; | |
453 | pchan->vchan = NULL; | |
454 | } | |
455 | } | |
456 | spin_unlock_irq(&vchan->vc.lock); | |
457 | } | |
458 | ||
459 | spin_lock_irq(&sdev->lock); | |
25a37c2f | 460 | for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) { |
55585930 MR |
461 | pchan = &sdev->pchans[pchan_idx]; |
462 | ||
463 | if (pchan->vchan || list_empty(&sdev->pending)) | |
464 | continue; | |
465 | ||
466 | vchan = list_first_entry(&sdev->pending, | |
467 | struct sun6i_vchan, node); | |
468 | ||
469 | /* Remove from pending channels */ | |
470 | list_del_init(&vchan->node); | |
471 | pchan_alloc |= BIT(pchan_idx); | |
472 | ||
473 | /* Mark this channel allocated */ | |
474 | pchan->vchan = vchan; | |
475 | vchan->phy = pchan; | |
476 | dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n", | |
477 | pchan->idx, &vchan->vc); | |
478 | } | |
479 | spin_unlock_irq(&sdev->lock); | |
480 | ||
25a37c2f | 481 | for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) { |
55585930 MR |
482 | if (!(pchan_alloc & BIT(pchan_idx))) |
483 | continue; | |
484 | ||
485 | pchan = sdev->pchans + pchan_idx; | |
486 | vchan = pchan->vchan; | |
487 | if (vchan) { | |
488 | spin_lock_irq(&vchan->vc.lock); | |
489 | sun6i_dma_start_desc(vchan); | |
490 | spin_unlock_irq(&vchan->vc.lock); | |
491 | } | |
492 | } | |
493 | } | |
494 | ||
495 | static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) | |
496 | { | |
497 | struct sun6i_dma_dev *sdev = dev_id; | |
498 | struct sun6i_vchan *vchan; | |
499 | struct sun6i_pchan *pchan; | |
500 | int i, j, ret = IRQ_NONE; | |
501 | u32 status; | |
502 | ||
25a37c2f | 503 | for (i = 0; i < sdev->cfg->nr_max_channels / DMA_IRQ_CHAN_NR; i++) { |
55585930 MR |
504 | status = readl(sdev->base + DMA_IRQ_STAT(i)); |
505 | if (!status) | |
506 | continue; | |
507 | ||
508 | dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n", | |
509 | i ? "high" : "low", status); | |
510 | ||
511 | writel(status, sdev->base + DMA_IRQ_STAT(i)); | |
512 | ||
25a37c2f | 513 | for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { |
55585930 MR |
514 | if (status & DMA_IRQ_QUEUE) { |
515 | pchan = sdev->pchans + j; | |
516 | vchan = pchan->vchan; | |
517 | ||
518 | if (vchan) { | |
519 | spin_lock(&vchan->vc.lock); | |
520 | vchan_cookie_complete(&pchan->desc->vd); | |
521 | pchan->done = pchan->desc; | |
522 | spin_unlock(&vchan->vc.lock); | |
523 | } | |
524 | } | |
525 | ||
25a37c2f | 526 | status = status >> DMA_IRQ_CHAN_WIDTH; |
55585930 MR |
527 | } |
528 | ||
529 | if (!atomic_read(&sdev->tasklet_shutdown)) | |
530 | tasklet_schedule(&sdev->task); | |
531 | ret = IRQ_HANDLED; | |
532 | } | |
533 | ||
534 | return ret; | |
535 | } | |
536 | ||
537 | static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( | |
538 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
539 | size_t len, unsigned long flags) | |
540 | { | |
541 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
542 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
543 | struct dma_slave_config *sconfig = &vchan->cfg; | |
544 | struct sun6i_dma_lli *v_lli; | |
545 | struct sun6i_desc *txd; | |
546 | dma_addr_t p_lli; | |
547 | int ret; | |
548 | ||
549 | dev_dbg(chan2dev(chan), | |
550 | "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n", | |
551 | __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags); | |
552 | ||
553 | if (!len) | |
554 | return NULL; | |
555 | ||
556 | txd = kzalloc(sizeof(*txd), GFP_NOWAIT); | |
557 | if (!txd) | |
558 | return NULL; | |
559 | ||
560 | v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli); | |
561 | if (!v_lli) { | |
562 | dev_err(sdev->slave.dev, "Failed to alloc lli memory\n"); | |
4fbd804e | 563 | goto err_txd_free; |
55585930 MR |
564 | } |
565 | ||
566 | ret = sun6i_dma_cfg_lli(v_lli, src, dest, len, sconfig); | |
567 | if (ret) | |
568 | goto err_dma_free; | |
569 | ||
570 | v_lli->cfg |= DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | | |
571 | DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | | |
572 | DMA_CHAN_CFG_DST_LINEAR_MODE | | |
573 | DMA_CHAN_CFG_SRC_LINEAR_MODE; | |
574 | ||
575 | sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); | |
576 | ||
577 | sun6i_dma_dump_lli(vchan, v_lli); | |
578 | ||
579 | return vchan_tx_prep(&vchan->vc, &txd->vd, flags); | |
580 | ||
581 | err_dma_free: | |
582 | dma_pool_free(sdev->pool, v_lli, p_lli); | |
4fbd804e MR |
583 | err_txd_free: |
584 | kfree(txd); | |
55585930 MR |
585 | return NULL; |
586 | } | |
587 | ||
588 | static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( | |
589 | struct dma_chan *chan, struct scatterlist *sgl, | |
590 | unsigned int sg_len, enum dma_transfer_direction dir, | |
591 | unsigned long flags, void *context) | |
592 | { | |
593 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
594 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
595 | struct dma_slave_config *sconfig = &vchan->cfg; | |
596 | struct sun6i_dma_lli *v_lli, *prev = NULL; | |
597 | struct sun6i_desc *txd; | |
598 | struct scatterlist *sg; | |
599 | dma_addr_t p_lli; | |
600 | int i, ret; | |
601 | ||
602 | if (!sgl) | |
603 | return NULL; | |
604 | ||
605 | if (!is_slave_direction(dir)) { | |
606 | dev_err(chan2dev(chan), "Invalid DMA direction\n"); | |
607 | return NULL; | |
608 | } | |
609 | ||
610 | txd = kzalloc(sizeof(*txd), GFP_NOWAIT); | |
611 | if (!txd) | |
612 | return NULL; | |
613 | ||
614 | for_each_sg(sgl, sg, sg_len, i) { | |
615 | v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli); | |
4fbd804e MR |
616 | if (!v_lli) |
617 | goto err_lli_free; | |
55585930 MR |
618 | |
619 | if (dir == DMA_MEM_TO_DEV) { | |
620 | ret = sun6i_dma_cfg_lli(v_lli, sg_dma_address(sg), | |
621 | sconfig->dst_addr, sg_dma_len(sg), | |
622 | sconfig); | |
623 | if (ret) | |
4fbd804e | 624 | goto err_cur_lli_free; |
55585930 MR |
625 | |
626 | v_lli->cfg |= DMA_CHAN_CFG_DST_IO_MODE | | |
627 | DMA_CHAN_CFG_SRC_LINEAR_MODE | | |
628 | DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | | |
629 | DMA_CHAN_CFG_DST_DRQ(vchan->port); | |
630 | ||
631 | dev_dbg(chan2dev(chan), | |
7f5e03e7 | 632 | "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", |
55585930 MR |
633 | __func__, vchan->vc.chan.chan_id, |
634 | &sconfig->dst_addr, &sg_dma_address(sg), | |
635 | sg_dma_len(sg), flags); | |
636 | ||
637 | } else { | |
638 | ret = sun6i_dma_cfg_lli(v_lli, sconfig->src_addr, | |
639 | sg_dma_address(sg), sg_dma_len(sg), | |
640 | sconfig); | |
641 | if (ret) | |
4fbd804e | 642 | goto err_cur_lli_free; |
55585930 MR |
643 | |
644 | v_lli->cfg |= DMA_CHAN_CFG_DST_LINEAR_MODE | | |
645 | DMA_CHAN_CFG_SRC_IO_MODE | | |
646 | DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | | |
647 | DMA_CHAN_CFG_SRC_DRQ(vchan->port); | |
648 | ||
649 | dev_dbg(chan2dev(chan), | |
7f5e03e7 | 650 | "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", |
55585930 MR |
651 | __func__, vchan->vc.chan.chan_id, |
652 | &sg_dma_address(sg), &sconfig->src_addr, | |
653 | sg_dma_len(sg), flags); | |
654 | } | |
655 | ||
656 | prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); | |
657 | } | |
658 | ||
659 | dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli); | |
660 | for (prev = txd->v_lli; prev; prev = prev->v_lli_next) | |
661 | sun6i_dma_dump_lli(vchan, prev); | |
662 | ||
663 | return vchan_tx_prep(&vchan->vc, &txd->vd, flags); | |
664 | ||
4fbd804e | 665 | err_cur_lli_free: |
55585930 | 666 | dma_pool_free(sdev->pool, v_lli, p_lli); |
4fbd804e MR |
667 | err_lli_free: |
668 | for (prev = txd->v_lli; prev; prev = prev->v_lli_next) | |
669 | dma_pool_free(sdev->pool, prev, virt_to_phys(prev)); | |
670 | kfree(txd); | |
55585930 MR |
671 | return NULL; |
672 | } | |
673 | ||
674 | static int sun6i_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
675 | unsigned long arg) | |
676 | { | |
677 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
678 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
679 | struct sun6i_pchan *pchan = vchan->phy; | |
680 | unsigned long flags; | |
681 | int ret = 0; | |
682 | ||
683 | switch (cmd) { | |
684 | case DMA_RESUME: | |
685 | dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc); | |
686 | ||
687 | spin_lock_irqsave(&vchan->vc.lock, flags); | |
688 | ||
689 | if (pchan) { | |
690 | writel(DMA_CHAN_PAUSE_RESUME, | |
691 | pchan->base + DMA_CHAN_PAUSE); | |
692 | } else if (!list_empty(&vchan->vc.desc_issued)) { | |
693 | spin_lock(&sdev->lock); | |
694 | list_add_tail(&vchan->node, &sdev->pending); | |
695 | spin_unlock(&sdev->lock); | |
696 | } | |
697 | ||
698 | spin_unlock_irqrestore(&vchan->vc.lock, flags); | |
699 | break; | |
700 | ||
701 | case DMA_PAUSE: | |
702 | dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc); | |
703 | ||
704 | if (pchan) { | |
705 | writel(DMA_CHAN_PAUSE_PAUSE, | |
706 | pchan->base + DMA_CHAN_PAUSE); | |
707 | } else { | |
708 | spin_lock(&sdev->lock); | |
709 | list_del_init(&vchan->node); | |
710 | spin_unlock(&sdev->lock); | |
711 | } | |
712 | break; | |
713 | ||
714 | case DMA_TERMINATE_ALL: | |
715 | ret = sun6i_dma_terminate_all(vchan); | |
716 | break; | |
717 | case DMA_SLAVE_CONFIG: | |
718 | memcpy(&vchan->cfg, (void *)arg, sizeof(struct dma_slave_config)); | |
719 | break; | |
720 | default: | |
721 | ret = -ENXIO; | |
722 | break; | |
723 | } | |
724 | return ret; | |
725 | } | |
726 | ||
727 | static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan, | |
728 | dma_cookie_t cookie, | |
729 | struct dma_tx_state *state) | |
730 | { | |
731 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
732 | struct sun6i_pchan *pchan = vchan->phy; | |
733 | struct sun6i_dma_lli *lli; | |
734 | struct virt_dma_desc *vd; | |
735 | struct sun6i_desc *txd; | |
736 | enum dma_status ret; | |
737 | unsigned long flags; | |
738 | size_t bytes = 0; | |
739 | ||
740 | ret = dma_cookie_status(chan, cookie, state); | |
741 | if (ret == DMA_COMPLETE) | |
742 | return ret; | |
743 | ||
744 | spin_lock_irqsave(&vchan->vc.lock, flags); | |
745 | ||
746 | vd = vchan_find_desc(&vchan->vc, cookie); | |
747 | txd = to_sun6i_desc(&vd->tx); | |
748 | ||
749 | if (vd) { | |
750 | for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next) | |
751 | bytes += lli->len; | |
752 | } else if (!pchan || !pchan->desc) { | |
753 | bytes = 0; | |
754 | } else { | |
755 | bytes = readl(pchan->base + DMA_CHAN_CUR_CNT); | |
756 | } | |
757 | ||
758 | spin_unlock_irqrestore(&vchan->vc.lock, flags); | |
759 | ||
760 | dma_set_residue(state, bytes); | |
761 | ||
762 | return ret; | |
763 | } | |
764 | ||
765 | static void sun6i_dma_issue_pending(struct dma_chan *chan) | |
766 | { | |
767 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
768 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
769 | unsigned long flags; | |
770 | ||
771 | spin_lock_irqsave(&vchan->vc.lock, flags); | |
772 | ||
773 | if (vchan_issue_pending(&vchan->vc)) { | |
774 | spin_lock(&sdev->lock); | |
775 | ||
776 | if (!vchan->phy && list_empty(&vchan->node)) { | |
777 | list_add_tail(&vchan->node, &sdev->pending); | |
778 | tasklet_schedule(&sdev->task); | |
779 | dev_dbg(chan2dev(chan), "vchan %p: issued\n", | |
780 | &vchan->vc); | |
781 | } | |
782 | ||
783 | spin_unlock(&sdev->lock); | |
784 | } else { | |
785 | dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n", | |
786 | &vchan->vc); | |
787 | } | |
788 | ||
789 | spin_unlock_irqrestore(&vchan->vc.lock, flags); | |
790 | } | |
791 | ||
792 | static int sun6i_dma_alloc_chan_resources(struct dma_chan *chan) | |
793 | { | |
794 | return 0; | |
795 | } | |
796 | ||
797 | static void sun6i_dma_free_chan_resources(struct dma_chan *chan) | |
798 | { | |
799 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
800 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
801 | unsigned long flags; | |
802 | ||
803 | spin_lock_irqsave(&sdev->lock, flags); | |
804 | list_del_init(&vchan->node); | |
805 | spin_unlock_irqrestore(&sdev->lock, flags); | |
806 | ||
807 | vchan_free_chan_resources(&vchan->vc); | |
808 | } | |
809 | ||
810 | static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec, | |
811 | struct of_dma *ofdma) | |
812 | { | |
813 | struct sun6i_dma_dev *sdev = ofdma->of_dma_data; | |
814 | struct sun6i_vchan *vchan; | |
815 | struct dma_chan *chan; | |
816 | u8 port = dma_spec->args[0]; | |
817 | ||
25a37c2f | 818 | if (port > sdev->cfg->nr_max_requests) |
55585930 MR |
819 | return NULL; |
820 | ||
821 | chan = dma_get_any_slave_channel(&sdev->slave); | |
822 | if (!chan) | |
823 | return NULL; | |
824 | ||
825 | vchan = to_sun6i_vchan(chan); | |
826 | vchan->port = port; | |
827 | ||
828 | return chan; | |
829 | } | |
830 | ||
831 | static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) | |
832 | { | |
833 | /* Disable all interrupts from DMA */ | |
834 | writel(0, sdev->base + DMA_IRQ_EN(0)); | |
835 | writel(0, sdev->base + DMA_IRQ_EN(1)); | |
836 | ||
837 | /* Prevent spurious interrupts from scheduling the tasklet */ | |
838 | atomic_inc(&sdev->tasklet_shutdown); | |
839 | ||
174427c1 MR |
840 | /* Make sure we won't have any further interrupts */ |
841 | devm_free_irq(sdev->slave.dev, sdev->irq, sdev); | |
55585930 MR |
842 | |
843 | /* Actually prevent the tasklet from being scheduled */ | |
844 | tasklet_kill(&sdev->task); | |
845 | } | |
846 | ||
847 | static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev) | |
848 | { | |
849 | int i; | |
850 | ||
25a37c2f | 851 | for (i = 0; i < sdev->cfg->nr_max_vchans; i++) { |
55585930 MR |
852 | struct sun6i_vchan *vchan = &sdev->vchans[i]; |
853 | ||
854 | list_del(&vchan->vc.chan.device_node); | |
855 | tasklet_kill(&vchan->vc.task); | |
856 | } | |
857 | } | |
858 | ||
25a37c2f CYT |
859 | /* |
860 | * For A31: | |
861 | * | |
862 | * There's 16 physical channels that can work in parallel. | |
863 | * | |
864 | * However we have 30 different endpoints for our requests. | |
865 | * | |
866 | * Since the channels are able to handle only an unidirectional | |
867 | * transfer, we need to allocate more virtual channels so that | |
868 | * everyone can grab one channel. | |
869 | * | |
870 | * Some devices can't work in both direction (mostly because it | |
871 | * wouldn't make sense), so we have a bit fewer virtual channels than | |
872 | * 2 channels per endpoints. | |
873 | */ | |
874 | ||
875 | static struct sun6i_dma_config sun6i_a31_dma_cfg = { | |
876 | .nr_max_channels = 16, | |
877 | .nr_max_requests = 30, | |
878 | .nr_max_vchans = 53, | |
879 | }; | |
880 | ||
881 | static struct of_device_id sun6i_dma_match[] = { | |
882 | { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg }, | |
883 | { /* sentinel */ } | |
884 | }; | |
885 | ||
55585930 MR |
886 | static int sun6i_dma_probe(struct platform_device *pdev) |
887 | { | |
25a37c2f | 888 | const struct of_device_id *device; |
55585930 MR |
889 | struct sun6i_dma_dev *sdc; |
890 | struct resource *res; | |
55585930 MR |
891 | int ret, i; |
892 | ||
893 | sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); | |
894 | if (!sdc) | |
895 | return -ENOMEM; | |
896 | ||
25a37c2f CYT |
897 | device = of_match_device(sun6i_dma_match, &pdev->dev); |
898 | if (!device) | |
899 | return -ENODEV; | |
900 | sdc->cfg = device->data; | |
901 | ||
55585930 MR |
902 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
903 | sdc->base = devm_ioremap_resource(&pdev->dev, res); | |
904 | if (IS_ERR(sdc->base)) | |
905 | return PTR_ERR(sdc->base); | |
906 | ||
907 | sdc->irq = platform_get_irq(pdev, 0); | |
908 | if (sdc->irq < 0) { | |
909 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
910 | return sdc->irq; | |
911 | } | |
912 | ||
913 | sdc->clk = devm_clk_get(&pdev->dev, NULL); | |
914 | if (IS_ERR(sdc->clk)) { | |
915 | dev_err(&pdev->dev, "No clock specified\n"); | |
916 | return PTR_ERR(sdc->clk); | |
917 | } | |
918 | ||
55585930 MR |
919 | sdc->rstc = devm_reset_control_get(&pdev->dev, NULL); |
920 | if (IS_ERR(sdc->rstc)) { | |
921 | dev_err(&pdev->dev, "No reset controller specified\n"); | |
922 | return PTR_ERR(sdc->rstc); | |
923 | } | |
924 | ||
925 | sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev, | |
926 | sizeof(struct sun6i_dma_lli), 4, 0); | |
927 | if (!sdc->pool) { | |
928 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
929 | return -ENOMEM; | |
930 | } | |
931 | ||
932 | platform_set_drvdata(pdev, sdc); | |
933 | INIT_LIST_HEAD(&sdc->pending); | |
934 | spin_lock_init(&sdc->lock); | |
935 | ||
936 | dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask); | |
937 | dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask); | |
938 | dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask); | |
939 | ||
940 | INIT_LIST_HEAD(&sdc->slave.channels); | |
941 | sdc->slave.device_alloc_chan_resources = sun6i_dma_alloc_chan_resources; | |
942 | sdc->slave.device_free_chan_resources = sun6i_dma_free_chan_resources; | |
943 | sdc->slave.device_tx_status = sun6i_dma_tx_status; | |
944 | sdc->slave.device_issue_pending = sun6i_dma_issue_pending; | |
945 | sdc->slave.device_prep_slave_sg = sun6i_dma_prep_slave_sg; | |
946 | sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy; | |
947 | sdc->slave.device_control = sun6i_dma_control; | |
55585930 MR |
948 | |
949 | sdc->slave.dev = &pdev->dev; | |
950 | ||
25a37c2f | 951 | sdc->pchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_channels, |
55585930 MR |
952 | sizeof(struct sun6i_pchan), GFP_KERNEL); |
953 | if (!sdc->pchans) | |
954 | return -ENOMEM; | |
955 | ||
25a37c2f | 956 | sdc->vchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_vchans, |
55585930 MR |
957 | sizeof(struct sun6i_vchan), GFP_KERNEL); |
958 | if (!sdc->vchans) | |
959 | return -ENOMEM; | |
960 | ||
961 | tasklet_init(&sdc->task, sun6i_dma_tasklet, (unsigned long)sdc); | |
962 | ||
25a37c2f | 963 | for (i = 0; i < sdc->cfg->nr_max_channels; i++) { |
55585930 MR |
964 | struct sun6i_pchan *pchan = &sdc->pchans[i]; |
965 | ||
966 | pchan->idx = i; | |
967 | pchan->base = sdc->base + 0x100 + i * 0x40; | |
968 | } | |
969 | ||
25a37c2f | 970 | for (i = 0; i < sdc->cfg->nr_max_vchans; i++) { |
55585930 MR |
971 | struct sun6i_vchan *vchan = &sdc->vchans[i]; |
972 | ||
973 | INIT_LIST_HEAD(&vchan->node); | |
974 | vchan->vc.desc_free = sun6i_dma_free_desc; | |
975 | vchan_init(&vchan->vc, &sdc->slave); | |
976 | } | |
977 | ||
978 | ret = reset_control_deassert(sdc->rstc); | |
979 | if (ret) { | |
980 | dev_err(&pdev->dev, "Couldn't deassert the device from reset\n"); | |
981 | goto err_chan_free; | |
982 | } | |
983 | ||
984 | ret = clk_prepare_enable(sdc->clk); | |
985 | if (ret) { | |
986 | dev_err(&pdev->dev, "Couldn't enable the clock\n"); | |
987 | goto err_reset_assert; | |
988 | } | |
989 | ||
990 | ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0, | |
991 | dev_name(&pdev->dev), sdc); | |
992 | if (ret) { | |
993 | dev_err(&pdev->dev, "Cannot request IRQ\n"); | |
994 | goto err_clk_disable; | |
995 | } | |
996 | ||
997 | ret = dma_async_device_register(&sdc->slave); | |
998 | if (ret) { | |
999 | dev_warn(&pdev->dev, "Failed to register DMA engine device\n"); | |
1000 | goto err_irq_disable; | |
1001 | } | |
1002 | ||
1003 | ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate, | |
1004 | sdc); | |
1005 | if (ret) { | |
1006 | dev_err(&pdev->dev, "of_dma_controller_register failed\n"); | |
1007 | goto err_dma_unregister; | |
1008 | } | |
1009 | ||
1010 | return 0; | |
1011 | ||
1012 | err_dma_unregister: | |
1013 | dma_async_device_unregister(&sdc->slave); | |
1014 | err_irq_disable: | |
1015 | sun6i_kill_tasklet(sdc); | |
1016 | err_clk_disable: | |
1017 | clk_disable_unprepare(sdc->clk); | |
1018 | err_reset_assert: | |
1019 | reset_control_assert(sdc->rstc); | |
1020 | err_chan_free: | |
1021 | sun6i_dma_free(sdc); | |
1022 | return ret; | |
1023 | } | |
1024 | ||
1025 | static int sun6i_dma_remove(struct platform_device *pdev) | |
1026 | { | |
1027 | struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev); | |
1028 | ||
1029 | of_dma_controller_free(pdev->dev.of_node); | |
1030 | dma_async_device_unregister(&sdc->slave); | |
1031 | ||
1032 | sun6i_kill_tasklet(sdc); | |
1033 | ||
1034 | clk_disable_unprepare(sdc->clk); | |
1035 | reset_control_assert(sdc->rstc); | |
1036 | ||
1037 | sun6i_dma_free(sdc); | |
1038 | ||
1039 | return 0; | |
1040 | } | |
1041 | ||
55585930 MR |
1042 | static struct platform_driver sun6i_dma_driver = { |
1043 | .probe = sun6i_dma_probe, | |
1044 | .remove = sun6i_dma_remove, | |
1045 | .driver = { | |
1046 | .name = "sun6i-dma", | |
1047 | .of_match_table = sun6i_dma_match, | |
1048 | }, | |
1049 | }; | |
1050 | module_platform_driver(sun6i_dma_driver); | |
1051 | ||
1052 | MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver"); | |
1053 | MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>"); | |
1054 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
1055 | MODULE_LICENSE("GPL"); |