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55585930 MR |
1 | /* |
2 | * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd | |
3 | * Author: Sugar <shuge@allwinnertech.com> | |
4 | * | |
5 | * Copyright (C) 2014 Maxime Ripard | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dmapool.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of_dma.h> | |
25a37c2f | 21 | #include <linux/of_device.h> |
55585930 MR |
22 | #include <linux/platform_device.h> |
23 | #include <linux/reset.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/types.h> | |
26 | ||
27 | #include "virt-dma.h" | |
28 | ||
55585930 MR |
29 | /* |
30 | * Common registers | |
31 | */ | |
32 | #define DMA_IRQ_EN(x) ((x) * 0x04) | |
33 | #define DMA_IRQ_HALF BIT(0) | |
34 | #define DMA_IRQ_PKG BIT(1) | |
35 | #define DMA_IRQ_QUEUE BIT(2) | |
36 | ||
37 | #define DMA_IRQ_CHAN_NR 8 | |
38 | #define DMA_IRQ_CHAN_WIDTH 4 | |
39 | ||
40 | ||
41 | #define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10) | |
42 | ||
43 | #define DMA_STAT 0x30 | |
44 | ||
0b04ddf8 CYT |
45 | /* |
46 | * sun8i specific registers | |
47 | */ | |
48 | #define SUN8I_DMA_GATE 0x20 | |
49 | #define SUN8I_DMA_GATE_ENABLE 0x4 | |
50 | ||
55585930 MR |
51 | /* |
52 | * Channels specific registers | |
53 | */ | |
54 | #define DMA_CHAN_ENABLE 0x00 | |
55 | #define DMA_CHAN_ENABLE_START BIT(0) | |
56 | #define DMA_CHAN_ENABLE_STOP 0 | |
57 | ||
58 | #define DMA_CHAN_PAUSE 0x04 | |
59 | #define DMA_CHAN_PAUSE_PAUSE BIT(1) | |
60 | #define DMA_CHAN_PAUSE_RESUME 0 | |
61 | ||
62 | #define DMA_CHAN_LLI_ADDR 0x08 | |
63 | ||
64 | #define DMA_CHAN_CUR_CFG 0x0c | |
65 | #define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f) | |
66 | #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) | |
67 | #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) | |
68 | #define DMA_CHAN_CFG_SRC_BURST(x) (((x) & 0x3) << 7) | |
69 | #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) | |
70 | ||
71 | #define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) | |
72 | #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) | |
73 | #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) | |
74 | #define DMA_CHAN_CFG_DST_BURST(x) (DMA_CHAN_CFG_SRC_BURST(x) << 16) | |
75 | #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) | |
76 | ||
77 | #define DMA_CHAN_CUR_SRC 0x10 | |
78 | ||
79 | #define DMA_CHAN_CUR_DST 0x14 | |
80 | ||
81 | #define DMA_CHAN_CUR_CNT 0x18 | |
82 | ||
83 | #define DMA_CHAN_CUR_PARA 0x1c | |
84 | ||
85 | ||
86 | /* | |
87 | * Various hardware related defines | |
88 | */ | |
89 | #define LLI_LAST_ITEM 0xfffff800 | |
90 | #define NORMAL_WAIT 8 | |
91 | #define DRQ_SDRAM 1 | |
92 | ||
25a37c2f CYT |
93 | /* |
94 | * Hardware channels / ports representation | |
95 | * | |
96 | * The hardware is used in several SoCs, with differing numbers | |
97 | * of channels and endpoints. This structure ties those numbers | |
98 | * to a certain compatible string. | |
99 | */ | |
100 | struct sun6i_dma_config { | |
101 | u32 nr_max_channels; | |
102 | u32 nr_max_requests; | |
103 | u32 nr_max_vchans; | |
104 | }; | |
105 | ||
55585930 MR |
106 | /* |
107 | * Hardware representation of the LLI | |
108 | * | |
109 | * The hardware will be fed the physical address of this structure, | |
110 | * and read its content in order to start the transfer. | |
111 | */ | |
112 | struct sun6i_dma_lli { | |
113 | u32 cfg; | |
114 | u32 src; | |
115 | u32 dst; | |
116 | u32 len; | |
117 | u32 para; | |
118 | u32 p_lli_next; | |
119 | ||
120 | /* | |
121 | * This field is not used by the DMA controller, but will be | |
122 | * used by the CPU to go through the list (mostly for dumping | |
123 | * or freeing it). | |
124 | */ | |
125 | struct sun6i_dma_lli *v_lli_next; | |
126 | }; | |
127 | ||
128 | ||
129 | struct sun6i_desc { | |
130 | struct virt_dma_desc vd; | |
131 | dma_addr_t p_lli; | |
132 | struct sun6i_dma_lli *v_lli; | |
133 | }; | |
134 | ||
135 | struct sun6i_pchan { | |
136 | u32 idx; | |
137 | void __iomem *base; | |
138 | struct sun6i_vchan *vchan; | |
139 | struct sun6i_desc *desc; | |
140 | struct sun6i_desc *done; | |
141 | }; | |
142 | ||
143 | struct sun6i_vchan { | |
144 | struct virt_dma_chan vc; | |
145 | struct list_head node; | |
146 | struct dma_slave_config cfg; | |
147 | struct sun6i_pchan *phy; | |
148 | u8 port; | |
149 | }; | |
150 | ||
151 | struct sun6i_dma_dev { | |
152 | struct dma_device slave; | |
153 | void __iomem *base; | |
154 | struct clk *clk; | |
155 | int irq; | |
156 | spinlock_t lock; | |
157 | struct reset_control *rstc; | |
158 | struct tasklet_struct task; | |
159 | atomic_t tasklet_shutdown; | |
160 | struct list_head pending; | |
161 | struct dma_pool *pool; | |
162 | struct sun6i_pchan *pchans; | |
163 | struct sun6i_vchan *vchans; | |
25a37c2f | 164 | const struct sun6i_dma_config *cfg; |
55585930 MR |
165 | }; |
166 | ||
167 | static struct device *chan2dev(struct dma_chan *chan) | |
168 | { | |
169 | return &chan->dev->device; | |
170 | } | |
171 | ||
172 | static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d) | |
173 | { | |
174 | return container_of(d, struct sun6i_dma_dev, slave); | |
175 | } | |
176 | ||
177 | static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan) | |
178 | { | |
179 | return container_of(chan, struct sun6i_vchan, vc.chan); | |
180 | } | |
181 | ||
182 | static inline struct sun6i_desc * | |
183 | to_sun6i_desc(struct dma_async_tx_descriptor *tx) | |
184 | { | |
185 | return container_of(tx, struct sun6i_desc, vd.tx); | |
186 | } | |
187 | ||
188 | static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) | |
189 | { | |
190 | dev_dbg(sdev->slave.dev, "Common register:\n" | |
191 | "\tmask0(%04x): 0x%08x\n" | |
192 | "\tmask1(%04x): 0x%08x\n" | |
193 | "\tpend0(%04x): 0x%08x\n" | |
194 | "\tpend1(%04x): 0x%08x\n" | |
195 | "\tstats(%04x): 0x%08x\n", | |
196 | DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)), | |
197 | DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)), | |
198 | DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)), | |
199 | DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)), | |
200 | DMA_STAT, readl(sdev->base + DMA_STAT)); | |
201 | } | |
202 | ||
203 | static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev, | |
204 | struct sun6i_pchan *pchan) | |
205 | { | |
42c0d54e | 206 | phys_addr_t reg = virt_to_phys(pchan->base); |
55585930 MR |
207 | |
208 | dev_dbg(sdev->slave.dev, "Chan %d reg: %pa\n" | |
209 | "\t___en(%04x): \t0x%08x\n" | |
210 | "\tpause(%04x): \t0x%08x\n" | |
211 | "\tstart(%04x): \t0x%08x\n" | |
212 | "\t__cfg(%04x): \t0x%08x\n" | |
213 | "\t__src(%04x): \t0x%08x\n" | |
214 | "\t__dst(%04x): \t0x%08x\n" | |
215 | "\tcount(%04x): \t0x%08x\n" | |
216 | "\t_para(%04x): \t0x%08x\n\n", | |
217 | pchan->idx, ®, | |
218 | DMA_CHAN_ENABLE, | |
219 | readl(pchan->base + DMA_CHAN_ENABLE), | |
220 | DMA_CHAN_PAUSE, | |
221 | readl(pchan->base + DMA_CHAN_PAUSE), | |
222 | DMA_CHAN_LLI_ADDR, | |
223 | readl(pchan->base + DMA_CHAN_LLI_ADDR), | |
224 | DMA_CHAN_CUR_CFG, | |
225 | readl(pchan->base + DMA_CHAN_CUR_CFG), | |
226 | DMA_CHAN_CUR_SRC, | |
227 | readl(pchan->base + DMA_CHAN_CUR_SRC), | |
228 | DMA_CHAN_CUR_DST, | |
229 | readl(pchan->base + DMA_CHAN_CUR_DST), | |
230 | DMA_CHAN_CUR_CNT, | |
231 | readl(pchan->base + DMA_CHAN_CUR_CNT), | |
232 | DMA_CHAN_CUR_PARA, | |
233 | readl(pchan->base + DMA_CHAN_CUR_PARA)); | |
234 | } | |
235 | ||
1f9cd915 | 236 | static inline s8 convert_burst(u32 maxburst) |
55585930 MR |
237 | { |
238 | switch (maxburst) { | |
239 | case 1: | |
1f9cd915 | 240 | return 0; |
55585930 | 241 | case 8: |
1f9cd915 | 242 | return 2; |
55585930 MR |
243 | default: |
244 | return -EINVAL; | |
245 | } | |
55585930 MR |
246 | } |
247 | ||
1f9cd915 | 248 | static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width) |
55585930 | 249 | { |
92e4a3bf MR |
250 | if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) || |
251 | (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
55585930 | 252 | return -EINVAL; |
55585930 | 253 | |
1f9cd915 | 254 | return addr_width >> 1; |
55585930 MR |
255 | } |
256 | ||
257 | static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev, | |
258 | struct sun6i_dma_lli *next, | |
259 | dma_addr_t next_phy, | |
260 | struct sun6i_desc *txd) | |
261 | { | |
262 | if ((!prev && !txd) || !next) | |
263 | return NULL; | |
264 | ||
265 | if (!prev) { | |
266 | txd->p_lli = next_phy; | |
267 | txd->v_lli = next; | |
268 | } else { | |
269 | prev->p_lli_next = next_phy; | |
270 | prev->v_lli_next = next; | |
271 | } | |
272 | ||
273 | next->p_lli_next = LLI_LAST_ITEM; | |
274 | next->v_lli_next = NULL; | |
275 | ||
276 | return next; | |
277 | } | |
278 | ||
55585930 MR |
279 | static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan, |
280 | struct sun6i_dma_lli *lli) | |
281 | { | |
42c0d54e | 282 | phys_addr_t p_lli = virt_to_phys(lli); |
55585930 MR |
283 | |
284 | dev_dbg(chan2dev(&vchan->vc.chan), | |
285 | "\n\tdesc: p - %pa v - 0x%p\n" | |
286 | "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n" | |
287 | "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n", | |
288 | &p_lli, lli, | |
289 | lli->cfg, lli->src, lli->dst, | |
290 | lli->len, lli->para, lli->p_lli_next); | |
291 | } | |
292 | ||
293 | static void sun6i_dma_free_desc(struct virt_dma_desc *vd) | |
294 | { | |
295 | struct sun6i_desc *txd = to_sun6i_desc(&vd->tx); | |
296 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device); | |
297 | struct sun6i_dma_lli *v_lli, *v_next; | |
298 | dma_addr_t p_lli, p_next; | |
299 | ||
300 | if (unlikely(!txd)) | |
301 | return; | |
302 | ||
303 | p_lli = txd->p_lli; | |
304 | v_lli = txd->v_lli; | |
305 | ||
306 | while (v_lli) { | |
307 | v_next = v_lli->v_lli_next; | |
308 | p_next = v_lli->p_lli_next; | |
309 | ||
310 | dma_pool_free(sdev->pool, v_lli, p_lli); | |
311 | ||
312 | v_lli = v_next; | |
313 | p_lli = p_next; | |
314 | } | |
315 | ||
316 | kfree(txd); | |
317 | } | |
318 | ||
55585930 MR |
319 | static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) |
320 | { | |
321 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device); | |
322 | struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc); | |
323 | struct sun6i_pchan *pchan = vchan->phy; | |
324 | u32 irq_val, irq_reg, irq_offset; | |
325 | ||
326 | if (!pchan) | |
327 | return -EAGAIN; | |
328 | ||
329 | if (!desc) { | |
330 | pchan->desc = NULL; | |
331 | pchan->done = NULL; | |
332 | return -EAGAIN; | |
333 | } | |
334 | ||
335 | list_del(&desc->node); | |
336 | ||
337 | pchan->desc = to_sun6i_desc(&desc->tx); | |
338 | pchan->done = NULL; | |
339 | ||
340 | sun6i_dma_dump_lli(vchan, pchan->desc->v_lli); | |
341 | ||
342 | irq_reg = pchan->idx / DMA_IRQ_CHAN_NR; | |
343 | irq_offset = pchan->idx % DMA_IRQ_CHAN_NR; | |
344 | ||
128fe7e9 | 345 | irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg)); |
55585930 | 346 | irq_val |= DMA_IRQ_QUEUE << (irq_offset * DMA_IRQ_CHAN_WIDTH); |
128fe7e9 | 347 | writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); |
55585930 MR |
348 | |
349 | writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR); | |
350 | writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE); | |
351 | ||
352 | sun6i_dma_dump_com_regs(sdev); | |
353 | sun6i_dma_dump_chan_regs(sdev, pchan); | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static void sun6i_dma_tasklet(unsigned long data) | |
359 | { | |
360 | struct sun6i_dma_dev *sdev = (struct sun6i_dma_dev *)data; | |
25a37c2f | 361 | const struct sun6i_dma_config *cfg = sdev->cfg; |
55585930 MR |
362 | struct sun6i_vchan *vchan; |
363 | struct sun6i_pchan *pchan; | |
364 | unsigned int pchan_alloc = 0; | |
365 | unsigned int pchan_idx; | |
366 | ||
367 | list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) { | |
368 | spin_lock_irq(&vchan->vc.lock); | |
369 | ||
370 | pchan = vchan->phy; | |
371 | ||
372 | if (pchan && pchan->done) { | |
373 | if (sun6i_dma_start_desc(vchan)) { | |
374 | /* | |
375 | * No current txd associated with this channel | |
376 | */ | |
377 | dev_dbg(sdev->slave.dev, "pchan %u: free\n", | |
378 | pchan->idx); | |
379 | ||
380 | /* Mark this channel free */ | |
381 | vchan->phy = NULL; | |
382 | pchan->vchan = NULL; | |
383 | } | |
384 | } | |
385 | spin_unlock_irq(&vchan->vc.lock); | |
386 | } | |
387 | ||
388 | spin_lock_irq(&sdev->lock); | |
25a37c2f | 389 | for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) { |
55585930 MR |
390 | pchan = &sdev->pchans[pchan_idx]; |
391 | ||
392 | if (pchan->vchan || list_empty(&sdev->pending)) | |
393 | continue; | |
394 | ||
395 | vchan = list_first_entry(&sdev->pending, | |
396 | struct sun6i_vchan, node); | |
397 | ||
398 | /* Remove from pending channels */ | |
399 | list_del_init(&vchan->node); | |
400 | pchan_alloc |= BIT(pchan_idx); | |
401 | ||
402 | /* Mark this channel allocated */ | |
403 | pchan->vchan = vchan; | |
404 | vchan->phy = pchan; | |
405 | dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n", | |
406 | pchan->idx, &vchan->vc); | |
407 | } | |
408 | spin_unlock_irq(&sdev->lock); | |
409 | ||
25a37c2f | 410 | for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) { |
55585930 MR |
411 | if (!(pchan_alloc & BIT(pchan_idx))) |
412 | continue; | |
413 | ||
414 | pchan = sdev->pchans + pchan_idx; | |
415 | vchan = pchan->vchan; | |
416 | if (vchan) { | |
417 | spin_lock_irq(&vchan->vc.lock); | |
418 | sun6i_dma_start_desc(vchan); | |
419 | spin_unlock_irq(&vchan->vc.lock); | |
420 | } | |
421 | } | |
422 | } | |
423 | ||
424 | static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) | |
425 | { | |
426 | struct sun6i_dma_dev *sdev = dev_id; | |
427 | struct sun6i_vchan *vchan; | |
428 | struct sun6i_pchan *pchan; | |
429 | int i, j, ret = IRQ_NONE; | |
430 | u32 status; | |
431 | ||
25a37c2f | 432 | for (i = 0; i < sdev->cfg->nr_max_channels / DMA_IRQ_CHAN_NR; i++) { |
55585930 MR |
433 | status = readl(sdev->base + DMA_IRQ_STAT(i)); |
434 | if (!status) | |
435 | continue; | |
436 | ||
437 | dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n", | |
438 | i ? "high" : "low", status); | |
439 | ||
440 | writel(status, sdev->base + DMA_IRQ_STAT(i)); | |
441 | ||
25a37c2f | 442 | for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { |
55585930 MR |
443 | if (status & DMA_IRQ_QUEUE) { |
444 | pchan = sdev->pchans + j; | |
445 | vchan = pchan->vchan; | |
446 | ||
447 | if (vchan) { | |
448 | spin_lock(&vchan->vc.lock); | |
449 | vchan_cookie_complete(&pchan->desc->vd); | |
450 | pchan->done = pchan->desc; | |
451 | spin_unlock(&vchan->vc.lock); | |
452 | } | |
453 | } | |
454 | ||
25a37c2f | 455 | status = status >> DMA_IRQ_CHAN_WIDTH; |
55585930 MR |
456 | } |
457 | ||
458 | if (!atomic_read(&sdev->tasklet_shutdown)) | |
459 | tasklet_schedule(&sdev->task); | |
460 | ret = IRQ_HANDLED; | |
461 | } | |
462 | ||
463 | return ret; | |
464 | } | |
465 | ||
52c87179 JFM |
466 | static int set_config(struct sun6i_dma_dev *sdev, |
467 | struct dma_slave_config *sconfig, | |
468 | enum dma_transfer_direction direction, | |
469 | u32 *p_cfg) | |
470 | { | |
471 | s8 src_width, dst_width, src_burst, dst_burst; | |
472 | ||
a4eb36b0 JFM |
473 | switch (direction) { |
474 | case DMA_MEM_TO_DEV: | |
475 | src_burst = convert_burst(sconfig->src_maxburst ? | |
476 | sconfig->src_maxburst : 8); | |
477 | src_width = convert_buswidth(sconfig->src_addr_width != | |
478 | DMA_SLAVE_BUSWIDTH_UNDEFINED ? | |
479 | sconfig->src_addr_width : | |
480 | DMA_SLAVE_BUSWIDTH_4_BYTES); | |
481 | dst_burst = convert_burst(sconfig->dst_maxburst); | |
482 | dst_width = convert_buswidth(sconfig->dst_addr_width); | |
483 | break; | |
484 | case DMA_DEV_TO_MEM: | |
485 | src_burst = convert_burst(sconfig->src_maxburst); | |
486 | src_width = convert_buswidth(sconfig->src_addr_width); | |
487 | dst_burst = convert_burst(sconfig->dst_maxburst ? | |
488 | sconfig->dst_maxburst : 8); | |
489 | dst_width = convert_buswidth(sconfig->dst_addr_width != | |
490 | DMA_SLAVE_BUSWIDTH_UNDEFINED ? | |
491 | sconfig->dst_addr_width : | |
492 | DMA_SLAVE_BUSWIDTH_4_BYTES); | |
493 | break; | |
494 | default: | |
495 | return -EINVAL; | |
496 | } | |
52c87179 JFM |
497 | |
498 | if (src_burst < 0) | |
499 | return src_burst; | |
500 | if (src_width < 0) | |
501 | return src_width; | |
502 | if (dst_burst < 0) | |
503 | return dst_burst; | |
504 | if (dst_width < 0) | |
505 | return dst_width; | |
506 | ||
507 | *p_cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) | | |
508 | DMA_CHAN_CFG_SRC_WIDTH(src_width) | | |
509 | DMA_CHAN_CFG_DST_BURST(dst_burst) | | |
510 | DMA_CHAN_CFG_DST_WIDTH(dst_width); | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
55585930 MR |
515 | static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( |
516 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
517 | size_t len, unsigned long flags) | |
518 | { | |
519 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
520 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
55585930 MR |
521 | struct sun6i_dma_lli *v_lli; |
522 | struct sun6i_desc *txd; | |
523 | dma_addr_t p_lli; | |
1f9cd915 | 524 | s8 burst, width; |
55585930 MR |
525 | |
526 | dev_dbg(chan2dev(chan), | |
527 | "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n", | |
528 | __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags); | |
529 | ||
530 | if (!len) | |
531 | return NULL; | |
532 | ||
533 | txd = kzalloc(sizeof(*txd), GFP_NOWAIT); | |
534 | if (!txd) | |
535 | return NULL; | |
536 | ||
537 | v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli); | |
538 | if (!v_lli) { | |
539 | dev_err(sdev->slave.dev, "Failed to alloc lli memory\n"); | |
4fbd804e | 540 | goto err_txd_free; |
55585930 MR |
541 | } |
542 | ||
1f9cd915 MR |
543 | v_lli->src = src; |
544 | v_lli->dst = dest; | |
545 | v_lli->len = len; | |
546 | v_lli->para = NORMAL_WAIT; | |
55585930 | 547 | |
1f9cd915 MR |
548 | burst = convert_burst(8); |
549 | width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES); | |
55585930 MR |
550 | v_lli->cfg |= DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | |
551 | DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | | |
552 | DMA_CHAN_CFG_DST_LINEAR_MODE | | |
1f9cd915 MR |
553 | DMA_CHAN_CFG_SRC_LINEAR_MODE | |
554 | DMA_CHAN_CFG_SRC_BURST(burst) | | |
555 | DMA_CHAN_CFG_SRC_WIDTH(width) | | |
556 | DMA_CHAN_CFG_DST_BURST(burst) | | |
557 | DMA_CHAN_CFG_DST_WIDTH(width); | |
55585930 MR |
558 | |
559 | sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); | |
560 | ||
561 | sun6i_dma_dump_lli(vchan, v_lli); | |
562 | ||
563 | return vchan_tx_prep(&vchan->vc, &txd->vd, flags); | |
564 | ||
4fbd804e MR |
565 | err_txd_free: |
566 | kfree(txd); | |
55585930 MR |
567 | return NULL; |
568 | } | |
569 | ||
570 | static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( | |
571 | struct dma_chan *chan, struct scatterlist *sgl, | |
572 | unsigned int sg_len, enum dma_transfer_direction dir, | |
573 | unsigned long flags, void *context) | |
574 | { | |
575 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
576 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
577 | struct dma_slave_config *sconfig = &vchan->cfg; | |
578 | struct sun6i_dma_lli *v_lli, *prev = NULL; | |
579 | struct sun6i_desc *txd; | |
580 | struct scatterlist *sg; | |
581 | dma_addr_t p_lli; | |
52c87179 | 582 | u32 lli_cfg; |
55585930 MR |
583 | int i, ret; |
584 | ||
585 | if (!sgl) | |
586 | return NULL; | |
587 | ||
52c87179 JFM |
588 | ret = set_config(sdev, sconfig, dir, &lli_cfg); |
589 | if (ret) { | |
590 | dev_err(chan2dev(chan), "Invalid DMA configuration\n"); | |
591 | return NULL; | |
592 | } | |
593 | ||
55585930 MR |
594 | txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
595 | if (!txd) | |
596 | return NULL; | |
597 | ||
598 | for_each_sg(sgl, sg, sg_len, i) { | |
599 | v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli); | |
4fbd804e MR |
600 | if (!v_lli) |
601 | goto err_lli_free; | |
55585930 | 602 | |
52c87179 JFM |
603 | v_lli->len = sg_dma_len(sg); |
604 | v_lli->para = NORMAL_WAIT; | |
55585930 | 605 | |
52c87179 JFM |
606 | if (dir == DMA_MEM_TO_DEV) { |
607 | v_lli->src = sg_dma_address(sg); | |
608 | v_lli->dst = sconfig->dst_addr; | |
609 | v_lli->cfg = lli_cfg | | |
610 | DMA_CHAN_CFG_DST_IO_MODE | | |
55585930 MR |
611 | DMA_CHAN_CFG_SRC_LINEAR_MODE | |
612 | DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | | |
613 | DMA_CHAN_CFG_DST_DRQ(vchan->port); | |
614 | ||
615 | dev_dbg(chan2dev(chan), | |
7f5e03e7 | 616 | "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", |
55585930 MR |
617 | __func__, vchan->vc.chan.chan_id, |
618 | &sconfig->dst_addr, &sg_dma_address(sg), | |
619 | sg_dma_len(sg), flags); | |
620 | ||
621 | } else { | |
52c87179 JFM |
622 | v_lli->src = sconfig->src_addr; |
623 | v_lli->dst = sg_dma_address(sg); | |
624 | v_lli->cfg = lli_cfg | | |
625 | DMA_CHAN_CFG_DST_LINEAR_MODE | | |
55585930 MR |
626 | DMA_CHAN_CFG_SRC_IO_MODE | |
627 | DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | | |
628 | DMA_CHAN_CFG_SRC_DRQ(vchan->port); | |
629 | ||
630 | dev_dbg(chan2dev(chan), | |
7f5e03e7 | 631 | "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", |
55585930 MR |
632 | __func__, vchan->vc.chan.chan_id, |
633 | &sg_dma_address(sg), &sconfig->src_addr, | |
634 | sg_dma_len(sg), flags); | |
635 | } | |
636 | ||
637 | prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); | |
638 | } | |
639 | ||
640 | dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli); | |
641 | for (prev = txd->v_lli; prev; prev = prev->v_lli_next) | |
642 | sun6i_dma_dump_lli(vchan, prev); | |
643 | ||
644 | return vchan_tx_prep(&vchan->vc, &txd->vd, flags); | |
645 | ||
4fbd804e MR |
646 | err_lli_free: |
647 | for (prev = txd->v_lli; prev; prev = prev->v_lli_next) | |
648 | dma_pool_free(sdev->pool, prev, virt_to_phys(prev)); | |
649 | kfree(txd); | |
55585930 MR |
650 | return NULL; |
651 | } | |
652 | ||
826b15a7 MR |
653 | static int sun6i_dma_config(struct dma_chan *chan, |
654 | struct dma_slave_config *config) | |
655 | { | |
656 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
657 | ||
658 | memcpy(&vchan->cfg, config, sizeof(*config)); | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
663 | static int sun6i_dma_pause(struct dma_chan *chan) | |
664 | { | |
665 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
666 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
667 | struct sun6i_pchan *pchan = vchan->phy; | |
668 | ||
669 | dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc); | |
670 | ||
671 | if (pchan) { | |
672 | writel(DMA_CHAN_PAUSE_PAUSE, | |
673 | pchan->base + DMA_CHAN_PAUSE); | |
674 | } else { | |
675 | spin_lock(&sdev->lock); | |
676 | list_del_init(&vchan->node); | |
677 | spin_unlock(&sdev->lock); | |
678 | } | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | static int sun6i_dma_resume(struct dma_chan *chan) | |
55585930 MR |
684 | { |
685 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
686 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
687 | struct sun6i_pchan *pchan = vchan->phy; | |
688 | unsigned long flags; | |
55585930 | 689 | |
826b15a7 | 690 | dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc); |
55585930 | 691 | |
826b15a7 | 692 | spin_lock_irqsave(&vchan->vc.lock, flags); |
55585930 | 693 | |
826b15a7 MR |
694 | if (pchan) { |
695 | writel(DMA_CHAN_PAUSE_RESUME, | |
696 | pchan->base + DMA_CHAN_PAUSE); | |
697 | } else if (!list_empty(&vchan->vc.desc_issued)) { | |
698 | spin_lock(&sdev->lock); | |
699 | list_add_tail(&vchan->node, &sdev->pending); | |
700 | spin_unlock(&sdev->lock); | |
701 | } | |
55585930 | 702 | |
826b15a7 | 703 | spin_unlock_irqrestore(&vchan->vc.lock, flags); |
55585930 | 704 | |
826b15a7 MR |
705 | return 0; |
706 | } | |
55585930 | 707 | |
826b15a7 MR |
708 | static int sun6i_dma_terminate_all(struct dma_chan *chan) |
709 | { | |
710 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
711 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
712 | struct sun6i_pchan *pchan = vchan->phy; | |
713 | unsigned long flags; | |
714 | LIST_HEAD(head); | |
715 | ||
716 | spin_lock(&sdev->lock); | |
717 | list_del_init(&vchan->node); | |
718 | spin_unlock(&sdev->lock); | |
719 | ||
720 | spin_lock_irqsave(&vchan->vc.lock, flags); | |
721 | ||
722 | vchan_get_all_descriptors(&vchan->vc, &head); | |
723 | ||
724 | if (pchan) { | |
725 | writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE); | |
726 | writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE); | |
727 | ||
728 | vchan->phy = NULL; | |
729 | pchan->vchan = NULL; | |
730 | pchan->desc = NULL; | |
731 | pchan->done = NULL; | |
55585930 | 732 | } |
826b15a7 MR |
733 | |
734 | spin_unlock_irqrestore(&vchan->vc.lock, flags); | |
735 | ||
736 | vchan_dma_desc_free_list(&vchan->vc, &head); | |
737 | ||
738 | return 0; | |
55585930 MR |
739 | } |
740 | ||
741 | static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan, | |
742 | dma_cookie_t cookie, | |
743 | struct dma_tx_state *state) | |
744 | { | |
745 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
746 | struct sun6i_pchan *pchan = vchan->phy; | |
747 | struct sun6i_dma_lli *lli; | |
748 | struct virt_dma_desc *vd; | |
749 | struct sun6i_desc *txd; | |
750 | enum dma_status ret; | |
751 | unsigned long flags; | |
752 | size_t bytes = 0; | |
753 | ||
754 | ret = dma_cookie_status(chan, cookie, state); | |
755 | if (ret == DMA_COMPLETE) | |
756 | return ret; | |
757 | ||
758 | spin_lock_irqsave(&vchan->vc.lock, flags); | |
759 | ||
760 | vd = vchan_find_desc(&vchan->vc, cookie); | |
761 | txd = to_sun6i_desc(&vd->tx); | |
762 | ||
763 | if (vd) { | |
764 | for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next) | |
765 | bytes += lli->len; | |
766 | } else if (!pchan || !pchan->desc) { | |
767 | bytes = 0; | |
768 | } else { | |
769 | bytes = readl(pchan->base + DMA_CHAN_CUR_CNT); | |
770 | } | |
771 | ||
772 | spin_unlock_irqrestore(&vchan->vc.lock, flags); | |
773 | ||
774 | dma_set_residue(state, bytes); | |
775 | ||
776 | return ret; | |
777 | } | |
778 | ||
779 | static void sun6i_dma_issue_pending(struct dma_chan *chan) | |
780 | { | |
781 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
782 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
783 | unsigned long flags; | |
784 | ||
785 | spin_lock_irqsave(&vchan->vc.lock, flags); | |
786 | ||
787 | if (vchan_issue_pending(&vchan->vc)) { | |
788 | spin_lock(&sdev->lock); | |
789 | ||
790 | if (!vchan->phy && list_empty(&vchan->node)) { | |
791 | list_add_tail(&vchan->node, &sdev->pending); | |
792 | tasklet_schedule(&sdev->task); | |
793 | dev_dbg(chan2dev(chan), "vchan %p: issued\n", | |
794 | &vchan->vc); | |
795 | } | |
796 | ||
797 | spin_unlock(&sdev->lock); | |
798 | } else { | |
799 | dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n", | |
800 | &vchan->vc); | |
801 | } | |
802 | ||
803 | spin_unlock_irqrestore(&vchan->vc.lock, flags); | |
804 | } | |
805 | ||
55585930 MR |
806 | static void sun6i_dma_free_chan_resources(struct dma_chan *chan) |
807 | { | |
808 | struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); | |
809 | struct sun6i_vchan *vchan = to_sun6i_vchan(chan); | |
810 | unsigned long flags; | |
811 | ||
812 | spin_lock_irqsave(&sdev->lock, flags); | |
813 | list_del_init(&vchan->node); | |
814 | spin_unlock_irqrestore(&sdev->lock, flags); | |
815 | ||
816 | vchan_free_chan_resources(&vchan->vc); | |
817 | } | |
818 | ||
819 | static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec, | |
820 | struct of_dma *ofdma) | |
821 | { | |
822 | struct sun6i_dma_dev *sdev = ofdma->of_dma_data; | |
823 | struct sun6i_vchan *vchan; | |
824 | struct dma_chan *chan; | |
825 | u8 port = dma_spec->args[0]; | |
826 | ||
25a37c2f | 827 | if (port > sdev->cfg->nr_max_requests) |
55585930 MR |
828 | return NULL; |
829 | ||
830 | chan = dma_get_any_slave_channel(&sdev->slave); | |
831 | if (!chan) | |
832 | return NULL; | |
833 | ||
834 | vchan = to_sun6i_vchan(chan); | |
835 | vchan->port = port; | |
836 | ||
837 | return chan; | |
838 | } | |
839 | ||
840 | static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) | |
841 | { | |
842 | /* Disable all interrupts from DMA */ | |
843 | writel(0, sdev->base + DMA_IRQ_EN(0)); | |
844 | writel(0, sdev->base + DMA_IRQ_EN(1)); | |
845 | ||
846 | /* Prevent spurious interrupts from scheduling the tasklet */ | |
847 | atomic_inc(&sdev->tasklet_shutdown); | |
848 | ||
174427c1 MR |
849 | /* Make sure we won't have any further interrupts */ |
850 | devm_free_irq(sdev->slave.dev, sdev->irq, sdev); | |
55585930 MR |
851 | |
852 | /* Actually prevent the tasklet from being scheduled */ | |
853 | tasklet_kill(&sdev->task); | |
854 | } | |
855 | ||
856 | static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev) | |
857 | { | |
858 | int i; | |
859 | ||
25a37c2f | 860 | for (i = 0; i < sdev->cfg->nr_max_vchans; i++) { |
55585930 MR |
861 | struct sun6i_vchan *vchan = &sdev->vchans[i]; |
862 | ||
863 | list_del(&vchan->vc.chan.device_node); | |
864 | tasklet_kill(&vchan->vc.task); | |
865 | } | |
866 | } | |
867 | ||
25a37c2f CYT |
868 | /* |
869 | * For A31: | |
870 | * | |
871 | * There's 16 physical channels that can work in parallel. | |
872 | * | |
873 | * However we have 30 different endpoints for our requests. | |
874 | * | |
875 | * Since the channels are able to handle only an unidirectional | |
876 | * transfer, we need to allocate more virtual channels so that | |
877 | * everyone can grab one channel. | |
878 | * | |
879 | * Some devices can't work in both direction (mostly because it | |
880 | * wouldn't make sense), so we have a bit fewer virtual channels than | |
881 | * 2 channels per endpoints. | |
882 | */ | |
883 | ||
884 | static struct sun6i_dma_config sun6i_a31_dma_cfg = { | |
885 | .nr_max_channels = 16, | |
886 | .nr_max_requests = 30, | |
887 | .nr_max_vchans = 53, | |
888 | }; | |
889 | ||
0b04ddf8 CYT |
890 | /* |
891 | * The A23 only has 8 physical channels, a maximum DRQ port id of 24, | |
892 | * and a total of 37 usable source and destination endpoints. | |
893 | */ | |
894 | ||
895 | static struct sun6i_dma_config sun8i_a23_dma_cfg = { | |
896 | .nr_max_channels = 8, | |
897 | .nr_max_requests = 24, | |
898 | .nr_max_vchans = 37, | |
899 | }; | |
900 | ||
f008db8c JK |
901 | /* |
902 | * The H3 has 12 physical channels, a maximum DRQ port id of 27, | |
903 | * and a total of 34 usable source and destination endpoints. | |
904 | */ | |
905 | ||
906 | static struct sun6i_dma_config sun8i_h3_dma_cfg = { | |
907 | .nr_max_channels = 12, | |
908 | .nr_max_requests = 27, | |
909 | .nr_max_vchans = 34, | |
910 | }; | |
911 | ||
57c03422 | 912 | static const struct of_device_id sun6i_dma_match[] = { |
25a37c2f | 913 | { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg }, |
0b04ddf8 | 914 | { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg }, |
f008db8c | 915 | { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, |
25a37c2f CYT |
916 | { /* sentinel */ } |
917 | }; | |
c719d7fa | 918 | MODULE_DEVICE_TABLE(of, sun6i_dma_match); |
25a37c2f | 919 | |
55585930 MR |
920 | static int sun6i_dma_probe(struct platform_device *pdev) |
921 | { | |
25a37c2f | 922 | const struct of_device_id *device; |
55585930 MR |
923 | struct sun6i_dma_dev *sdc; |
924 | struct resource *res; | |
55585930 MR |
925 | int ret, i; |
926 | ||
927 | sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); | |
928 | if (!sdc) | |
929 | return -ENOMEM; | |
930 | ||
25a37c2f CYT |
931 | device = of_match_device(sun6i_dma_match, &pdev->dev); |
932 | if (!device) | |
933 | return -ENODEV; | |
934 | sdc->cfg = device->data; | |
935 | ||
55585930 MR |
936 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
937 | sdc->base = devm_ioremap_resource(&pdev->dev, res); | |
938 | if (IS_ERR(sdc->base)) | |
939 | return PTR_ERR(sdc->base); | |
940 | ||
941 | sdc->irq = platform_get_irq(pdev, 0); | |
942 | if (sdc->irq < 0) { | |
943 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
944 | return sdc->irq; | |
945 | } | |
946 | ||
947 | sdc->clk = devm_clk_get(&pdev->dev, NULL); | |
948 | if (IS_ERR(sdc->clk)) { | |
949 | dev_err(&pdev->dev, "No clock specified\n"); | |
950 | return PTR_ERR(sdc->clk); | |
951 | } | |
952 | ||
55585930 MR |
953 | sdc->rstc = devm_reset_control_get(&pdev->dev, NULL); |
954 | if (IS_ERR(sdc->rstc)) { | |
955 | dev_err(&pdev->dev, "No reset controller specified\n"); | |
956 | return PTR_ERR(sdc->rstc); | |
957 | } | |
958 | ||
959 | sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev, | |
960 | sizeof(struct sun6i_dma_lli), 4, 0); | |
961 | if (!sdc->pool) { | |
962 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
963 | return -ENOMEM; | |
964 | } | |
965 | ||
966 | platform_set_drvdata(pdev, sdc); | |
967 | INIT_LIST_HEAD(&sdc->pending); | |
968 | spin_lock_init(&sdc->lock); | |
969 | ||
970 | dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask); | |
971 | dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask); | |
972 | dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask); | |
973 | ||
974 | INIT_LIST_HEAD(&sdc->slave.channels); | |
55585930 MR |
975 | sdc->slave.device_free_chan_resources = sun6i_dma_free_chan_resources; |
976 | sdc->slave.device_tx_status = sun6i_dma_tx_status; | |
977 | sdc->slave.device_issue_pending = sun6i_dma_issue_pending; | |
978 | sdc->slave.device_prep_slave_sg = sun6i_dma_prep_slave_sg; | |
979 | sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy; | |
77a68e56 | 980 | sdc->slave.copy_align = DMAENGINE_ALIGN_4_BYTES; |
826b15a7 MR |
981 | sdc->slave.device_config = sun6i_dma_config; |
982 | sdc->slave.device_pause = sun6i_dma_pause; | |
983 | sdc->slave.device_resume = sun6i_dma_resume; | |
984 | sdc->slave.device_terminate_all = sun6i_dma_terminate_all; | |
1cac81b4 MR |
985 | sdc->slave.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | |
986 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | | |
987 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); | |
988 | sdc->slave.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | | |
989 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | | |
990 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); | |
991 | sdc->slave.directions = BIT(DMA_DEV_TO_MEM) | | |
992 | BIT(DMA_MEM_TO_DEV); | |
993 | sdc->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
55585930 MR |
994 | sdc->slave.dev = &pdev->dev; |
995 | ||
25a37c2f | 996 | sdc->pchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_channels, |
55585930 MR |
997 | sizeof(struct sun6i_pchan), GFP_KERNEL); |
998 | if (!sdc->pchans) | |
999 | return -ENOMEM; | |
1000 | ||
25a37c2f | 1001 | sdc->vchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_vchans, |
55585930 MR |
1002 | sizeof(struct sun6i_vchan), GFP_KERNEL); |
1003 | if (!sdc->vchans) | |
1004 | return -ENOMEM; | |
1005 | ||
1006 | tasklet_init(&sdc->task, sun6i_dma_tasklet, (unsigned long)sdc); | |
1007 | ||
25a37c2f | 1008 | for (i = 0; i < sdc->cfg->nr_max_channels; i++) { |
55585930 MR |
1009 | struct sun6i_pchan *pchan = &sdc->pchans[i]; |
1010 | ||
1011 | pchan->idx = i; | |
1012 | pchan->base = sdc->base + 0x100 + i * 0x40; | |
1013 | } | |
1014 | ||
25a37c2f | 1015 | for (i = 0; i < sdc->cfg->nr_max_vchans; i++) { |
55585930 MR |
1016 | struct sun6i_vchan *vchan = &sdc->vchans[i]; |
1017 | ||
1018 | INIT_LIST_HEAD(&vchan->node); | |
1019 | vchan->vc.desc_free = sun6i_dma_free_desc; | |
1020 | vchan_init(&vchan->vc, &sdc->slave); | |
1021 | } | |
1022 | ||
1023 | ret = reset_control_deassert(sdc->rstc); | |
1024 | if (ret) { | |
1025 | dev_err(&pdev->dev, "Couldn't deassert the device from reset\n"); | |
1026 | goto err_chan_free; | |
1027 | } | |
1028 | ||
1029 | ret = clk_prepare_enable(sdc->clk); | |
1030 | if (ret) { | |
1031 | dev_err(&pdev->dev, "Couldn't enable the clock\n"); | |
1032 | goto err_reset_assert; | |
1033 | } | |
1034 | ||
1035 | ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0, | |
1036 | dev_name(&pdev->dev), sdc); | |
1037 | if (ret) { | |
1038 | dev_err(&pdev->dev, "Cannot request IRQ\n"); | |
1039 | goto err_clk_disable; | |
1040 | } | |
1041 | ||
1042 | ret = dma_async_device_register(&sdc->slave); | |
1043 | if (ret) { | |
1044 | dev_warn(&pdev->dev, "Failed to register DMA engine device\n"); | |
1045 | goto err_irq_disable; | |
1046 | } | |
1047 | ||
1048 | ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate, | |
1049 | sdc); | |
1050 | if (ret) { | |
1051 | dev_err(&pdev->dev, "of_dma_controller_register failed\n"); | |
1052 | goto err_dma_unregister; | |
1053 | } | |
1054 | ||
0b04ddf8 CYT |
1055 | /* |
1056 | * sun8i variant requires us to toggle a dma gating register, | |
1057 | * as seen in Allwinner's SDK. This register is not documented | |
1058 | * in the A23 user manual. | |
1059 | */ | |
1060 | if (of_device_is_compatible(pdev->dev.of_node, | |
1061 | "allwinner,sun8i-a23-dma")) | |
1062 | writel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE); | |
1063 | ||
55585930 MR |
1064 | return 0; |
1065 | ||
1066 | err_dma_unregister: | |
1067 | dma_async_device_unregister(&sdc->slave); | |
1068 | err_irq_disable: | |
1069 | sun6i_kill_tasklet(sdc); | |
1070 | err_clk_disable: | |
1071 | clk_disable_unprepare(sdc->clk); | |
1072 | err_reset_assert: | |
1073 | reset_control_assert(sdc->rstc); | |
1074 | err_chan_free: | |
1075 | sun6i_dma_free(sdc); | |
1076 | return ret; | |
1077 | } | |
1078 | ||
1079 | static int sun6i_dma_remove(struct platform_device *pdev) | |
1080 | { | |
1081 | struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev); | |
1082 | ||
1083 | of_dma_controller_free(pdev->dev.of_node); | |
1084 | dma_async_device_unregister(&sdc->slave); | |
1085 | ||
1086 | sun6i_kill_tasklet(sdc); | |
1087 | ||
1088 | clk_disable_unprepare(sdc->clk); | |
1089 | reset_control_assert(sdc->rstc); | |
1090 | ||
1091 | sun6i_dma_free(sdc); | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
55585930 MR |
1096 | static struct platform_driver sun6i_dma_driver = { |
1097 | .probe = sun6i_dma_probe, | |
1098 | .remove = sun6i_dma_remove, | |
1099 | .driver = { | |
1100 | .name = "sun6i-dma", | |
1101 | .of_match_table = sun6i_dma_match, | |
1102 | }, | |
1103 | }; | |
1104 | module_platform_driver(sun6i_dma_driver); | |
1105 | ||
1106 | MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver"); | |
1107 | MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>"); | |
1108 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
1109 | MODULE_LICENSE("GPL"); |