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dma: tegra: use reset framework
[mirror_ubuntu-zesty-kernel.git] / drivers / dma / tegra20-apb-dma.c
CommitLineData
ec8a1586
LD		 1/*
2 * DMA driver for Nvidia's Tegra20 APB DMA controller.
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/bitops.h>
20#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/dmaengine.h>
23#include <linux/dma-mapping.h>
7331205a 24#include <linux/err.h>
ec8a1586
LD		 25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/mm.h>
29#include <linux/module.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/platform_device.h>
3065c194 33#include <linux/pm.h>
ec8a1586 34#include <linux/pm_runtime.h>
9aa433d2 35#include <linux/reset.h>
ec8a1586
LD		 36#include <linux/slab.h>
37
ec8a1586
LD		 38#include "dmaengine.h"
39
40#define TEGRA_APBDMA_GENERAL 0x0
41#define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
42
43#define TEGRA_APBDMA_CONTROL 0x010
44#define TEGRA_APBDMA_IRQ_MASK 0x01c
45#define TEGRA_APBDMA_IRQ_MASK_SET 0x020
46
47/* CSR register */
48#define TEGRA_APBDMA_CHAN_CSR 0x00
49#define TEGRA_APBDMA_CSR_ENB BIT(31)
50#define TEGRA_APBDMA_CSR_IE_EOC BIT(30)
51#define TEGRA_APBDMA_CSR_HOLD BIT(29)
52#define TEGRA_APBDMA_CSR_DIR BIT(28)
53#define TEGRA_APBDMA_CSR_ONCE BIT(27)
54#define TEGRA_APBDMA_CSR_FLOW BIT(21)
55#define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16
56#define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC
57
58/* STATUS register */
59#define TEGRA_APBDMA_CHAN_STATUS 0x004
60#define TEGRA_APBDMA_STATUS_BUSY BIT(31)
61#define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)
62#define TEGRA_APBDMA_STATUS_HALT BIT(29)
63#define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)
64#define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2
65#define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
66
1b140908
LD		 67#define TEGRA_APBDMA_CHAN_CSRE 0x00C
68#define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)
69
ec8a1586
LD		 70/* AHB memory address */
71#define TEGRA_APBDMA_CHAN_AHBPTR 0x010
72
73/* AHB sequence register */
74#define TEGRA_APBDMA_CHAN_AHBSEQ 0x14
75#define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)
76#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)
77#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)
78#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)
79#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)
80#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
81#define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)
82#define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)
83#define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)
84#define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)
85#define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)
86#define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16
87#define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0
88
89/* APB address */
90#define TEGRA_APBDMA_CHAN_APBPTR 0x018
91
92/* APB sequence register */
93#define TEGRA_APBDMA_CHAN_APBSEQ 0x01c
94#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28)
95#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
96#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
97#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28)
98#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
99#define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27)
100#define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16)
101
102/*
103 * If any burst is in flight and DMA paused then this is the time to complete
104 * on-flight burst and update DMA status register.
105 */
106#define TEGRA_APBDMA_BURST_COMPLETE_TIME 20
107
108/* Channel base address offset from APBDMA base address */
109#define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
110
111/* DMA channel register space size */
112#define TEGRA_APBDMA_CHANNEL_REGISTER_SIZE 0x20
113
114struct tegra_dma;
115
116/*
117 * tegra_dma_chip_data Tegra chip specific DMA data
118 * @nr_channels: Number of channels available in the controller.
119 * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
1b140908 120 * @support_channel_pause: Support channel wise pause of dma.
ec8a1586
LD		 121 */
122struct tegra_dma_chip_data {
123 int nr_channels;
124 int max_dma_count;
1b140908 125 bool support_channel_pause;
ec8a1586
LD		 126};
127
128/* DMA channel registers */
129struct tegra_dma_channel_regs {
130 unsigned long csr;
131 unsigned long ahb_ptr;
132 unsigned long apb_ptr;
133 unsigned long ahb_seq;
134 unsigned long apb_seq;
135};
136
137/*
138 * tegra_dma_sg_req: Dma request details to configure hardware. This
139 * contains the details for one transfer to configure DMA hw.
140 * The client's request for data transfer can be broken into multiple
141 * sub-transfer as per requester details and hw support.
142 * This sub transfer get added in the list of transfer and point to Tegra
143 * DMA descriptor which manages the transfer details.
144 */
145struct tegra_dma_sg_req {
146 struct tegra_dma_channel_regs ch_regs;
147 int req_len;
148 bool configured;
149 bool last_sg;
150 bool half_done;
151 struct list_head node;
152 struct tegra_dma_desc *dma_desc;
153};
154
155/*
156 * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
157 * This descriptor keep track of transfer status, callbacks and request
158 * counts etc.
159 */
160struct tegra_dma_desc {
161 struct dma_async_tx_descriptor txd;
162 int bytes_requested;
163 int bytes_transferred;
164 enum dma_status dma_status;
165 struct list_head node;
166 struct list_head tx_list;
167 struct list_head cb_node;
168 int cb_count;
169};
170
171struct tegra_dma_channel;
172
173typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
174 bool to_terminate);
175
176/* tegra_dma_channel: Channel specific information */
177struct tegra_dma_channel {
178 struct dma_chan dma_chan;
d0fc9054 179 char name[30];
ec8a1586
LD		 180 bool config_init;
181 int id;
182 int irq;
183 unsigned long chan_base_offset;
184 spinlock_t lock;
185 bool busy;
186 struct tegra_dma *tdma;
187 bool cyclic;
188
189 /* Different lists for managing the requests */
190 struct list_head free_sg_req;
191 struct list_head pending_sg_req;
192 struct list_head free_dma_desc;
193 struct list_head cb_desc;
194
195 /* ISR handler and tasklet for bottom half of isr handling */
196 dma_isr_handler isr_handler;
197 struct tasklet_struct tasklet;
198 dma_async_tx_callback callback;
199 void *callback_param;
200
201 /* Channel-slave specific configuration */
202 struct dma_slave_config dma_sconfig;
3065c194 203 struct tegra_dma_channel_regs channel_reg;
ec8a1586
LD		 204};
205
206/* tegra_dma: Tegra DMA specific information */
207struct tegra_dma {
208 struct dma_device dma_dev;
209 struct device *dev;
210 struct clk *dma_clk;
9aa433d2 211 struct reset_control *rst;
ec8a1586
LD		 212 spinlock_t global_lock;
213 void __iomem *base_addr;
83a1ef2e 214 const struct tegra_dma_chip_data *chip_data;
ec8a1586
LD		 215
216 /* Some register need to be cache before suspend */
217 u32 reg_gen;
218
219 /* Last member of the structure */
220 struct tegra_dma_channel channels[0];
221};
222
223static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
224{
225 writel(val, tdma->base_addr + reg);
226}
227
228static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
229{
230 return readl(tdma->base_addr + reg);
231}
232
233static inline void tdc_write(struct tegra_dma_channel *tdc,
234 u32 reg, u32 val)
235{
236 writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
237}
238
239static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
240{
241 return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
242}
243
244static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
245{
246 return container_of(dc, struct tegra_dma_channel, dma_chan);
247}
248
249static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
250 struct dma_async_tx_descriptor *td)
251{
252 return container_of(td, struct tegra_dma_desc, txd);
253}
254
255static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
256{
257 return &tdc->dma_chan.dev->device;
258}
259
260static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
261static int tegra_dma_runtime_suspend(struct device *dev);
262static int tegra_dma_runtime_resume(struct device *dev);
263
264/* Get DMA desc from free list, if not there then allocate it. */
265static struct tegra_dma_desc *tegra_dma_desc_get(
266 struct tegra_dma_channel *tdc)
267{
268 struct tegra_dma_desc *dma_desc;
269 unsigned long flags;
270
271 spin_lock_irqsave(&tdc->lock, flags);
272
273 /* Do not allocate if desc are waiting for ack */
274 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
275 if (async_tx_test_ack(&dma_desc->txd)) {
276 list_del(&dma_desc->node);
277 spin_unlock_irqrestore(&tdc->lock, flags);
b9bb37f5 278 dma_desc->txd.flags = 0;
ec8a1586
LD		 279 return dma_desc;
280 }
281 }
282
283 spin_unlock_irqrestore(&tdc->lock, flags);
284
285 /* Allocate DMA desc */
286 dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
287 if (!dma_desc) {
288 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
289 return NULL;
290 }
291
292 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
293 dma_desc->txd.tx_submit = tegra_dma_tx_submit;
294 dma_desc->txd.flags = 0;
295 return dma_desc;
296}
297
298static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
299 struct tegra_dma_desc *dma_desc)
300{
301 unsigned long flags;
302
303 spin_lock_irqsave(&tdc->lock, flags);
304 if (!list_empty(&dma_desc->tx_list))
305 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
306 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
307 spin_unlock_irqrestore(&tdc->lock, flags);
308}
309
310static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
311 struct tegra_dma_channel *tdc)
312{
313 struct tegra_dma_sg_req *sg_req = NULL;
314 unsigned long flags;
315
316 spin_lock_irqsave(&tdc->lock, flags);
317 if (!list_empty(&tdc->free_sg_req)) {
318 sg_req = list_first_entry(&tdc->free_sg_req,
319 typeof(*sg_req), node);
320 list_del(&sg_req->node);
321 spin_unlock_irqrestore(&tdc->lock, flags);
322 return sg_req;
323 }
324 spin_unlock_irqrestore(&tdc->lock, flags);
325
326 sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
327 if (!sg_req)
328 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
329 return sg_req;
330}
331
332static int tegra_dma_slave_config(struct dma_chan *dc,
333 struct dma_slave_config *sconfig)
334{
335 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
336
337 if (!list_empty(&tdc->pending_sg_req)) {
338 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
339 return -EBUSY;
340 }
341
342 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
343 tdc->config_init = true;
344 return 0;
345}
346
347static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
348 bool wait_for_burst_complete)
349{
350 struct tegra_dma *tdma = tdc->tdma;
351
352 spin_lock(&tdma->global_lock);
353 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
354 if (wait_for_burst_complete)
355 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
356}
357
358static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
359{
360 struct tegra_dma *tdma = tdc->tdma;
361
362 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
363 spin_unlock(&tdma->global_lock);
364}
365
1b140908
LD		 366static void tegra_dma_pause(struct tegra_dma_channel *tdc,
367 bool wait_for_burst_complete)
368{
369 struct tegra_dma *tdma = tdc->tdma;
370
371 if (tdma->chip_data->support_channel_pause) {
372 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
373 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
374 if (wait_for_burst_complete)
375 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
376 } else {
377 tegra_dma_global_pause(tdc, wait_for_burst_complete);
378 }
379}
380
381static void tegra_dma_resume(struct tegra_dma_channel *tdc)
382{
383 struct tegra_dma *tdma = tdc->tdma;
384
385 if (tdma->chip_data->support_channel_pause) {
386 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
387 } else {
388 tegra_dma_global_resume(tdc);
389 }
390}
391
ec8a1586
LD		 392static void tegra_dma_stop(struct tegra_dma_channel *tdc)
393{
394 u32 csr;
395 u32 status;
396
397 /* Disable interrupts */
398 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
399 csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
400 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
401
402 /* Disable DMA */
403 csr &= ~TEGRA_APBDMA_CSR_ENB;
404 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
405
406 /* Clear interrupt status if it is there */
407 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
408 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
409 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
410 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
411 }
412 tdc->busy = false;
413}
414
415static void tegra_dma_start(struct tegra_dma_channel *tdc,
416 struct tegra_dma_sg_req *sg_req)
417{
418 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
419
420 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
421 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
422 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
423 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
424 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
425
426 /* Start DMA */
427 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
428 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
429}
430
431static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
432 struct tegra_dma_sg_req *nsg_req)
433{
434 unsigned long status;
435
436 /*
437 * The DMA controller reloads the new configuration for next transfer
438 * after last burst of current transfer completes.
439 * If there is no IEC status then this makes sure that last burst
440 * has not be completed. There may be case that last burst is on
441 * flight and so it can complete but because DMA is paused, it
442 * will not generates interrupt as well as not reload the new
443 * configuration.
444 * If there is already IEC status then interrupt handler need to
445 * load new configuration.
446 */
1b140908 447 tegra_dma_pause(tdc, false);
ec8a1586
LD		 448 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
449
450 /*
451 * If interrupt is pending then do nothing as the ISR will handle
452 * the programing for new request.
453 */
454 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
455 dev_err(tdc2dev(tdc),
456 "Skipping new configuration as interrupt is pending\n");
1b140908 457 tegra_dma_resume(tdc);
ec8a1586
LD		 458 return;
459 }
460
461 /* Safe to program new configuration */
462 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
463 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
464 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
465 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
466 nsg_req->configured = true;
467
1b140908 468 tegra_dma_resume(tdc);
ec8a1586
LD		 469}
470
471static void tdc_start_head_req(struct tegra_dma_channel *tdc)
472{
473 struct tegra_dma_sg_req *sg_req;
474
475 if (list_empty(&tdc->pending_sg_req))
476 return;
477
478 sg_req = list_first_entry(&tdc->pending_sg_req,
479 typeof(*sg_req), node);
480 tegra_dma_start(tdc, sg_req);
481 sg_req->configured = true;
482 tdc->busy = true;
483}
484
485static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
486{
487 struct tegra_dma_sg_req *hsgreq;
488 struct tegra_dma_sg_req *hnsgreq;
489
490 if (list_empty(&tdc->pending_sg_req))
491 return;
492
493 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
494 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
495 hnsgreq = list_first_entry(&hsgreq->node,
496 typeof(*hnsgreq), node);
497 tegra_dma_configure_for_next(tdc, hnsgreq);
498 }
499}
500
501static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
502 struct tegra_dma_sg_req *sg_req, unsigned long status)
503{
504 return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
505}
506
507static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
508{
509 struct tegra_dma_sg_req *sgreq;
510 struct tegra_dma_desc *dma_desc;
511
512 while (!list_empty(&tdc->pending_sg_req)) {
513 sgreq = list_first_entry(&tdc->pending_sg_req,
514 typeof(*sgreq), node);
2cc44e63 515 list_move_tail(&sgreq->node, &tdc->free_sg_req);
ec8a1586
LD		 516 if (sgreq->last_sg) {
517 dma_desc = sgreq->dma_desc;
518 dma_desc->dma_status = DMA_ERROR;
519 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
520
521 /* Add in cb list if it is not there. */
522 if (!dma_desc->cb_count)
523 list_add_tail(&dma_desc->cb_node,
524 &tdc->cb_desc);
525 dma_desc->cb_count++;
526 }
527 }
528 tdc->isr_handler = NULL;
529}
530
531static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
532 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
533{
534 struct tegra_dma_sg_req *hsgreq = NULL;
535
536 if (list_empty(&tdc->pending_sg_req)) {
537 dev_err(tdc2dev(tdc), "Dma is running without req\n");
538 tegra_dma_stop(tdc);
539 return false;
540 }
541
542 /*
543 * Check that head req on list should be in flight.
544 * If it is not in flight then abort transfer as
545 * looping of transfer can not continue.
546 */
547 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
548 if (!hsgreq->configured) {
549 tegra_dma_stop(tdc);
550 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
551 tegra_dma_abort_all(tdc);
552 return false;
553 }
554
555 /* Configure next request */
556 if (!to_terminate)
557 tdc_configure_next_head_desc(tdc);
558 return true;
559}
560
561static void handle_once_dma_done(struct tegra_dma_channel *tdc,
562 bool to_terminate)
563{
564 struct tegra_dma_sg_req *sgreq;
565 struct tegra_dma_desc *dma_desc;
566
567 tdc->busy = false;
568 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
569 dma_desc = sgreq->dma_desc;
570 dma_desc->bytes_transferred += sgreq->req_len;
571
572 list_del(&sgreq->node);
573 if (sgreq->last_sg) {
00d696f5 574 dma_desc->dma_status = DMA_COMPLETE;
ec8a1586
LD		 575 dma_cookie_complete(&dma_desc->txd);
576 if (!dma_desc->cb_count)
577 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
578 dma_desc->cb_count++;
579 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
580 }
581 list_add_tail(&sgreq->node, &tdc->free_sg_req);
582
583 /* Do not start DMA if it is going to be terminate */
584 if (to_terminate || list_empty(&tdc->pending_sg_req))
585 return;
586
587 tdc_start_head_req(tdc);
588 return;
589}
590
591static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
592 bool to_terminate)
593{
594 struct tegra_dma_sg_req *sgreq;
595 struct tegra_dma_desc *dma_desc;
596 bool st;
597
598 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
599 dma_desc = sgreq->dma_desc;
600 dma_desc->bytes_transferred += sgreq->req_len;
601
602 /* Callback need to be call */
603 if (!dma_desc->cb_count)
604 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
605 dma_desc->cb_count++;
606
607 /* If not last req then put at end of pending list */
608 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
2cc44e63 609 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
ec8a1586
LD		 610 sgreq->configured = false;
611 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
612 if (!st)
613 dma_desc->dma_status = DMA_ERROR;
614 }
615 return;
616}
617
618static void tegra_dma_tasklet(unsigned long data)
619{
620 struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
621 dma_async_tx_callback callback = NULL;
622 void *callback_param = NULL;
623 struct tegra_dma_desc *dma_desc;
624 unsigned long flags;
625 int cb_count;
626
627 spin_lock_irqsave(&tdc->lock, flags);
628 while (!list_empty(&tdc->cb_desc)) {
629 dma_desc = list_first_entry(&tdc->cb_desc,
630 typeof(*dma_desc), cb_node);
631 list_del(&dma_desc->cb_node);
632 callback = dma_desc->txd.callback;
633 callback_param = dma_desc->txd.callback_param;
634 cb_count = dma_desc->cb_count;
635 dma_desc->cb_count = 0;
636 spin_unlock_irqrestore(&tdc->lock, flags);
637 while (cb_count-- && callback)
638 callback(callback_param);
639 spin_lock_irqsave(&tdc->lock, flags);
640 }
641 spin_unlock_irqrestore(&tdc->lock, flags);
642}
643
644static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
645{
646 struct tegra_dma_channel *tdc = dev_id;
647 unsigned long status;
648 unsigned long flags;
649
650 spin_lock_irqsave(&tdc->lock, flags);
651
652 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
653 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
654 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
655 tdc->isr_handler(tdc, false);
656 tasklet_schedule(&tdc->tasklet);
657 spin_unlock_irqrestore(&tdc->lock, flags);
658 return IRQ_HANDLED;
659 }
660
661 spin_unlock_irqrestore(&tdc->lock, flags);
662 dev_info(tdc2dev(tdc),
663 "Interrupt already served status 0x%08lx\n", status);
664 return IRQ_NONE;
665}
666
667static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
668{
669 struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
670 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
671 unsigned long flags;
672 dma_cookie_t cookie;
673
674 spin_lock_irqsave(&tdc->lock, flags);
675 dma_desc->dma_status = DMA_IN_PROGRESS;
676 cookie = dma_cookie_assign(&dma_desc->txd);
677 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
678 spin_unlock_irqrestore(&tdc->lock, flags);
679 return cookie;
680}
681
682static void tegra_dma_issue_pending(struct dma_chan *dc)
683{
684 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
685 unsigned long flags;
686
687 spin_lock_irqsave(&tdc->lock, flags);
688 if (list_empty(&tdc->pending_sg_req)) {
689 dev_err(tdc2dev(tdc), "No DMA request\n");
690 goto end;
691 }
692 if (!tdc->busy) {
693 tdc_start_head_req(tdc);
694
695 /* Continuous single mode: Configure next req */
696 if (tdc->cyclic) {
697 /*
698 * Wait for 1 burst time for configure DMA for
699 * next transfer.
700 */
701 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
702 tdc_configure_next_head_desc(tdc);
703 }
704 }
705end:
706 spin_unlock_irqrestore(&tdc->lock, flags);
707 return;
708}
709
710static void tegra_dma_terminate_all(struct dma_chan *dc)
711{
712 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
713 struct tegra_dma_sg_req *sgreq;
714 struct tegra_dma_desc *dma_desc;
715 unsigned long flags;
716 unsigned long status;
717 bool was_busy;
718
719 spin_lock_irqsave(&tdc->lock, flags);
720 if (list_empty(&tdc->pending_sg_req)) {
721 spin_unlock_irqrestore(&tdc->lock, flags);
722 return;
723 }
724
725 if (!tdc->busy)
726 goto skip_dma_stop;
727
728 /* Pause DMA before checking the queue status */
1b140908 729 tegra_dma_pause(tdc, true);
ec8a1586
LD		 730
731 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
732 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
733 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
734 tdc->isr_handler(tdc, true);
735 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
736 }
737
738 was_busy = tdc->busy;
739 tegra_dma_stop(tdc);
740
741 if (!list_empty(&tdc->pending_sg_req) && was_busy) {
742 sgreq = list_first_entry(&tdc->pending_sg_req,
743 typeof(*sgreq), node);
744 sgreq->dma_desc->bytes_transferred +=
745 get_current_xferred_count(tdc, sgreq, status);
746 }
1b140908 747 tegra_dma_resume(tdc);
ec8a1586
LD		 748
749skip_dma_stop:
750 tegra_dma_abort_all(tdc);
751
752 while (!list_empty(&tdc->cb_desc)) {
753 dma_desc = list_first_entry(&tdc->cb_desc,
754 typeof(*dma_desc), cb_node);
755 list_del(&dma_desc->cb_node);
756 dma_desc->cb_count = 0;
757 }
758 spin_unlock_irqrestore(&tdc->lock, flags);
759}
760
761static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
762 dma_cookie_t cookie, struct dma_tx_state *txstate)
763{
764 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
765 struct tegra_dma_desc *dma_desc;
766 struct tegra_dma_sg_req *sg_req;
767 enum dma_status ret;
768 unsigned long flags;
4a46ba36 769 unsigned int residual;
ec8a1586 770
ec8a1586 771 ret = dma_cookie_status(dc, cookie, txstate);
00d696f5 772 if (ret == DMA_COMPLETE)
ec8a1586 773 return ret;
0a0aee20
AS		 774
775 spin_lock_irqsave(&tdc->lock, flags);
ec8a1586
LD		 776
777 /* Check on wait_ack desc status */
778 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
779 if (dma_desc->txd.cookie == cookie) {
4a46ba36
LD		 780 residual = dma_desc->bytes_requested -
781 (dma_desc->bytes_transferred %
782 dma_desc->bytes_requested);
783 dma_set_residue(txstate, residual);
ec8a1586
LD		 784 ret = dma_desc->dma_status;
785 spin_unlock_irqrestore(&tdc->lock, flags);
786 return ret;
787 }
788 }
789
790 /* Check in pending list */
791 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
792 dma_desc = sg_req->dma_desc;
793 if (dma_desc->txd.cookie == cookie) {
4a46ba36
LD		 794 residual = dma_desc->bytes_requested -
795 (dma_desc->bytes_transferred %
796 dma_desc->bytes_requested);
797 dma_set_residue(txstate, residual);
ec8a1586
LD		 798 ret = dma_desc->dma_status;
799 spin_unlock_irqrestore(&tdc->lock, flags);
800 return ret;
801 }
802 }
803
804 dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
805 spin_unlock_irqrestore(&tdc->lock, flags);
806 return ret;
807}
808
809static int tegra_dma_device_control(struct dma_chan *dc, enum dma_ctrl_cmd cmd,
810 unsigned long arg)
811{
812 switch (cmd) {
813 case DMA_SLAVE_CONFIG:
814 return tegra_dma_slave_config(dc,
815 (struct dma_slave_config *)arg);
816
817 case DMA_TERMINATE_ALL:
818 tegra_dma_terminate_all(dc);
819 return 0;
820
821 default:
822 break;
823 }
824
825 return -ENXIO;
826}
827
828static inline int get_bus_width(struct tegra_dma_channel *tdc,
829 enum dma_slave_buswidth slave_bw)
830{
831 switch (slave_bw) {
832 case DMA_SLAVE_BUSWIDTH_1_BYTE:
833 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
834 case DMA_SLAVE_BUSWIDTH_2_BYTES:
835 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
836 case DMA_SLAVE_BUSWIDTH_4_BYTES:
837 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
838 case DMA_SLAVE_BUSWIDTH_8_BYTES:
839 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
840 default:
841 dev_warn(tdc2dev(tdc),
842 "slave bw is not supported, using 32bits\n");
843 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
844 }
845}
846
847static inline int get_burst_size(struct tegra_dma_channel *tdc,
848 u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
849{
850 int burst_byte;
851 int burst_ahb_width;
852
853 /*
854 * burst_size from client is in terms of the bus_width.
855 * convert them into AHB memory width which is 4 byte.
856 */
857 burst_byte = burst_size * slave_bw;
858 burst_ahb_width = burst_byte / 4;
859
860 /* If burst size is 0 then calculate the burst size based on length */
861 if (!burst_ahb_width) {
862 if (len & 0xF)
863 return TEGRA_APBDMA_AHBSEQ_BURST_1;
864 else if ((len >> 4) & 0x1)
865 return TEGRA_APBDMA_AHBSEQ_BURST_4;
866 else
867 return TEGRA_APBDMA_AHBSEQ_BURST_8;
868 }
869 if (burst_ahb_width < 4)
870 return TEGRA_APBDMA_AHBSEQ_BURST_1;
871 else if (burst_ahb_width < 8)
872 return TEGRA_APBDMA_AHBSEQ_BURST_4;
873 else
874 return TEGRA_APBDMA_AHBSEQ_BURST_8;
875}
876
877static int get_transfer_param(struct tegra_dma_channel *tdc,
878 enum dma_transfer_direction direction, unsigned long *apb_addr,
879 unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
880 enum dma_slave_buswidth *slave_bw)
881{
882
883 switch (direction) {
884 case DMA_MEM_TO_DEV:
885 *apb_addr = tdc->dma_sconfig.dst_addr;
886 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
887 *burst_size = tdc->dma_sconfig.dst_maxburst;
888 *slave_bw = tdc->dma_sconfig.dst_addr_width;
889 *csr = TEGRA_APBDMA_CSR_DIR;
890 return 0;
891
892 case DMA_DEV_TO_MEM:
893 *apb_addr = tdc->dma_sconfig.src_addr;
894 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
895 *burst_size = tdc->dma_sconfig.src_maxburst;
896 *slave_bw = tdc->dma_sconfig.src_addr_width;
897 *csr = 0;
898 return 0;
899
900 default:
901 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
902 return -EINVAL;
903 }
904 return -EINVAL;
905}
906
907static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
908 struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
909 enum dma_transfer_direction direction, unsigned long flags,
910 void *context)
911{
912 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
913 struct tegra_dma_desc *dma_desc;
914 unsigned int i;
915 struct scatterlist *sg;
916 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
917 struct list_head req_list;
918 struct tegra_dma_sg_req *sg_req = NULL;
919 u32 burst_size;
920 enum dma_slave_buswidth slave_bw;
921 int ret;
922
923 if (!tdc->config_init) {
924 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
925 return NULL;
926 }
927 if (sg_len < 1) {
928 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
929 return NULL;
930 }
931
932 ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
933 &burst_size, &slave_bw);
934 if (ret < 0)
935 return NULL;
936
937 INIT_LIST_HEAD(&req_list);
938
939 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
940 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
941 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
942 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
943
944 csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
945 csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
946 if (flags & DMA_PREP_INTERRUPT)
947 csr |= TEGRA_APBDMA_CSR_IE_EOC;
948
949 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
950
951 dma_desc = tegra_dma_desc_get(tdc);
952 if (!dma_desc) {
953 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
954 return NULL;
955 }
956 INIT_LIST_HEAD(&dma_desc->tx_list);
957 INIT_LIST_HEAD(&dma_desc->cb_node);
958 dma_desc->cb_count = 0;
959 dma_desc->bytes_requested = 0;
960 dma_desc->bytes_transferred = 0;
961 dma_desc->dma_status = DMA_IN_PROGRESS;
962
963 /* Make transfer requests */
964 for_each_sg(sgl, sg, sg_len, i) {
965 u32 len, mem;
966
597c8549 967 mem = sg_dma_address(sg);
ec8a1586
LD		 968 len = sg_dma_len(sg);
969
970 if ((len & 3) || (mem & 3) ||
971 (len > tdc->tdma->chip_data->max_dma_count)) {
972 dev_err(tdc2dev(tdc),
973 "Dma length/memory address is not supported\n");
974 tegra_dma_desc_put(tdc, dma_desc);
975 return NULL;
976 }
977
978 sg_req = tegra_dma_sg_req_get(tdc);
979 if (!sg_req) {
980 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
981 tegra_dma_desc_put(tdc, dma_desc);
982 return NULL;
983 }
984
985 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
986 dma_desc->bytes_requested += len;
987
988 sg_req->ch_regs.apb_ptr = apb_ptr;
989 sg_req->ch_regs.ahb_ptr = mem;
990 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
991 sg_req->ch_regs.apb_seq = apb_seq;
992 sg_req->ch_regs.ahb_seq = ahb_seq;
993 sg_req->configured = false;
994 sg_req->last_sg = false;
995 sg_req->dma_desc = dma_desc;
996 sg_req->req_len = len;
997
998 list_add_tail(&sg_req->node, &dma_desc->tx_list);
999 }
1000 sg_req->last_sg = true;
1001 if (flags & DMA_CTRL_ACK)
1002 dma_desc->txd.flags = DMA_CTRL_ACK;
1003
1004 /*
1005 * Make sure that mode should not be conflicting with currently
1006 * configured mode.
1007 */
1008 if (!tdc->isr_handler) {
1009 tdc->isr_handler = handle_once_dma_done;
1010 tdc->cyclic = false;
1011 } else {
1012 if (tdc->cyclic) {
1013 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1014 tegra_dma_desc_put(tdc, dma_desc);
1015 return NULL;
1016 }
1017 }
1018
1019 return &dma_desc->txd;
1020}
1021
404ff669 1022static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
ec8a1586
LD		 1023 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1024 size_t period_len, enum dma_transfer_direction direction,
ec8b5e48 1025 unsigned long flags, void *context)
ec8a1586
LD		 1026{
1027 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1028 struct tegra_dma_desc *dma_desc = NULL;
1029 struct tegra_dma_sg_req *sg_req = NULL;
1030 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1031 int len;
1032 size_t remain_len;
1033 dma_addr_t mem = buf_addr;
1034 u32 burst_size;
1035 enum dma_slave_buswidth slave_bw;
1036 int ret;
1037
1038 if (!buf_len || !period_len) {
1039 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1040 return NULL;
1041 }
1042
1043 if (!tdc->config_init) {
1044 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1045 return NULL;
1046 }
1047
1048 /*
1049 * We allow to take more number of requests till DMA is
1050 * not started. The driver will loop over all requests.
1051 * Once DMA is started then new requests can be queued only after
1052 * terminating the DMA.
1053 */
1054 if (tdc->busy) {
1055 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1056 return NULL;
1057 }
1058
1059 /*
1060 * We only support cycle transfer when buf_len is multiple of
1061 * period_len.
1062 */
1063 if (buf_len % period_len) {
1064 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1065 return NULL;
1066 }
1067
1068 len = period_len;
1069 if ((len & 3) || (buf_addr & 3) ||
1070 (len > tdc->tdma->chip_data->max_dma_count)) {
1071 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1072 return NULL;
1073 }
1074
1075 ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1076 &burst_size, &slave_bw);
1077 if (ret < 0)
1078 return NULL;
1079
1080
1081 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1082 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1083 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1084 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1085
b9bb37f5
LD		 1086 csr |= TEGRA_APBDMA_CSR_FLOW;
1087 if (flags & DMA_PREP_INTERRUPT)
1088 csr |= TEGRA_APBDMA_CSR_IE_EOC;
ec8a1586
LD		 1089 csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1090
1091 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1092
1093 dma_desc = tegra_dma_desc_get(tdc);
1094 if (!dma_desc) {
1095 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1096 return NULL;
1097 }
1098
1099 INIT_LIST_HEAD(&dma_desc->tx_list);
1100 INIT_LIST_HEAD(&dma_desc->cb_node);
1101 dma_desc->cb_count = 0;
1102
1103 dma_desc->bytes_transferred = 0;
1104 dma_desc->bytes_requested = buf_len;
1105 remain_len = buf_len;
1106
1107 /* Split transfer equal to period size */
1108 while (remain_len) {
1109 sg_req = tegra_dma_sg_req_get(tdc);
1110 if (!sg_req) {
1111 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1112 tegra_dma_desc_put(tdc, dma_desc);
1113 return NULL;
1114 }
1115
1116 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1117 sg_req->ch_regs.apb_ptr = apb_ptr;
1118 sg_req->ch_regs.ahb_ptr = mem;
1119 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
1120 sg_req->ch_regs.apb_seq = apb_seq;
1121 sg_req->ch_regs.ahb_seq = ahb_seq;
1122 sg_req->configured = false;
1123 sg_req->half_done = false;
1124 sg_req->last_sg = false;
1125 sg_req->dma_desc = dma_desc;
1126 sg_req->req_len = len;
1127
1128 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1129 remain_len -= len;
1130 mem += len;
1131 }
1132 sg_req->last_sg = true;
b9bb37f5
LD		 1133 if (flags & DMA_CTRL_ACK)
1134 dma_desc->txd.flags = DMA_CTRL_ACK;
ec8a1586
LD		 1135
1136 /*
1137 * Make sure that mode should not be conflicting with currently
1138 * configured mode.
1139 */
1140 if (!tdc->isr_handler) {
1141 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1142 tdc->cyclic = true;
1143 } else {
1144 if (!tdc->cyclic) {
1145 dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1146 tegra_dma_desc_put(tdc, dma_desc);
1147 return NULL;
1148 }
1149 }
1150
1151 return &dma_desc->txd;
1152}
1153
1154static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1155{
1156 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
ffc49306
LD		 1157 struct tegra_dma *tdma = tdc->tdma;
1158 int ret;
ec8a1586
LD		 1159
1160 dma_cookie_init(&tdc->dma_chan);
1161 tdc->config_init = false;
ffc49306
LD		 1162 ret = clk_prepare_enable(tdma->dma_clk);
1163 if (ret < 0)
1164 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1165 return ret;
ec8a1586
LD		 1166}
1167
1168static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1169{
1170 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
ffc49306 1171 struct tegra_dma *tdma = tdc->tdma;
ec8a1586
LD		 1172
1173 struct tegra_dma_desc *dma_desc;
1174 struct tegra_dma_sg_req *sg_req;
1175 struct list_head dma_desc_list;
1176 struct list_head sg_req_list;
1177 unsigned long flags;
1178
1179 INIT_LIST_HEAD(&dma_desc_list);
1180 INIT_LIST_HEAD(&sg_req_list);
1181
1182 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1183
1184 if (tdc->busy)
1185 tegra_dma_terminate_all(dc);
1186
1187 spin_lock_irqsave(&tdc->lock, flags);
1188 list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1189 list_splice_init(&tdc->free_sg_req, &sg_req_list);
1190 list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1191 INIT_LIST_HEAD(&tdc->cb_desc);
1192 tdc->config_init = false;
7bdc1e27 1193 tdc->isr_handler = NULL;
ec8a1586
LD		 1194 spin_unlock_irqrestore(&tdc->lock, flags);
1195
1196 while (!list_empty(&dma_desc_list)) {
1197 dma_desc = list_first_entry(&dma_desc_list,
1198 typeof(*dma_desc), node);
1199 list_del(&dma_desc->node);
1200 kfree(dma_desc);
1201 }
1202
1203 while (!list_empty(&sg_req_list)) {
1204 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1205 list_del(&sg_req->node);
1206 kfree(sg_req);
1207 }
ffc49306 1208 clk_disable_unprepare(tdma->dma_clk);
ec8a1586
LD		 1209}
1210
1211/* Tegra20 specific DMA controller information */
75f21631 1212static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
ec8a1586
LD		 1213 .nr_channels = 16,
1214 .max_dma_count = 1024UL * 64,
1b140908 1215 .support_channel_pause = false,
ec8a1586
LD		 1216};
1217
ec8a1586 1218/* Tegra30 specific DMA controller information */
75f21631 1219static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
ec8a1586
LD		 1220 .nr_channels = 32,
1221 .max_dma_count = 1024UL * 64,
1b140908 1222 .support_channel_pause = false,
ec8a1586
LD		 1223};
1224
5ea7caf3
LD		 1225/* Tegra114 specific DMA controller information */
1226static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1227 .nr_channels = 32,
1228 .max_dma_count = 1024UL * 64,
1229 .support_channel_pause = true,
1230};
1231
1232
4bf27b8b 1233static const struct of_device_id tegra_dma_of_match[] = {
ec8a1586 1234 {
5ea7caf3
LD		 1235 .compatible = "nvidia,tegra114-apbdma",
1236 .data = &tegra114_dma_chip_data,
1237 }, {
cd9092c6 1238 .compatible = "nvidia,tegra30-apbdma",
ec8a1586
LD		 1239 .data = &tegra30_dma_chip_data,
1240 }, {
cd9092c6 1241 .compatible = "nvidia,tegra20-apbdma",
ec8a1586
LD		 1242 .data = &tegra20_dma_chip_data,
1243 }, {
1244 },
1245};
1246MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
ec8a1586 1247
463a1f8b 1248static int tegra_dma_probe(struct platform_device *pdev)
ec8a1586
LD		 1249{
1250 struct resource *res;
1251 struct tegra_dma *tdma;
1252 int ret;
1253 int i;
83a1ef2e 1254 const struct tegra_dma_chip_data *cdata = NULL;
dc7badba 1255 const struct of_device_id *match;
ec8a1586 1256
dc7badba
SW		 1257 match = of_match_device(tegra_dma_of_match, &pdev->dev);
1258 if (!match) {
1259 dev_err(&pdev->dev, "Error: No device match found\n");
1260 return -ENODEV;
ec8a1586 1261 }
dc7badba 1262 cdata = match->data;
ec8a1586
LD		 1263
1264 tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1265 sizeof(struct tegra_dma_channel), GFP_KERNEL);
1266 if (!tdma) {
1267 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1268 return -ENOMEM;
1269 }
1270
1271 tdma->dev = &pdev->dev;
1272 tdma->chip_data = cdata;
1273 platform_set_drvdata(pdev, tdma);
1274
1275 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7331205a
TR		 1276 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1277 if (IS_ERR(tdma->base_addr))
1278 return PTR_ERR(tdma->base_addr);
ec8a1586
LD		 1279
1280 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1281 if (IS_ERR(tdma->dma_clk)) {
1282 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1283 return PTR_ERR(tdma->dma_clk);
1284 }
1285
9aa433d2
SW		 1286 tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1287 if (IS_ERR(tdma->rst)) {
1288 dev_err(&pdev->dev, "Error: Missing reset\n");
1289 return PTR_ERR(tdma->rst);
1290 }
1291
ec8a1586
LD		 1292 spin_lock_init(&tdma->global_lock);
1293
1294 pm_runtime_enable(&pdev->dev);
1295 if (!pm_runtime_enabled(&pdev->dev)) {
1296 ret = tegra_dma_runtime_resume(&pdev->dev);
1297 if (ret) {
1298 dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
1299 ret);
1300 goto err_pm_disable;
1301 }
1302 }
1303
ffc49306
LD		 1304 /* Enable clock before accessing registers */
1305 ret = clk_prepare_enable(tdma->dma_clk);
1306 if (ret < 0) {
1307 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1308 goto err_pm_disable;
1309 }
1310
ec8a1586 1311 /* Reset DMA controller */
9aa433d2 1312 reset_control_assert(tdma->rst);
ec8a1586 1313 udelay(2);
9aa433d2 1314 reset_control_deassert(tdma->rst);
ec8a1586
LD		 1315
1316 /* Enable global DMA registers */
1317 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1318 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1319 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1320
ffc49306
LD		 1321 clk_disable_unprepare(tdma->dma_clk);
1322
ec8a1586
LD		 1323 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1324 for (i = 0; i < cdata->nr_channels; i++) {
1325 struct tegra_dma_channel *tdc = &tdma->channels[i];
ec8a1586
LD		 1326
1327 tdc->chan_base_offset = TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1328 i * TEGRA_APBDMA_CHANNEL_REGISTER_SIZE;
1329
1330 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1331 if (!res) {
1332 ret = -EINVAL;
1333 dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1334 goto err_irq;
1335 }
1336 tdc->irq = res->start;
d0fc9054 1337 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
ec8a1586 1338 ret = devm_request_irq(&pdev->dev, tdc->irq,
d0fc9054 1339 tegra_dma_isr, 0, tdc->name, tdc);
ec8a1586
LD		 1340 if (ret) {
1341 dev_err(&pdev->dev,
1342 "request_irq failed with err %d channel %d\n",
ac7ae754 1343 ret, i);
ec8a1586
LD		 1344 goto err_irq;
1345 }
1346
1347 tdc->dma_chan.device = &tdma->dma_dev;
1348 dma_cookie_init(&tdc->dma_chan);
1349 list_add_tail(&tdc->dma_chan.device_node,
1350 &tdma->dma_dev.channels);
1351 tdc->tdma = tdma;
1352 tdc->id = i;
1353
1354 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1355 (unsigned long)tdc);
1356 spin_lock_init(&tdc->lock);
1357
1358 INIT_LIST_HEAD(&tdc->pending_sg_req);
1359 INIT_LIST_HEAD(&tdc->free_sg_req);
1360 INIT_LIST_HEAD(&tdc->free_dma_desc);
1361 INIT_LIST_HEAD(&tdc->cb_desc);
1362 }
1363
1364 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1365 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
46fb3f8e
LD		 1366 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1367
ec8a1586
LD		 1368 tdma->dma_dev.dev = &pdev->dev;
1369 tdma->dma_dev.device_alloc_chan_resources =
1370 tegra_dma_alloc_chan_resources;
1371 tdma->dma_dev.device_free_chan_resources =
1372 tegra_dma_free_chan_resources;
1373 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1374 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1375 tdma->dma_dev.device_control = tegra_dma_device_control;
1376 tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1377 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1378
1379 ret = dma_async_device_register(&tdma->dma_dev);
1380 if (ret < 0) {
1381 dev_err(&pdev->dev,
1382 "Tegra20 APB DMA driver registration failed %d\n", ret);
1383 goto err_irq;
1384 }
1385
1386 dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1387 cdata->nr_channels);
1388 return 0;
1389
1390err_irq:
1391 while (--i >= 0) {
1392 struct tegra_dma_channel *tdc = &tdma->channels[i];
1393 tasklet_kill(&tdc->tasklet);
1394 }
1395
1396err_pm_disable:
1397 pm_runtime_disable(&pdev->dev);
1398 if (!pm_runtime_status_suspended(&pdev->dev))
1399 tegra_dma_runtime_suspend(&pdev->dev);
1400 return ret;
1401}
1402
4bf27b8b 1403static int tegra_dma_remove(struct platform_device *pdev)
ec8a1586
LD		 1404{
1405 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1406 int i;
1407 struct tegra_dma_channel *tdc;
1408
1409 dma_async_device_unregister(&tdma->dma_dev);
1410
1411 for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1412 tdc = &tdma->channels[i];
1413 tasklet_kill(&tdc->tasklet);
1414 }
1415
1416 pm_runtime_disable(&pdev->dev);
1417 if (!pm_runtime_status_suspended(&pdev->dev))
1418 tegra_dma_runtime_suspend(&pdev->dev);
1419
1420 return 0;
1421}
1422
1423static int tegra_dma_runtime_suspend(struct device *dev)
1424{
1425 struct platform_device *pdev = to_platform_device(dev);
1426 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1427
56482ec0 1428 clk_disable_unprepare(tdma->dma_clk);
ec8a1586
LD		 1429 return 0;
1430}
1431
1432static int tegra_dma_runtime_resume(struct device *dev)
1433{
1434 struct platform_device *pdev = to_platform_device(dev);
1435 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1436 int ret;
1437
56482ec0 1438 ret = clk_prepare_enable(tdma->dma_clk);
ec8a1586
LD		 1439 if (ret < 0) {
1440 dev_err(dev, "clk_enable failed: %d\n", ret);
1441 return ret;
1442 }
1443 return 0;
1444}
1445
3065c194
LD		 1446#ifdef CONFIG_PM_SLEEP
1447static int tegra_dma_pm_suspend(struct device *dev)
1448{
1449 struct tegra_dma *tdma = dev_get_drvdata(dev);
1450 int i;
1451 int ret;
1452
1453 /* Enable clock before accessing register */
1454 ret = tegra_dma_runtime_resume(dev);
1455 if (ret < 0)
1456 return ret;
1457
1458 tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1459 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1460 struct tegra_dma_channel *tdc = &tdma->channels[i];
1461 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1462
1463 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1464 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1465 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1466 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1467 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1468 }
1469
1470 /* Disable clock */
1471 tegra_dma_runtime_suspend(dev);
1472 return 0;
1473}
1474
1475static int tegra_dma_pm_resume(struct device *dev)
1476{
1477 struct tegra_dma *tdma = dev_get_drvdata(dev);
1478 int i;
1479 int ret;
1480
1481 /* Enable clock before accessing register */
1482 ret = tegra_dma_runtime_resume(dev);
1483 if (ret < 0)
1484 return ret;
1485
1486 tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1487 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1488 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1489
1490 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1491 struct tegra_dma_channel *tdc = &tdma->channels[i];
1492 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1493
1494 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1495 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1496 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1497 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1498 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1499 (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1500 }
1501
1502 /* Disable clock */
1503 tegra_dma_runtime_suspend(dev);
1504 return 0;
1505}
1506#endif
1507
4bf27b8b 1508static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
ec8a1586
LD		 1509#ifdef CONFIG_PM_RUNTIME
1510 .runtime_suspend = tegra_dma_runtime_suspend,
1511 .runtime_resume = tegra_dma_runtime_resume,
1512#endif
3065c194 1513 SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
ec8a1586
LD		 1514};
1515
1516static struct platform_driver tegra_dmac_driver = {
1517 .driver = {
cd9092c6 1518 .name = "tegra-apbdma",
ec8a1586
LD		 1519 .owner = THIS_MODULE,
1520 .pm = &tegra_dma_dev_pm_ops,
dc7badba 1521 .of_match_table = tegra_dma_of_match,
ec8a1586
LD		 1522 },
1523 .probe = tegra_dma_probe,
a7d6e3ec 1524 .remove = tegra_dma_remove,
ec8a1586
LD		 1525};
1526
1527module_platform_driver(tegra_dmac_driver);
1528
1529MODULE_ALIAS("platform:tegra20-apbdma");
1530MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1531MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1532MODULE_LICENSE("GPL v2");
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