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dmaengine: tegra-apb: Remove unnecessary return statements and variables
[mirror_ubuntu-zesty-kernel.git] / drivers / dma / tegra20-apb-dma.c
CommitLineData
ec8a1586
LD		 1/*
2 * DMA driver for Nvidia's Tegra20 APB DMA controller.
3 *
996556c9 4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
ec8a1586
LD		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/bitops.h>
20#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/dmaengine.h>
23#include <linux/dma-mapping.h>
7331205a 24#include <linux/err.h>
ec8a1586
LD		 25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/mm.h>
29#include <linux/module.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
996556c9 32#include <linux/of_dma.h>
ec8a1586 33#include <linux/platform_device.h>
3065c194 34#include <linux/pm.h>
ec8a1586 35#include <linux/pm_runtime.h>
9aa433d2 36#include <linux/reset.h>
ec8a1586
LD		 37#include <linux/slab.h>
38
ec8a1586
LD		 39#include "dmaengine.h"
40
41#define TEGRA_APBDMA_GENERAL 0x0
42#define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
43
44#define TEGRA_APBDMA_CONTROL 0x010
45#define TEGRA_APBDMA_IRQ_MASK 0x01c
46#define TEGRA_APBDMA_IRQ_MASK_SET 0x020
47
48/* CSR register */
49#define TEGRA_APBDMA_CHAN_CSR 0x00
50#define TEGRA_APBDMA_CSR_ENB BIT(31)
51#define TEGRA_APBDMA_CSR_IE_EOC BIT(30)
52#define TEGRA_APBDMA_CSR_HOLD BIT(29)
53#define TEGRA_APBDMA_CSR_DIR BIT(28)
54#define TEGRA_APBDMA_CSR_ONCE BIT(27)
55#define TEGRA_APBDMA_CSR_FLOW BIT(21)
56#define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16
57#define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC
58
59/* STATUS register */
60#define TEGRA_APBDMA_CHAN_STATUS 0x004
61#define TEGRA_APBDMA_STATUS_BUSY BIT(31)
62#define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)
63#define TEGRA_APBDMA_STATUS_HALT BIT(29)
64#define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)
65#define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2
66#define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
67
1b140908
LD		 68#define TEGRA_APBDMA_CHAN_CSRE 0x00C
69#define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)
70
ec8a1586
LD		 71/* AHB memory address */
72#define TEGRA_APBDMA_CHAN_AHBPTR 0x010
73
74/* AHB sequence register */
75#define TEGRA_APBDMA_CHAN_AHBSEQ 0x14
76#define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)
77#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)
78#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)
79#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)
80#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)
81#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
82#define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)
83#define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)
84#define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)
85#define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)
86#define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)
87#define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16
88#define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0
89
90/* APB address */
91#define TEGRA_APBDMA_CHAN_APBPTR 0x018
92
93/* APB sequence register */
94#define TEGRA_APBDMA_CHAN_APBSEQ 0x01c
95#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28)
96#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
97#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
98#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28)
99#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
100#define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27)
101#define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16)
102
911daccc
LD		 103/* Tegra148 specific registers */
104#define TEGRA_APBDMA_CHAN_WCOUNT 0x20
105
106#define TEGRA_APBDMA_CHAN_WORD_TRANSFER 0x24
107
ec8a1586
LD		 108/*
109 * If any burst is in flight and DMA paused then this is the time to complete
110 * on-flight burst and update DMA status register.
111 */
112#define TEGRA_APBDMA_BURST_COMPLETE_TIME 20
113
114/* Channel base address offset from APBDMA base address */
115#define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
116
ec8a1586
LD		 117struct tegra_dma;
118
119/*
120 * tegra_dma_chip_data Tegra chip specific DMA data
121 * @nr_channels: Number of channels available in the controller.
911daccc 122 * @channel_reg_size: Channel register size/stride.
ec8a1586 123 * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
1b140908 124 * @support_channel_pause: Support channel wise pause of dma.
911daccc 125 * @support_separate_wcount_reg: Support separate word count register.
ec8a1586
LD		 126 */
127struct tegra_dma_chip_data {
128 int nr_channels;
911daccc 129 int channel_reg_size;
ec8a1586 130 int max_dma_count;
1b140908 131 bool support_channel_pause;
911daccc 132 bool support_separate_wcount_reg;
ec8a1586
LD		 133};
134
135/* DMA channel registers */
136struct tegra_dma_channel_regs {
137 unsigned long csr;
138 unsigned long ahb_ptr;
139 unsigned long apb_ptr;
140 unsigned long ahb_seq;
141 unsigned long apb_seq;
911daccc 142 unsigned long wcount;
ec8a1586
LD		 143};
144
145/*
146 * tegra_dma_sg_req: Dma request details to configure hardware. This
147 * contains the details for one transfer to configure DMA hw.
148 * The client's request for data transfer can be broken into multiple
149 * sub-transfer as per requester details and hw support.
150 * This sub transfer get added in the list of transfer and point to Tegra
151 * DMA descriptor which manages the transfer details.
152 */
153struct tegra_dma_sg_req {
154 struct tegra_dma_channel_regs ch_regs;
155 int req_len;
156 bool configured;
157 bool last_sg;
ec8a1586
LD		 158 struct list_head node;
159 struct tegra_dma_desc *dma_desc;
160};
161
162/*
163 * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
164 * This descriptor keep track of transfer status, callbacks and request
165 * counts etc.
166 */
167struct tegra_dma_desc {
168 struct dma_async_tx_descriptor txd;
169 int bytes_requested;
170 int bytes_transferred;
171 enum dma_status dma_status;
172 struct list_head node;
173 struct list_head tx_list;
174 struct list_head cb_node;
175 int cb_count;
176};
177
178struct tegra_dma_channel;
179
180typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
181 bool to_terminate);
182
183/* tegra_dma_channel: Channel specific information */
184struct tegra_dma_channel {
185 struct dma_chan dma_chan;
d0fc9054 186 char name[30];
ec8a1586
LD		 187 bool config_init;
188 int id;
189 int irq;
13a33286 190 void __iomem *chan_addr;
ec8a1586
LD		 191 spinlock_t lock;
192 bool busy;
193 struct tegra_dma *tdma;
194 bool cyclic;
195
196 /* Different lists for managing the requests */
197 struct list_head free_sg_req;
198 struct list_head pending_sg_req;
199 struct list_head free_dma_desc;
200 struct list_head cb_desc;
201
202 /* ISR handler and tasklet for bottom half of isr handling */
203 dma_isr_handler isr_handler;
204 struct tasklet_struct tasklet;
ec8a1586
LD		 205
206 /* Channel-slave specific configuration */
996556c9 207 unsigned int slave_id;
ec8a1586 208 struct dma_slave_config dma_sconfig;
3065c194 209 struct tegra_dma_channel_regs channel_reg;
ec8a1586
LD		 210};
211
212/* tegra_dma: Tegra DMA specific information */
213struct tegra_dma {
214 struct dma_device dma_dev;
215 struct device *dev;
216 struct clk *dma_clk;
9aa433d2 217 struct reset_control *rst;
ec8a1586
LD		 218 spinlock_t global_lock;
219 void __iomem *base_addr;
83a1ef2e 220 const struct tegra_dma_chip_data *chip_data;
ec8a1586
LD		 221
222 /* Some register need to be cache before suspend */
223 u32 reg_gen;
224
225 /* Last member of the structure */
226 struct tegra_dma_channel channels[0];
227};
228
229static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
230{
231 writel(val, tdma->base_addr + reg);
232}
233
234static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
235{
236 return readl(tdma->base_addr + reg);
237}
238
239static inline void tdc_write(struct tegra_dma_channel *tdc,
240 u32 reg, u32 val)
241{
13a33286 242 writel(val, tdc->chan_addr + reg);
ec8a1586
LD		 243}
244
245static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
246{
13a33286 247 return readl(tdc->chan_addr + reg);
ec8a1586
LD		 248}
249
250static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
251{
252 return container_of(dc, struct tegra_dma_channel, dma_chan);
253}
254
255static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
256 struct dma_async_tx_descriptor *td)
257{
258 return container_of(td, struct tegra_dma_desc, txd);
259}
260
261static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
262{
263 return &tdc->dma_chan.dev->device;
264}
265
266static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
267static int tegra_dma_runtime_suspend(struct device *dev);
268static int tegra_dma_runtime_resume(struct device *dev);
269
270/* Get DMA desc from free list, if not there then allocate it. */
271static struct tegra_dma_desc *tegra_dma_desc_get(
272 struct tegra_dma_channel *tdc)
273{
274 struct tegra_dma_desc *dma_desc;
275 unsigned long flags;
276
277 spin_lock_irqsave(&tdc->lock, flags);
278
279 /* Do not allocate if desc are waiting for ack */
280 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
281 if (async_tx_test_ack(&dma_desc->txd)) {
282 list_del(&dma_desc->node);
283 spin_unlock_irqrestore(&tdc->lock, flags);
b9bb37f5 284 dma_desc->txd.flags = 0;
ec8a1586
LD		 285 return dma_desc;
286 }
287 }
288
289 spin_unlock_irqrestore(&tdc->lock, flags);
290
291 /* Allocate DMA desc */
292 dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
293 if (!dma_desc) {
294 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
295 return NULL;
296 }
297
298 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
299 dma_desc->txd.tx_submit = tegra_dma_tx_submit;
300 dma_desc->txd.flags = 0;
301 return dma_desc;
302}
303
304static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
305 struct tegra_dma_desc *dma_desc)
306{
307 unsigned long flags;
308
309 spin_lock_irqsave(&tdc->lock, flags);
310 if (!list_empty(&dma_desc->tx_list))
311 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
312 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
313 spin_unlock_irqrestore(&tdc->lock, flags);
314}
315
316static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
317 struct tegra_dma_channel *tdc)
318{
319 struct tegra_dma_sg_req *sg_req = NULL;
320 unsigned long flags;
321
322 spin_lock_irqsave(&tdc->lock, flags);
323 if (!list_empty(&tdc->free_sg_req)) {
324 sg_req = list_first_entry(&tdc->free_sg_req,
325 typeof(*sg_req), node);
326 list_del(&sg_req->node);
327 spin_unlock_irqrestore(&tdc->lock, flags);
328 return sg_req;
329 }
330 spin_unlock_irqrestore(&tdc->lock, flags);
331
332 sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
333 if (!sg_req)
334 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
335 return sg_req;
336}
337
338static int tegra_dma_slave_config(struct dma_chan *dc,
339 struct dma_slave_config *sconfig)
340{
341 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
342
343 if (!list_empty(&tdc->pending_sg_req)) {
344 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
345 return -EBUSY;
346 }
347
348 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
996556c9
SW		 349 if (!tdc->slave_id)
350 tdc->slave_id = sconfig->slave_id;
ec8a1586
LD		 351 tdc->config_init = true;
352 return 0;
353}
354
355static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
356 bool wait_for_burst_complete)
357{
358 struct tegra_dma *tdma = tdc->tdma;
359
360 spin_lock(&tdma->global_lock);
361 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
362 if (wait_for_burst_complete)
363 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
364}
365
366static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
367{
368 struct tegra_dma *tdma = tdc->tdma;
369
370 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
371 spin_unlock(&tdma->global_lock);
372}
373
1b140908
LD		 374static void tegra_dma_pause(struct tegra_dma_channel *tdc,
375 bool wait_for_burst_complete)
376{
377 struct tegra_dma *tdma = tdc->tdma;
378
379 if (tdma->chip_data->support_channel_pause) {
380 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
381 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
382 if (wait_for_burst_complete)
383 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
384 } else {
385 tegra_dma_global_pause(tdc, wait_for_burst_complete);
386 }
387}
388
389static void tegra_dma_resume(struct tegra_dma_channel *tdc)
390{
391 struct tegra_dma *tdma = tdc->tdma;
392
393 if (tdma->chip_data->support_channel_pause) {
394 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
395 } else {
396 tegra_dma_global_resume(tdc);
397 }
398}
399
ec8a1586
LD		 400static void tegra_dma_stop(struct tegra_dma_channel *tdc)
401{
402 u32 csr;
403 u32 status;
404
405 /* Disable interrupts */
406 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
407 csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
408 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
409
410 /* Disable DMA */
411 csr &= ~TEGRA_APBDMA_CSR_ENB;
412 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
413
414 /* Clear interrupt status if it is there */
415 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
416 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
417 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
418 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
419 }
420 tdc->busy = false;
421}
422
423static void tegra_dma_start(struct tegra_dma_channel *tdc,
424 struct tegra_dma_sg_req *sg_req)
425{
426 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
427
428 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
429 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
430 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
431 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
432 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
911daccc
LD		 433 if (tdc->tdma->chip_data->support_separate_wcount_reg)
434 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount);
ec8a1586
LD		 435
436 /* Start DMA */
437 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
438 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
439}
440
441static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
442 struct tegra_dma_sg_req *nsg_req)
443{
444 unsigned long status;
445
446 /*
447 * The DMA controller reloads the new configuration for next transfer
448 * after last burst of current transfer completes.
449 * If there is no IEC status then this makes sure that last burst
450 * has not be completed. There may be case that last burst is on
451 * flight and so it can complete but because DMA is paused, it
452 * will not generates interrupt as well as not reload the new
453 * configuration.
454 * If there is already IEC status then interrupt handler need to
455 * load new configuration.
456 */
1b140908 457 tegra_dma_pause(tdc, false);
ec8a1586
LD		 458 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
459
460 /*
461 * If interrupt is pending then do nothing as the ISR will handle
462 * the programing for new request.
463 */
464 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
465 dev_err(tdc2dev(tdc),
466 "Skipping new configuration as interrupt is pending\n");
1b140908 467 tegra_dma_resume(tdc);
ec8a1586
LD		 468 return;
469 }
470
471 /* Safe to program new configuration */
472 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
473 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
911daccc
LD		 474 if (tdc->tdma->chip_data->support_separate_wcount_reg)
475 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
476 nsg_req->ch_regs.wcount);
ec8a1586
LD		 477 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
478 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
479 nsg_req->configured = true;
480
1b140908 481 tegra_dma_resume(tdc);
ec8a1586
LD		 482}
483
484static void tdc_start_head_req(struct tegra_dma_channel *tdc)
485{
486 struct tegra_dma_sg_req *sg_req;
487
488 if (list_empty(&tdc->pending_sg_req))
489 return;
490
491 sg_req = list_first_entry(&tdc->pending_sg_req,
492 typeof(*sg_req), node);
493 tegra_dma_start(tdc, sg_req);
494 sg_req->configured = true;
495 tdc->busy = true;
496}
497
498static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
499{
500 struct tegra_dma_sg_req *hsgreq;
501 struct tegra_dma_sg_req *hnsgreq;
502
503 if (list_empty(&tdc->pending_sg_req))
504 return;
505
506 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
507 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
508 hnsgreq = list_first_entry(&hsgreq->node,
509 typeof(*hnsgreq), node);
510 tegra_dma_configure_for_next(tdc, hnsgreq);
511 }
512}
513
514static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
515 struct tegra_dma_sg_req *sg_req, unsigned long status)
516{
517 return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
518}
519
520static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
521{
522 struct tegra_dma_sg_req *sgreq;
523 struct tegra_dma_desc *dma_desc;
524
525 while (!list_empty(&tdc->pending_sg_req)) {
526 sgreq = list_first_entry(&tdc->pending_sg_req,
527 typeof(*sgreq), node);
2cc44e63 528 list_move_tail(&sgreq->node, &tdc->free_sg_req);
ec8a1586
LD		 529 if (sgreq->last_sg) {
530 dma_desc = sgreq->dma_desc;
531 dma_desc->dma_status = DMA_ERROR;
532 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
533
534 /* Add in cb list if it is not there. */
535 if (!dma_desc->cb_count)
536 list_add_tail(&dma_desc->cb_node,
537 &tdc->cb_desc);
538 dma_desc->cb_count++;
539 }
540 }
541 tdc->isr_handler = NULL;
542}
543
544static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
545 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
546{
547 struct tegra_dma_sg_req *hsgreq = NULL;
548
549 if (list_empty(&tdc->pending_sg_req)) {
550 dev_err(tdc2dev(tdc), "Dma is running without req\n");
551 tegra_dma_stop(tdc);
552 return false;
553 }
554
555 /*
556 * Check that head req on list should be in flight.
557 * If it is not in flight then abort transfer as
558 * looping of transfer can not continue.
559 */
560 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
561 if (!hsgreq->configured) {
562 tegra_dma_stop(tdc);
563 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
564 tegra_dma_abort_all(tdc);
565 return false;
566 }
567
568 /* Configure next request */
569 if (!to_terminate)
570 tdc_configure_next_head_desc(tdc);
571 return true;
572}
573
574static void handle_once_dma_done(struct tegra_dma_channel *tdc,
575 bool to_terminate)
576{
577 struct tegra_dma_sg_req *sgreq;
578 struct tegra_dma_desc *dma_desc;
579
580 tdc->busy = false;
581 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
582 dma_desc = sgreq->dma_desc;
583 dma_desc->bytes_transferred += sgreq->req_len;
584
585 list_del(&sgreq->node);
586 if (sgreq->last_sg) {
00d696f5 587 dma_desc->dma_status = DMA_COMPLETE;
ec8a1586
LD		 588 dma_cookie_complete(&dma_desc->txd);
589 if (!dma_desc->cb_count)
590 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
591 dma_desc->cb_count++;
592 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
593 }
594 list_add_tail(&sgreq->node, &tdc->free_sg_req);
595
596 /* Do not start DMA if it is going to be terminate */
597 if (to_terminate || list_empty(&tdc->pending_sg_req))
598 return;
599
600 tdc_start_head_req(tdc);
ec8a1586
LD		 601}
602
603static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
604 bool to_terminate)
605{
606 struct tegra_dma_sg_req *sgreq;
607 struct tegra_dma_desc *dma_desc;
608 bool st;
609
610 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
611 dma_desc = sgreq->dma_desc;
612 dma_desc->bytes_transferred += sgreq->req_len;
613
614 /* Callback need to be call */
615 if (!dma_desc->cb_count)
616 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
617 dma_desc->cb_count++;
618
619 /* If not last req then put at end of pending list */
620 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
2cc44e63 621 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
ec8a1586
LD		 622 sgreq->configured = false;
623 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
624 if (!st)
625 dma_desc->dma_status = DMA_ERROR;
626 }
ec8a1586
LD		 627}
628
629static void tegra_dma_tasklet(unsigned long data)
630{
631 struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
632 dma_async_tx_callback callback = NULL;
633 void *callback_param = NULL;
634 struct tegra_dma_desc *dma_desc;
635 unsigned long flags;
636 int cb_count;
637
638 spin_lock_irqsave(&tdc->lock, flags);
639 while (!list_empty(&tdc->cb_desc)) {
640 dma_desc = list_first_entry(&tdc->cb_desc,
641 typeof(*dma_desc), cb_node);
642 list_del(&dma_desc->cb_node);
643 callback = dma_desc->txd.callback;
644 callback_param = dma_desc->txd.callback_param;
645 cb_count = dma_desc->cb_count;
646 dma_desc->cb_count = 0;
647 spin_unlock_irqrestore(&tdc->lock, flags);
648 while (cb_count-- && callback)
649 callback(callback_param);
650 spin_lock_irqsave(&tdc->lock, flags);
651 }
652 spin_unlock_irqrestore(&tdc->lock, flags);
653}
654
655static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
656{
657 struct tegra_dma_channel *tdc = dev_id;
658 unsigned long status;
659 unsigned long flags;
660
661 spin_lock_irqsave(&tdc->lock, flags);
662
663 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
664 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
665 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
666 tdc->isr_handler(tdc, false);
667 tasklet_schedule(&tdc->tasklet);
668 spin_unlock_irqrestore(&tdc->lock, flags);
669 return IRQ_HANDLED;
670 }
671
672 spin_unlock_irqrestore(&tdc->lock, flags);
673 dev_info(tdc2dev(tdc),
674 "Interrupt already served status 0x%08lx\n", status);
675 return IRQ_NONE;
676}
677
678static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
679{
680 struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
681 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
682 unsigned long flags;
683 dma_cookie_t cookie;
684
685 spin_lock_irqsave(&tdc->lock, flags);
686 dma_desc->dma_status = DMA_IN_PROGRESS;
687 cookie = dma_cookie_assign(&dma_desc->txd);
688 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
689 spin_unlock_irqrestore(&tdc->lock, flags);
690 return cookie;
691}
692
693static void tegra_dma_issue_pending(struct dma_chan *dc)
694{
695 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
696 unsigned long flags;
697
698 spin_lock_irqsave(&tdc->lock, flags);
699 if (list_empty(&tdc->pending_sg_req)) {
700 dev_err(tdc2dev(tdc), "No DMA request\n");
701 goto end;
702 }
703 if (!tdc->busy) {
704 tdc_start_head_req(tdc);
705
706 /* Continuous single mode: Configure next req */
707 if (tdc->cyclic) {
708 /*
709 * Wait for 1 burst time for configure DMA for
710 * next transfer.
711 */
712 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
713 tdc_configure_next_head_desc(tdc);
714 }
715 }
716end:
717 spin_unlock_irqrestore(&tdc->lock, flags);
ec8a1586
LD		 718}
719
a7c439a4 720static int tegra_dma_terminate_all(struct dma_chan *dc)
ec8a1586
LD		 721{
722 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
723 struct tegra_dma_sg_req *sgreq;
724 struct tegra_dma_desc *dma_desc;
725 unsigned long flags;
726 unsigned long status;
911daccc 727 unsigned long wcount;
ec8a1586
LD		 728 bool was_busy;
729
730 spin_lock_irqsave(&tdc->lock, flags);
731 if (list_empty(&tdc->pending_sg_req)) {
732 spin_unlock_irqrestore(&tdc->lock, flags);
a7c439a4 733 return 0;
ec8a1586
LD		 734 }
735
736 if (!tdc->busy)
737 goto skip_dma_stop;
738
739 /* Pause DMA before checking the queue status */
1b140908 740 tegra_dma_pause(tdc, true);
ec8a1586
LD		 741
742 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
743 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
744 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
745 tdc->isr_handler(tdc, true);
746 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
747 }
911daccc
LD		 748 if (tdc->tdma->chip_data->support_separate_wcount_reg)
749 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
750 else
751 wcount = status;
ec8a1586
LD		 752
753 was_busy = tdc->busy;
754 tegra_dma_stop(tdc);
755
756 if (!list_empty(&tdc->pending_sg_req) && was_busy) {
757 sgreq = list_first_entry(&tdc->pending_sg_req,
758 typeof(*sgreq), node);
759 sgreq->dma_desc->bytes_transferred +=
911daccc 760 get_current_xferred_count(tdc, sgreq, wcount);
ec8a1586 761 }
1b140908 762 tegra_dma_resume(tdc);
ec8a1586
LD		 763
764skip_dma_stop:
765 tegra_dma_abort_all(tdc);
766
767 while (!list_empty(&tdc->cb_desc)) {
768 dma_desc = list_first_entry(&tdc->cb_desc,
769 typeof(*dma_desc), cb_node);
770 list_del(&dma_desc->cb_node);
771 dma_desc->cb_count = 0;
772 }
773 spin_unlock_irqrestore(&tdc->lock, flags);
a7c439a4 774 return 0;
ec8a1586
LD		 775}
776
777static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
778 dma_cookie_t cookie, struct dma_tx_state *txstate)
779{
780 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
781 struct tegra_dma_desc *dma_desc;
782 struct tegra_dma_sg_req *sg_req;
783 enum dma_status ret;
784 unsigned long flags;
4a46ba36 785 unsigned int residual;
ec8a1586 786
ec8a1586 787 ret = dma_cookie_status(dc, cookie, txstate);
00d696f5 788 if (ret == DMA_COMPLETE)
ec8a1586 789 return ret;
0a0aee20
AS		 790
791 spin_lock_irqsave(&tdc->lock, flags);
ec8a1586
LD		 792
793 /* Check on wait_ack desc status */
794 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
795 if (dma_desc->txd.cookie == cookie) {
4a46ba36
LD		 796 residual = dma_desc->bytes_requested -
797 (dma_desc->bytes_transferred %
798 dma_desc->bytes_requested);
799 dma_set_residue(txstate, residual);
ec8a1586
LD		 800 ret = dma_desc->dma_status;
801 spin_unlock_irqrestore(&tdc->lock, flags);
802 return ret;
803 }
804 }
805
806 /* Check in pending list */
807 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
808 dma_desc = sg_req->dma_desc;
809 if (dma_desc->txd.cookie == cookie) {
4a46ba36
LD		 810 residual = dma_desc->bytes_requested -
811 (dma_desc->bytes_transferred %
812 dma_desc->bytes_requested);
813 dma_set_residue(txstate, residual);
ec8a1586
LD		 814 ret = dma_desc->dma_status;
815 spin_unlock_irqrestore(&tdc->lock, flags);
816 return ret;
817 }
818 }
819
820 dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
821 spin_unlock_irqrestore(&tdc->lock, flags);
822 return ret;
823}
824
ec8a1586
LD		 825static inline int get_bus_width(struct tegra_dma_channel *tdc,
826 enum dma_slave_buswidth slave_bw)
827{
828 switch (slave_bw) {
829 case DMA_SLAVE_BUSWIDTH_1_BYTE:
830 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
831 case DMA_SLAVE_BUSWIDTH_2_BYTES:
832 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
833 case DMA_SLAVE_BUSWIDTH_4_BYTES:
834 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
835 case DMA_SLAVE_BUSWIDTH_8_BYTES:
836 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
837 default:
838 dev_warn(tdc2dev(tdc),
839 "slave bw is not supported, using 32bits\n");
840 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
841 }
842}
843
844static inline int get_burst_size(struct tegra_dma_channel *tdc,
845 u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
846{
847 int burst_byte;
848 int burst_ahb_width;
849
850 /*
851 * burst_size from client is in terms of the bus_width.
852 * convert them into AHB memory width which is 4 byte.
853 */
854 burst_byte = burst_size * slave_bw;
855 burst_ahb_width = burst_byte / 4;
856
857 /* If burst size is 0 then calculate the burst size based on length */
858 if (!burst_ahb_width) {
859 if (len & 0xF)
860 return TEGRA_APBDMA_AHBSEQ_BURST_1;
861 else if ((len >> 4) & 0x1)
862 return TEGRA_APBDMA_AHBSEQ_BURST_4;
863 else
864 return TEGRA_APBDMA_AHBSEQ_BURST_8;
865 }
866 if (burst_ahb_width < 4)
867 return TEGRA_APBDMA_AHBSEQ_BURST_1;
868 else if (burst_ahb_width < 8)
869 return TEGRA_APBDMA_AHBSEQ_BURST_4;
870 else
871 return TEGRA_APBDMA_AHBSEQ_BURST_8;
872}
873
874static int get_transfer_param(struct tegra_dma_channel *tdc,
875 enum dma_transfer_direction direction, unsigned long *apb_addr,
876 unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
877 enum dma_slave_buswidth *slave_bw)
878{
879
880 switch (direction) {
881 case DMA_MEM_TO_DEV:
882 *apb_addr = tdc->dma_sconfig.dst_addr;
883 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
884 *burst_size = tdc->dma_sconfig.dst_maxburst;
885 *slave_bw = tdc->dma_sconfig.dst_addr_width;
886 *csr = TEGRA_APBDMA_CSR_DIR;
887 return 0;
888
889 case DMA_DEV_TO_MEM:
890 *apb_addr = tdc->dma_sconfig.src_addr;
891 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
892 *burst_size = tdc->dma_sconfig.src_maxburst;
893 *slave_bw = tdc->dma_sconfig.src_addr_width;
894 *csr = 0;
895 return 0;
896
897 default:
898 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
899 return -EINVAL;
900 }
901 return -EINVAL;
902}
903
911daccc
LD		 904static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
905 struct tegra_dma_channel_regs *ch_regs, u32 len)
906{
907 u32 len_field = (len - 4) & 0xFFFC;
908
909 if (tdc->tdma->chip_data->support_separate_wcount_reg)
910 ch_regs->wcount = len_field;
911 else
912 ch_regs->csr |= len_field;
913}
914
ec8a1586
LD		 915static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
916 struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
917 enum dma_transfer_direction direction, unsigned long flags,
918 void *context)
919{
920 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
921 struct tegra_dma_desc *dma_desc;
922 unsigned int i;
923 struct scatterlist *sg;
924 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
925 struct list_head req_list;
926 struct tegra_dma_sg_req *sg_req = NULL;
927 u32 burst_size;
928 enum dma_slave_buswidth slave_bw;
ec8a1586
LD		 929
930 if (!tdc->config_init) {
931 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
932 return NULL;
933 }
934 if (sg_len < 1) {
935 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
936 return NULL;
937 }
938
dc1ff4b3
JH		 939 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
940 &burst_size, &slave_bw) < 0)
ec8a1586
LD		 941 return NULL;
942
943 INIT_LIST_HEAD(&req_list);
944
945 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
946 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
947 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
948 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
949
950 csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
996556c9 951 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
ec8a1586
LD		 952 if (flags & DMA_PREP_INTERRUPT)
953 csr |= TEGRA_APBDMA_CSR_IE_EOC;
954
955 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
956
957 dma_desc = tegra_dma_desc_get(tdc);
958 if (!dma_desc) {
959 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
960 return NULL;
961 }
962 INIT_LIST_HEAD(&dma_desc->tx_list);
963 INIT_LIST_HEAD(&dma_desc->cb_node);
964 dma_desc->cb_count = 0;
965 dma_desc->bytes_requested = 0;
966 dma_desc->bytes_transferred = 0;
967 dma_desc->dma_status = DMA_IN_PROGRESS;
968
969 /* Make transfer requests */
970 for_each_sg(sgl, sg, sg_len, i) {
971 u32 len, mem;
972
597c8549 973 mem = sg_dma_address(sg);
ec8a1586
LD		 974 len = sg_dma_len(sg);
975
976 if ((len & 3) || (mem & 3) ||
977 (len > tdc->tdma->chip_data->max_dma_count)) {
978 dev_err(tdc2dev(tdc),
979 "Dma length/memory address is not supported\n");
980 tegra_dma_desc_put(tdc, dma_desc);
981 return NULL;
982 }
983
984 sg_req = tegra_dma_sg_req_get(tdc);
985 if (!sg_req) {
986 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
987 tegra_dma_desc_put(tdc, dma_desc);
988 return NULL;
989 }
990
991 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
992 dma_desc->bytes_requested += len;
993
994 sg_req->ch_regs.apb_ptr = apb_ptr;
995 sg_req->ch_regs.ahb_ptr = mem;
911daccc
LD		 996 sg_req->ch_regs.csr = csr;
997 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
ec8a1586
LD		 998 sg_req->ch_regs.apb_seq = apb_seq;
999 sg_req->ch_regs.ahb_seq = ahb_seq;
1000 sg_req->configured = false;
1001 sg_req->last_sg = false;
1002 sg_req->dma_desc = dma_desc;
1003 sg_req->req_len = len;
1004
1005 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1006 }
1007 sg_req->last_sg = true;
1008 if (flags & DMA_CTRL_ACK)
1009 dma_desc->txd.flags = DMA_CTRL_ACK;
1010
1011 /*
1012 * Make sure that mode should not be conflicting with currently
1013 * configured mode.
1014 */
1015 if (!tdc->isr_handler) {
1016 tdc->isr_handler = handle_once_dma_done;
1017 tdc->cyclic = false;
1018 } else {
1019 if (tdc->cyclic) {
1020 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1021 tegra_dma_desc_put(tdc, dma_desc);
1022 return NULL;
1023 }
1024 }
1025
1026 return &dma_desc->txd;
1027}
1028
404ff669 1029static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
ec8a1586
LD		 1030 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1031 size_t period_len, enum dma_transfer_direction direction,
31c1e5a1 1032 unsigned long flags)
ec8a1586
LD		 1033{
1034 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1035 struct tegra_dma_desc *dma_desc = NULL;
1036 struct tegra_dma_sg_req *sg_req = NULL;
1037 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1038 int len;
1039 size_t remain_len;
1040 dma_addr_t mem = buf_addr;
1041 u32 burst_size;
1042 enum dma_slave_buswidth slave_bw;
ec8a1586
LD		 1043
1044 if (!buf_len || !period_len) {
1045 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1046 return NULL;
1047 }
1048
1049 if (!tdc->config_init) {
1050 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1051 return NULL;
1052 }
1053
1054 /*
1055 * We allow to take more number of requests till DMA is
1056 * not started. The driver will loop over all requests.
1057 * Once DMA is started then new requests can be queued only after
1058 * terminating the DMA.
1059 */
1060 if (tdc->busy) {
1061 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1062 return NULL;
1063 }
1064
1065 /*
1066 * We only support cycle transfer when buf_len is multiple of
1067 * period_len.
1068 */
1069 if (buf_len % period_len) {
1070 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1071 return NULL;
1072 }
1073
1074 len = period_len;
1075 if ((len & 3) || (buf_addr & 3) ||
1076 (len > tdc->tdma->chip_data->max_dma_count)) {
1077 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1078 return NULL;
1079 }
1080
dc1ff4b3
JH		 1081 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1082 &burst_size, &slave_bw) < 0)
ec8a1586
LD		 1083 return NULL;
1084
ec8a1586
LD		 1085 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1086 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1087 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1088 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1089
b9bb37f5
LD		 1090 csr |= TEGRA_APBDMA_CSR_FLOW;
1091 if (flags & DMA_PREP_INTERRUPT)
1092 csr |= TEGRA_APBDMA_CSR_IE_EOC;
996556c9 1093 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
ec8a1586
LD		 1094
1095 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1096
1097 dma_desc = tegra_dma_desc_get(tdc);
1098 if (!dma_desc) {
1099 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1100 return NULL;
1101 }
1102
1103 INIT_LIST_HEAD(&dma_desc->tx_list);
1104 INIT_LIST_HEAD(&dma_desc->cb_node);
1105 dma_desc->cb_count = 0;
1106
1107 dma_desc->bytes_transferred = 0;
1108 dma_desc->bytes_requested = buf_len;
1109 remain_len = buf_len;
1110
1111 /* Split transfer equal to period size */
1112 while (remain_len) {
1113 sg_req = tegra_dma_sg_req_get(tdc);
1114 if (!sg_req) {
1115 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1116 tegra_dma_desc_put(tdc, dma_desc);
1117 return NULL;
1118 }
1119
1120 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1121 sg_req->ch_regs.apb_ptr = apb_ptr;
1122 sg_req->ch_regs.ahb_ptr = mem;
911daccc
LD		 1123 sg_req->ch_regs.csr = csr;
1124 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
ec8a1586
LD		 1125 sg_req->ch_regs.apb_seq = apb_seq;
1126 sg_req->ch_regs.ahb_seq = ahb_seq;
1127 sg_req->configured = false;
ec8a1586
LD		 1128 sg_req->last_sg = false;
1129 sg_req->dma_desc = dma_desc;
1130 sg_req->req_len = len;
1131
1132 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1133 remain_len -= len;
1134 mem += len;
1135 }
1136 sg_req->last_sg = true;
b9bb37f5
LD		 1137 if (flags & DMA_CTRL_ACK)
1138 dma_desc->txd.flags = DMA_CTRL_ACK;
ec8a1586
LD		 1139
1140 /*
1141 * Make sure that mode should not be conflicting with currently
1142 * configured mode.
1143 */
1144 if (!tdc->isr_handler) {
1145 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1146 tdc->cyclic = true;
1147 } else {
1148 if (!tdc->cyclic) {
1149 dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1150 tegra_dma_desc_put(tdc, dma_desc);
1151 return NULL;
1152 }
1153 }
1154
1155 return &dma_desc->txd;
1156}
1157
1158static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1159{
1160 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
ffc49306
LD		 1161 struct tegra_dma *tdma = tdc->tdma;
1162 int ret;
ec8a1586
LD		 1163
1164 dma_cookie_init(&tdc->dma_chan);
1165 tdc->config_init = false;
ffc49306
LD		 1166 ret = clk_prepare_enable(tdma->dma_clk);
1167 if (ret < 0)
1168 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1169 return ret;
ec8a1586
LD		 1170}
1171
1172static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1173{
1174 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
ffc49306 1175 struct tegra_dma *tdma = tdc->tdma;
ec8a1586
LD		 1176
1177 struct tegra_dma_desc *dma_desc;
1178 struct tegra_dma_sg_req *sg_req;
1179 struct list_head dma_desc_list;
1180 struct list_head sg_req_list;
1181 unsigned long flags;
1182
1183 INIT_LIST_HEAD(&dma_desc_list);
1184 INIT_LIST_HEAD(&sg_req_list);
1185
1186 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1187
1188 if (tdc->busy)
1189 tegra_dma_terminate_all(dc);
1190
1191 spin_lock_irqsave(&tdc->lock, flags);
1192 list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1193 list_splice_init(&tdc->free_sg_req, &sg_req_list);
1194 list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1195 INIT_LIST_HEAD(&tdc->cb_desc);
1196 tdc->config_init = false;
7bdc1e27 1197 tdc->isr_handler = NULL;
ec8a1586
LD		 1198 spin_unlock_irqrestore(&tdc->lock, flags);
1199
1200 while (!list_empty(&dma_desc_list)) {
1201 dma_desc = list_first_entry(&dma_desc_list,
1202 typeof(*dma_desc), node);
1203 list_del(&dma_desc->node);
1204 kfree(dma_desc);
1205 }
1206
1207 while (!list_empty(&sg_req_list)) {
1208 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1209 list_del(&sg_req->node);
1210 kfree(sg_req);
1211 }
ffc49306 1212 clk_disable_unprepare(tdma->dma_clk);
996556c9
SW		 1213
1214 tdc->slave_id = 0;
1215}
1216
1217static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
1218 struct of_dma *ofdma)
1219{
1220 struct tegra_dma *tdma = ofdma->of_dma_data;
1221 struct dma_chan *chan;
1222 struct tegra_dma_channel *tdc;
1223
1224 chan = dma_get_any_slave_channel(&tdma->dma_dev);
1225 if (!chan)
1226 return NULL;
1227
1228 tdc = to_tegra_dma_chan(chan);
1229 tdc->slave_id = dma_spec->args[0];
1230
1231 return chan;
ec8a1586
LD		 1232}
1233
1234/* Tegra20 specific DMA controller information */
75f21631 1235static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
ec8a1586 1236 .nr_channels = 16,
911daccc 1237 .channel_reg_size = 0x20,
ec8a1586 1238 .max_dma_count = 1024UL * 64,
1b140908 1239 .support_channel_pause = false,
911daccc 1240 .support_separate_wcount_reg = false,
ec8a1586
LD		 1241};
1242
ec8a1586 1243/* Tegra30 specific DMA controller information */
75f21631 1244static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
ec8a1586 1245 .nr_channels = 32,
911daccc 1246 .channel_reg_size = 0x20,
ec8a1586 1247 .max_dma_count = 1024UL * 64,
1b140908 1248 .support_channel_pause = false,
911daccc 1249 .support_separate_wcount_reg = false,
ec8a1586
LD		 1250};
1251
5ea7caf3
LD		 1252/* Tegra114 specific DMA controller information */
1253static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1254 .nr_channels = 32,
911daccc 1255 .channel_reg_size = 0x20,
5ea7caf3
LD		 1256 .max_dma_count = 1024UL * 64,
1257 .support_channel_pause = true,
911daccc
LD		 1258 .support_separate_wcount_reg = false,
1259};
1260
1261/* Tegra148 specific DMA controller information */
1262static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
1263 .nr_channels = 32,
1264 .channel_reg_size = 0x40,
1265 .max_dma_count = 1024UL * 64,
1266 .support_channel_pause = true,
1267 .support_separate_wcount_reg = true,
5ea7caf3
LD		 1268};
1269
1270
4bf27b8b 1271static const struct of_device_id tegra_dma_of_match[] = {
ec8a1586 1272 {
911daccc
LD		 1273 .compatible = "nvidia,tegra148-apbdma",
1274 .data = &tegra148_dma_chip_data,
1275 }, {
5ea7caf3
LD		 1276 .compatible = "nvidia,tegra114-apbdma",
1277 .data = &tegra114_dma_chip_data,
1278 }, {
cd9092c6 1279 .compatible = "nvidia,tegra30-apbdma",
ec8a1586
LD		 1280 .data = &tegra30_dma_chip_data,
1281 }, {
cd9092c6 1282 .compatible = "nvidia,tegra20-apbdma",
ec8a1586
LD		 1283 .data = &tegra20_dma_chip_data,
1284 }, {
1285 },
1286};
1287MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
ec8a1586 1288
463a1f8b 1289static int tegra_dma_probe(struct platform_device *pdev)
ec8a1586
LD		 1290{
1291 struct resource *res;
1292 struct tegra_dma *tdma;
1293 int ret;
1294 int i;
83a1ef2e 1295 const struct tegra_dma_chip_data *cdata = NULL;
dc7badba 1296 const struct of_device_id *match;
ec8a1586 1297
dc7badba
SW		 1298 match = of_match_device(tegra_dma_of_match, &pdev->dev);
1299 if (!match) {
1300 dev_err(&pdev->dev, "Error: No device match found\n");
1301 return -ENODEV;
ec8a1586 1302 }
dc7badba 1303 cdata = match->data;
ec8a1586
LD		 1304
1305 tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1306 sizeof(struct tegra_dma_channel), GFP_KERNEL);
1307 if (!tdma) {
1308 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1309 return -ENOMEM;
1310 }
1311
1312 tdma->dev = &pdev->dev;
1313 tdma->chip_data = cdata;
1314 platform_set_drvdata(pdev, tdma);
1315
1316 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7331205a
TR		 1317 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1318 if (IS_ERR(tdma->base_addr))
1319 return PTR_ERR(tdma->base_addr);
ec8a1586
LD		 1320
1321 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1322 if (IS_ERR(tdma->dma_clk)) {
1323 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1324 return PTR_ERR(tdma->dma_clk);
1325 }
1326
9aa433d2
SW		 1327 tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1328 if (IS_ERR(tdma->rst)) {
1329 dev_err(&pdev->dev, "Error: Missing reset\n");
1330 return PTR_ERR(tdma->rst);
1331 }
1332
ec8a1586
LD		 1333 spin_lock_init(&tdma->global_lock);
1334
1335 pm_runtime_enable(&pdev->dev);
1336 if (!pm_runtime_enabled(&pdev->dev)) {
1337 ret = tegra_dma_runtime_resume(&pdev->dev);
1338 if (ret) {
1339 dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
1340 ret);
1341 goto err_pm_disable;
1342 }
1343 }
1344
ffc49306
LD		 1345 /* Enable clock before accessing registers */
1346 ret = clk_prepare_enable(tdma->dma_clk);
1347 if (ret < 0) {
1348 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1349 goto err_pm_disable;
1350 }
1351
ec8a1586 1352 /* Reset DMA controller */
9aa433d2 1353 reset_control_assert(tdma->rst);
ec8a1586 1354 udelay(2);
9aa433d2 1355 reset_control_deassert(tdma->rst);
ec8a1586
LD		 1356
1357 /* Enable global DMA registers */
1358 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1359 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1360 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1361
ffc49306
LD		 1362 clk_disable_unprepare(tdma->dma_clk);
1363
ec8a1586
LD		 1364 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1365 for (i = 0; i < cdata->nr_channels; i++) {
1366 struct tegra_dma_channel *tdc = &tdma->channels[i];
ec8a1586 1367
13a33286
JH		 1368 tdc->chan_addr = tdma->base_addr +
1369 TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1370 (i * cdata->channel_reg_size);
ec8a1586
LD		 1371
1372 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1373 if (!res) {
1374 ret = -EINVAL;
1375 dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1376 goto err_irq;
1377 }
1378 tdc->irq = res->start;
d0fc9054 1379 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
ec8a1586 1380 ret = devm_request_irq(&pdev->dev, tdc->irq,
d0fc9054 1381 tegra_dma_isr, 0, tdc->name, tdc);
ec8a1586
LD		 1382 if (ret) {
1383 dev_err(&pdev->dev,
1384 "request_irq failed with err %d channel %d\n",
ac7ae754 1385 ret, i);
ec8a1586
LD		 1386 goto err_irq;
1387 }
1388
1389 tdc->dma_chan.device = &tdma->dma_dev;
1390 dma_cookie_init(&tdc->dma_chan);
1391 list_add_tail(&tdc->dma_chan.device_node,
1392 &tdma->dma_dev.channels);
1393 tdc->tdma = tdma;
1394 tdc->id = i;
1395
1396 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1397 (unsigned long)tdc);
1398 spin_lock_init(&tdc->lock);
1399
1400 INIT_LIST_HEAD(&tdc->pending_sg_req);
1401 INIT_LIST_HEAD(&tdc->free_sg_req);
1402 INIT_LIST_HEAD(&tdc->free_dma_desc);
1403 INIT_LIST_HEAD(&tdc->cb_desc);
1404 }
1405
1406 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1407 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
46fb3f8e
LD		 1408 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1409
ec8a1586
LD		 1410 tdma->dma_dev.dev = &pdev->dev;
1411 tdma->dma_dev.device_alloc_chan_resources =
1412 tegra_dma_alloc_chan_resources;
1413 tdma->dma_dev.device_free_chan_resources =
1414 tegra_dma_free_chan_resources;
1415 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1416 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
891653ab
PW		 1417 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1418 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1419 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1420 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1421 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1422 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1423 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1424 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1425 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1426 /*
1427 * XXX The hardware appears to support
1428 * DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
1429 * only used by this driver during tegra_dma_terminate_all()
1430 */
1431 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
662f1ac3
MR		 1432 tdma->dma_dev.device_config = tegra_dma_slave_config;
1433 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
ec8a1586
LD		 1434 tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1435 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1436
1437 ret = dma_async_device_register(&tdma->dma_dev);
1438 if (ret < 0) {
1439 dev_err(&pdev->dev,
1440 "Tegra20 APB DMA driver registration failed %d\n", ret);
1441 goto err_irq;
1442 }
1443
996556c9
SW		 1444 ret = of_dma_controller_register(pdev->dev.of_node,
1445 tegra_dma_of_xlate, tdma);
1446 if (ret < 0) {
1447 dev_err(&pdev->dev,
1448 "Tegra20 APB DMA OF registration failed %d\n", ret);
1449 goto err_unregister_dma_dev;
1450 }
1451
ec8a1586
LD		 1452 dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1453 cdata->nr_channels);
1454 return 0;
1455
996556c9
SW		 1456err_unregister_dma_dev:
1457 dma_async_device_unregister(&tdma->dma_dev);
ec8a1586
LD		 1458err_irq:
1459 while (--i >= 0) {
1460 struct tegra_dma_channel *tdc = &tdma->channels[i];
1461 tasklet_kill(&tdc->tasklet);
1462 }
1463
1464err_pm_disable:
1465 pm_runtime_disable(&pdev->dev);
1466 if (!pm_runtime_status_suspended(&pdev->dev))
1467 tegra_dma_runtime_suspend(&pdev->dev);
1468 return ret;
1469}
1470
4bf27b8b 1471static int tegra_dma_remove(struct platform_device *pdev)
ec8a1586
LD		 1472{
1473 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1474 int i;
1475 struct tegra_dma_channel *tdc;
1476
1477 dma_async_device_unregister(&tdma->dma_dev);
1478
1479 for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1480 tdc = &tdma->channels[i];
1481 tasklet_kill(&tdc->tasklet);
1482 }
1483
1484 pm_runtime_disable(&pdev->dev);
1485 if (!pm_runtime_status_suspended(&pdev->dev))
1486 tegra_dma_runtime_suspend(&pdev->dev);
1487
1488 return 0;
1489}
1490
1491static int tegra_dma_runtime_suspend(struct device *dev)
1492{
1493 struct platform_device *pdev = to_platform_device(dev);
1494 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1495
56482ec0 1496 clk_disable_unprepare(tdma->dma_clk);
ec8a1586
LD		 1497 return 0;
1498}
1499
1500static int tegra_dma_runtime_resume(struct device *dev)
1501{
1502 struct platform_device *pdev = to_platform_device(dev);
1503 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1504 int ret;
1505
56482ec0 1506 ret = clk_prepare_enable(tdma->dma_clk);
ec8a1586
LD		 1507 if (ret < 0) {
1508 dev_err(dev, "clk_enable failed: %d\n", ret);
1509 return ret;
1510 }
1511 return 0;
1512}
1513
3065c194
LD		 1514#ifdef CONFIG_PM_SLEEP
1515static int tegra_dma_pm_suspend(struct device *dev)
1516{
1517 struct tegra_dma *tdma = dev_get_drvdata(dev);
1518 int i;
1519 int ret;
1520
1521 /* Enable clock before accessing register */
1522 ret = tegra_dma_runtime_resume(dev);
1523 if (ret < 0)
1524 return ret;
1525
1526 tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1527 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1528 struct tegra_dma_channel *tdc = &tdma->channels[i];
1529 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1530
1531 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1532 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1533 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1534 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1535 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1536 }
1537
1538 /* Disable clock */
1539 tegra_dma_runtime_suspend(dev);
1540 return 0;
1541}
1542
1543static int tegra_dma_pm_resume(struct device *dev)
1544{
1545 struct tegra_dma *tdma = dev_get_drvdata(dev);
1546 int i;
1547 int ret;
1548
1549 /* Enable clock before accessing register */
1550 ret = tegra_dma_runtime_resume(dev);
1551 if (ret < 0)
1552 return ret;
1553
1554 tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1555 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1556 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1557
1558 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1559 struct tegra_dma_channel *tdc = &tdma->channels[i];
1560 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1561
1562 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1563 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1564 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1565 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1566 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1567 (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1568 }
1569
1570 /* Disable clock */
1571 tegra_dma_runtime_suspend(dev);
1572 return 0;
1573}
1574#endif
1575
4bf27b8b 1576static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
ee343504 1577#ifdef CONFIG_PM
ec8a1586
LD		 1578 .runtime_suspend = tegra_dma_runtime_suspend,
1579 .runtime_resume = tegra_dma_runtime_resume,
1580#endif
3065c194 1581 SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
ec8a1586
LD		 1582};
1583
1584static struct platform_driver tegra_dmac_driver = {
1585 .driver = {
cd9092c6 1586 .name = "tegra-apbdma",
ec8a1586 1587 .pm = &tegra_dma_dev_pm_ops,
dc7badba 1588 .of_match_table = tegra_dma_of_match,
ec8a1586
LD		 1589 },
1590 .probe = tegra_dma_probe,
a7d6e3ec 1591 .remove = tegra_dma_remove,
ec8a1586
LD		 1592};
1593
1594module_platform_driver(tegra_dmac_driver);
1595
1596MODULE_ALIAS("platform:tegra20-apbdma");
1597MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1598MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1599MODULE_LICENSE("GPL v2");
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