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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[mirror_ubuntu-artful-kernel.git] / drivers / dma / timb_dma.c
CommitLineData
de5d4453
RR		 1/*
2 * timb_dma.c timberdale FPGA DMA driver
3 * Copyright (c) 2010 Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* Supports:
20 * Timberdale FPGA DMA engine
21 */
22
23#include <linux/dmaengine.h>
24#include <linux/dma-mapping.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
6a3cd3ea 30#include <linux/slab.h>
de5d4453
RR		 31
32#include <linux/timb_dma.h>
33
d2ebfb33
RKAL		 34#include "dmaengine.h"
35
de5d4453
RR		 36#define DRIVER_NAME "timb-dma"
37
38/* Global DMA registers */
39#define TIMBDMA_ACR 0x34
40#define TIMBDMA_32BIT_ADDR 0x01
41
42#define TIMBDMA_ISR 0x080000
43#define TIMBDMA_IPR 0x080004
44#define TIMBDMA_IER 0x080008
45
46/* Channel specific registers */
47/* RX instances base addresses are 0x00, 0x40, 0x80 ...
48 * TX instances base addresses are 0x18, 0x58, 0x98 ...
49 */
50#define TIMBDMA_INSTANCE_OFFSET 0x40
51#define TIMBDMA_INSTANCE_TX_OFFSET 0x18
52
53/* RX registers, relative the instance base */
54#define TIMBDMA_OFFS_RX_DHAR 0x00
55#define TIMBDMA_OFFS_RX_DLAR 0x04
56#define TIMBDMA_OFFS_RX_LR 0x0C
57#define TIMBDMA_OFFS_RX_BLR 0x10
58#define TIMBDMA_OFFS_RX_ER 0x14
59#define TIMBDMA_RX_EN 0x01
60/* bytes per Row, video specific register
61 * which is placed after the TX registers...
62 */
63#define TIMBDMA_OFFS_RX_BPRR 0x30
64
65/* TX registers, relative the instance base */
66#define TIMBDMA_OFFS_TX_DHAR 0x00
67#define TIMBDMA_OFFS_TX_DLAR 0x04
68#define TIMBDMA_OFFS_TX_BLR 0x0C
69#define TIMBDMA_OFFS_TX_LR 0x14
70
71
72#define TIMB_DMA_DESC_SIZE 8
73
74struct timb_dma_desc {
75 struct list_head desc_node;
76 struct dma_async_tx_descriptor txd;
77 u8 *desc_list;
78 unsigned int desc_list_len;
79 bool interrupt;
80};
81
82struct timb_dma_chan {
83 struct dma_chan chan;
84 void __iomem *membase;
0f65169b
RR		 85 spinlock_t lock; /* Used to protect data structures,
86 especially the lists and descriptors,
87 from races between the tasklet and calls
88 from above */
de5d4453
RR		 89 bool ongoing;
90 struct list_head active_list;
91 struct list_head queue;
92 struct list_head free_list;
93 unsigned int bytes_per_line;
db8196df 94 enum dma_transfer_direction direction;
de5d4453
RR		 95 unsigned int descs; /* Descriptors to allocate */
96 unsigned int desc_elems; /* number of elems per descriptor */
97};
98
99struct timb_dma {
100 struct dma_device dma;
101 void __iomem *membase;
102 struct tasklet_struct tasklet;
103 struct timb_dma_chan channels[0];
104};
105
106static struct device *chan2dev(struct dma_chan *chan)
107{
108 return &chan->dev->device;
109}
110static struct device *chan2dmadev(struct dma_chan *chan)
111{
112 return chan2dev(chan)->parent->parent;
113}
114
115static struct timb_dma *tdchantotd(struct timb_dma_chan *td_chan)
116{
117 int id = td_chan->chan.chan_id;
118 return (struct timb_dma *)((u8 *)td_chan -
119 id * sizeof(struct timb_dma_chan) - sizeof(struct timb_dma));
120}
121
122/* Must be called with the spinlock held */
123static void __td_enable_chan_irq(struct timb_dma_chan *td_chan)
124{
125 int id = td_chan->chan.chan_id;
126 struct timb_dma *td = tdchantotd(td_chan);
127 u32 ier;
128
129 /* enable interrupt for this channel */
130 ier = ioread32(td->membase + TIMBDMA_IER);
131 ier |= 1 << id;
132 dev_dbg(chan2dev(&td_chan->chan), "Enabling irq: %d, IER: 0x%x\n", id,
133 ier);
134 iowrite32(ier, td->membase + TIMBDMA_IER);
135}
136
137/* Should be called with the spinlock held */
138static bool __td_dma_done_ack(struct timb_dma_chan *td_chan)
139{
140 int id = td_chan->chan.chan_id;
141 struct timb_dma *td = (struct timb_dma *)((u8 *)td_chan -
142 id * sizeof(struct timb_dma_chan) - sizeof(struct timb_dma));
143 u32 isr;
144 bool done = false;
145
146 dev_dbg(chan2dev(&td_chan->chan), "Checking irq: %d, td: %p\n", id, td);
147
148 isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id);
149 if (isr) {
150 iowrite32(isr, td->membase + TIMBDMA_ISR);
151 done = true;
152 }
153
154 return done;
155}
156
de5d4453
RR		 157static int td_fill_desc(struct timb_dma_chan *td_chan, u8 *dma_desc,
158 struct scatterlist *sg, bool last)
159{
4be929be 160 if (sg_dma_len(sg) > USHRT_MAX) {
de5d4453
RR		 161 dev_err(chan2dev(&td_chan->chan), "Too big sg element\n");
162 return -EINVAL;
163 }
164
165 /* length must be word aligned */
166 if (sg_dma_len(sg) % sizeof(u32)) {
167 dev_err(chan2dev(&td_chan->chan), "Incorrect length: %d\n",
168 sg_dma_len(sg));
169 return -EINVAL;
170 }
171
efcc2898
DC		 172 dev_dbg(chan2dev(&td_chan->chan), "desc: %p, addr: 0x%llx\n",
173 dma_desc, (unsigned long long)sg_dma_address(sg));
de5d4453
RR		 174
175 dma_desc[7] = (sg_dma_address(sg) >> 24) & 0xff;
176 dma_desc[6] = (sg_dma_address(sg) >> 16) & 0xff;
177 dma_desc[5] = (sg_dma_address(sg) >> 8) & 0xff;
178 dma_desc[4] = (sg_dma_address(sg) >> 0) & 0xff;
179
180 dma_desc[3] = (sg_dma_len(sg) >> 8) & 0xff;
181 dma_desc[2] = (sg_dma_len(sg) >> 0) & 0xff;
182
183 dma_desc[1] = 0x00;
184 dma_desc[0] = 0x21 | (last ? 0x02 : 0); /* tran, valid */
185
186 return 0;
187}
188
189/* Must be called with the spinlock held */
190static void __td_start_dma(struct timb_dma_chan *td_chan)
191{
192 struct timb_dma_desc *td_desc;
193
194 if (td_chan->ongoing) {
195 dev_err(chan2dev(&td_chan->chan),
196 "Transfer already ongoing\n");
197 return;
198 }
199
200 td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc,
201 desc_node);
202
203 dev_dbg(chan2dev(&td_chan->chan),
204 "td_chan: %p, chan: %d, membase: %p\n",
205 td_chan, td_chan->chan.chan_id, td_chan->membase);
206
db8196df 207 if (td_chan->direction == DMA_DEV_TO_MEM) {
de5d4453
RR		 208
209 /* descriptor address */
210 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR);
211 iowrite32(td_desc->txd.phys, td_chan->membase +
212 TIMBDMA_OFFS_RX_DLAR);
213 /* Bytes per line */
214 iowrite32(td_chan->bytes_per_line, td_chan->membase +
215 TIMBDMA_OFFS_RX_BPRR);
216 /* enable RX */
217 iowrite32(TIMBDMA_RX_EN, td_chan->membase + TIMBDMA_OFFS_RX_ER);
218 } else {
219 /* address high */
220 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DHAR);
221 iowrite32(td_desc->txd.phys, td_chan->membase +
222 TIMBDMA_OFFS_TX_DLAR);
223 }
224
225 td_chan->ongoing = true;
226
227 if (td_desc->interrupt)
228 __td_enable_chan_irq(td_chan);
229}
230
231static void __td_finish(struct timb_dma_chan *td_chan)
232{
233 dma_async_tx_callback callback;
234 void *param;
235 struct dma_async_tx_descriptor *txd;
236 struct timb_dma_desc *td_desc;
237
238 /* can happen if the descriptor is canceled */
239 if (list_empty(&td_chan->active_list))
240 return;
241
242 td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc,
243 desc_node);
244 txd = &td_desc->txd;
245
246 dev_dbg(chan2dev(&td_chan->chan), "descriptor %u complete\n",
247 txd->cookie);
248
249 /* make sure to stop the transfer */
db8196df 250 if (td_chan->direction == DMA_DEV_TO_MEM)
de5d4453
RR		 251 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER);
252/* Currently no support for stopping DMA transfers
253 else
254 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR);
255*/
f7fbce07 256 dma_cookie_complete(txd);
de5d4453
RR		 257 td_chan->ongoing = false;
258
259 callback = txd->callback;
260 param = txd->callback_param;
261
262 list_move(&td_desc->desc_node, &td_chan->free_list);
263
d38a8c62 264 dma_descriptor_unmap(txd);
de5d4453
RR		 265 /*
266 * The API requires that no submissions are done from a
267 * callback, so we don't need to drop the lock here
268 */
269 if (callback)
270 callback(param);
271}
272
273static u32 __td_ier_mask(struct timb_dma *td)
274{
275 int i;
276 u32 ret = 0;
277
278 for (i = 0; i < td->dma.chancnt; i++) {
279 struct timb_dma_chan *td_chan = td->channels + i;
280 if (td_chan->ongoing) {
281 struct timb_dma_desc *td_desc =
282 list_entry(td_chan->active_list.next,
283 struct timb_dma_desc, desc_node);
284 if (td_desc->interrupt)
285 ret |= 1 << i;
286 }
287 }
288
289 return ret;
290}
291
292static void __td_start_next(struct timb_dma_chan *td_chan)
293{
294 struct timb_dma_desc *td_desc;
295
296 BUG_ON(list_empty(&td_chan->queue));
297 BUG_ON(td_chan->ongoing);
298
299 td_desc = list_entry(td_chan->queue.next, struct timb_dma_desc,
300 desc_node);
301
302 dev_dbg(chan2dev(&td_chan->chan), "%s: started %u\n",
303 __func__, td_desc->txd.cookie);
304
305 list_move(&td_desc->desc_node, &td_chan->active_list);
306 __td_start_dma(td_chan);
307}
308
309static dma_cookie_t td_tx_submit(struct dma_async_tx_descriptor *txd)
310{
311 struct timb_dma_desc *td_desc = container_of(txd, struct timb_dma_desc,
312 txd);
313 struct timb_dma_chan *td_chan = container_of(txd->chan,
314 struct timb_dma_chan, chan);
315 dma_cookie_t cookie;
316
317 spin_lock_bh(&td_chan->lock);
884485e1 318 cookie = dma_cookie_assign(txd);
de5d4453
RR		 319
320 if (list_empty(&td_chan->active_list)) {
321 dev_dbg(chan2dev(txd->chan), "%s: started %u\n", __func__,
322 txd->cookie);
323 list_add_tail(&td_desc->desc_node, &td_chan->active_list);
324 __td_start_dma(td_chan);
325 } else {
326 dev_dbg(chan2dev(txd->chan), "tx_submit: queued %u\n",
327 txd->cookie);
328
329 list_add_tail(&td_desc->desc_node, &td_chan->queue);
330 }
331
332 spin_unlock_bh(&td_chan->lock);
333
334 return cookie;
335}
336
337static struct timb_dma_desc *td_alloc_init_desc(struct timb_dma_chan *td_chan)
338{
339 struct dma_chan *chan = &td_chan->chan;
340 struct timb_dma_desc *td_desc;
341 int err;
342
343 td_desc = kzalloc(sizeof(struct timb_dma_desc), GFP_KERNEL);
344 if (!td_desc) {
345 dev_err(chan2dev(chan), "Failed to alloc descriptor\n");
48568005 346 goto out;
de5d4453
RR		 347 }
348
349 td_desc->desc_list_len = td_chan->desc_elems * TIMB_DMA_DESC_SIZE;
350
351 td_desc->desc_list = kzalloc(td_desc->desc_list_len, GFP_KERNEL);
352 if (!td_desc->desc_list) {
353 dev_err(chan2dev(chan), "Failed to alloc descriptor\n");
354 goto err;
355 }
356
357 dma_async_tx_descriptor_init(&td_desc->txd, chan);
358 td_desc->txd.tx_submit = td_tx_submit;
359 td_desc->txd.flags = DMA_CTRL_ACK;
360
361 td_desc->txd.phys = dma_map_single(chan2dmadev(chan),
d5613947 362 td_desc->desc_list, td_desc->desc_list_len, DMA_TO_DEVICE);
de5d4453
RR		 363
364 err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys);
365 if (err) {
366 dev_err(chan2dev(chan), "DMA mapping error: %d\n", err);
367 goto err;
368 }
369
370 return td_desc;
371err:
372 kfree(td_desc->desc_list);
373 kfree(td_desc);
48568005 374out:
de5d4453
RR		 375 return NULL;
376
377}
378
379static void td_free_desc(struct timb_dma_desc *td_desc)
380{
381 dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc);
382 dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys,
d5613947 383 td_desc->desc_list_len, DMA_TO_DEVICE);
de5d4453
RR		 384
385 kfree(td_desc->desc_list);
386 kfree(td_desc);
387}
388
389static void td_desc_put(struct timb_dma_chan *td_chan,
390 struct timb_dma_desc *td_desc)
391{
392 dev_dbg(chan2dev(&td_chan->chan), "Putting desc: %p\n", td_desc);
393
394 spin_lock_bh(&td_chan->lock);
395 list_add(&td_desc->desc_node, &td_chan->free_list);
396 spin_unlock_bh(&td_chan->lock);
397}
398
399static struct timb_dma_desc *td_desc_get(struct timb_dma_chan *td_chan)
400{
401 struct timb_dma_desc *td_desc, *_td_desc;
402 struct timb_dma_desc *ret = NULL;
403
404 spin_lock_bh(&td_chan->lock);
405 list_for_each_entry_safe(td_desc, _td_desc, &td_chan->free_list,
406 desc_node) {
407 if (async_tx_test_ack(&td_desc->txd)) {
408 list_del(&td_desc->desc_node);
409 ret = td_desc;
410 break;
411 }
412 dev_dbg(chan2dev(&td_chan->chan), "desc %p not ACKed\n",
413 td_desc);
414 }
415 spin_unlock_bh(&td_chan->lock);
416
417 return ret;
418}
419
420static int td_alloc_chan_resources(struct dma_chan *chan)
421{
422 struct timb_dma_chan *td_chan =
423 container_of(chan, struct timb_dma_chan, chan);
424 int i;
425
426 dev_dbg(chan2dev(chan), "%s: entry\n", __func__);
427
428 BUG_ON(!list_empty(&td_chan->free_list));
429 for (i = 0; i < td_chan->descs; i++) {
430 struct timb_dma_desc *td_desc = td_alloc_init_desc(td_chan);
431 if (!td_desc) {
432 if (i)
433 break;
434 else {
435 dev_err(chan2dev(chan),
436 "Couldnt allocate any descriptors\n");
437 return -ENOMEM;
438 }
439 }
440
441 td_desc_put(td_chan, td_desc);
442 }
443
444 spin_lock_bh(&td_chan->lock);
d3ee98cd 445 dma_cookie_init(chan);
de5d4453
RR		 446 spin_unlock_bh(&td_chan->lock);
447
448 return 0;
449}
450
451static void td_free_chan_resources(struct dma_chan *chan)
452{
453 struct timb_dma_chan *td_chan =
454 container_of(chan, struct timb_dma_chan, chan);
455 struct timb_dma_desc *td_desc, *_td_desc;
456 LIST_HEAD(list);
457
458 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
459
460 /* check that all descriptors are free */
461 BUG_ON(!list_empty(&td_chan->active_list));
462 BUG_ON(!list_empty(&td_chan->queue));
463
464 spin_lock_bh(&td_chan->lock);
465 list_splice_init(&td_chan->free_list, &list);
466 spin_unlock_bh(&td_chan->lock);
467
468 list_for_each_entry_safe(td_desc, _td_desc, &list, desc_node) {
469 dev_dbg(chan2dev(chan), "%s: Freeing desc: %p\n", __func__,
470 td_desc);
471 td_free_desc(td_desc);
472 }
473}
474
07934481
LW		 475static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
476 struct dma_tx_state *txstate)
de5d4453 477{
96a2af41 478 enum dma_status ret;
de5d4453
RR		 479
480 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
481
96a2af41 482 ret = dma_cookie_status(chan, cookie, txstate);
de5d4453 483
949ff5b8 484 dev_dbg(chan2dev(chan), "%s: exit, ret: %d\n", __func__, ret);
de5d4453
RR		 485
486 return ret;
487}
488
489static void td_issue_pending(struct dma_chan *chan)
490{
491 struct timb_dma_chan *td_chan =
492 container_of(chan, struct timb_dma_chan, chan);
493
494 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
495 spin_lock_bh(&td_chan->lock);
496
497 if (!list_empty(&td_chan->active_list))
498 /* transfer ongoing */
499 if (__td_dma_done_ack(td_chan))
500 __td_finish(td_chan);
501
502 if (list_empty(&td_chan->active_list) && !list_empty(&td_chan->queue))
503 __td_start_next(td_chan);
504
505 spin_unlock_bh(&td_chan->lock);
506}
507
508static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
509 struct scatterlist *sgl, unsigned int sg_len,
185ecb5f
AB		 510 enum dma_transfer_direction direction, unsigned long flags,
511 void *context)
de5d4453
RR		 512{
513 struct timb_dma_chan *td_chan =
514 container_of(chan, struct timb_dma_chan, chan);
515 struct timb_dma_desc *td_desc;
516 struct scatterlist *sg;
517 unsigned int i;
518 unsigned int desc_usage = 0;
519
520 if (!sgl || !sg_len) {
521 dev_err(chan2dev(chan), "%s: No SG list\n", __func__);
522 return NULL;
523 }
524
525 /* even channels are for RX, odd for TX */
526 if (td_chan->direction != direction) {
527 dev_err(chan2dev(chan),
528 "Requesting channel in wrong direction\n");
529 return NULL;
530 }
531
532 td_desc = td_desc_get(td_chan);
533 if (!td_desc) {
534 dev_err(chan2dev(chan), "Not enough descriptors available\n");
535 return NULL;
536 }
537
538 td_desc->interrupt = (flags & DMA_PREP_INTERRUPT) != 0;
539
540 for_each_sg(sgl, sg, sg_len, i) {
541 int err;
542 if (desc_usage > td_desc->desc_list_len) {
543 dev_err(chan2dev(chan), "No descriptor space\n");
544 return NULL;
545 }
546
547 err = td_fill_desc(td_chan, td_desc->desc_list + desc_usage, sg,
548 i == (sg_len - 1));
549 if (err) {
550 dev_err(chan2dev(chan), "Failed to update desc: %d\n",
551 err);
552 td_desc_put(td_chan, td_desc);
553 return NULL;
554 }
555 desc_usage += TIMB_DMA_DESC_SIZE;
556 }
557
558 dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys,
db8196df 559 td_desc->desc_list_len, DMA_MEM_TO_DEV);
de5d4453
RR		 560
561 return &td_desc->txd;
562}
563
05827630
LW		 564static int td_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
565 unsigned long arg)
de5d4453
RR		 566{
567 struct timb_dma_chan *td_chan =
568 container_of(chan, struct timb_dma_chan, chan);
569 struct timb_dma_desc *td_desc, *_td_desc;
570
571 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
572
c3635c78
LW		 573 if (cmd != DMA_TERMINATE_ALL)
574 return -ENXIO;
575
de5d4453
RR		 576 /* first the easy part, put the queue into the free list */
577 spin_lock_bh(&td_chan->lock);
578 list_for_each_entry_safe(td_desc, _td_desc, &td_chan->queue,
579 desc_node)
580 list_move(&td_desc->desc_node, &td_chan->free_list);
581
ae0e47f0 582 /* now tear down the running */
de5d4453
RR		 583 __td_finish(td_chan);
584 spin_unlock_bh(&td_chan->lock);
c3635c78
LW		 585
586 return 0;
de5d4453
RR		 587}
588
589static void td_tasklet(unsigned long data)
590{
591 struct timb_dma *td = (struct timb_dma *)data;
592 u32 isr;
593 u32 ipr;
594 u32 ier;
595 int i;
596
597 isr = ioread32(td->membase + TIMBDMA_ISR);
598 ipr = isr & __td_ier_mask(td);
599
600 /* ack the interrupts */
601 iowrite32(ipr, td->membase + TIMBDMA_ISR);
602
603 for (i = 0; i < td->dma.chancnt; i++)
604 if (ipr & (1 << i)) {
605 struct timb_dma_chan *td_chan = td->channels + i;
606 spin_lock(&td_chan->lock);
607 __td_finish(td_chan);
608 if (!list_empty(&td_chan->queue))
609 __td_start_next(td_chan);
610 spin_unlock(&td_chan->lock);
611 }
612
613 ier = __td_ier_mask(td);
614 iowrite32(ier, td->membase + TIMBDMA_IER);
615}
616
617
618static irqreturn_t td_irq(int irq, void *devid)
619{
620 struct timb_dma *td = devid;
621 u32 ipr = ioread32(td->membase + TIMBDMA_IPR);
622
623 if (ipr) {
624 /* disable interrupts, will be re-enabled in tasklet */
625 iowrite32(0, td->membase + TIMBDMA_IER);
626
627 tasklet_schedule(&td->tasklet);
628
629 return IRQ_HANDLED;
630 } else
631 return IRQ_NONE;
632}
633
634
463a1f8b 635static int td_probe(struct platform_device *pdev)
de5d4453 636{
d4adcc01 637 struct timb_dma_platform_data *pdata = dev_get_platdata(&pdev->dev);
de5d4453
RR		 638 struct timb_dma *td;
639 struct resource *iomem;
640 int irq;
641 int err;
642 int i;
643
644 if (!pdata) {
645 dev_err(&pdev->dev, "No platform data\n");
646 return -EINVAL;
647 }
648
649 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
650 if (!iomem)
651 return -EINVAL;
652
653 irq = platform_get_irq(pdev, 0);
654 if (irq < 0)
655 return irq;
656
657 if (!request_mem_region(iomem->start, resource_size(iomem),
658 DRIVER_NAME))
659 return -EBUSY;
660
661 td = kzalloc(sizeof(struct timb_dma) +
662 sizeof(struct timb_dma_chan) * pdata->nr_channels, GFP_KERNEL);
663 if (!td) {
664 err = -ENOMEM;
665 goto err_release_region;
666 }
667
668 dev_dbg(&pdev->dev, "Allocated TD: %p\n", td);
669
670 td->membase = ioremap(iomem->start, resource_size(iomem));
671 if (!td->membase) {
672 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
673 err = -ENOMEM;
674 goto err_free_mem;
675 }
676
677 /* 32bit addressing */
678 iowrite32(TIMBDMA_32BIT_ADDR, td->membase + TIMBDMA_ACR);
679
680 /* disable and clear any interrupts */
681 iowrite32(0x0, td->membase + TIMBDMA_IER);
682 iowrite32(0xFFFFFFFF, td->membase + TIMBDMA_ISR);
683
684 tasklet_init(&td->tasklet, td_tasklet, (unsigned long)td);
685
686 err = request_irq(irq, td_irq, IRQF_SHARED, DRIVER_NAME, td);
687 if (err) {
688 dev_err(&pdev->dev, "Failed to request IRQ\n");
689 goto err_tasklet_kill;
690 }
691
692 td->dma.device_alloc_chan_resources = td_alloc_chan_resources;
693 td->dma.device_free_chan_resources = td_free_chan_resources;
07934481 694 td->dma.device_tx_status = td_tx_status;
de5d4453
RR		 695 td->dma.device_issue_pending = td_issue_pending;
696
697 dma_cap_set(DMA_SLAVE, td->dma.cap_mask);
698 dma_cap_set(DMA_PRIVATE, td->dma.cap_mask);
699 td->dma.device_prep_slave_sg = td_prep_slave_sg;
c3635c78 700 td->dma.device_control = td_control;
de5d4453
RR		 701
702 td->dma.dev = &pdev->dev;
703
704 INIT_LIST_HEAD(&td->dma.channels);
705
46389470 706 for (i = 0; i < pdata->nr_channels; i++) {
de5d4453
RR		 707 struct timb_dma_chan *td_chan = &td->channels[i];
708 struct timb_dma_platform_data_channel *pchan =
709 pdata->channels + i;
710
711 /* even channels are RX, odd are TX */
9cb047d4 712 if ((i % 2) == pchan->rx) {
de5d4453
RR		 713 dev_err(&pdev->dev, "Wrong channel configuration\n");
714 err = -EINVAL;
f80befe0 715 goto err_free_irq;
de5d4453
RR		 716 }
717
718 td_chan->chan.device = &td->dma;
d3ee98cd 719 dma_cookie_init(&td_chan->chan);
de5d4453
RR		 720 spin_lock_init(&td_chan->lock);
721 INIT_LIST_HEAD(&td_chan->active_list);
722 INIT_LIST_HEAD(&td_chan->queue);
723 INIT_LIST_HEAD(&td_chan->free_list);
724
725 td_chan->descs = pchan->descriptors;
726 td_chan->desc_elems = pchan->descriptor_elements;
727 td_chan->bytes_per_line = pchan->bytes_per_line;
db8196df
VK		 728 td_chan->direction = pchan->rx ? DMA_DEV_TO_MEM :
729 DMA_MEM_TO_DEV;
de5d4453
RR		 730
731 td_chan->membase = td->membase +
732 (i / 2) * TIMBDMA_INSTANCE_OFFSET +
733 (pchan->rx ? 0 : TIMBDMA_INSTANCE_TX_OFFSET);
734
735 dev_dbg(&pdev->dev, "Chan: %d, membase: %p\n",
736 i, td_chan->membase);
737
738 list_add_tail(&td_chan->chan.device_node, &td->dma.channels);
739 }
740
741 err = dma_async_device_register(&td->dma);
742 if (err) {
743 dev_err(&pdev->dev, "Failed to register async device\n");
744 goto err_free_irq;
745 }
746
747 platform_set_drvdata(pdev, td);
748
749 dev_dbg(&pdev->dev, "Probe result: %d\n", err);
750 return err;
751
752err_free_irq:
753 free_irq(irq, td);
754err_tasklet_kill:
755 tasklet_kill(&td->tasklet);
756 iounmap(td->membase);
757err_free_mem:
758 kfree(td);
759err_release_region:
760 release_mem_region(iomem->start, resource_size(iomem));
761
762 return err;
763
764}
765
4bf27b8b 766static int td_remove(struct platform_device *pdev)
de5d4453
RR		 767{
768 struct timb_dma *td = platform_get_drvdata(pdev);
769 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
770 int irq = platform_get_irq(pdev, 0);
771
772 dma_async_device_unregister(&td->dma);
773 free_irq(irq, td);
774 tasklet_kill(&td->tasklet);
775 iounmap(td->membase);
776 kfree(td);
777 release_mem_region(iomem->start, resource_size(iomem));
778
de5d4453
RR		 779 dev_dbg(&pdev->dev, "Removed...\n");
780 return 0;
781}
782
783static struct platform_driver td_driver = {
784 .driver = {
785 .name = DRIVER_NAME,
786 .owner = THIS_MODULE,
787 },
788 .probe = td_probe,
234846d4 789 .remove = td_remove,
de5d4453
RR		 790};
791
c94e9105 792module_platform_driver(td_driver);
de5d4453
RR		 793
794MODULE_LICENSE("GPL v2");
795MODULE_DESCRIPTION("Timberdale DMA controller driver");
796MODULE_AUTHOR("Pelagicore AB <info@pelagicore.com>");
797MODULE_ALIAS("platform:"DRIVER_NAME);
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