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9f2fd0df RPS |
1 | /* |
2 | * Applied Micro X-Gene SoC DMA engine Driver | |
3 | * | |
4 | * Copyright (c) 2015, Applied Micro Circuits Corporation | |
5 | * Authors: Rameshwar Prasad Sahu <rsahu@apm.com> | |
6 | * Loc Ho <lho@apm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | * | |
21 | * NOTE: PM support is currently not available. | |
22 | */ | |
23 | ||
24 | #include <linux/clk.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/dmaengine.h> | |
28 | #include <linux/dmapool.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/of_device.h> | |
33 | ||
34 | #include "dmaengine.h" | |
35 | ||
36 | /* X-Gene DMA ring csr registers and bit definations */ | |
37 | #define XGENE_DMA_RING_CONFIG 0x04 | |
38 | #define XGENE_DMA_RING_ENABLE BIT(31) | |
39 | #define XGENE_DMA_RING_ID 0x08 | |
40 | #define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31)) | |
41 | #define XGENE_DMA_RING_ID_BUF 0x0C | |
42 | #define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) | |
43 | #define XGENE_DMA_RING_THRESLD0_SET1 0x30 | |
44 | #define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64 | |
45 | #define XGENE_DMA_RING_THRESLD1_SET1 0x34 | |
46 | #define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8 | |
47 | #define XGENE_DMA_RING_HYSTERESIS 0x68 | |
48 | #define XGENE_DMA_RING_HYSTERESIS_VAL 0xFFFFFFFF | |
49 | #define XGENE_DMA_RING_STATE 0x6C | |
50 | #define XGENE_DMA_RING_STATE_WR_BASE 0x70 | |
51 | #define XGENE_DMA_RING_NE_INT_MODE 0x017C | |
52 | #define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \ | |
53 | ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) | |
54 | #define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \ | |
55 | ((m) &= (~BIT(31 - (v)))) | |
56 | #define XGENE_DMA_RING_CLKEN 0xC208 | |
57 | #define XGENE_DMA_RING_SRST 0xC200 | |
58 | #define XGENE_DMA_RING_MEM_RAM_SHUTDOWN 0xD070 | |
59 | #define XGENE_DMA_RING_BLK_MEM_RDY 0xD074 | |
60 | #define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0xFFFFFFFF | |
61 | #define XGENE_DMA_RING_DESC_CNT(v) (((v) & 0x0001FFFE) >> 1) | |
62 | #define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num)) | |
63 | #define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v)) | |
64 | #define XGENE_DMA_RING_CMD_OFFSET 0x2C | |
65 | #define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6) | |
66 | #define XGENE_DMA_RING_COHERENT_SET(m) \ | |
67 | (((u32 *)(m))[2] |= BIT(4)) | |
68 | #define XGENE_DMA_RING_ADDRL_SET(m, v) \ | |
69 | (((u32 *)(m))[2] |= (((v) >> 8) << 5)) | |
70 | #define XGENE_DMA_RING_ADDRH_SET(m, v) \ | |
71 | (((u32 *)(m))[3] |= ((v) >> 35)) | |
72 | #define XGENE_DMA_RING_ACCEPTLERR_SET(m) \ | |
73 | (((u32 *)(m))[3] |= BIT(19)) | |
74 | #define XGENE_DMA_RING_SIZE_SET(m, v) \ | |
75 | (((u32 *)(m))[3] |= ((v) << 23)) | |
76 | #define XGENE_DMA_RING_RECOMBBUF_SET(m) \ | |
77 | (((u32 *)(m))[3] |= BIT(27)) | |
78 | #define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m) \ | |
79 | (((u32 *)(m))[3] |= (0x7 << 28)) | |
80 | #define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m) \ | |
81 | (((u32 *)(m))[4] |= 0x3) | |
82 | #define XGENE_DMA_RING_SELTHRSH_SET(m) \ | |
83 | (((u32 *)(m))[4] |= BIT(3)) | |
84 | #define XGENE_DMA_RING_TYPE_SET(m, v) \ | |
85 | (((u32 *)(m))[4] |= ((v) << 19)) | |
86 | ||
87 | /* X-Gene DMA device csr registers and bit definitions */ | |
88 | #define XGENE_DMA_IPBRR 0x0 | |
89 | #define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF) | |
90 | #define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3) | |
91 | #define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3) | |
92 | #define XGENE_DMA_GCR 0x10 | |
93 | #define XGENE_DMA_CH_SETUP(v) \ | |
94 | ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF) | |
95 | #define XGENE_DMA_ENABLE(v) ((v) |= BIT(31)) | |
96 | #define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31)) | |
97 | #define XGENE_DMA_RAID6_CONT 0x14 | |
98 | #define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24) | |
99 | #define XGENE_DMA_INT 0x70 | |
100 | #define XGENE_DMA_INT_MASK 0x74 | |
101 | #define XGENE_DMA_INT_ALL_MASK 0xFFFFFFFF | |
102 | #define XGENE_DMA_INT_ALL_UNMASK 0x0 | |
103 | #define XGENE_DMA_INT_MASK_SHIFT 0x14 | |
104 | #define XGENE_DMA_RING_INT0_MASK 0x90A0 | |
105 | #define XGENE_DMA_RING_INT1_MASK 0x90A8 | |
106 | #define XGENE_DMA_RING_INT2_MASK 0x90B0 | |
107 | #define XGENE_DMA_RING_INT3_MASK 0x90B8 | |
108 | #define XGENE_DMA_RING_INT4_MASK 0x90C0 | |
109 | #define XGENE_DMA_CFG_RING_WQ_ASSOC 0x90E0 | |
110 | #define XGENE_DMA_ASSOC_RING_MNGR1 0xFFFFFFFF | |
111 | #define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070 | |
112 | #define XGENE_DMA_BLK_MEM_RDY 0xD074 | |
113 | #define XGENE_DMA_BLK_MEM_RDY_VAL 0xFFFFFFFF | |
114 | ||
115 | /* X-Gene SoC EFUSE csr register and bit defination */ | |
116 | #define XGENE_SOC_JTAG1_SHADOW 0x18 | |
117 | #define XGENE_DMA_PQ_DISABLE_MASK BIT(13) | |
118 | ||
119 | /* X-Gene DMA Descriptor format */ | |
120 | #define XGENE_DMA_DESC_NV_BIT BIT_ULL(50) | |
121 | #define XGENE_DMA_DESC_IN_BIT BIT_ULL(55) | |
122 | #define XGENE_DMA_DESC_C_BIT BIT_ULL(63) | |
123 | #define XGENE_DMA_DESC_DR_BIT BIT_ULL(61) | |
124 | #define XGENE_DMA_DESC_ELERR_POS 46 | |
125 | #define XGENE_DMA_DESC_RTYPE_POS 56 | |
126 | #define XGENE_DMA_DESC_LERR_POS 60 | |
9f2fd0df RPS |
127 | #define XGENE_DMA_DESC_BUFLEN_POS 48 |
128 | #define XGENE_DMA_DESC_HOENQ_NUM_POS 48 | |
9f2fd0df RPS |
129 | #define XGENE_DMA_DESC_ELERR_RD(m) \ |
130 | (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3) | |
131 | #define XGENE_DMA_DESC_LERR_RD(m) \ | |
132 | (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7) | |
133 | #define XGENE_DMA_DESC_STATUS(elerr, lerr) \ | |
134 | (((elerr) << 4) | (lerr)) | |
135 | ||
136 | /* X-Gene DMA descriptor empty s/w signature */ | |
9f2fd0df | 137 | #define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL |
9f2fd0df RPS |
138 | |
139 | /* X-Gene DMA configurable parameters defines */ | |
140 | #define XGENE_DMA_RING_NUM 512 | |
141 | #define XGENE_DMA_BUFNUM 0x0 | |
142 | #define XGENE_DMA_CPU_BUFNUM 0x18 | |
143 | #define XGENE_DMA_RING_OWNER_DMA 0x03 | |
144 | #define XGENE_DMA_RING_OWNER_CPU 0x0F | |
145 | #define XGENE_DMA_RING_TYPE_REGULAR 0x01 | |
146 | #define XGENE_DMA_RING_WQ_DESC_SIZE 32 /* 32 Bytes */ | |
147 | #define XGENE_DMA_RING_NUM_CONFIG 5 | |
148 | #define XGENE_DMA_MAX_CHANNEL 4 | |
149 | #define XGENE_DMA_XOR_CHANNEL 0 | |
150 | #define XGENE_DMA_PQ_CHANNEL 1 | |
151 | #define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */ | |
152 | #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */ | |
9f2fd0df RPS |
153 | #define XGENE_DMA_MAX_XOR_SRC 5 |
154 | #define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0 | |
6d0767c1 | 155 | #define XGENE_DMA_INVALID_LEN_CODE 0x7800000000000000ULL |
9f2fd0df RPS |
156 | |
157 | /* X-Gene DMA descriptor error codes */ | |
158 | #define ERR_DESC_AXI 0x01 | |
159 | #define ERR_BAD_DESC 0x02 | |
160 | #define ERR_READ_DATA_AXI 0x03 | |
161 | #define ERR_WRITE_DATA_AXI 0x04 | |
162 | #define ERR_FBP_TIMEOUT 0x05 | |
163 | #define ERR_ECC 0x06 | |
164 | #define ERR_DIFF_SIZE 0x08 | |
165 | #define ERR_SCT_GAT_LEN 0x09 | |
166 | #define ERR_CRC_ERR 0x11 | |
167 | #define ERR_CHKSUM 0x12 | |
168 | #define ERR_DIF 0x13 | |
169 | ||
170 | /* X-Gene DMA error interrupt codes */ | |
171 | #define ERR_DIF_SIZE_INT 0x0 | |
172 | #define ERR_GS_ERR_INT 0x1 | |
173 | #define ERR_FPB_TIMEO_INT 0x2 | |
174 | #define ERR_WFIFO_OVF_INT 0x3 | |
175 | #define ERR_RFIFO_OVF_INT 0x4 | |
176 | #define ERR_WR_TIMEO_INT 0x5 | |
177 | #define ERR_RD_TIMEO_INT 0x6 | |
178 | #define ERR_WR_ERR_INT 0x7 | |
179 | #define ERR_RD_ERR_INT 0x8 | |
180 | #define ERR_BAD_DESC_INT 0x9 | |
181 | #define ERR_DESC_DST_INT 0xA | |
182 | #define ERR_DESC_SRC_INT 0xB | |
183 | ||
184 | /* X-Gene DMA flyby operation code */ | |
6d0767c1 RPS |
185 | #define FLYBY_2SRC_XOR 0x80 |
186 | #define FLYBY_3SRC_XOR 0x90 | |
187 | #define FLYBY_4SRC_XOR 0xA0 | |
188 | #define FLYBY_5SRC_XOR 0xB0 | |
9f2fd0df RPS |
189 | |
190 | /* X-Gene DMA SW descriptor flags */ | |
191 | #define XGENE_DMA_FLAG_64B_DESC BIT(0) | |
192 | ||
193 | /* Define to dump X-Gene DMA descriptor */ | |
194 | #define XGENE_DMA_DESC_DUMP(desc, m) \ | |
195 | print_hex_dump(KERN_ERR, (m), \ | |
196 | DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0) | |
197 | ||
198 | #define to_dma_desc_sw(tx) \ | |
199 | container_of(tx, struct xgene_dma_desc_sw, tx) | |
200 | #define to_dma_chan(dchan) \ | |
201 | container_of(dchan, struct xgene_dma_chan, dma_chan) | |
202 | ||
203 | #define chan_dbg(chan, fmt, arg...) \ | |
204 | dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) | |
205 | #define chan_err(chan, fmt, arg...) \ | |
206 | dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) | |
207 | ||
208 | struct xgene_dma_desc_hw { | |
6d0767c1 RPS |
209 | __le64 m0; |
210 | __le64 m1; | |
211 | __le64 m2; | |
212 | __le64 m3; | |
9f2fd0df RPS |
213 | }; |
214 | ||
215 | enum xgene_dma_ring_cfgsize { | |
216 | XGENE_DMA_RING_CFG_SIZE_512B, | |
217 | XGENE_DMA_RING_CFG_SIZE_2KB, | |
218 | XGENE_DMA_RING_CFG_SIZE_16KB, | |
219 | XGENE_DMA_RING_CFG_SIZE_64KB, | |
220 | XGENE_DMA_RING_CFG_SIZE_512KB, | |
221 | XGENE_DMA_RING_CFG_SIZE_INVALID | |
222 | }; | |
223 | ||
224 | struct xgene_dma_ring { | |
225 | struct xgene_dma *pdma; | |
226 | u8 buf_num; | |
227 | u16 id; | |
228 | u16 num; | |
229 | u16 head; | |
230 | u16 owner; | |
231 | u16 slots; | |
232 | u16 dst_ring_num; | |
233 | u32 size; | |
234 | void __iomem *cmd; | |
235 | void __iomem *cmd_base; | |
236 | dma_addr_t desc_paddr; | |
237 | u32 state[XGENE_DMA_RING_NUM_CONFIG]; | |
238 | enum xgene_dma_ring_cfgsize cfgsize; | |
239 | union { | |
240 | void *desc_vaddr; | |
241 | struct xgene_dma_desc_hw *desc_hw; | |
242 | }; | |
243 | }; | |
244 | ||
245 | struct xgene_dma_desc_sw { | |
246 | struct xgene_dma_desc_hw desc1; | |
247 | struct xgene_dma_desc_hw desc2; | |
248 | u32 flags; | |
249 | struct list_head node; | |
250 | struct list_head tx_list; | |
251 | struct dma_async_tx_descriptor tx; | |
252 | }; | |
253 | ||
254 | /** | |
255 | * struct xgene_dma_chan - internal representation of an X-Gene DMA channel | |
256 | * @dma_chan: dmaengine channel object member | |
257 | * @pdma: X-Gene DMA device structure reference | |
258 | * @dev: struct device reference for dma mapping api | |
259 | * @id: raw id of this channel | |
260 | * @rx_irq: channel IRQ | |
261 | * @name: name of X-Gene DMA channel | |
262 | * @lock: serializes enqueue/dequeue operations to the descriptor pool | |
263 | * @pending: number of transaction request pushed to DMA controller for | |
264 | * execution, but still waiting for completion, | |
265 | * @max_outstanding: max number of outstanding request we can push to channel | |
266 | * @ld_pending: descriptors which are queued to run, but have not yet been | |
267 | * submitted to the hardware for execution | |
268 | * @ld_running: descriptors which are currently being executing by the hardware | |
269 | * @ld_completed: descriptors which have finished execution by the hardware. | |
270 | * These descriptors have already had their cleanup actions run. They | |
271 | * are waiting for the ACK bit to be set by the async tx API. | |
272 | * @desc_pool: descriptor pool for DMA operations | |
273 | * @tasklet: bottom half where all completed descriptors cleans | |
274 | * @tx_ring: transmit ring descriptor that we use to prepare actual | |
275 | * descriptors for further executions | |
276 | * @rx_ring: receive ring descriptor that we use to get completed DMA | |
277 | * descriptors during cleanup time | |
278 | */ | |
279 | struct xgene_dma_chan { | |
280 | struct dma_chan dma_chan; | |
281 | struct xgene_dma *pdma; | |
282 | struct device *dev; | |
283 | int id; | |
284 | int rx_irq; | |
ed1f0418 | 285 | char name[10]; |
9f2fd0df RPS |
286 | spinlock_t lock; |
287 | int pending; | |
288 | int max_outstanding; | |
289 | struct list_head ld_pending; | |
290 | struct list_head ld_running; | |
291 | struct list_head ld_completed; | |
292 | struct dma_pool *desc_pool; | |
293 | struct tasklet_struct tasklet; | |
294 | struct xgene_dma_ring tx_ring; | |
295 | struct xgene_dma_ring rx_ring; | |
296 | }; | |
297 | ||
298 | /** | |
299 | * struct xgene_dma - internal representation of an X-Gene DMA device | |
300 | * @err_irq: DMA error irq number | |
301 | * @ring_num: start id number for DMA ring | |
302 | * @csr_dma: base for DMA register access | |
303 | * @csr_ring: base for DMA ring register access | |
304 | * @csr_ring_cmd: base for DMA ring command register access | |
305 | * @csr_efuse: base for efuse register access | |
306 | * @dma_dev: embedded struct dma_device | |
307 | * @chan: reference to X-Gene DMA channels | |
308 | */ | |
309 | struct xgene_dma { | |
310 | struct device *dev; | |
311 | struct clk *clk; | |
312 | int err_irq; | |
313 | int ring_num; | |
314 | void __iomem *csr_dma; | |
315 | void __iomem *csr_ring; | |
316 | void __iomem *csr_ring_cmd; | |
317 | void __iomem *csr_efuse; | |
318 | struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL]; | |
319 | struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL]; | |
320 | }; | |
321 | ||
322 | static const char * const xgene_dma_desc_err[] = { | |
323 | [ERR_DESC_AXI] = "AXI error when reading src/dst link list", | |
324 | [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc", | |
325 | [ERR_READ_DATA_AXI] = "AXI error when reading data", | |
326 | [ERR_WRITE_DATA_AXI] = "AXI error when writing data", | |
327 | [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch", | |
328 | [ERR_ECC] = "ECC double bit error", | |
329 | [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result", | |
330 | [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same", | |
331 | [ERR_CRC_ERR] = "CRC error", | |
332 | [ERR_CHKSUM] = "Checksum error", | |
333 | [ERR_DIF] = "DIF error", | |
334 | }; | |
335 | ||
336 | static const char * const xgene_dma_err[] = { | |
337 | [ERR_DIF_SIZE_INT] = "DIF size error", | |
338 | [ERR_GS_ERR_INT] = "Gather scatter not same size error", | |
339 | [ERR_FPB_TIMEO_INT] = "Free pool time out error", | |
340 | [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error", | |
341 | [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error", | |
342 | [ERR_WR_TIMEO_INT] = "Write time out error", | |
343 | [ERR_RD_TIMEO_INT] = "Read time out error", | |
344 | [ERR_WR_ERR_INT] = "HBF bus write error", | |
345 | [ERR_RD_ERR_INT] = "HBF bus read error", | |
346 | [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error", | |
347 | [ERR_DESC_DST_INT] = "HFB reading dst link address error", | |
348 | [ERR_DESC_SRC_INT] = "HFB reading src link address error", | |
349 | }; | |
350 | ||
351 | static bool is_pq_enabled(struct xgene_dma *pdma) | |
352 | { | |
353 | u32 val; | |
354 | ||
355 | val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW); | |
356 | return !(val & XGENE_DMA_PQ_DISABLE_MASK); | |
357 | } | |
358 | ||
6d0767c1 | 359 | static u64 xgene_dma_encode_len(size_t len) |
9f2fd0df RPS |
360 | { |
361 | return (len < XGENE_DMA_MAX_BYTE_CNT) ? | |
6d0767c1 RPS |
362 | ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) : |
363 | XGENE_DMA_16K_BUFFER_LEN_CODE; | |
9f2fd0df RPS |
364 | } |
365 | ||
366 | static u8 xgene_dma_encode_xor_flyby(u32 src_cnt) | |
367 | { | |
368 | static u8 flyby_type[] = { | |
369 | FLYBY_2SRC_XOR, /* Dummy */ | |
370 | FLYBY_2SRC_XOR, /* Dummy */ | |
371 | FLYBY_2SRC_XOR, | |
372 | FLYBY_3SRC_XOR, | |
373 | FLYBY_4SRC_XOR, | |
374 | FLYBY_5SRC_XOR | |
375 | }; | |
376 | ||
377 | return flyby_type[src_cnt]; | |
378 | } | |
379 | ||
380 | static u32 xgene_dma_ring_desc_cnt(struct xgene_dma_ring *ring) | |
381 | { | |
382 | u32 __iomem *cmd_base = ring->cmd_base; | |
383 | u32 ring_state = ioread32(&cmd_base[1]); | |
384 | ||
385 | return XGENE_DMA_RING_DESC_CNT(ring_state); | |
386 | } | |
387 | ||
6d0767c1 | 388 | static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len, |
9f2fd0df RPS |
389 | dma_addr_t *paddr) |
390 | { | |
391 | size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ? | |
392 | *len : XGENE_DMA_MAX_BYTE_CNT; | |
393 | ||
6d0767c1 RPS |
394 | *ext8 |= cpu_to_le64(*paddr); |
395 | *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes)); | |
9f2fd0df RPS |
396 | *len -= nbytes; |
397 | *paddr += nbytes; | |
398 | } | |
399 | ||
6d0767c1 | 400 | static void xgene_dma_invalidate_buffer(__le64 *ext8) |
9f2fd0df | 401 | { |
6d0767c1 | 402 | *ext8 |= cpu_to_le64(XGENE_DMA_INVALID_LEN_CODE); |
9f2fd0df RPS |
403 | } |
404 | ||
6d0767c1 | 405 | static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx) |
9f2fd0df | 406 | { |
6d0767c1 RPS |
407 | switch (idx) { |
408 | case 0: | |
409 | return &desc->m1; | |
410 | case 1: | |
411 | return &desc->m0; | |
412 | case 2: | |
413 | return &desc->m3; | |
414 | case 3: | |
415 | return &desc->m2; | |
416 | default: | |
417 | pr_err("Invalid dma descriptor index\n"); | |
418 | } | |
419 | ||
420 | return NULL; | |
9f2fd0df RPS |
421 | } |
422 | ||
6d0767c1 RPS |
423 | static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc, |
424 | u16 dst_ring_num) | |
9f2fd0df | 425 | { |
6d0767c1 RPS |
426 | desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT); |
427 | desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA << | |
428 | XGENE_DMA_DESC_RTYPE_POS); | |
429 | desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT); | |
430 | desc->m3 |= cpu_to_le64((u64)dst_ring_num << | |
431 | XGENE_DMA_DESC_HOENQ_NUM_POS); | |
9f2fd0df RPS |
432 | } |
433 | ||
434 | static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan *chan, | |
435 | struct xgene_dma_desc_sw *desc_sw, | |
436 | dma_addr_t dst, dma_addr_t src, | |
437 | size_t len) | |
438 | { | |
6d0767c1 | 439 | struct xgene_dma_desc_hw *desc1, *desc2; |
9f2fd0df RPS |
440 | int i; |
441 | ||
442 | /* Get 1st descriptor */ | |
443 | desc1 = &desc_sw->desc1; | |
444 | xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num); | |
445 | ||
446 | /* Set destination address */ | |
6d0767c1 RPS |
447 | desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT); |
448 | desc1->m3 |= cpu_to_le64(dst); | |
9f2fd0df RPS |
449 | |
450 | /* Set 1st source address */ | |
6d0767c1 | 451 | xgene_dma_set_src_buffer(&desc1->m1, &len, &src); |
9f2fd0df | 452 | |
6d0767c1 RPS |
453 | if (!len) |
454 | return; | |
9f2fd0df RPS |
455 | |
456 | /* | |
457 | * We need to split this source buffer, | |
458 | * and need to use 2nd descriptor | |
459 | */ | |
460 | desc2 = &desc_sw->desc2; | |
6d0767c1 | 461 | desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT); |
9f2fd0df RPS |
462 | |
463 | /* Set 2nd to 5th source address */ | |
464 | for (i = 0; i < 4 && len; i++) | |
465 | xgene_dma_set_src_buffer(xgene_dma_lookup_ext8(desc2, i), | |
466 | &len, &src); | |
467 | ||
468 | /* Invalidate unused source address field */ | |
469 | for (; i < 4; i++) | |
470 | xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i)); | |
471 | ||
472 | /* Updated flag that we have prepared 64B descriptor */ | |
473 | desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC; | |
9f2fd0df RPS |
474 | } |
475 | ||
476 | static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan, | |
477 | struct xgene_dma_desc_sw *desc_sw, | |
478 | dma_addr_t *dst, dma_addr_t *src, | |
479 | u32 src_cnt, size_t *nbytes, | |
480 | const u8 *scf) | |
481 | { | |
6d0767c1 | 482 | struct xgene_dma_desc_hw *desc1, *desc2; |
9f2fd0df RPS |
483 | size_t len = *nbytes; |
484 | int i; | |
485 | ||
486 | desc1 = &desc_sw->desc1; | |
487 | desc2 = &desc_sw->desc2; | |
488 | ||
489 | /* Initialize DMA descriptor */ | |
490 | xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num); | |
491 | ||
492 | /* Set destination address */ | |
6d0767c1 RPS |
493 | desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT); |
494 | desc1->m3 |= cpu_to_le64(*dst); | |
9f2fd0df RPS |
495 | |
496 | /* We have multiple source addresses, so need to set NV bit*/ | |
6d0767c1 | 497 | desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT); |
9f2fd0df RPS |
498 | |
499 | /* Set flyby opcode */ | |
6d0767c1 | 500 | desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt)); |
9f2fd0df RPS |
501 | |
502 | /* Set 1st to 5th source addresses */ | |
503 | for (i = 0; i < src_cnt; i++) { | |
504 | len = *nbytes; | |
6d0767c1 | 505 | xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 : |
9f2fd0df RPS |
506 | xgene_dma_lookup_ext8(desc2, i - 1), |
507 | &len, &src[i]); | |
6d0767c1 | 508 | desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8))); |
9f2fd0df RPS |
509 | } |
510 | ||
9f2fd0df RPS |
511 | /* Update meta data */ |
512 | *nbytes = len; | |
513 | *dst += XGENE_DMA_MAX_BYTE_CNT; | |
514 | ||
515 | /* We need always 64B descriptor to perform xor or pq operations */ | |
516 | desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC; | |
517 | } | |
518 | ||
519 | static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx) | |
520 | { | |
521 | struct xgene_dma_desc_sw *desc; | |
522 | struct xgene_dma_chan *chan; | |
523 | dma_cookie_t cookie; | |
524 | ||
525 | if (unlikely(!tx)) | |
526 | return -EINVAL; | |
527 | ||
528 | chan = to_dma_chan(tx->chan); | |
529 | desc = to_dma_desc_sw(tx); | |
530 | ||
531 | spin_lock_bh(&chan->lock); | |
532 | ||
533 | cookie = dma_cookie_assign(tx); | |
534 | ||
535 | /* Add this transaction list onto the tail of the pending queue */ | |
536 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
537 | ||
538 | spin_unlock_bh(&chan->lock); | |
539 | ||
540 | return cookie; | |
541 | } | |
542 | ||
543 | static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan, | |
544 | struct xgene_dma_desc_sw *desc) | |
545 | { | |
546 | list_del(&desc->node); | |
547 | chan_dbg(chan, "LD %p free\n", desc); | |
548 | dma_pool_free(chan->desc_pool, desc, desc->tx.phys); | |
549 | } | |
550 | ||
551 | static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor( | |
552 | struct xgene_dma_chan *chan) | |
553 | { | |
554 | struct xgene_dma_desc_sw *desc; | |
555 | dma_addr_t phys; | |
556 | ||
557 | desc = dma_pool_alloc(chan->desc_pool, GFP_NOWAIT, &phys); | |
558 | if (!desc) { | |
559 | chan_err(chan, "Failed to allocate LDs\n"); | |
560 | return NULL; | |
561 | } | |
562 | ||
563 | memset(desc, 0, sizeof(*desc)); | |
564 | ||
565 | INIT_LIST_HEAD(&desc->tx_list); | |
566 | desc->tx.phys = phys; | |
567 | desc->tx.tx_submit = xgene_dma_tx_submit; | |
568 | dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan); | |
569 | ||
570 | chan_dbg(chan, "LD %p allocated\n", desc); | |
571 | ||
572 | return desc; | |
573 | } | |
574 | ||
575 | /** | |
576 | * xgene_dma_clean_completed_descriptor - free all descriptors which | |
577 | * has been completed and acked | |
578 | * @chan: X-Gene DMA channel | |
579 | * | |
580 | * This function is used on all completed and acked descriptors. | |
581 | */ | |
582 | static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan) | |
583 | { | |
584 | struct xgene_dma_desc_sw *desc, *_desc; | |
585 | ||
586 | /* Run the callback for each descriptor, in order */ | |
587 | list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) { | |
588 | if (async_tx_test_ack(&desc->tx)) | |
589 | xgene_dma_clean_descriptor(chan, desc); | |
590 | } | |
591 | } | |
592 | ||
593 | /** | |
594 | * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor | |
595 | * @chan: X-Gene DMA channel | |
596 | * @desc: descriptor to cleanup and free | |
597 | * | |
598 | * This function is used on a descriptor which has been executed by the DMA | |
599 | * controller. It will run any callbacks, submit any dependencies. | |
600 | */ | |
601 | static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan, | |
602 | struct xgene_dma_desc_sw *desc) | |
603 | { | |
604 | struct dma_async_tx_descriptor *tx = &desc->tx; | |
605 | ||
606 | /* | |
607 | * If this is not the last transaction in the group, | |
608 | * then no need to complete cookie and run any callback as | |
609 | * this is not the tx_descriptor which had been sent to caller | |
610 | * of this DMA request | |
611 | */ | |
612 | ||
613 | if (tx->cookie == 0) | |
614 | return; | |
615 | ||
616 | dma_cookie_complete(tx); | |
617 | ||
618 | /* Run the link descriptor callback function */ | |
619 | if (tx->callback) | |
620 | tx->callback(tx->callback_param); | |
621 | ||
622 | dma_descriptor_unmap(tx); | |
623 | ||
624 | /* Run any dependencies */ | |
625 | dma_run_dependencies(tx); | |
626 | } | |
627 | ||
628 | /** | |
629 | * xgene_dma_clean_running_descriptor - move the completed descriptor from | |
630 | * ld_running to ld_completed | |
631 | * @chan: X-Gene DMA channel | |
632 | * @desc: the descriptor which is completed | |
633 | * | |
634 | * Free the descriptor directly if acked by async_tx api, | |
635 | * else move it to queue ld_completed. | |
636 | */ | |
637 | static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan, | |
638 | struct xgene_dma_desc_sw *desc) | |
639 | { | |
640 | /* Remove from the list of running transactions */ | |
641 | list_del(&desc->node); | |
642 | ||
643 | /* | |
644 | * the client is allowed to attach dependent operations | |
645 | * until 'ack' is set | |
646 | */ | |
647 | if (!async_tx_test_ack(&desc->tx)) { | |
648 | /* | |
649 | * Move this descriptor to the list of descriptors which is | |
650 | * completed, but still awaiting the 'ack' bit to be set. | |
651 | */ | |
652 | list_add_tail(&desc->node, &chan->ld_completed); | |
653 | return; | |
654 | } | |
655 | ||
656 | chan_dbg(chan, "LD %p free\n", desc); | |
657 | dma_pool_free(chan->desc_pool, desc, desc->tx.phys); | |
658 | } | |
659 | ||
660 | static int xgene_chan_xfer_request(struct xgene_dma_ring *ring, | |
661 | struct xgene_dma_desc_sw *desc_sw) | |
662 | { | |
663 | struct xgene_dma_desc_hw *desc_hw; | |
664 | ||
665 | /* Check if can push more descriptor to hw for execution */ | |
666 | if (xgene_dma_ring_desc_cnt(ring) > (ring->slots - 2)) | |
667 | return -EBUSY; | |
668 | ||
669 | /* Get hw descriptor from DMA tx ring */ | |
670 | desc_hw = &ring->desc_hw[ring->head]; | |
671 | ||
672 | /* | |
673 | * Increment the head count to point next | |
674 | * descriptor for next time | |
675 | */ | |
676 | if (++ring->head == ring->slots) | |
677 | ring->head = 0; | |
678 | ||
679 | /* Copy prepared sw descriptor data to hw descriptor */ | |
680 | memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw)); | |
681 | ||
682 | /* | |
683 | * Check if we have prepared 64B descriptor, | |
684 | * in this case we need one more hw descriptor | |
685 | */ | |
686 | if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) { | |
687 | desc_hw = &ring->desc_hw[ring->head]; | |
688 | ||
689 | if (++ring->head == ring->slots) | |
690 | ring->head = 0; | |
691 | ||
692 | memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw)); | |
693 | } | |
694 | ||
695 | /* Notify the hw that we have descriptor ready for execution */ | |
696 | iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ? | |
697 | 2 : 1, ring->cmd); | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
702 | /** | |
703 | * xgene_chan_xfer_ld_pending - push any pending transactions to hw | |
704 | * @chan : X-Gene DMA channel | |
705 | * | |
6d0767c1 | 706 | * LOCKING: must hold chan->lock |
9f2fd0df RPS |
707 | */ |
708 | static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan) | |
709 | { | |
710 | struct xgene_dma_desc_sw *desc_sw, *_desc_sw; | |
711 | int ret; | |
712 | ||
713 | /* | |
714 | * If the list of pending descriptors is empty, then we | |
715 | * don't need to do any work at all | |
716 | */ | |
717 | if (list_empty(&chan->ld_pending)) { | |
718 | chan_dbg(chan, "No pending LDs\n"); | |
719 | return; | |
720 | } | |
721 | ||
722 | /* | |
723 | * Move elements from the queue of pending transactions onto the list | |
724 | * of running transactions and push it to hw for further executions | |
725 | */ | |
726 | list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) { | |
727 | /* | |
728 | * Check if have pushed max number of transactions to hw | |
729 | * as capable, so let's stop here and will push remaining | |
730 | * elements from pening ld queue after completing some | |
731 | * descriptors that we have already pushed | |
732 | */ | |
733 | if (chan->pending >= chan->max_outstanding) | |
734 | return; | |
735 | ||
736 | ret = xgene_chan_xfer_request(&chan->tx_ring, desc_sw); | |
737 | if (ret) | |
738 | return; | |
739 | ||
740 | /* | |
741 | * Delete this element from ld pending queue and append it to | |
742 | * ld running queue | |
743 | */ | |
744 | list_move_tail(&desc_sw->node, &chan->ld_running); | |
745 | ||
746 | /* Increment the pending transaction count */ | |
747 | chan->pending++; | |
748 | } | |
749 | } | |
750 | ||
751 | /** | |
752 | * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed | |
753 | * and move them to ld_completed to free until flag 'ack' is set | |
754 | * @chan: X-Gene DMA channel | |
755 | * | |
756 | * This function is used on descriptors which have been executed by the DMA | |
757 | * controller. It will run any callbacks, submit any dependencies, then | |
758 | * free these descriptors if flag 'ack' is set. | |
759 | */ | |
760 | static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan) | |
761 | { | |
762 | struct xgene_dma_ring *ring = &chan->rx_ring; | |
763 | struct xgene_dma_desc_sw *desc_sw, *_desc_sw; | |
764 | struct xgene_dma_desc_hw *desc_hw; | |
765 | u8 status; | |
766 | ||
767 | /* Clean already completed and acked descriptors */ | |
768 | xgene_dma_clean_completed_descriptor(chan); | |
769 | ||
770 | /* Run the callback for each descriptor, in order */ | |
771 | list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) { | |
772 | /* Get subsequent hw descriptor from DMA rx ring */ | |
773 | desc_hw = &ring->desc_hw[ring->head]; | |
774 | ||
775 | /* Check if this descriptor has been completed */ | |
6d0767c1 RPS |
776 | if (unlikely(le64_to_cpu(desc_hw->m0) == |
777 | XGENE_DMA_DESC_EMPTY_SIGNATURE)) | |
9f2fd0df RPS |
778 | break; |
779 | ||
780 | if (++ring->head == ring->slots) | |
781 | ring->head = 0; | |
782 | ||
783 | /* Check if we have any error with DMA transactions */ | |
784 | status = XGENE_DMA_DESC_STATUS( | |
785 | XGENE_DMA_DESC_ELERR_RD(le64_to_cpu( | |
786 | desc_hw->m0)), | |
787 | XGENE_DMA_DESC_LERR_RD(le64_to_cpu( | |
788 | desc_hw->m0))); | |
789 | if (status) { | |
790 | /* Print the DMA error type */ | |
791 | chan_err(chan, "%s\n", xgene_dma_desc_err[status]); | |
792 | ||
793 | /* | |
794 | * We have DMA transactions error here. Dump DMA Tx | |
795 | * and Rx descriptors for this request */ | |
796 | XGENE_DMA_DESC_DUMP(&desc_sw->desc1, | |
797 | "X-Gene DMA TX DESC1: "); | |
798 | ||
799 | if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) | |
800 | XGENE_DMA_DESC_DUMP(&desc_sw->desc2, | |
801 | "X-Gene DMA TX DESC2: "); | |
802 | ||
803 | XGENE_DMA_DESC_DUMP(desc_hw, | |
804 | "X-Gene DMA RX ERR DESC: "); | |
805 | } | |
806 | ||
807 | /* Notify the hw about this completed descriptor */ | |
808 | iowrite32(-1, ring->cmd); | |
809 | ||
810 | /* Mark this hw descriptor as processed */ | |
6d0767c1 | 811 | desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE); |
9f2fd0df RPS |
812 | |
813 | xgene_dma_run_tx_complete_actions(chan, desc_sw); | |
814 | ||
815 | xgene_dma_clean_running_descriptor(chan, desc_sw); | |
816 | ||
817 | /* | |
818 | * Decrement the pending transaction count | |
819 | * as we have processed one | |
820 | */ | |
821 | chan->pending--; | |
822 | } | |
823 | ||
824 | /* | |
825 | * Start any pending transactions automatically | |
826 | * In the ideal case, we keep the DMA controller busy while we go | |
827 | * ahead and free the descriptors below. | |
828 | */ | |
829 | xgene_chan_xfer_ld_pending(chan); | |
830 | } | |
831 | ||
832 | static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan) | |
833 | { | |
834 | struct xgene_dma_chan *chan = to_dma_chan(dchan); | |
835 | ||
836 | /* Has this channel already been allocated? */ | |
837 | if (chan->desc_pool) | |
838 | return 1; | |
839 | ||
840 | chan->desc_pool = dma_pool_create(chan->name, chan->dev, | |
841 | sizeof(struct xgene_dma_desc_sw), | |
842 | 0, 0); | |
843 | if (!chan->desc_pool) { | |
844 | chan_err(chan, "Failed to allocate descriptor pool\n"); | |
845 | return -ENOMEM; | |
846 | } | |
847 | ||
848 | chan_dbg(chan, "Allocate descripto pool\n"); | |
849 | ||
850 | return 1; | |
851 | } | |
852 | ||
853 | /** | |
854 | * xgene_dma_free_desc_list - Free all descriptors in a queue | |
855 | * @chan: X-Gene DMA channel | |
856 | * @list: the list to free | |
857 | * | |
6d0767c1 | 858 | * LOCKING: must hold chan->lock |
9f2fd0df RPS |
859 | */ |
860 | static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan, | |
861 | struct list_head *list) | |
862 | { | |
863 | struct xgene_dma_desc_sw *desc, *_desc; | |
864 | ||
865 | list_for_each_entry_safe(desc, _desc, list, node) | |
866 | xgene_dma_clean_descriptor(chan, desc); | |
867 | } | |
868 | ||
9f2fd0df RPS |
869 | static void xgene_dma_free_chan_resources(struct dma_chan *dchan) |
870 | { | |
871 | struct xgene_dma_chan *chan = to_dma_chan(dchan); | |
872 | ||
873 | chan_dbg(chan, "Free all resources\n"); | |
874 | ||
875 | if (!chan->desc_pool) | |
876 | return; | |
877 | ||
878 | spin_lock_bh(&chan->lock); | |
879 | ||
880 | /* Process all running descriptor */ | |
881 | xgene_dma_cleanup_descriptors(chan); | |
882 | ||
883 | /* Clean all link descriptor queues */ | |
884 | xgene_dma_free_desc_list(chan, &chan->ld_pending); | |
885 | xgene_dma_free_desc_list(chan, &chan->ld_running); | |
886 | xgene_dma_free_desc_list(chan, &chan->ld_completed); | |
887 | ||
888 | spin_unlock_bh(&chan->lock); | |
889 | ||
890 | /* Delete this channel DMA pool */ | |
891 | dma_pool_destroy(chan->desc_pool); | |
892 | chan->desc_pool = NULL; | |
893 | } | |
894 | ||
895 | static struct dma_async_tx_descriptor *xgene_dma_prep_memcpy( | |
896 | struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src, | |
897 | size_t len, unsigned long flags) | |
898 | { | |
899 | struct xgene_dma_desc_sw *first = NULL, *new; | |
900 | struct xgene_dma_chan *chan; | |
901 | size_t copy; | |
902 | ||
903 | if (unlikely(!dchan || !len)) | |
904 | return NULL; | |
905 | ||
906 | chan = to_dma_chan(dchan); | |
907 | ||
908 | do { | |
909 | /* Allocate the link descriptor from DMA pool */ | |
910 | new = xgene_dma_alloc_descriptor(chan); | |
911 | if (!new) | |
912 | goto fail; | |
913 | ||
914 | /* Create the largest transaction possible */ | |
915 | copy = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT); | |
916 | ||
917 | /* Prepare DMA descriptor */ | |
918 | xgene_dma_prep_cpy_desc(chan, new, dst, src, copy); | |
919 | ||
920 | if (!first) | |
921 | first = new; | |
922 | ||
923 | new->tx.cookie = 0; | |
924 | async_tx_ack(&new->tx); | |
925 | ||
926 | /* Update metadata */ | |
927 | len -= copy; | |
928 | dst += copy; | |
929 | src += copy; | |
930 | ||
931 | /* Insert the link descriptor to the LD ring */ | |
932 | list_add_tail(&new->node, &first->tx_list); | |
933 | } while (len); | |
934 | ||
935 | new->tx.flags = flags; /* client is in control of this ack */ | |
936 | new->tx.cookie = -EBUSY; | |
937 | list_splice(&first->tx_list, &new->tx_list); | |
938 | ||
939 | return &new->tx; | |
940 | ||
941 | fail: | |
942 | if (!first) | |
943 | return NULL; | |
944 | ||
6d0767c1 | 945 | xgene_dma_free_desc_list(chan, &first->tx_list); |
9f2fd0df RPS |
946 | return NULL; |
947 | } | |
948 | ||
949 | static struct dma_async_tx_descriptor *xgene_dma_prep_sg( | |
950 | struct dma_chan *dchan, struct scatterlist *dst_sg, | |
951 | u32 dst_nents, struct scatterlist *src_sg, | |
952 | u32 src_nents, unsigned long flags) | |
953 | { | |
954 | struct xgene_dma_desc_sw *first = NULL, *new = NULL; | |
955 | struct xgene_dma_chan *chan; | |
956 | size_t dst_avail, src_avail; | |
957 | dma_addr_t dst, src; | |
958 | size_t len; | |
959 | ||
960 | if (unlikely(!dchan)) | |
961 | return NULL; | |
962 | ||
963 | if (unlikely(!dst_nents || !src_nents)) | |
964 | return NULL; | |
965 | ||
966 | if (unlikely(!dst_sg || !src_sg)) | |
967 | return NULL; | |
968 | ||
969 | chan = to_dma_chan(dchan); | |
970 | ||
971 | /* Get prepared for the loop */ | |
972 | dst_avail = sg_dma_len(dst_sg); | |
973 | src_avail = sg_dma_len(src_sg); | |
974 | dst_nents--; | |
975 | src_nents--; | |
976 | ||
977 | /* Run until we are out of scatterlist entries */ | |
978 | while (true) { | |
979 | /* Create the largest transaction possible */ | |
980 | len = min_t(size_t, src_avail, dst_avail); | |
981 | len = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT); | |
982 | if (len == 0) | |
983 | goto fetch; | |
984 | ||
985 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; | |
986 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; | |
987 | ||
988 | /* Allocate the link descriptor from DMA pool */ | |
989 | new = xgene_dma_alloc_descriptor(chan); | |
990 | if (!new) | |
991 | goto fail; | |
992 | ||
993 | /* Prepare DMA descriptor */ | |
994 | xgene_dma_prep_cpy_desc(chan, new, dst, src, len); | |
995 | ||
996 | if (!first) | |
997 | first = new; | |
998 | ||
999 | new->tx.cookie = 0; | |
1000 | async_tx_ack(&new->tx); | |
1001 | ||
1002 | /* update metadata */ | |
1003 | dst_avail -= len; | |
1004 | src_avail -= len; | |
1005 | ||
1006 | /* Insert the link descriptor to the LD ring */ | |
1007 | list_add_tail(&new->node, &first->tx_list); | |
1008 | ||
1009 | fetch: | |
1010 | /* fetch the next dst scatterlist entry */ | |
1011 | if (dst_avail == 0) { | |
1012 | /* no more entries: we're done */ | |
1013 | if (dst_nents == 0) | |
1014 | break; | |
1015 | ||
1016 | /* fetch the next entry: if there are no more: done */ | |
1017 | dst_sg = sg_next(dst_sg); | |
1018 | if (!dst_sg) | |
1019 | break; | |
1020 | ||
1021 | dst_nents--; | |
1022 | dst_avail = sg_dma_len(dst_sg); | |
1023 | } | |
1024 | ||
1025 | /* fetch the next src scatterlist entry */ | |
1026 | if (src_avail == 0) { | |
1027 | /* no more entries: we're done */ | |
1028 | if (src_nents == 0) | |
1029 | break; | |
1030 | ||
1031 | /* fetch the next entry: if there are no more: done */ | |
1032 | src_sg = sg_next(src_sg); | |
1033 | if (!src_sg) | |
1034 | break; | |
1035 | ||
1036 | src_nents--; | |
1037 | src_avail = sg_dma_len(src_sg); | |
1038 | } | |
1039 | } | |
1040 | ||
1041 | if (!new) | |
1042 | return NULL; | |
1043 | ||
1044 | new->tx.flags = flags; /* client is in control of this ack */ | |
1045 | new->tx.cookie = -EBUSY; | |
1046 | list_splice(&first->tx_list, &new->tx_list); | |
1047 | ||
1048 | return &new->tx; | |
1049 | fail: | |
1050 | if (!first) | |
1051 | return NULL; | |
1052 | ||
6d0767c1 | 1053 | xgene_dma_free_desc_list(chan, &first->tx_list); |
9f2fd0df RPS |
1054 | return NULL; |
1055 | } | |
1056 | ||
1057 | static struct dma_async_tx_descriptor *xgene_dma_prep_xor( | |
1058 | struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src, | |
1059 | u32 src_cnt, size_t len, unsigned long flags) | |
1060 | { | |
1061 | struct xgene_dma_desc_sw *first = NULL, *new; | |
1062 | struct xgene_dma_chan *chan; | |
1063 | static u8 multi[XGENE_DMA_MAX_XOR_SRC] = { | |
1064 | 0x01, 0x01, 0x01, 0x01, 0x01}; | |
1065 | ||
1066 | if (unlikely(!dchan || !len)) | |
1067 | return NULL; | |
1068 | ||
1069 | chan = to_dma_chan(dchan); | |
1070 | ||
1071 | do { | |
1072 | /* Allocate the link descriptor from DMA pool */ | |
1073 | new = xgene_dma_alloc_descriptor(chan); | |
1074 | if (!new) | |
1075 | goto fail; | |
1076 | ||
1077 | /* Prepare xor DMA descriptor */ | |
1078 | xgene_dma_prep_xor_desc(chan, new, &dst, src, | |
1079 | src_cnt, &len, multi); | |
1080 | ||
1081 | if (!first) | |
1082 | first = new; | |
1083 | ||
1084 | new->tx.cookie = 0; | |
1085 | async_tx_ack(&new->tx); | |
1086 | ||
1087 | /* Insert the link descriptor to the LD ring */ | |
1088 | list_add_tail(&new->node, &first->tx_list); | |
1089 | } while (len); | |
1090 | ||
1091 | new->tx.flags = flags; /* client is in control of this ack */ | |
1092 | new->tx.cookie = -EBUSY; | |
1093 | list_splice(&first->tx_list, &new->tx_list); | |
1094 | ||
1095 | return &new->tx; | |
1096 | ||
1097 | fail: | |
1098 | if (!first) | |
1099 | return NULL; | |
1100 | ||
6d0767c1 | 1101 | xgene_dma_free_desc_list(chan, &first->tx_list); |
9f2fd0df RPS |
1102 | return NULL; |
1103 | } | |
1104 | ||
1105 | static struct dma_async_tx_descriptor *xgene_dma_prep_pq( | |
1106 | struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src, | |
1107 | u32 src_cnt, const u8 *scf, size_t len, unsigned long flags) | |
1108 | { | |
1109 | struct xgene_dma_desc_sw *first = NULL, *new; | |
1110 | struct xgene_dma_chan *chan; | |
1111 | size_t _len = len; | |
1112 | dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC]; | |
1113 | static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01}; | |
1114 | ||
1115 | if (unlikely(!dchan || !len)) | |
1116 | return NULL; | |
1117 | ||
1118 | chan = to_dma_chan(dchan); | |
1119 | ||
1120 | /* | |
1121 | * Save source addresses on local variable, may be we have to | |
1122 | * prepare two descriptor to generate P and Q if both enabled | |
1123 | * in the flags by client | |
1124 | */ | |
1125 | memcpy(_src, src, sizeof(*src) * src_cnt); | |
1126 | ||
1127 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
1128 | len = 0; | |
1129 | ||
1130 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
1131 | _len = 0; | |
1132 | ||
1133 | do { | |
1134 | /* Allocate the link descriptor from DMA pool */ | |
1135 | new = xgene_dma_alloc_descriptor(chan); | |
1136 | if (!new) | |
1137 | goto fail; | |
1138 | ||
1139 | if (!first) | |
1140 | first = new; | |
1141 | ||
1142 | new->tx.cookie = 0; | |
1143 | async_tx_ack(&new->tx); | |
1144 | ||
1145 | /* Insert the link descriptor to the LD ring */ | |
1146 | list_add_tail(&new->node, &first->tx_list); | |
1147 | ||
1148 | /* | |
1149 | * Prepare DMA descriptor to generate P, | |
1150 | * if DMA_PREP_PQ_DISABLE_P flag is not set | |
1151 | */ | |
1152 | if (len) { | |
1153 | xgene_dma_prep_xor_desc(chan, new, &dst[0], src, | |
1154 | src_cnt, &len, multi); | |
1155 | continue; | |
1156 | } | |
1157 | ||
1158 | /* | |
1159 | * Prepare DMA descriptor to generate Q, | |
1160 | * if DMA_PREP_PQ_DISABLE_Q flag is not set | |
1161 | */ | |
1162 | if (_len) { | |
1163 | xgene_dma_prep_xor_desc(chan, new, &dst[1], _src, | |
1164 | src_cnt, &_len, scf); | |
1165 | } | |
1166 | } while (len || _len); | |
1167 | ||
1168 | new->tx.flags = flags; /* client is in control of this ack */ | |
1169 | new->tx.cookie = -EBUSY; | |
1170 | list_splice(&first->tx_list, &new->tx_list); | |
1171 | ||
1172 | return &new->tx; | |
1173 | ||
1174 | fail: | |
1175 | if (!first) | |
1176 | return NULL; | |
1177 | ||
6d0767c1 | 1178 | xgene_dma_free_desc_list(chan, &first->tx_list); |
9f2fd0df RPS |
1179 | return NULL; |
1180 | } | |
1181 | ||
1182 | static void xgene_dma_issue_pending(struct dma_chan *dchan) | |
1183 | { | |
1184 | struct xgene_dma_chan *chan = to_dma_chan(dchan); | |
1185 | ||
1186 | spin_lock_bh(&chan->lock); | |
1187 | xgene_chan_xfer_ld_pending(chan); | |
1188 | spin_unlock_bh(&chan->lock); | |
1189 | } | |
1190 | ||
1191 | static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan, | |
1192 | dma_cookie_t cookie, | |
1193 | struct dma_tx_state *txstate) | |
1194 | { | |
1195 | return dma_cookie_status(dchan, cookie, txstate); | |
1196 | } | |
1197 | ||
1198 | static void xgene_dma_tasklet_cb(unsigned long data) | |
1199 | { | |
1200 | struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data; | |
1201 | ||
1202 | spin_lock_bh(&chan->lock); | |
1203 | ||
1204 | /* Run all cleanup for descriptors which have been completed */ | |
1205 | xgene_dma_cleanup_descriptors(chan); | |
1206 | ||
1207 | /* Re-enable DMA channel IRQ */ | |
1208 | enable_irq(chan->rx_irq); | |
1209 | ||
1210 | spin_unlock_bh(&chan->lock); | |
1211 | } | |
1212 | ||
1213 | static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id) | |
1214 | { | |
1215 | struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id; | |
1216 | ||
1217 | BUG_ON(!chan); | |
1218 | ||
1219 | /* | |
1220 | * Disable DMA channel IRQ until we process completed | |
1221 | * descriptors | |
1222 | */ | |
1223 | disable_irq_nosync(chan->rx_irq); | |
1224 | ||
1225 | /* | |
1226 | * Schedule the tasklet to handle all cleanup of the current | |
1227 | * transaction. It will start a new transaction if there is | |
1228 | * one pending. | |
1229 | */ | |
1230 | tasklet_schedule(&chan->tasklet); | |
1231 | ||
1232 | return IRQ_HANDLED; | |
1233 | } | |
1234 | ||
1235 | static irqreturn_t xgene_dma_err_isr(int irq, void *id) | |
1236 | { | |
1237 | struct xgene_dma *pdma = (struct xgene_dma *)id; | |
1238 | unsigned long int_mask; | |
1239 | u32 val, i; | |
1240 | ||
1241 | val = ioread32(pdma->csr_dma + XGENE_DMA_INT); | |
1242 | ||
1243 | /* Clear DMA interrupts */ | |
1244 | iowrite32(val, pdma->csr_dma + XGENE_DMA_INT); | |
1245 | ||
1246 | /* Print DMA error info */ | |
1247 | int_mask = val >> XGENE_DMA_INT_MASK_SHIFT; | |
1248 | for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err)) | |
1249 | dev_err(pdma->dev, | |
1250 | "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]); | |
1251 | ||
1252 | return IRQ_HANDLED; | |
1253 | } | |
1254 | ||
1255 | static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring) | |
1256 | { | |
1257 | int i; | |
1258 | ||
1259 | iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE); | |
1260 | ||
1261 | for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++) | |
1262 | iowrite32(ring->state[i], ring->pdma->csr_ring + | |
1263 | XGENE_DMA_RING_STATE_WR_BASE + (i * 4)); | |
1264 | } | |
1265 | ||
1266 | static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring) | |
1267 | { | |
1268 | memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG); | |
1269 | xgene_dma_wr_ring_state(ring); | |
1270 | } | |
1271 | ||
1272 | static void xgene_dma_setup_ring(struct xgene_dma_ring *ring) | |
1273 | { | |
1274 | void *ring_cfg = ring->state; | |
1275 | u64 addr = ring->desc_paddr; | |
9f2fd0df RPS |
1276 | u32 i, val; |
1277 | ||
1278 | ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE; | |
1279 | ||
1280 | /* Clear DMA ring state */ | |
1281 | xgene_dma_clr_ring_state(ring); | |
1282 | ||
1283 | /* Set DMA ring type */ | |
1284 | XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR); | |
1285 | ||
1286 | if (ring->owner == XGENE_DMA_RING_OWNER_DMA) { | |
1287 | /* Set recombination buffer and timeout */ | |
1288 | XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg); | |
1289 | XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg); | |
1290 | XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg); | |
1291 | } | |
1292 | ||
1293 | /* Initialize DMA ring state */ | |
1294 | XGENE_DMA_RING_SELTHRSH_SET(ring_cfg); | |
1295 | XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg); | |
1296 | XGENE_DMA_RING_COHERENT_SET(ring_cfg); | |
1297 | XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr); | |
1298 | XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr); | |
1299 | XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize); | |
1300 | ||
1301 | /* Write DMA ring configurations */ | |
1302 | xgene_dma_wr_ring_state(ring); | |
1303 | ||
1304 | /* Set DMA ring id */ | |
1305 | iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id), | |
1306 | ring->pdma->csr_ring + XGENE_DMA_RING_ID); | |
1307 | ||
1308 | /* Set DMA ring buffer */ | |
1309 | iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num), | |
1310 | ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF); | |
1311 | ||
1312 | if (ring->owner != XGENE_DMA_RING_OWNER_CPU) | |
1313 | return; | |
1314 | ||
1315 | /* Set empty signature to DMA Rx ring descriptors */ | |
1316 | for (i = 0; i < ring->slots; i++) { | |
6d0767c1 RPS |
1317 | struct xgene_dma_desc_hw *desc; |
1318 | ||
9f2fd0df | 1319 | desc = &ring->desc_hw[i]; |
6d0767c1 | 1320 | desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE); |
9f2fd0df RPS |
1321 | } |
1322 | ||
1323 | /* Enable DMA Rx ring interrupt */ | |
1324 | val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE); | |
1325 | XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num); | |
1326 | iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE); | |
1327 | } | |
1328 | ||
1329 | static void xgene_dma_clear_ring(struct xgene_dma_ring *ring) | |
1330 | { | |
1331 | u32 ring_id, val; | |
1332 | ||
1333 | if (ring->owner == XGENE_DMA_RING_OWNER_CPU) { | |
1334 | /* Disable DMA Rx ring interrupt */ | |
1335 | val = ioread32(ring->pdma->csr_ring + | |
1336 | XGENE_DMA_RING_NE_INT_MODE); | |
1337 | XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num); | |
1338 | iowrite32(val, ring->pdma->csr_ring + | |
1339 | XGENE_DMA_RING_NE_INT_MODE); | |
1340 | } | |
1341 | ||
1342 | /* Clear DMA ring state */ | |
1343 | ring_id = XGENE_DMA_RING_ID_SETUP(ring->id); | |
1344 | iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID); | |
1345 | ||
1346 | iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF); | |
1347 | xgene_dma_clr_ring_state(ring); | |
1348 | } | |
1349 | ||
1350 | static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring) | |
1351 | { | |
1352 | ring->cmd_base = ring->pdma->csr_ring_cmd + | |
1353 | XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num - | |
1354 | XGENE_DMA_RING_NUM)); | |
1355 | ||
1356 | ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET; | |
1357 | } | |
1358 | ||
1359 | static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan, | |
1360 | enum xgene_dma_ring_cfgsize cfgsize) | |
1361 | { | |
1362 | int size; | |
1363 | ||
1364 | switch (cfgsize) { | |
1365 | case XGENE_DMA_RING_CFG_SIZE_512B: | |
1366 | size = 0x200; | |
1367 | break; | |
1368 | case XGENE_DMA_RING_CFG_SIZE_2KB: | |
1369 | size = 0x800; | |
1370 | break; | |
1371 | case XGENE_DMA_RING_CFG_SIZE_16KB: | |
1372 | size = 0x4000; | |
1373 | break; | |
1374 | case XGENE_DMA_RING_CFG_SIZE_64KB: | |
1375 | size = 0x10000; | |
1376 | break; | |
1377 | case XGENE_DMA_RING_CFG_SIZE_512KB: | |
1378 | size = 0x80000; | |
1379 | break; | |
1380 | default: | |
1381 | chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize); | |
1382 | return -EINVAL; | |
1383 | } | |
1384 | ||
1385 | return size; | |
1386 | } | |
1387 | ||
1388 | static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring) | |
1389 | { | |
1390 | /* Clear DMA ring configurations */ | |
1391 | xgene_dma_clear_ring(ring); | |
1392 | ||
1393 | /* De-allocate DMA ring descriptor */ | |
1394 | if (ring->desc_vaddr) { | |
1395 | dma_free_coherent(ring->pdma->dev, ring->size, | |
1396 | ring->desc_vaddr, ring->desc_paddr); | |
1397 | ring->desc_vaddr = NULL; | |
1398 | } | |
1399 | } | |
1400 | ||
1401 | static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan) | |
1402 | { | |
1403 | xgene_dma_delete_ring_one(&chan->rx_ring); | |
1404 | xgene_dma_delete_ring_one(&chan->tx_ring); | |
1405 | } | |
1406 | ||
1407 | static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan, | |
1408 | struct xgene_dma_ring *ring, | |
1409 | enum xgene_dma_ring_cfgsize cfgsize) | |
1410 | { | |
1411 | /* Setup DMA ring descriptor variables */ | |
1412 | ring->pdma = chan->pdma; | |
1413 | ring->cfgsize = cfgsize; | |
1414 | ring->num = chan->pdma->ring_num++; | |
1415 | ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num); | |
1416 | ||
1417 | ring->size = xgene_dma_get_ring_size(chan, cfgsize); | |
1418 | if (ring->size <= 0) | |
1419 | return ring->size; | |
1420 | ||
1421 | /* Allocate memory for DMA ring descriptor */ | |
1422 | ring->desc_vaddr = dma_zalloc_coherent(chan->dev, ring->size, | |
1423 | &ring->desc_paddr, GFP_KERNEL); | |
1424 | if (!ring->desc_vaddr) { | |
1425 | chan_err(chan, "Failed to allocate ring desc\n"); | |
1426 | return -ENOMEM; | |
1427 | } | |
1428 | ||
1429 | /* Configure and enable DMA ring */ | |
1430 | xgene_dma_set_ring_cmd(ring); | |
1431 | xgene_dma_setup_ring(ring); | |
1432 | ||
1433 | return 0; | |
1434 | } | |
1435 | ||
1436 | static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan) | |
1437 | { | |
1438 | struct xgene_dma_ring *rx_ring = &chan->rx_ring; | |
1439 | struct xgene_dma_ring *tx_ring = &chan->tx_ring; | |
1440 | int ret; | |
1441 | ||
1442 | /* Create DMA Rx ring descriptor */ | |
1443 | rx_ring->owner = XGENE_DMA_RING_OWNER_CPU; | |
1444 | rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id; | |
1445 | ||
1446 | ret = xgene_dma_create_ring_one(chan, rx_ring, | |
1447 | XGENE_DMA_RING_CFG_SIZE_64KB); | |
1448 | if (ret) | |
1449 | return ret; | |
1450 | ||
1451 | chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n", | |
1452 | rx_ring->id, rx_ring->num, rx_ring->desc_vaddr); | |
1453 | ||
1454 | /* Create DMA Tx ring descriptor */ | |
1455 | tx_ring->owner = XGENE_DMA_RING_OWNER_DMA; | |
1456 | tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id; | |
1457 | ||
1458 | ret = xgene_dma_create_ring_one(chan, tx_ring, | |
1459 | XGENE_DMA_RING_CFG_SIZE_64KB); | |
1460 | if (ret) { | |
1461 | xgene_dma_delete_ring_one(rx_ring); | |
1462 | return ret; | |
1463 | } | |
1464 | ||
1465 | tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num); | |
1466 | ||
1467 | chan_dbg(chan, | |
1468 | "Tx ring id 0x%X num %d desc 0x%p\n", | |
1469 | tx_ring->id, tx_ring->num, tx_ring->desc_vaddr); | |
1470 | ||
1471 | /* Set the max outstanding request possible to this channel */ | |
1472 | chan->max_outstanding = rx_ring->slots; | |
1473 | ||
1474 | return ret; | |
1475 | } | |
1476 | ||
1477 | static int xgene_dma_init_rings(struct xgene_dma *pdma) | |
1478 | { | |
1479 | int ret, i, j; | |
1480 | ||
1481 | for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { | |
1482 | ret = xgene_dma_create_chan_rings(&pdma->chan[i]); | |
1483 | if (ret) { | |
1484 | for (j = 0; j < i; j++) | |
1485 | xgene_dma_delete_chan_rings(&pdma->chan[j]); | |
1486 | return ret; | |
1487 | } | |
1488 | } | |
1489 | ||
1490 | return ret; | |
1491 | } | |
1492 | ||
1493 | static void xgene_dma_enable(struct xgene_dma *pdma) | |
1494 | { | |
1495 | u32 val; | |
1496 | ||
1497 | /* Configure and enable DMA engine */ | |
1498 | val = ioread32(pdma->csr_dma + XGENE_DMA_GCR); | |
1499 | XGENE_DMA_CH_SETUP(val); | |
1500 | XGENE_DMA_ENABLE(val); | |
1501 | iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR); | |
1502 | } | |
1503 | ||
1504 | static void xgene_dma_disable(struct xgene_dma *pdma) | |
1505 | { | |
1506 | u32 val; | |
1507 | ||
1508 | val = ioread32(pdma->csr_dma + XGENE_DMA_GCR); | |
1509 | XGENE_DMA_DISABLE(val); | |
1510 | iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR); | |
1511 | } | |
1512 | ||
1513 | static void xgene_dma_mask_interrupts(struct xgene_dma *pdma) | |
1514 | { | |
1515 | /* | |
1516 | * Mask DMA ring overflow, underflow and | |
1517 | * AXI write/read error interrupts | |
1518 | */ | |
1519 | iowrite32(XGENE_DMA_INT_ALL_MASK, | |
1520 | pdma->csr_dma + XGENE_DMA_RING_INT0_MASK); | |
1521 | iowrite32(XGENE_DMA_INT_ALL_MASK, | |
1522 | pdma->csr_dma + XGENE_DMA_RING_INT1_MASK); | |
1523 | iowrite32(XGENE_DMA_INT_ALL_MASK, | |
1524 | pdma->csr_dma + XGENE_DMA_RING_INT2_MASK); | |
1525 | iowrite32(XGENE_DMA_INT_ALL_MASK, | |
1526 | pdma->csr_dma + XGENE_DMA_RING_INT3_MASK); | |
1527 | iowrite32(XGENE_DMA_INT_ALL_MASK, | |
1528 | pdma->csr_dma + XGENE_DMA_RING_INT4_MASK); | |
1529 | ||
1530 | /* Mask DMA error interrupts */ | |
1531 | iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK); | |
1532 | } | |
1533 | ||
1534 | static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma) | |
1535 | { | |
1536 | /* | |
1537 | * Unmask DMA ring overflow, underflow and | |
1538 | * AXI write/read error interrupts | |
1539 | */ | |
1540 | iowrite32(XGENE_DMA_INT_ALL_UNMASK, | |
1541 | pdma->csr_dma + XGENE_DMA_RING_INT0_MASK); | |
1542 | iowrite32(XGENE_DMA_INT_ALL_UNMASK, | |
1543 | pdma->csr_dma + XGENE_DMA_RING_INT1_MASK); | |
1544 | iowrite32(XGENE_DMA_INT_ALL_UNMASK, | |
1545 | pdma->csr_dma + XGENE_DMA_RING_INT2_MASK); | |
1546 | iowrite32(XGENE_DMA_INT_ALL_UNMASK, | |
1547 | pdma->csr_dma + XGENE_DMA_RING_INT3_MASK); | |
1548 | iowrite32(XGENE_DMA_INT_ALL_UNMASK, | |
1549 | pdma->csr_dma + XGENE_DMA_RING_INT4_MASK); | |
1550 | ||
1551 | /* Unmask DMA error interrupts */ | |
1552 | iowrite32(XGENE_DMA_INT_ALL_UNMASK, | |
1553 | pdma->csr_dma + XGENE_DMA_INT_MASK); | |
1554 | } | |
1555 | ||
1556 | static void xgene_dma_init_hw(struct xgene_dma *pdma) | |
1557 | { | |
1558 | u32 val; | |
1559 | ||
1560 | /* Associate DMA ring to corresponding ring HW */ | |
1561 | iowrite32(XGENE_DMA_ASSOC_RING_MNGR1, | |
1562 | pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC); | |
1563 | ||
1564 | /* Configure RAID6 polynomial control setting */ | |
1565 | if (is_pq_enabled(pdma)) | |
1566 | iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D), | |
1567 | pdma->csr_dma + XGENE_DMA_RAID6_CONT); | |
1568 | else | |
1569 | dev_info(pdma->dev, "PQ is disabled in HW\n"); | |
1570 | ||
1571 | xgene_dma_enable(pdma); | |
1572 | xgene_dma_unmask_interrupts(pdma); | |
1573 | ||
1574 | /* Get DMA id and version info */ | |
1575 | val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR); | |
1576 | ||
1577 | /* DMA device info */ | |
1578 | dev_info(pdma->dev, | |
1579 | "X-Gene DMA v%d.%02d.%02d driver registered %d channels", | |
1580 | XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val), | |
1581 | XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL); | |
1582 | } | |
1583 | ||
a3f92e8e | 1584 | static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma) |
9f2fd0df RPS |
1585 | { |
1586 | if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) && | |
1587 | (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST))) | |
1588 | return 0; | |
1589 | ||
1590 | iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN); | |
1591 | iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST); | |
1592 | ||
1593 | /* Bring up memory */ | |
1594 | iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN); | |
1595 | ||
1596 | /* Force a barrier */ | |
1597 | ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN); | |
1598 | ||
1599 | /* reset may take up to 1ms */ | |
1600 | usleep_range(1000, 1100); | |
1601 | ||
1602 | if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY) | |
1603 | != XGENE_DMA_RING_BLK_MEM_RDY_VAL) { | |
1604 | dev_err(pdma->dev, | |
1605 | "Failed to release ring mngr memory from shutdown\n"); | |
1606 | return -ENODEV; | |
1607 | } | |
1608 | ||
1609 | /* program threshold set 1 and all hysteresis */ | |
1610 | iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL, | |
1611 | pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1); | |
1612 | iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL, | |
1613 | pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1); | |
1614 | iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL, | |
1615 | pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS); | |
1616 | ||
1617 | /* Enable QPcore and assign error queue */ | |
1618 | iowrite32(XGENE_DMA_RING_ENABLE, | |
1619 | pdma->csr_ring + XGENE_DMA_RING_CONFIG); | |
1620 | ||
1621 | return 0; | |
1622 | } | |
1623 | ||
1624 | static int xgene_dma_init_mem(struct xgene_dma *pdma) | |
1625 | { | |
1626 | int ret; | |
1627 | ||
1628 | ret = xgene_dma_init_ring_mngr(pdma); | |
1629 | if (ret) | |
1630 | return ret; | |
1631 | ||
1632 | /* Bring up memory */ | |
1633 | iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN); | |
1634 | ||
1635 | /* Force a barrier */ | |
1636 | ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN); | |
1637 | ||
1638 | /* reset may take up to 1ms */ | |
1639 | usleep_range(1000, 1100); | |
1640 | ||
1641 | if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY) | |
1642 | != XGENE_DMA_BLK_MEM_RDY_VAL) { | |
1643 | dev_err(pdma->dev, | |
1644 | "Failed to release DMA memory from shutdown\n"); | |
1645 | return -ENODEV; | |
1646 | } | |
1647 | ||
1648 | return 0; | |
1649 | } | |
1650 | ||
1651 | static int xgene_dma_request_irqs(struct xgene_dma *pdma) | |
1652 | { | |
1653 | struct xgene_dma_chan *chan; | |
1654 | int ret, i, j; | |
1655 | ||
1656 | /* Register DMA error irq */ | |
1657 | ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr, | |
1658 | 0, "dma_error", pdma); | |
1659 | if (ret) { | |
1660 | dev_err(pdma->dev, | |
1661 | "Failed to register error IRQ %d\n", pdma->err_irq); | |
1662 | return ret; | |
1663 | } | |
1664 | ||
1665 | /* Register DMA channel rx irq */ | |
1666 | for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { | |
1667 | chan = &pdma->chan[i]; | |
1668 | ret = devm_request_irq(chan->dev, chan->rx_irq, | |
1669 | xgene_dma_chan_ring_isr, | |
1670 | 0, chan->name, chan); | |
1671 | if (ret) { | |
1672 | chan_err(chan, "Failed to register Rx IRQ %d\n", | |
1673 | chan->rx_irq); | |
1674 | devm_free_irq(pdma->dev, pdma->err_irq, pdma); | |
1675 | ||
1676 | for (j = 0; j < i; j++) { | |
1677 | chan = &pdma->chan[i]; | |
1678 | devm_free_irq(chan->dev, chan->rx_irq, chan); | |
1679 | } | |
1680 | ||
1681 | return ret; | |
1682 | } | |
1683 | } | |
1684 | ||
1685 | return 0; | |
1686 | } | |
1687 | ||
1688 | static void xgene_dma_free_irqs(struct xgene_dma *pdma) | |
1689 | { | |
1690 | struct xgene_dma_chan *chan; | |
1691 | int i; | |
1692 | ||
1693 | /* Free DMA device error irq */ | |
1694 | devm_free_irq(pdma->dev, pdma->err_irq, pdma); | |
1695 | ||
1696 | for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { | |
1697 | chan = &pdma->chan[i]; | |
1698 | devm_free_irq(chan->dev, chan->rx_irq, chan); | |
1699 | } | |
1700 | } | |
1701 | ||
1702 | static void xgene_dma_set_caps(struct xgene_dma_chan *chan, | |
1703 | struct dma_device *dma_dev) | |
1704 | { | |
1705 | /* Initialize DMA device capability mask */ | |
1706 | dma_cap_zero(dma_dev->cap_mask); | |
1707 | ||
1708 | /* Set DMA device capability */ | |
1709 | dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); | |
1710 | dma_cap_set(DMA_SG, dma_dev->cap_mask); | |
1711 | ||
1712 | /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR | |
1713 | * and channel 1 supports XOR, PQ both. First thing here is we have | |
1714 | * mechanism in hw to enable/disable PQ/XOR supports on channel 1, | |
1715 | * we can make sure this by reading SoC Efuse register. | |
1716 | * Second thing, we have hw errata that if we run channel 0 and | |
1717 | * channel 1 simultaneously with executing XOR and PQ request, | |
1718 | * suddenly DMA engine hangs, So here we enable XOR on channel 0 only | |
1719 | * if XOR and PQ supports on channel 1 is disabled. | |
1720 | */ | |
1721 | if ((chan->id == XGENE_DMA_PQ_CHANNEL) && | |
1722 | is_pq_enabled(chan->pdma)) { | |
1723 | dma_cap_set(DMA_PQ, dma_dev->cap_mask); | |
1724 | dma_cap_set(DMA_XOR, dma_dev->cap_mask); | |
1725 | } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) && | |
1726 | !is_pq_enabled(chan->pdma)) { | |
1727 | dma_cap_set(DMA_XOR, dma_dev->cap_mask); | |
1728 | } | |
1729 | ||
1730 | /* Set base and prep routines */ | |
1731 | dma_dev->dev = chan->dev; | |
1732 | dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources; | |
1733 | dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources; | |
1734 | dma_dev->device_issue_pending = xgene_dma_issue_pending; | |
1735 | dma_dev->device_tx_status = xgene_dma_tx_status; | |
1736 | dma_dev->device_prep_dma_memcpy = xgene_dma_prep_memcpy; | |
1737 | dma_dev->device_prep_dma_sg = xgene_dma_prep_sg; | |
1738 | ||
1739 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { | |
1740 | dma_dev->device_prep_dma_xor = xgene_dma_prep_xor; | |
1741 | dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC; | |
77a68e56 | 1742 | dma_dev->xor_align = DMAENGINE_ALIGN_64_BYTES; |
9f2fd0df RPS |
1743 | } |
1744 | ||
1745 | if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { | |
1746 | dma_dev->device_prep_dma_pq = xgene_dma_prep_pq; | |
1747 | dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC; | |
77a68e56 | 1748 | dma_dev->pq_align = DMAENGINE_ALIGN_64_BYTES; |
9f2fd0df RPS |
1749 | } |
1750 | } | |
1751 | ||
1752 | static int xgene_dma_async_register(struct xgene_dma *pdma, int id) | |
1753 | { | |
1754 | struct xgene_dma_chan *chan = &pdma->chan[id]; | |
1755 | struct dma_device *dma_dev = &pdma->dma_dev[id]; | |
1756 | int ret; | |
1757 | ||
1758 | chan->dma_chan.device = dma_dev; | |
1759 | ||
1760 | spin_lock_init(&chan->lock); | |
1761 | INIT_LIST_HEAD(&chan->ld_pending); | |
1762 | INIT_LIST_HEAD(&chan->ld_running); | |
1763 | INIT_LIST_HEAD(&chan->ld_completed); | |
1764 | tasklet_init(&chan->tasklet, xgene_dma_tasklet_cb, | |
1765 | (unsigned long)chan); | |
1766 | ||
1767 | chan->pending = 0; | |
1768 | chan->desc_pool = NULL; | |
1769 | dma_cookie_init(&chan->dma_chan); | |
1770 | ||
1771 | /* Setup dma device capabilities and prep routines */ | |
1772 | xgene_dma_set_caps(chan, dma_dev); | |
1773 | ||
1774 | /* Initialize DMA device list head */ | |
1775 | INIT_LIST_HEAD(&dma_dev->channels); | |
1776 | list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels); | |
1777 | ||
1778 | /* Register with Linux async DMA framework*/ | |
1779 | ret = dma_async_device_register(dma_dev); | |
1780 | if (ret) { | |
1781 | chan_err(chan, "Failed to register async device %d", ret); | |
1782 | tasklet_kill(&chan->tasklet); | |
1783 | ||
1784 | return ret; | |
1785 | } | |
1786 | ||
1787 | /* DMA capability info */ | |
1788 | dev_info(pdma->dev, | |
1789 | "%s: CAPABILITY ( %s%s%s%s)\n", dma_chan_name(&chan->dma_chan), | |
1790 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "MEMCPY " : "", | |
1791 | dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "", | |
1792 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "", | |
1793 | dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : ""); | |
1794 | ||
1795 | return 0; | |
1796 | } | |
1797 | ||
1798 | static int xgene_dma_init_async(struct xgene_dma *pdma) | |
1799 | { | |
1800 | int ret, i, j; | |
1801 | ||
1802 | for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) { | |
1803 | ret = xgene_dma_async_register(pdma, i); | |
1804 | if (ret) { | |
1805 | for (j = 0; j < i; j++) { | |
1806 | dma_async_device_unregister(&pdma->dma_dev[j]); | |
1807 | tasklet_kill(&pdma->chan[j].tasklet); | |
1808 | } | |
1809 | ||
1810 | return ret; | |
1811 | } | |
1812 | } | |
1813 | ||
1814 | return ret; | |
1815 | } | |
1816 | ||
1817 | static void xgene_dma_async_unregister(struct xgene_dma *pdma) | |
1818 | { | |
1819 | int i; | |
1820 | ||
1821 | for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) | |
1822 | dma_async_device_unregister(&pdma->dma_dev[i]); | |
1823 | } | |
1824 | ||
1825 | static void xgene_dma_init_channels(struct xgene_dma *pdma) | |
1826 | { | |
1827 | struct xgene_dma_chan *chan; | |
1828 | int i; | |
1829 | ||
1830 | pdma->ring_num = XGENE_DMA_RING_NUM; | |
1831 | ||
1832 | for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { | |
1833 | chan = &pdma->chan[i]; | |
1834 | chan->dev = pdma->dev; | |
1835 | chan->pdma = pdma; | |
1836 | chan->id = i; | |
ed1f0418 | 1837 | snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id); |
9f2fd0df RPS |
1838 | } |
1839 | } | |
1840 | ||
1841 | static int xgene_dma_get_resources(struct platform_device *pdev, | |
1842 | struct xgene_dma *pdma) | |
1843 | { | |
1844 | struct resource *res; | |
1845 | int irq, i; | |
1846 | ||
1847 | /* Get DMA csr region */ | |
1848 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1849 | if (!res) { | |
1850 | dev_err(&pdev->dev, "Failed to get csr region\n"); | |
1851 | return -ENXIO; | |
1852 | } | |
1853 | ||
1854 | pdma->csr_dma = devm_ioremap(&pdev->dev, res->start, | |
1855 | resource_size(res)); | |
9c361b1a | 1856 | if (!pdma->csr_dma) { |
9f2fd0df | 1857 | dev_err(&pdev->dev, "Failed to ioremap csr region"); |
9c361b1a | 1858 | return -ENOMEM; |
9f2fd0df RPS |
1859 | } |
1860 | ||
1861 | /* Get DMA ring csr region */ | |
1862 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1863 | if (!res) { | |
1864 | dev_err(&pdev->dev, "Failed to get ring csr region\n"); | |
1865 | return -ENXIO; | |
1866 | } | |
1867 | ||
1868 | pdma->csr_ring = devm_ioremap(&pdev->dev, res->start, | |
1869 | resource_size(res)); | |
9c361b1a | 1870 | if (!pdma->csr_ring) { |
9f2fd0df | 1871 | dev_err(&pdev->dev, "Failed to ioremap ring csr region"); |
9c361b1a | 1872 | return -ENOMEM; |
9f2fd0df RPS |
1873 | } |
1874 | ||
1875 | /* Get DMA ring cmd csr region */ | |
1876 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
1877 | if (!res) { | |
1878 | dev_err(&pdev->dev, "Failed to get ring cmd csr region\n"); | |
1879 | return -ENXIO; | |
1880 | } | |
1881 | ||
1882 | pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start, | |
1883 | resource_size(res)); | |
9c361b1a | 1884 | if (!pdma->csr_ring_cmd) { |
9f2fd0df | 1885 | dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region"); |
9c361b1a | 1886 | return -ENOMEM; |
9f2fd0df RPS |
1887 | } |
1888 | ||
1889 | /* Get efuse csr region */ | |
1890 | res = platform_get_resource(pdev, IORESOURCE_MEM, 3); | |
1891 | if (!res) { | |
1892 | dev_err(&pdev->dev, "Failed to get efuse csr region\n"); | |
1893 | return -ENXIO; | |
1894 | } | |
1895 | ||
1896 | pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start, | |
1897 | resource_size(res)); | |
9c361b1a | 1898 | if (!pdma->csr_efuse) { |
9f2fd0df | 1899 | dev_err(&pdev->dev, "Failed to ioremap efuse csr region"); |
9c361b1a | 1900 | return -ENOMEM; |
9f2fd0df RPS |
1901 | } |
1902 | ||
1903 | /* Get DMA error interrupt */ | |
1904 | irq = platform_get_irq(pdev, 0); | |
1905 | if (irq <= 0) { | |
1906 | dev_err(&pdev->dev, "Failed to get Error IRQ\n"); | |
1907 | return -ENXIO; | |
1908 | } | |
1909 | ||
1910 | pdma->err_irq = irq; | |
1911 | ||
1912 | /* Get DMA Rx ring descriptor interrupts for all DMA channels */ | |
1913 | for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) { | |
1914 | irq = platform_get_irq(pdev, i); | |
1915 | if (irq <= 0) { | |
1916 | dev_err(&pdev->dev, "Failed to get Rx IRQ\n"); | |
1917 | return -ENXIO; | |
1918 | } | |
1919 | ||
1920 | pdma->chan[i - 1].rx_irq = irq; | |
1921 | } | |
1922 | ||
1923 | return 0; | |
1924 | } | |
1925 | ||
1926 | static int xgene_dma_probe(struct platform_device *pdev) | |
1927 | { | |
1928 | struct xgene_dma *pdma; | |
1929 | int ret, i; | |
1930 | ||
1931 | pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL); | |
1932 | if (!pdma) | |
1933 | return -ENOMEM; | |
1934 | ||
1935 | pdma->dev = &pdev->dev; | |
1936 | platform_set_drvdata(pdev, pdma); | |
1937 | ||
1938 | ret = xgene_dma_get_resources(pdev, pdma); | |
1939 | if (ret) | |
1940 | return ret; | |
1941 | ||
1942 | pdma->clk = devm_clk_get(&pdev->dev, NULL); | |
1943 | if (IS_ERR(pdma->clk)) { | |
1944 | dev_err(&pdev->dev, "Failed to get clk\n"); | |
1945 | return PTR_ERR(pdma->clk); | |
1946 | } | |
1947 | ||
1948 | /* Enable clk before accessing registers */ | |
1949 | ret = clk_prepare_enable(pdma->clk); | |
1950 | if (ret) { | |
1951 | dev_err(&pdev->dev, "Failed to enable clk %d\n", ret); | |
1952 | return ret; | |
1953 | } | |
1954 | ||
1955 | /* Remove DMA RAM out of shutdown */ | |
1956 | ret = xgene_dma_init_mem(pdma); | |
1957 | if (ret) | |
1958 | goto err_clk_enable; | |
1959 | ||
1960 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42)); | |
1961 | if (ret) { | |
1962 | dev_err(&pdev->dev, "No usable DMA configuration\n"); | |
1963 | goto err_dma_mask; | |
1964 | } | |
1965 | ||
1966 | /* Initialize DMA channels software state */ | |
1967 | xgene_dma_init_channels(pdma); | |
1968 | ||
1969 | /* Configue DMA rings */ | |
1970 | ret = xgene_dma_init_rings(pdma); | |
1971 | if (ret) | |
1972 | goto err_clk_enable; | |
1973 | ||
1974 | ret = xgene_dma_request_irqs(pdma); | |
1975 | if (ret) | |
1976 | goto err_request_irq; | |
1977 | ||
1978 | /* Configure and enable DMA engine */ | |
1979 | xgene_dma_init_hw(pdma); | |
1980 | ||
1981 | /* Register DMA device with linux async framework */ | |
1982 | ret = xgene_dma_init_async(pdma); | |
1983 | if (ret) | |
1984 | goto err_async_init; | |
1985 | ||
1986 | return 0; | |
1987 | ||
1988 | err_async_init: | |
1989 | xgene_dma_free_irqs(pdma); | |
1990 | ||
1991 | err_request_irq: | |
1992 | for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) | |
1993 | xgene_dma_delete_chan_rings(&pdma->chan[i]); | |
1994 | ||
1995 | err_dma_mask: | |
1996 | err_clk_enable: | |
1997 | clk_disable_unprepare(pdma->clk); | |
1998 | ||
1999 | return ret; | |
2000 | } | |
2001 | ||
2002 | static int xgene_dma_remove(struct platform_device *pdev) | |
2003 | { | |
2004 | struct xgene_dma *pdma = platform_get_drvdata(pdev); | |
2005 | struct xgene_dma_chan *chan; | |
2006 | int i; | |
2007 | ||
2008 | xgene_dma_async_unregister(pdma); | |
2009 | ||
2010 | /* Mask interrupts and disable DMA engine */ | |
2011 | xgene_dma_mask_interrupts(pdma); | |
2012 | xgene_dma_disable(pdma); | |
2013 | xgene_dma_free_irqs(pdma); | |
2014 | ||
2015 | for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { | |
2016 | chan = &pdma->chan[i]; | |
2017 | tasklet_kill(&chan->tasklet); | |
2018 | xgene_dma_delete_chan_rings(chan); | |
2019 | } | |
2020 | ||
2021 | clk_disable_unprepare(pdma->clk); | |
2022 | ||
2023 | return 0; | |
2024 | } | |
2025 | ||
2026 | static const struct of_device_id xgene_dma_of_match_ptr[] = { | |
2027 | {.compatible = "apm,xgene-storm-dma",}, | |
2028 | {}, | |
2029 | }; | |
2030 | MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr); | |
2031 | ||
2032 | static struct platform_driver xgene_dma_driver = { | |
2033 | .probe = xgene_dma_probe, | |
2034 | .remove = xgene_dma_remove, | |
2035 | .driver = { | |
2036 | .name = "X-Gene-DMA", | |
9f2fd0df RPS |
2037 | .of_match_table = xgene_dma_of_match_ptr, |
2038 | }, | |
2039 | }; | |
2040 | ||
2041 | module_platform_driver(xgene_dma_driver); | |
2042 | ||
2043 | MODULE_DESCRIPTION("APM X-Gene SoC DMA driver"); | |
2044 | MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>"); | |
2045 | MODULE_AUTHOR("Loc Ho <lho@apm.com>"); | |
2046 | MODULE_LICENSE("GPL"); | |
2047 | MODULE_VERSION("1.0"); |