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e941759c ML |
1 | /* |
2 | * Fence mechanism for dma-buf and to allow for asynchronous dma access | |
3 | * | |
4 | * Copyright (C) 2012 Canonical Ltd | |
5 | * Copyright (C) 2012 Texas Instruments | |
6 | * | |
7 | * Authors: | |
8 | * Rob Clark <robdclark@gmail.com> | |
9 | * Maarten Lankhorst <maarten.lankhorst@canonical.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License version 2 as published by | |
13 | * the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | */ | |
20 | ||
21 | #include <linux/slab.h> | |
22 | #include <linux/export.h> | |
23 | #include <linux/atomic.h> | |
f54d1867 | 24 | #include <linux/dma-fence.h> |
e941759c ML |
25 | |
26 | #define CREATE_TRACE_POINTS | |
f54d1867 | 27 | #include <trace/events/dma_fence.h> |
e941759c | 28 | |
f54d1867 CW |
29 | EXPORT_TRACEPOINT_SYMBOL(dma_fence_annotate_wait_on); |
30 | EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit); | |
e941759c | 31 | |
e9f3b796 | 32 | /* |
e941759c ML |
33 | * fence context counter: each execution context should have its own |
34 | * fence context, this allows checking if fences belong to the same | |
35 | * context or not. One device can have multiple separate contexts, | |
36 | * and they're used if some engine can run independently of another. | |
37 | */ | |
f54d1867 | 38 | static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(0); |
e941759c ML |
39 | |
40 | /** | |
f54d1867 | 41 | * dma_fence_context_alloc - allocate an array of fence contexts |
e941759c ML |
42 | * @num: [in] amount of contexts to allocate |
43 | * | |
44 | * This function will return the first index of the number of fences allocated. | |
45 | * The fence context is used for setting fence->context to a unique number. | |
46 | */ | |
f54d1867 | 47 | u64 dma_fence_context_alloc(unsigned num) |
e941759c ML |
48 | { |
49 | BUG_ON(!num); | |
f54d1867 | 50 | return atomic64_add_return(num, &dma_fence_context_counter) - num; |
e941759c | 51 | } |
f54d1867 | 52 | EXPORT_SYMBOL(dma_fence_context_alloc); |
e941759c ML |
53 | |
54 | /** | |
f54d1867 | 55 | * dma_fence_signal_locked - signal completion of a fence |
e941759c ML |
56 | * @fence: the fence to signal |
57 | * | |
58 | * Signal completion for software callbacks on a fence, this will unblock | |
f54d1867 CW |
59 | * dma_fence_wait() calls and run all the callbacks added with |
60 | * dma_fence_add_callback(). Can be called multiple times, but since a fence | |
e941759c ML |
61 | * can only go from unsignaled to signaled state, it will only be effective |
62 | * the first time. | |
63 | * | |
f54d1867 | 64 | * Unlike dma_fence_signal, this function must be called with fence->lock held. |
e941759c | 65 | */ |
f54d1867 | 66 | int dma_fence_signal_locked(struct dma_fence *fence) |
e941759c | 67 | { |
f54d1867 | 68 | struct dma_fence_cb *cur, *tmp; |
e941759c ML |
69 | int ret = 0; |
70 | ||
78010cd9 RC |
71 | lockdep_assert_held(fence->lock); |
72 | ||
e941759c ML |
73 | if (WARN_ON(!fence)) |
74 | return -EINVAL; | |
75 | ||
76 | if (!ktime_to_ns(fence->timestamp)) { | |
77 | fence->timestamp = ktime_get(); | |
78 | smp_mb__before_atomic(); | |
79 | } | |
80 | ||
f54d1867 | 81 | if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
e941759c ML |
82 | ret = -EINVAL; |
83 | ||
84 | /* | |
f54d1867 | 85 | * we might have raced with the unlocked dma_fence_signal, |
e941759c ML |
86 | * still run through all callbacks |
87 | */ | |
88 | } else | |
f54d1867 | 89 | trace_dma_fence_signaled(fence); |
e941759c ML |
90 | |
91 | list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) { | |
92 | list_del_init(&cur->node); | |
93 | cur->func(fence, cur); | |
94 | } | |
95 | return ret; | |
96 | } | |
f54d1867 | 97 | EXPORT_SYMBOL(dma_fence_signal_locked); |
e941759c ML |
98 | |
99 | /** | |
f54d1867 | 100 | * dma_fence_signal - signal completion of a fence |
e941759c ML |
101 | * @fence: the fence to signal |
102 | * | |
103 | * Signal completion for software callbacks on a fence, this will unblock | |
f54d1867 CW |
104 | * dma_fence_wait() calls and run all the callbacks added with |
105 | * dma_fence_add_callback(). Can be called multiple times, but since a fence | |
e941759c ML |
106 | * can only go from unsignaled to signaled state, it will only be effective |
107 | * the first time. | |
108 | */ | |
f54d1867 | 109 | int dma_fence_signal(struct dma_fence *fence) |
e941759c ML |
110 | { |
111 | unsigned long flags; | |
112 | ||
113 | if (!fence) | |
114 | return -EINVAL; | |
115 | ||
116 | if (!ktime_to_ns(fence->timestamp)) { | |
117 | fence->timestamp = ktime_get(); | |
118 | smp_mb__before_atomic(); | |
119 | } | |
120 | ||
f54d1867 | 121 | if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
e941759c ML |
122 | return -EINVAL; |
123 | ||
f54d1867 | 124 | trace_dma_fence_signaled(fence); |
e941759c | 125 | |
f54d1867 CW |
126 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags)) { |
127 | struct dma_fence_cb *cur, *tmp; | |
e941759c ML |
128 | |
129 | spin_lock_irqsave(fence->lock, flags); | |
130 | list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) { | |
131 | list_del_init(&cur->node); | |
132 | cur->func(fence, cur); | |
133 | } | |
134 | spin_unlock_irqrestore(fence->lock, flags); | |
135 | } | |
136 | return 0; | |
137 | } | |
f54d1867 | 138 | EXPORT_SYMBOL(dma_fence_signal); |
e941759c ML |
139 | |
140 | /** | |
f54d1867 | 141 | * dma_fence_wait_timeout - sleep until the fence gets signaled |
e941759c ML |
142 | * or until timeout elapses |
143 | * @fence: [in] the fence to wait on | |
144 | * @intr: [in] if true, do an interruptible wait | |
145 | * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT | |
146 | * | |
147 | * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the | |
148 | * remaining timeout in jiffies on success. Other error values may be | |
149 | * returned on custom implementations. | |
150 | * | |
151 | * Performs a synchronous wait on this fence. It is assumed the caller | |
152 | * directly or indirectly (buf-mgr between reservation and committing) | |
153 | * holds a reference to the fence, otherwise the fence might be | |
154 | * freed before return, resulting in undefined behavior. | |
155 | */ | |
156 | signed long | |
f54d1867 | 157 | dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) |
e941759c ML |
158 | { |
159 | signed long ret; | |
160 | ||
161 | if (WARN_ON(timeout < 0)) | |
162 | return -EINVAL; | |
163 | ||
f54d1867 | 164 | trace_dma_fence_wait_start(fence); |
e941759c | 165 | ret = fence->ops->wait(fence, intr, timeout); |
f54d1867 | 166 | trace_dma_fence_wait_end(fence); |
e941759c ML |
167 | return ret; |
168 | } | |
f54d1867 | 169 | EXPORT_SYMBOL(dma_fence_wait_timeout); |
e941759c | 170 | |
f54d1867 | 171 | void dma_fence_release(struct kref *kref) |
e941759c | 172 | { |
f54d1867 CW |
173 | struct dma_fence *fence = |
174 | container_of(kref, struct dma_fence, refcount); | |
e941759c | 175 | |
f54d1867 | 176 | trace_dma_fence_destroy(fence); |
e941759c ML |
177 | |
178 | BUG_ON(!list_empty(&fence->cb_list)); | |
179 | ||
180 | if (fence->ops->release) | |
181 | fence->ops->release(fence); | |
182 | else | |
f54d1867 | 183 | dma_fence_free(fence); |
e941759c | 184 | } |
f54d1867 | 185 | EXPORT_SYMBOL(dma_fence_release); |
e941759c | 186 | |
f54d1867 | 187 | void dma_fence_free(struct dma_fence *fence) |
e941759c | 188 | { |
3c3b177a | 189 | kfree_rcu(fence, rcu); |
e941759c | 190 | } |
f54d1867 | 191 | EXPORT_SYMBOL(dma_fence_free); |
e941759c ML |
192 | |
193 | /** | |
f54d1867 | 194 | * dma_fence_enable_sw_signaling - enable signaling on fence |
e941759c ML |
195 | * @fence: [in] the fence to enable |
196 | * | |
197 | * this will request for sw signaling to be enabled, to make the fence | |
198 | * complete as soon as possible | |
199 | */ | |
f54d1867 | 200 | void dma_fence_enable_sw_signaling(struct dma_fence *fence) |
e941759c ML |
201 | { |
202 | unsigned long flags; | |
203 | ||
f54d1867 CW |
204 | if (!test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, |
205 | &fence->flags) && | |
206 | !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { | |
207 | trace_dma_fence_enable_signal(fence); | |
e941759c ML |
208 | |
209 | spin_lock_irqsave(fence->lock, flags); | |
210 | ||
211 | if (!fence->ops->enable_signaling(fence)) | |
f54d1867 | 212 | dma_fence_signal_locked(fence); |
e941759c ML |
213 | |
214 | spin_unlock_irqrestore(fence->lock, flags); | |
215 | } | |
216 | } | |
f54d1867 | 217 | EXPORT_SYMBOL(dma_fence_enable_sw_signaling); |
e941759c ML |
218 | |
219 | /** | |
f54d1867 | 220 | * dma_fence_add_callback - add a callback to be called when the fence |
e941759c ML |
221 | * is signaled |
222 | * @fence: [in] the fence to wait on | |
223 | * @cb: [in] the callback to register | |
224 | * @func: [in] the function to call | |
225 | * | |
f54d1867 | 226 | * cb will be initialized by dma_fence_add_callback, no initialization |
e941759c ML |
227 | * by the caller is required. Any number of callbacks can be registered |
228 | * to a fence, but a callback can only be registered to one fence at a time. | |
229 | * | |
230 | * Note that the callback can be called from an atomic context. If | |
231 | * fence is already signaled, this function will return -ENOENT (and | |
232 | * *not* call the callback) | |
233 | * | |
234 | * Add a software callback to the fence. Same restrictions apply to | |
f54d1867 | 235 | * refcount as it does to dma_fence_wait, however the caller doesn't need to |
e941759c ML |
236 | * keep a refcount to fence afterwards: when software access is enabled, |
237 | * the creator of the fence is required to keep the fence alive until | |
f54d1867 | 238 | * after it signals with dma_fence_signal. The callback itself can be called |
e941759c ML |
239 | * from irq context. |
240 | * | |
241 | */ | |
f54d1867 CW |
242 | int dma_fence_add_callback(struct dma_fence *fence, struct dma_fence_cb *cb, |
243 | dma_fence_func_t func) | |
e941759c ML |
244 | { |
245 | unsigned long flags; | |
246 | int ret = 0; | |
247 | bool was_set; | |
248 | ||
249 | if (WARN_ON(!fence || !func)) | |
250 | return -EINVAL; | |
251 | ||
f54d1867 | 252 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
e941759c ML |
253 | INIT_LIST_HEAD(&cb->node); |
254 | return -ENOENT; | |
255 | } | |
256 | ||
257 | spin_lock_irqsave(fence->lock, flags); | |
258 | ||
f54d1867 CW |
259 | was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, |
260 | &fence->flags); | |
e941759c | 261 | |
f54d1867 | 262 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
e941759c ML |
263 | ret = -ENOENT; |
264 | else if (!was_set) { | |
f54d1867 | 265 | trace_dma_fence_enable_signal(fence); |
e941759c ML |
266 | |
267 | if (!fence->ops->enable_signaling(fence)) { | |
f54d1867 | 268 | dma_fence_signal_locked(fence); |
e941759c ML |
269 | ret = -ENOENT; |
270 | } | |
271 | } | |
272 | ||
273 | if (!ret) { | |
274 | cb->func = func; | |
275 | list_add_tail(&cb->node, &fence->cb_list); | |
276 | } else | |
277 | INIT_LIST_HEAD(&cb->node); | |
278 | spin_unlock_irqrestore(fence->lock, flags); | |
279 | ||
280 | return ret; | |
281 | } | |
f54d1867 | 282 | EXPORT_SYMBOL(dma_fence_add_callback); |
e941759c ML |
283 | |
284 | /** | |
f54d1867 | 285 | * dma_fence_remove_callback - remove a callback from the signaling list |
e941759c ML |
286 | * @fence: [in] the fence to wait on |
287 | * @cb: [in] the callback to remove | |
288 | * | |
289 | * Remove a previously queued callback from the fence. This function returns | |
f353d71f | 290 | * true if the callback is successfully removed, or false if the fence has |
e941759c ML |
291 | * already been signaled. |
292 | * | |
293 | * *WARNING*: | |
294 | * Cancelling a callback should only be done if you really know what you're | |
295 | * doing, since deadlocks and race conditions could occur all too easily. For | |
296 | * this reason, it should only ever be done on hardware lockup recovery, | |
297 | * with a reference held to the fence. | |
298 | */ | |
299 | bool | |
f54d1867 | 300 | dma_fence_remove_callback(struct dma_fence *fence, struct dma_fence_cb *cb) |
e941759c ML |
301 | { |
302 | unsigned long flags; | |
303 | bool ret; | |
304 | ||
305 | spin_lock_irqsave(fence->lock, flags); | |
306 | ||
307 | ret = !list_empty(&cb->node); | |
308 | if (ret) | |
309 | list_del_init(&cb->node); | |
310 | ||
311 | spin_unlock_irqrestore(fence->lock, flags); | |
312 | ||
313 | return ret; | |
314 | } | |
f54d1867 | 315 | EXPORT_SYMBOL(dma_fence_remove_callback); |
e941759c ML |
316 | |
317 | struct default_wait_cb { | |
f54d1867 | 318 | struct dma_fence_cb base; |
e941759c ML |
319 | struct task_struct *task; |
320 | }; | |
321 | ||
322 | static void | |
f54d1867 | 323 | dma_fence_default_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb) |
e941759c ML |
324 | { |
325 | struct default_wait_cb *wait = | |
326 | container_of(cb, struct default_wait_cb, base); | |
327 | ||
328 | wake_up_state(wait->task, TASK_NORMAL); | |
329 | } | |
330 | ||
331 | /** | |
f54d1867 | 332 | * dma_fence_default_wait - default sleep until the fence gets signaled |
e941759c ML |
333 | * or until timeout elapses |
334 | * @fence: [in] the fence to wait on | |
335 | * @intr: [in] if true, do an interruptible wait | |
336 | * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT | |
337 | * | |
338 | * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the | |
bcc004b6 AD |
339 | * remaining timeout in jiffies on success. If timeout is zero the value one is |
340 | * returned if the fence is already signaled for consistency with other | |
341 | * functions taking a jiffies timeout. | |
e941759c ML |
342 | */ |
343 | signed long | |
f54d1867 | 344 | dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) |
e941759c ML |
345 | { |
346 | struct default_wait_cb cb; | |
347 | unsigned long flags; | |
bcc004b6 | 348 | signed long ret = timeout ? timeout : 1; |
e941759c ML |
349 | bool was_set; |
350 | ||
f54d1867 | 351 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
bcc004b6 | 352 | return ret; |
e941759c ML |
353 | |
354 | spin_lock_irqsave(fence->lock, flags); | |
355 | ||
356 | if (intr && signal_pending(current)) { | |
357 | ret = -ERESTARTSYS; | |
358 | goto out; | |
359 | } | |
360 | ||
f54d1867 CW |
361 | was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, |
362 | &fence->flags); | |
e941759c | 363 | |
f54d1867 | 364 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
e941759c ML |
365 | goto out; |
366 | ||
367 | if (!was_set) { | |
f54d1867 | 368 | trace_dma_fence_enable_signal(fence); |
e941759c ML |
369 | |
370 | if (!fence->ops->enable_signaling(fence)) { | |
f54d1867 | 371 | dma_fence_signal_locked(fence); |
e941759c ML |
372 | goto out; |
373 | } | |
374 | } | |
375 | ||
f54d1867 | 376 | cb.base.func = dma_fence_default_wait_cb; |
e941759c ML |
377 | cb.task = current; |
378 | list_add(&cb.base.node, &fence->cb_list); | |
379 | ||
f54d1867 | 380 | while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) { |
e941759c ML |
381 | if (intr) |
382 | __set_current_state(TASK_INTERRUPTIBLE); | |
383 | else | |
384 | __set_current_state(TASK_UNINTERRUPTIBLE); | |
385 | spin_unlock_irqrestore(fence->lock, flags); | |
386 | ||
387 | ret = schedule_timeout(ret); | |
388 | ||
389 | spin_lock_irqsave(fence->lock, flags); | |
390 | if (ret > 0 && intr && signal_pending(current)) | |
391 | ret = -ERESTARTSYS; | |
392 | } | |
393 | ||
394 | if (!list_empty(&cb.base.node)) | |
395 | list_del(&cb.base.node); | |
396 | __set_current_state(TASK_RUNNING); | |
397 | ||
398 | out: | |
399 | spin_unlock_irqrestore(fence->lock, flags); | |
400 | return ret; | |
401 | } | |
f54d1867 | 402 | EXPORT_SYMBOL(dma_fence_default_wait); |
e941759c | 403 | |
a519435a | 404 | static bool |
7392b4bb | 405 | dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, |
406 | uint32_t *idx) | |
a519435a CK |
407 | { |
408 | int i; | |
409 | ||
410 | for (i = 0; i < count; ++i) { | |
f54d1867 | 411 | struct dma_fence *fence = fences[i]; |
7392b4bb | 412 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
413 | if (idx) | |
414 | *idx = i; | |
a519435a | 415 | return true; |
7392b4bb | 416 | } |
a519435a CK |
417 | } |
418 | return false; | |
419 | } | |
420 | ||
421 | /** | |
f54d1867 | 422 | * dma_fence_wait_any_timeout - sleep until any fence gets signaled |
a519435a CK |
423 | * or until timeout elapses |
424 | * @fences: [in] array of fences to wait on | |
425 | * @count: [in] number of fences to wait on | |
426 | * @intr: [in] if true, do an interruptible wait | |
427 | * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT | |
7392b4bb | 428 | * @idx: [out] the first signaled fence index, meaningful only on |
429 | * positive return | |
a519435a CK |
430 | * |
431 | * Returns -EINVAL on custom fence wait implementation, -ERESTARTSYS if | |
432 | * interrupted, 0 if the wait timed out, or the remaining timeout in jiffies | |
433 | * on success. | |
434 | * | |
435 | * Synchronous waits for the first fence in the array to be signaled. The | |
436 | * caller needs to hold a reference to all fences in the array, otherwise a | |
437 | * fence might be freed before return, resulting in undefined behavior. | |
438 | */ | |
439 | signed long | |
f54d1867 | 440 | dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, |
7392b4bb | 441 | bool intr, signed long timeout, uint32_t *idx) |
a519435a CK |
442 | { |
443 | struct default_wait_cb *cb; | |
444 | signed long ret = timeout; | |
445 | unsigned i; | |
446 | ||
447 | if (WARN_ON(!fences || !count || timeout < 0)) | |
448 | return -EINVAL; | |
449 | ||
450 | if (timeout == 0) { | |
451 | for (i = 0; i < count; ++i) | |
7392b4bb | 452 | if (dma_fence_is_signaled(fences[i])) { |
453 | if (idx) | |
454 | *idx = i; | |
a519435a | 455 | return 1; |
7392b4bb | 456 | } |
a519435a CK |
457 | |
458 | return 0; | |
459 | } | |
460 | ||
461 | cb = kcalloc(count, sizeof(struct default_wait_cb), GFP_KERNEL); | |
462 | if (cb == NULL) { | |
463 | ret = -ENOMEM; | |
464 | goto err_free_cb; | |
465 | } | |
466 | ||
467 | for (i = 0; i < count; ++i) { | |
f54d1867 | 468 | struct dma_fence *fence = fences[i]; |
a519435a | 469 | |
f54d1867 | 470 | if (fence->ops->wait != dma_fence_default_wait) { |
a519435a CK |
471 | ret = -EINVAL; |
472 | goto fence_rm_cb; | |
473 | } | |
474 | ||
475 | cb[i].task = current; | |
f54d1867 CW |
476 | if (dma_fence_add_callback(fence, &cb[i].base, |
477 | dma_fence_default_wait_cb)) { | |
a519435a | 478 | /* This fence is already signaled */ |
7392b4bb | 479 | if (idx) |
480 | *idx = i; | |
a519435a CK |
481 | goto fence_rm_cb; |
482 | } | |
483 | } | |
484 | ||
485 | while (ret > 0) { | |
486 | if (intr) | |
487 | set_current_state(TASK_INTERRUPTIBLE); | |
488 | else | |
489 | set_current_state(TASK_UNINTERRUPTIBLE); | |
490 | ||
7392b4bb | 491 | if (dma_fence_test_signaled_any(fences, count, idx)) |
a519435a CK |
492 | break; |
493 | ||
494 | ret = schedule_timeout(ret); | |
495 | ||
496 | if (ret > 0 && intr && signal_pending(current)) | |
497 | ret = -ERESTARTSYS; | |
498 | } | |
499 | ||
500 | __set_current_state(TASK_RUNNING); | |
501 | ||
502 | fence_rm_cb: | |
503 | while (i-- > 0) | |
f54d1867 | 504 | dma_fence_remove_callback(fences[i], &cb[i].base); |
a519435a CK |
505 | |
506 | err_free_cb: | |
507 | kfree(cb); | |
508 | ||
509 | return ret; | |
510 | } | |
f54d1867 | 511 | EXPORT_SYMBOL(dma_fence_wait_any_timeout); |
a519435a | 512 | |
e941759c | 513 | /** |
f54d1867 | 514 | * dma_fence_init - Initialize a custom fence. |
e941759c | 515 | * @fence: [in] the fence to initialize |
f54d1867 | 516 | * @ops: [in] the dma_fence_ops for operations on this fence |
e941759c ML |
517 | * @lock: [in] the irqsafe spinlock to use for locking this fence |
518 | * @context: [in] the execution context this fence is run on | |
519 | * @seqno: [in] a linear increasing sequence number for this context | |
520 | * | |
521 | * Initializes an allocated fence, the caller doesn't have to keep its | |
522 | * refcount after committing with this fence, but it will need to hold a | |
f54d1867 | 523 | * refcount again if dma_fence_ops.enable_signaling gets called. This can |
e941759c ML |
524 | * be used for other implementing other types of fence. |
525 | * | |
526 | * context and seqno are used for easy comparison between fences, allowing | |
f54d1867 | 527 | * to check which fence is later by simply using dma_fence_later. |
e941759c ML |
528 | */ |
529 | void | |
f54d1867 CW |
530 | dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, |
531 | spinlock_t *lock, u64 context, unsigned seqno) | |
e941759c ML |
532 | { |
533 | BUG_ON(!lock); | |
534 | BUG_ON(!ops || !ops->wait || !ops->enable_signaling || | |
535 | !ops->get_driver_name || !ops->get_timeline_name); | |
536 | ||
537 | kref_init(&fence->refcount); | |
538 | fence->ops = ops; | |
539 | INIT_LIST_HEAD(&fence->cb_list); | |
540 | fence->lock = lock; | |
541 | fence->context = context; | |
542 | fence->seqno = seqno; | |
543 | fence->flags = 0UL; | |
544 | ||
f54d1867 | 545 | trace_dma_fence_init(fence); |
e941759c | 546 | } |
f54d1867 | 547 | EXPORT_SYMBOL(dma_fence_init); |