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e941759c ML |
1 | /* |
2 | * Fence mechanism for dma-buf and to allow for asynchronous dma access | |
3 | * | |
4 | * Copyright (C) 2012 Canonical Ltd | |
5 | * Copyright (C) 2012 Texas Instruments | |
6 | * | |
7 | * Authors: | |
8 | * Rob Clark <robdclark@gmail.com> | |
9 | * Maarten Lankhorst <maarten.lankhorst@canonical.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License version 2 as published by | |
13 | * the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | */ | |
20 | ||
21 | #include <linux/slab.h> | |
22 | #include <linux/export.h> | |
23 | #include <linux/atomic.h> | |
f54d1867 | 24 | #include <linux/dma-fence.h> |
174cd4b1 | 25 | #include <linux/sched/signal.h> |
e941759c ML |
26 | |
27 | #define CREATE_TRACE_POINTS | |
f54d1867 | 28 | #include <trace/events/dma_fence.h> |
e941759c | 29 | |
f54d1867 CW |
30 | EXPORT_TRACEPOINT_SYMBOL(dma_fence_annotate_wait_on); |
31 | EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit); | |
8c96c678 | 32 | EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal); |
e941759c | 33 | |
e9f3b796 | 34 | /* |
e941759c ML |
35 | * fence context counter: each execution context should have its own |
36 | * fence context, this allows checking if fences belong to the same | |
37 | * context or not. One device can have multiple separate contexts, | |
38 | * and they're used if some engine can run independently of another. | |
39 | */ | |
f54d1867 | 40 | static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(0); |
e941759c ML |
41 | |
42 | /** | |
f54d1867 | 43 | * dma_fence_context_alloc - allocate an array of fence contexts |
e941759c ML |
44 | * @num: [in] amount of contexts to allocate |
45 | * | |
46 | * This function will return the first index of the number of fences allocated. | |
47 | * The fence context is used for setting fence->context to a unique number. | |
48 | */ | |
f54d1867 | 49 | u64 dma_fence_context_alloc(unsigned num) |
e941759c ML |
50 | { |
51 | BUG_ON(!num); | |
f54d1867 | 52 | return atomic64_add_return(num, &dma_fence_context_counter) - num; |
e941759c | 53 | } |
f54d1867 | 54 | EXPORT_SYMBOL(dma_fence_context_alloc); |
e941759c ML |
55 | |
56 | /** | |
f54d1867 | 57 | * dma_fence_signal_locked - signal completion of a fence |
e941759c ML |
58 | * @fence: the fence to signal |
59 | * | |
60 | * Signal completion for software callbacks on a fence, this will unblock | |
f54d1867 CW |
61 | * dma_fence_wait() calls and run all the callbacks added with |
62 | * dma_fence_add_callback(). Can be called multiple times, but since a fence | |
e941759c ML |
63 | * can only go from unsignaled to signaled state, it will only be effective |
64 | * the first time. | |
65 | * | |
f54d1867 | 66 | * Unlike dma_fence_signal, this function must be called with fence->lock held. |
e941759c | 67 | */ |
f54d1867 | 68 | int dma_fence_signal_locked(struct dma_fence *fence) |
e941759c | 69 | { |
f54d1867 | 70 | struct dma_fence_cb *cur, *tmp; |
e941759c ML |
71 | int ret = 0; |
72 | ||
78010cd9 RC |
73 | lockdep_assert_held(fence->lock); |
74 | ||
e941759c ML |
75 | if (WARN_ON(!fence)) |
76 | return -EINVAL; | |
77 | ||
f54d1867 | 78 | if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
e941759c ML |
79 | ret = -EINVAL; |
80 | ||
81 | /* | |
f54d1867 | 82 | * we might have raced with the unlocked dma_fence_signal, |
e941759c ML |
83 | * still run through all callbacks |
84 | */ | |
76250f2b CW |
85 | } else { |
86 | fence->timestamp = ktime_get(); | |
87 | set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags); | |
f54d1867 | 88 | trace_dma_fence_signaled(fence); |
76250f2b | 89 | } |
e941759c ML |
90 | |
91 | list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) { | |
92 | list_del_init(&cur->node); | |
93 | cur->func(fence, cur); | |
94 | } | |
95 | return ret; | |
96 | } | |
f54d1867 | 97 | EXPORT_SYMBOL(dma_fence_signal_locked); |
e941759c ML |
98 | |
99 | /** | |
f54d1867 | 100 | * dma_fence_signal - signal completion of a fence |
e941759c ML |
101 | * @fence: the fence to signal |
102 | * | |
103 | * Signal completion for software callbacks on a fence, this will unblock | |
f54d1867 CW |
104 | * dma_fence_wait() calls and run all the callbacks added with |
105 | * dma_fence_add_callback(). Can be called multiple times, but since a fence | |
e941759c ML |
106 | * can only go from unsignaled to signaled state, it will only be effective |
107 | * the first time. | |
108 | */ | |
f54d1867 | 109 | int dma_fence_signal(struct dma_fence *fence) |
e941759c ML |
110 | { |
111 | unsigned long flags; | |
112 | ||
113 | if (!fence) | |
114 | return -EINVAL; | |
115 | ||
f54d1867 | 116 | if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
e941759c ML |
117 | return -EINVAL; |
118 | ||
76250f2b CW |
119 | fence->timestamp = ktime_get(); |
120 | set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags); | |
f54d1867 | 121 | trace_dma_fence_signaled(fence); |
e941759c | 122 | |
f54d1867 CW |
123 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags)) { |
124 | struct dma_fence_cb *cur, *tmp; | |
e941759c ML |
125 | |
126 | spin_lock_irqsave(fence->lock, flags); | |
127 | list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) { | |
128 | list_del_init(&cur->node); | |
129 | cur->func(fence, cur); | |
130 | } | |
131 | spin_unlock_irqrestore(fence->lock, flags); | |
132 | } | |
133 | return 0; | |
134 | } | |
f54d1867 | 135 | EXPORT_SYMBOL(dma_fence_signal); |
e941759c ML |
136 | |
137 | /** | |
f54d1867 | 138 | * dma_fence_wait_timeout - sleep until the fence gets signaled |
e941759c ML |
139 | * or until timeout elapses |
140 | * @fence: [in] the fence to wait on | |
141 | * @intr: [in] if true, do an interruptible wait | |
142 | * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT | |
143 | * | |
144 | * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the | |
145 | * remaining timeout in jiffies on success. Other error values may be | |
146 | * returned on custom implementations. | |
147 | * | |
148 | * Performs a synchronous wait on this fence. It is assumed the caller | |
149 | * directly or indirectly (buf-mgr between reservation and committing) | |
150 | * holds a reference to the fence, otherwise the fence might be | |
151 | * freed before return, resulting in undefined behavior. | |
152 | */ | |
153 | signed long | |
f54d1867 | 154 | dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) |
e941759c ML |
155 | { |
156 | signed long ret; | |
157 | ||
158 | if (WARN_ON(timeout < 0)) | |
159 | return -EINVAL; | |
160 | ||
f54d1867 | 161 | trace_dma_fence_wait_start(fence); |
e941759c | 162 | ret = fence->ops->wait(fence, intr, timeout); |
f54d1867 | 163 | trace_dma_fence_wait_end(fence); |
e941759c ML |
164 | return ret; |
165 | } | |
f54d1867 | 166 | EXPORT_SYMBOL(dma_fence_wait_timeout); |
e941759c | 167 | |
f54d1867 | 168 | void dma_fence_release(struct kref *kref) |
e941759c | 169 | { |
f54d1867 CW |
170 | struct dma_fence *fence = |
171 | container_of(kref, struct dma_fence, refcount); | |
e941759c | 172 | |
f54d1867 | 173 | trace_dma_fence_destroy(fence); |
e941759c ML |
174 | |
175 | BUG_ON(!list_empty(&fence->cb_list)); | |
176 | ||
177 | if (fence->ops->release) | |
178 | fence->ops->release(fence); | |
179 | else | |
f54d1867 | 180 | dma_fence_free(fence); |
e941759c | 181 | } |
f54d1867 | 182 | EXPORT_SYMBOL(dma_fence_release); |
e941759c | 183 | |
f54d1867 | 184 | void dma_fence_free(struct dma_fence *fence) |
e941759c | 185 | { |
3c3b177a | 186 | kfree_rcu(fence, rcu); |
e941759c | 187 | } |
f54d1867 | 188 | EXPORT_SYMBOL(dma_fence_free); |
e941759c ML |
189 | |
190 | /** | |
f54d1867 | 191 | * dma_fence_enable_sw_signaling - enable signaling on fence |
e941759c ML |
192 | * @fence: [in] the fence to enable |
193 | * | |
194 | * this will request for sw signaling to be enabled, to make the fence | |
195 | * complete as soon as possible | |
196 | */ | |
f54d1867 | 197 | void dma_fence_enable_sw_signaling(struct dma_fence *fence) |
e941759c ML |
198 | { |
199 | unsigned long flags; | |
200 | ||
f54d1867 CW |
201 | if (!test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, |
202 | &fence->flags) && | |
203 | !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { | |
204 | trace_dma_fence_enable_signal(fence); | |
e941759c ML |
205 | |
206 | spin_lock_irqsave(fence->lock, flags); | |
207 | ||
208 | if (!fence->ops->enable_signaling(fence)) | |
f54d1867 | 209 | dma_fence_signal_locked(fence); |
e941759c ML |
210 | |
211 | spin_unlock_irqrestore(fence->lock, flags); | |
212 | } | |
213 | } | |
f54d1867 | 214 | EXPORT_SYMBOL(dma_fence_enable_sw_signaling); |
e941759c ML |
215 | |
216 | /** | |
f54d1867 | 217 | * dma_fence_add_callback - add a callback to be called when the fence |
e941759c ML |
218 | * is signaled |
219 | * @fence: [in] the fence to wait on | |
220 | * @cb: [in] the callback to register | |
221 | * @func: [in] the function to call | |
222 | * | |
f54d1867 | 223 | * cb will be initialized by dma_fence_add_callback, no initialization |
e941759c ML |
224 | * by the caller is required. Any number of callbacks can be registered |
225 | * to a fence, but a callback can only be registered to one fence at a time. | |
226 | * | |
227 | * Note that the callback can be called from an atomic context. If | |
228 | * fence is already signaled, this function will return -ENOENT (and | |
229 | * *not* call the callback) | |
230 | * | |
231 | * Add a software callback to the fence. Same restrictions apply to | |
f54d1867 | 232 | * refcount as it does to dma_fence_wait, however the caller doesn't need to |
e941759c ML |
233 | * keep a refcount to fence afterwards: when software access is enabled, |
234 | * the creator of the fence is required to keep the fence alive until | |
f54d1867 | 235 | * after it signals with dma_fence_signal. The callback itself can be called |
e941759c ML |
236 | * from irq context. |
237 | * | |
f642de16 GP |
238 | * Returns 0 in case of success, -ENOENT if the fence is already signaled |
239 | * and -EINVAL in case of error. | |
e941759c | 240 | */ |
f54d1867 CW |
241 | int dma_fence_add_callback(struct dma_fence *fence, struct dma_fence_cb *cb, |
242 | dma_fence_func_t func) | |
e941759c ML |
243 | { |
244 | unsigned long flags; | |
245 | int ret = 0; | |
246 | bool was_set; | |
247 | ||
248 | if (WARN_ON(!fence || !func)) | |
249 | return -EINVAL; | |
250 | ||
f54d1867 | 251 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
e941759c ML |
252 | INIT_LIST_HEAD(&cb->node); |
253 | return -ENOENT; | |
254 | } | |
255 | ||
256 | spin_lock_irqsave(fence->lock, flags); | |
257 | ||
f54d1867 CW |
258 | was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, |
259 | &fence->flags); | |
e941759c | 260 | |
f54d1867 | 261 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
e941759c ML |
262 | ret = -ENOENT; |
263 | else if (!was_set) { | |
f54d1867 | 264 | trace_dma_fence_enable_signal(fence); |
e941759c ML |
265 | |
266 | if (!fence->ops->enable_signaling(fence)) { | |
f54d1867 | 267 | dma_fence_signal_locked(fence); |
e941759c ML |
268 | ret = -ENOENT; |
269 | } | |
270 | } | |
271 | ||
272 | if (!ret) { | |
273 | cb->func = func; | |
274 | list_add_tail(&cb->node, &fence->cb_list); | |
275 | } else | |
276 | INIT_LIST_HEAD(&cb->node); | |
277 | spin_unlock_irqrestore(fence->lock, flags); | |
278 | ||
279 | return ret; | |
280 | } | |
f54d1867 | 281 | EXPORT_SYMBOL(dma_fence_add_callback); |
e941759c | 282 | |
d6c99f4b CW |
283 | /** |
284 | * dma_fence_get_status - returns the status upon completion | |
285 | * @fence: [in] the dma_fence to query | |
286 | * | |
287 | * This wraps dma_fence_get_status_locked() to return the error status | |
288 | * condition on a signaled fence. See dma_fence_get_status_locked() for more | |
289 | * details. | |
290 | * | |
291 | * Returns 0 if the fence has not yet been signaled, 1 if the fence has | |
292 | * been signaled without an error condition, or a negative error code | |
293 | * if the fence has been completed in err. | |
294 | */ | |
295 | int dma_fence_get_status(struct dma_fence *fence) | |
296 | { | |
297 | unsigned long flags; | |
298 | int status; | |
299 | ||
300 | spin_lock_irqsave(fence->lock, flags); | |
301 | status = dma_fence_get_status_locked(fence); | |
302 | spin_unlock_irqrestore(fence->lock, flags); | |
303 | ||
304 | return status; | |
305 | } | |
306 | EXPORT_SYMBOL(dma_fence_get_status); | |
307 | ||
e941759c | 308 | /** |
f54d1867 | 309 | * dma_fence_remove_callback - remove a callback from the signaling list |
e941759c ML |
310 | * @fence: [in] the fence to wait on |
311 | * @cb: [in] the callback to remove | |
312 | * | |
313 | * Remove a previously queued callback from the fence. This function returns | |
f353d71f | 314 | * true if the callback is successfully removed, or false if the fence has |
e941759c ML |
315 | * already been signaled. |
316 | * | |
317 | * *WARNING*: | |
318 | * Cancelling a callback should only be done if you really know what you're | |
319 | * doing, since deadlocks and race conditions could occur all too easily. For | |
320 | * this reason, it should only ever be done on hardware lockup recovery, | |
321 | * with a reference held to the fence. | |
322 | */ | |
323 | bool | |
f54d1867 | 324 | dma_fence_remove_callback(struct dma_fence *fence, struct dma_fence_cb *cb) |
e941759c ML |
325 | { |
326 | unsigned long flags; | |
327 | bool ret; | |
328 | ||
329 | spin_lock_irqsave(fence->lock, flags); | |
330 | ||
331 | ret = !list_empty(&cb->node); | |
332 | if (ret) | |
333 | list_del_init(&cb->node); | |
334 | ||
335 | spin_unlock_irqrestore(fence->lock, flags); | |
336 | ||
337 | return ret; | |
338 | } | |
f54d1867 | 339 | EXPORT_SYMBOL(dma_fence_remove_callback); |
e941759c ML |
340 | |
341 | struct default_wait_cb { | |
f54d1867 | 342 | struct dma_fence_cb base; |
e941759c ML |
343 | struct task_struct *task; |
344 | }; | |
345 | ||
346 | static void | |
f54d1867 | 347 | dma_fence_default_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb) |
e941759c ML |
348 | { |
349 | struct default_wait_cb *wait = | |
350 | container_of(cb, struct default_wait_cb, base); | |
351 | ||
352 | wake_up_state(wait->task, TASK_NORMAL); | |
353 | } | |
354 | ||
355 | /** | |
f54d1867 | 356 | * dma_fence_default_wait - default sleep until the fence gets signaled |
e941759c ML |
357 | * or until timeout elapses |
358 | * @fence: [in] the fence to wait on | |
359 | * @intr: [in] if true, do an interruptible wait | |
360 | * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT | |
361 | * | |
362 | * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the | |
bcc004b6 AD |
363 | * remaining timeout in jiffies on success. If timeout is zero the value one is |
364 | * returned if the fence is already signaled for consistency with other | |
365 | * functions taking a jiffies timeout. | |
e941759c ML |
366 | */ |
367 | signed long | |
f54d1867 | 368 | dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) |
e941759c ML |
369 | { |
370 | struct default_wait_cb cb; | |
371 | unsigned long flags; | |
bcc004b6 | 372 | signed long ret = timeout ? timeout : 1; |
e941759c ML |
373 | bool was_set; |
374 | ||
f54d1867 | 375 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
bcc004b6 | 376 | return ret; |
e941759c ML |
377 | |
378 | spin_lock_irqsave(fence->lock, flags); | |
379 | ||
380 | if (intr && signal_pending(current)) { | |
381 | ret = -ERESTARTSYS; | |
382 | goto out; | |
383 | } | |
384 | ||
f54d1867 CW |
385 | was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, |
386 | &fence->flags); | |
e941759c | 387 | |
f54d1867 | 388 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
e941759c ML |
389 | goto out; |
390 | ||
391 | if (!was_set) { | |
f54d1867 | 392 | trace_dma_fence_enable_signal(fence); |
e941759c ML |
393 | |
394 | if (!fence->ops->enable_signaling(fence)) { | |
f54d1867 | 395 | dma_fence_signal_locked(fence); |
e941759c ML |
396 | goto out; |
397 | } | |
398 | } | |
399 | ||
03c0c5f6 AR |
400 | if (!timeout) { |
401 | ret = 0; | |
402 | goto out; | |
403 | } | |
404 | ||
f54d1867 | 405 | cb.base.func = dma_fence_default_wait_cb; |
e941759c ML |
406 | cb.task = current; |
407 | list_add(&cb.base.node, &fence->cb_list); | |
408 | ||
f54d1867 | 409 | while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) { |
e941759c ML |
410 | if (intr) |
411 | __set_current_state(TASK_INTERRUPTIBLE); | |
412 | else | |
413 | __set_current_state(TASK_UNINTERRUPTIBLE); | |
414 | spin_unlock_irqrestore(fence->lock, flags); | |
415 | ||
416 | ret = schedule_timeout(ret); | |
417 | ||
418 | spin_lock_irqsave(fence->lock, flags); | |
419 | if (ret > 0 && intr && signal_pending(current)) | |
420 | ret = -ERESTARTSYS; | |
421 | } | |
422 | ||
423 | if (!list_empty(&cb.base.node)) | |
424 | list_del(&cb.base.node); | |
425 | __set_current_state(TASK_RUNNING); | |
426 | ||
427 | out: | |
428 | spin_unlock_irqrestore(fence->lock, flags); | |
429 | return ret; | |
430 | } | |
f54d1867 | 431 | EXPORT_SYMBOL(dma_fence_default_wait); |
e941759c | 432 | |
a519435a | 433 | static bool |
7392b4bb | 434 | dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, |
435 | uint32_t *idx) | |
a519435a CK |
436 | { |
437 | int i; | |
438 | ||
439 | for (i = 0; i < count; ++i) { | |
f54d1867 | 440 | struct dma_fence *fence = fences[i]; |
7392b4bb | 441 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
442 | if (idx) | |
443 | *idx = i; | |
a519435a | 444 | return true; |
7392b4bb | 445 | } |
a519435a CK |
446 | } |
447 | return false; | |
448 | } | |
449 | ||
450 | /** | |
f54d1867 | 451 | * dma_fence_wait_any_timeout - sleep until any fence gets signaled |
a519435a CK |
452 | * or until timeout elapses |
453 | * @fences: [in] array of fences to wait on | |
454 | * @count: [in] number of fences to wait on | |
455 | * @intr: [in] if true, do an interruptible wait | |
456 | * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT | |
7392b4bb | 457 | * @idx: [out] the first signaled fence index, meaningful only on |
458 | * positive return | |
a519435a CK |
459 | * |
460 | * Returns -EINVAL on custom fence wait implementation, -ERESTARTSYS if | |
461 | * interrupted, 0 if the wait timed out, or the remaining timeout in jiffies | |
462 | * on success. | |
463 | * | |
464 | * Synchronous waits for the first fence in the array to be signaled. The | |
465 | * caller needs to hold a reference to all fences in the array, otherwise a | |
466 | * fence might be freed before return, resulting in undefined behavior. | |
467 | */ | |
468 | signed long | |
f54d1867 | 469 | dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, |
7392b4bb | 470 | bool intr, signed long timeout, uint32_t *idx) |
a519435a CK |
471 | { |
472 | struct default_wait_cb *cb; | |
473 | signed long ret = timeout; | |
474 | unsigned i; | |
475 | ||
476 | if (WARN_ON(!fences || !count || timeout < 0)) | |
477 | return -EINVAL; | |
478 | ||
479 | if (timeout == 0) { | |
480 | for (i = 0; i < count; ++i) | |
7392b4bb | 481 | if (dma_fence_is_signaled(fences[i])) { |
482 | if (idx) | |
483 | *idx = i; | |
a519435a | 484 | return 1; |
7392b4bb | 485 | } |
a519435a CK |
486 | |
487 | return 0; | |
488 | } | |
489 | ||
490 | cb = kcalloc(count, sizeof(struct default_wait_cb), GFP_KERNEL); | |
491 | if (cb == NULL) { | |
492 | ret = -ENOMEM; | |
493 | goto err_free_cb; | |
494 | } | |
495 | ||
496 | for (i = 0; i < count; ++i) { | |
f54d1867 | 497 | struct dma_fence *fence = fences[i]; |
a519435a | 498 | |
f54d1867 | 499 | if (fence->ops->wait != dma_fence_default_wait) { |
a519435a CK |
500 | ret = -EINVAL; |
501 | goto fence_rm_cb; | |
502 | } | |
503 | ||
504 | cb[i].task = current; | |
f54d1867 CW |
505 | if (dma_fence_add_callback(fence, &cb[i].base, |
506 | dma_fence_default_wait_cb)) { | |
a519435a | 507 | /* This fence is already signaled */ |
7392b4bb | 508 | if (idx) |
509 | *idx = i; | |
a519435a CK |
510 | goto fence_rm_cb; |
511 | } | |
512 | } | |
513 | ||
514 | while (ret > 0) { | |
515 | if (intr) | |
516 | set_current_state(TASK_INTERRUPTIBLE); | |
517 | else | |
518 | set_current_state(TASK_UNINTERRUPTIBLE); | |
519 | ||
7392b4bb | 520 | if (dma_fence_test_signaled_any(fences, count, idx)) |
a519435a CK |
521 | break; |
522 | ||
523 | ret = schedule_timeout(ret); | |
524 | ||
525 | if (ret > 0 && intr && signal_pending(current)) | |
526 | ret = -ERESTARTSYS; | |
527 | } | |
528 | ||
529 | __set_current_state(TASK_RUNNING); | |
530 | ||
531 | fence_rm_cb: | |
532 | while (i-- > 0) | |
f54d1867 | 533 | dma_fence_remove_callback(fences[i], &cb[i].base); |
a519435a CK |
534 | |
535 | err_free_cb: | |
536 | kfree(cb); | |
537 | ||
538 | return ret; | |
539 | } | |
f54d1867 | 540 | EXPORT_SYMBOL(dma_fence_wait_any_timeout); |
a519435a | 541 | |
e941759c | 542 | /** |
f54d1867 | 543 | * dma_fence_init - Initialize a custom fence. |
e941759c | 544 | * @fence: [in] the fence to initialize |
f54d1867 | 545 | * @ops: [in] the dma_fence_ops for operations on this fence |
e941759c ML |
546 | * @lock: [in] the irqsafe spinlock to use for locking this fence |
547 | * @context: [in] the execution context this fence is run on | |
548 | * @seqno: [in] a linear increasing sequence number for this context | |
549 | * | |
550 | * Initializes an allocated fence, the caller doesn't have to keep its | |
551 | * refcount after committing with this fence, but it will need to hold a | |
f54d1867 | 552 | * refcount again if dma_fence_ops.enable_signaling gets called. This can |
e941759c ML |
553 | * be used for other implementing other types of fence. |
554 | * | |
555 | * context and seqno are used for easy comparison between fences, allowing | |
f54d1867 | 556 | * to check which fence is later by simply using dma_fence_later. |
e941759c ML |
557 | */ |
558 | void | |
f54d1867 CW |
559 | dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, |
560 | spinlock_t *lock, u64 context, unsigned seqno) | |
e941759c ML |
561 | { |
562 | BUG_ON(!lock); | |
563 | BUG_ON(!ops || !ops->wait || !ops->enable_signaling || | |
564 | !ops->get_driver_name || !ops->get_timeline_name); | |
565 | ||
566 | kref_init(&fence->refcount); | |
567 | fence->ops = ops; | |
568 | INIT_LIST_HEAD(&fence->cb_list); | |
569 | fence->lock = lock; | |
570 | fence->context = context; | |
571 | fence->seqno = seqno; | |
572 | fence->flags = 0UL; | |
a009e975 | 573 | fence->error = 0; |
e941759c | 574 | |
f54d1867 | 575 | trace_dma_fence_init(fence); |
e941759c | 576 | } |
f54d1867 | 577 | EXPORT_SYMBOL(dma_fence_init); |