]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/dma-buf/dma-fence.c
sched/headers: Prepare to move signal wakeup & sigpending methods from <linux/sched...
[mirror_ubuntu-hirsute-kernel.git] / drivers / dma-buf / dma-fence.c
CommitLineData
e941759c
ML
1/*
2 * Fence mechanism for dma-buf and to allow for asynchronous dma access
3 *
4 * Copyright (C) 2012 Canonical Ltd
5 * Copyright (C) 2012 Texas Instruments
6 *
7 * Authors:
8 * Rob Clark <robdclark@gmail.com>
9 * Maarten Lankhorst <maarten.lankhorst@canonical.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 */
20
21#include <linux/slab.h>
22#include <linux/export.h>
23#include <linux/atomic.h>
f54d1867 24#include <linux/dma-fence.h>
174cd4b1 25#include <linux/sched/signal.h>
e941759c
ML
26
27#define CREATE_TRACE_POINTS
f54d1867 28#include <trace/events/dma_fence.h>
e941759c 29
f54d1867
CW
30EXPORT_TRACEPOINT_SYMBOL(dma_fence_annotate_wait_on);
31EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
8c96c678 32EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
e941759c 33
e9f3b796 34/*
e941759c
ML
35 * fence context counter: each execution context should have its own
36 * fence context, this allows checking if fences belong to the same
37 * context or not. One device can have multiple separate contexts,
38 * and they're used if some engine can run independently of another.
39 */
f54d1867 40static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(0);
e941759c
ML
41
42/**
f54d1867 43 * dma_fence_context_alloc - allocate an array of fence contexts
e941759c
ML
44 * @num: [in] amount of contexts to allocate
45 *
46 * This function will return the first index of the number of fences allocated.
47 * The fence context is used for setting fence->context to a unique number.
48 */
f54d1867 49u64 dma_fence_context_alloc(unsigned num)
e941759c
ML
50{
51 BUG_ON(!num);
f54d1867 52 return atomic64_add_return(num, &dma_fence_context_counter) - num;
e941759c 53}
f54d1867 54EXPORT_SYMBOL(dma_fence_context_alloc);
e941759c
ML
55
56/**
f54d1867 57 * dma_fence_signal_locked - signal completion of a fence
e941759c
ML
58 * @fence: the fence to signal
59 *
60 * Signal completion for software callbacks on a fence, this will unblock
f54d1867
CW
61 * dma_fence_wait() calls and run all the callbacks added with
62 * dma_fence_add_callback(). Can be called multiple times, but since a fence
e941759c
ML
63 * can only go from unsignaled to signaled state, it will only be effective
64 * the first time.
65 *
f54d1867 66 * Unlike dma_fence_signal, this function must be called with fence->lock held.
e941759c 67 */
f54d1867 68int dma_fence_signal_locked(struct dma_fence *fence)
e941759c 69{
f54d1867 70 struct dma_fence_cb *cur, *tmp;
e941759c
ML
71 int ret = 0;
72
78010cd9
RC
73 lockdep_assert_held(fence->lock);
74
e941759c
ML
75 if (WARN_ON(!fence))
76 return -EINVAL;
77
78 if (!ktime_to_ns(fence->timestamp)) {
79 fence->timestamp = ktime_get();
80 smp_mb__before_atomic();
81 }
82
f54d1867 83 if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
e941759c
ML
84 ret = -EINVAL;
85
86 /*
f54d1867 87 * we might have raced with the unlocked dma_fence_signal,
e941759c
ML
88 * still run through all callbacks
89 */
90 } else
f54d1867 91 trace_dma_fence_signaled(fence);
e941759c
ML
92
93 list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) {
94 list_del_init(&cur->node);
95 cur->func(fence, cur);
96 }
97 return ret;
98}
f54d1867 99EXPORT_SYMBOL(dma_fence_signal_locked);
e941759c
ML
100
101/**
f54d1867 102 * dma_fence_signal - signal completion of a fence
e941759c
ML
103 * @fence: the fence to signal
104 *
105 * Signal completion for software callbacks on a fence, this will unblock
f54d1867
CW
106 * dma_fence_wait() calls and run all the callbacks added with
107 * dma_fence_add_callback(). Can be called multiple times, but since a fence
e941759c
ML
108 * can only go from unsignaled to signaled state, it will only be effective
109 * the first time.
110 */
f54d1867 111int dma_fence_signal(struct dma_fence *fence)
e941759c
ML
112{
113 unsigned long flags;
114
115 if (!fence)
116 return -EINVAL;
117
118 if (!ktime_to_ns(fence->timestamp)) {
119 fence->timestamp = ktime_get();
120 smp_mb__before_atomic();
121 }
122
f54d1867 123 if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
e941759c
ML
124 return -EINVAL;
125
f54d1867 126 trace_dma_fence_signaled(fence);
e941759c 127
f54d1867
CW
128 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags)) {
129 struct dma_fence_cb *cur, *tmp;
e941759c
ML
130
131 spin_lock_irqsave(fence->lock, flags);
132 list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) {
133 list_del_init(&cur->node);
134 cur->func(fence, cur);
135 }
136 spin_unlock_irqrestore(fence->lock, flags);
137 }
138 return 0;
139}
f54d1867 140EXPORT_SYMBOL(dma_fence_signal);
e941759c
ML
141
142/**
f54d1867 143 * dma_fence_wait_timeout - sleep until the fence gets signaled
e941759c
ML
144 * or until timeout elapses
145 * @fence: [in] the fence to wait on
146 * @intr: [in] if true, do an interruptible wait
147 * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
148 *
149 * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the
150 * remaining timeout in jiffies on success. Other error values may be
151 * returned on custom implementations.
152 *
153 * Performs a synchronous wait on this fence. It is assumed the caller
154 * directly or indirectly (buf-mgr between reservation and committing)
155 * holds a reference to the fence, otherwise the fence might be
156 * freed before return, resulting in undefined behavior.
157 */
158signed long
f54d1867 159dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout)
e941759c
ML
160{
161 signed long ret;
162
163 if (WARN_ON(timeout < 0))
164 return -EINVAL;
165
f54d1867 166 trace_dma_fence_wait_start(fence);
e941759c 167 ret = fence->ops->wait(fence, intr, timeout);
f54d1867 168 trace_dma_fence_wait_end(fence);
e941759c
ML
169 return ret;
170}
f54d1867 171EXPORT_SYMBOL(dma_fence_wait_timeout);
e941759c 172
f54d1867 173void dma_fence_release(struct kref *kref)
e941759c 174{
f54d1867
CW
175 struct dma_fence *fence =
176 container_of(kref, struct dma_fence, refcount);
e941759c 177
f54d1867 178 trace_dma_fence_destroy(fence);
e941759c
ML
179
180 BUG_ON(!list_empty(&fence->cb_list));
181
182 if (fence->ops->release)
183 fence->ops->release(fence);
184 else
f54d1867 185 dma_fence_free(fence);
e941759c 186}
f54d1867 187EXPORT_SYMBOL(dma_fence_release);
e941759c 188
f54d1867 189void dma_fence_free(struct dma_fence *fence)
e941759c 190{
3c3b177a 191 kfree_rcu(fence, rcu);
e941759c 192}
f54d1867 193EXPORT_SYMBOL(dma_fence_free);
e941759c
ML
194
195/**
f54d1867 196 * dma_fence_enable_sw_signaling - enable signaling on fence
e941759c
ML
197 * @fence: [in] the fence to enable
198 *
199 * this will request for sw signaling to be enabled, to make the fence
200 * complete as soon as possible
201 */
f54d1867 202void dma_fence_enable_sw_signaling(struct dma_fence *fence)
e941759c
ML
203{
204 unsigned long flags;
205
f54d1867
CW
206 if (!test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
207 &fence->flags) &&
208 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
209 trace_dma_fence_enable_signal(fence);
e941759c
ML
210
211 spin_lock_irqsave(fence->lock, flags);
212
213 if (!fence->ops->enable_signaling(fence))
f54d1867 214 dma_fence_signal_locked(fence);
e941759c
ML
215
216 spin_unlock_irqrestore(fence->lock, flags);
217 }
218}
f54d1867 219EXPORT_SYMBOL(dma_fence_enable_sw_signaling);
e941759c
ML
220
221/**
f54d1867 222 * dma_fence_add_callback - add a callback to be called when the fence
e941759c
ML
223 * is signaled
224 * @fence: [in] the fence to wait on
225 * @cb: [in] the callback to register
226 * @func: [in] the function to call
227 *
f54d1867 228 * cb will be initialized by dma_fence_add_callback, no initialization
e941759c
ML
229 * by the caller is required. Any number of callbacks can be registered
230 * to a fence, but a callback can only be registered to one fence at a time.
231 *
232 * Note that the callback can be called from an atomic context. If
233 * fence is already signaled, this function will return -ENOENT (and
234 * *not* call the callback)
235 *
236 * Add a software callback to the fence. Same restrictions apply to
f54d1867 237 * refcount as it does to dma_fence_wait, however the caller doesn't need to
e941759c
ML
238 * keep a refcount to fence afterwards: when software access is enabled,
239 * the creator of the fence is required to keep the fence alive until
f54d1867 240 * after it signals with dma_fence_signal. The callback itself can be called
e941759c
ML
241 * from irq context.
242 *
243 */
f54d1867
CW
244int dma_fence_add_callback(struct dma_fence *fence, struct dma_fence_cb *cb,
245 dma_fence_func_t func)
e941759c
ML
246{
247 unsigned long flags;
248 int ret = 0;
249 bool was_set;
250
251 if (WARN_ON(!fence || !func))
252 return -EINVAL;
253
f54d1867 254 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
e941759c
ML
255 INIT_LIST_HEAD(&cb->node);
256 return -ENOENT;
257 }
258
259 spin_lock_irqsave(fence->lock, flags);
260
f54d1867
CW
261 was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
262 &fence->flags);
e941759c 263
f54d1867 264 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
e941759c
ML
265 ret = -ENOENT;
266 else if (!was_set) {
f54d1867 267 trace_dma_fence_enable_signal(fence);
e941759c
ML
268
269 if (!fence->ops->enable_signaling(fence)) {
f54d1867 270 dma_fence_signal_locked(fence);
e941759c
ML
271 ret = -ENOENT;
272 }
273 }
274
275 if (!ret) {
276 cb->func = func;
277 list_add_tail(&cb->node, &fence->cb_list);
278 } else
279 INIT_LIST_HEAD(&cb->node);
280 spin_unlock_irqrestore(fence->lock, flags);
281
282 return ret;
283}
f54d1867 284EXPORT_SYMBOL(dma_fence_add_callback);
e941759c 285
d6c99f4b
CW
286/**
287 * dma_fence_get_status - returns the status upon completion
288 * @fence: [in] the dma_fence to query
289 *
290 * This wraps dma_fence_get_status_locked() to return the error status
291 * condition on a signaled fence. See dma_fence_get_status_locked() for more
292 * details.
293 *
294 * Returns 0 if the fence has not yet been signaled, 1 if the fence has
295 * been signaled without an error condition, or a negative error code
296 * if the fence has been completed in err.
297 */
298int dma_fence_get_status(struct dma_fence *fence)
299{
300 unsigned long flags;
301 int status;
302
303 spin_lock_irqsave(fence->lock, flags);
304 status = dma_fence_get_status_locked(fence);
305 spin_unlock_irqrestore(fence->lock, flags);
306
307 return status;
308}
309EXPORT_SYMBOL(dma_fence_get_status);
310
e941759c 311/**
f54d1867 312 * dma_fence_remove_callback - remove a callback from the signaling list
e941759c
ML
313 * @fence: [in] the fence to wait on
314 * @cb: [in] the callback to remove
315 *
316 * Remove a previously queued callback from the fence. This function returns
f353d71f 317 * true if the callback is successfully removed, or false if the fence has
e941759c
ML
318 * already been signaled.
319 *
320 * *WARNING*:
321 * Cancelling a callback should only be done if you really know what you're
322 * doing, since deadlocks and race conditions could occur all too easily. For
323 * this reason, it should only ever be done on hardware lockup recovery,
324 * with a reference held to the fence.
325 */
326bool
f54d1867 327dma_fence_remove_callback(struct dma_fence *fence, struct dma_fence_cb *cb)
e941759c
ML
328{
329 unsigned long flags;
330 bool ret;
331
332 spin_lock_irqsave(fence->lock, flags);
333
334 ret = !list_empty(&cb->node);
335 if (ret)
336 list_del_init(&cb->node);
337
338 spin_unlock_irqrestore(fence->lock, flags);
339
340 return ret;
341}
f54d1867 342EXPORT_SYMBOL(dma_fence_remove_callback);
e941759c
ML
343
344struct default_wait_cb {
f54d1867 345 struct dma_fence_cb base;
e941759c
ML
346 struct task_struct *task;
347};
348
349static void
f54d1867 350dma_fence_default_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb)
e941759c
ML
351{
352 struct default_wait_cb *wait =
353 container_of(cb, struct default_wait_cb, base);
354
355 wake_up_state(wait->task, TASK_NORMAL);
356}
357
358/**
f54d1867 359 * dma_fence_default_wait - default sleep until the fence gets signaled
e941759c
ML
360 * or until timeout elapses
361 * @fence: [in] the fence to wait on
362 * @intr: [in] if true, do an interruptible wait
363 * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
364 *
365 * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the
bcc004b6
AD
366 * remaining timeout in jiffies on success. If timeout is zero the value one is
367 * returned if the fence is already signaled for consistency with other
368 * functions taking a jiffies timeout.
e941759c
ML
369 */
370signed long
f54d1867 371dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout)
e941759c
ML
372{
373 struct default_wait_cb cb;
374 unsigned long flags;
bcc004b6 375 signed long ret = timeout ? timeout : 1;
e941759c
ML
376 bool was_set;
377
f54d1867 378 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
bcc004b6 379 return ret;
e941759c
ML
380
381 spin_lock_irqsave(fence->lock, flags);
382
383 if (intr && signal_pending(current)) {
384 ret = -ERESTARTSYS;
385 goto out;
386 }
387
f54d1867
CW
388 was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
389 &fence->flags);
e941759c 390
f54d1867 391 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
e941759c
ML
392 goto out;
393
394 if (!was_set) {
f54d1867 395 trace_dma_fence_enable_signal(fence);
e941759c
ML
396
397 if (!fence->ops->enable_signaling(fence)) {
f54d1867 398 dma_fence_signal_locked(fence);
e941759c
ML
399 goto out;
400 }
401 }
402
f54d1867 403 cb.base.func = dma_fence_default_wait_cb;
e941759c
ML
404 cb.task = current;
405 list_add(&cb.base.node, &fence->cb_list);
406
f54d1867 407 while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) {
e941759c
ML
408 if (intr)
409 __set_current_state(TASK_INTERRUPTIBLE);
410 else
411 __set_current_state(TASK_UNINTERRUPTIBLE);
412 spin_unlock_irqrestore(fence->lock, flags);
413
414 ret = schedule_timeout(ret);
415
416 spin_lock_irqsave(fence->lock, flags);
417 if (ret > 0 && intr && signal_pending(current))
418 ret = -ERESTARTSYS;
419 }
420
421 if (!list_empty(&cb.base.node))
422 list_del(&cb.base.node);
423 __set_current_state(TASK_RUNNING);
424
425out:
426 spin_unlock_irqrestore(fence->lock, flags);
427 return ret;
428}
f54d1867 429EXPORT_SYMBOL(dma_fence_default_wait);
e941759c 430
a519435a 431static bool
7392b4bb 432dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count,
433 uint32_t *idx)
a519435a
CK
434{
435 int i;
436
437 for (i = 0; i < count; ++i) {
f54d1867 438 struct dma_fence *fence = fences[i];
7392b4bb 439 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
440 if (idx)
441 *idx = i;
a519435a 442 return true;
7392b4bb 443 }
a519435a
CK
444 }
445 return false;
446}
447
448/**
f54d1867 449 * dma_fence_wait_any_timeout - sleep until any fence gets signaled
a519435a
CK
450 * or until timeout elapses
451 * @fences: [in] array of fences to wait on
452 * @count: [in] number of fences to wait on
453 * @intr: [in] if true, do an interruptible wait
454 * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
7392b4bb 455 * @idx: [out] the first signaled fence index, meaningful only on
456 * positive return
a519435a
CK
457 *
458 * Returns -EINVAL on custom fence wait implementation, -ERESTARTSYS if
459 * interrupted, 0 if the wait timed out, or the remaining timeout in jiffies
460 * on success.
461 *
462 * Synchronous waits for the first fence in the array to be signaled. The
463 * caller needs to hold a reference to all fences in the array, otherwise a
464 * fence might be freed before return, resulting in undefined behavior.
465 */
466signed long
f54d1867 467dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count,
7392b4bb 468 bool intr, signed long timeout, uint32_t *idx)
a519435a
CK
469{
470 struct default_wait_cb *cb;
471 signed long ret = timeout;
472 unsigned i;
473
474 if (WARN_ON(!fences || !count || timeout < 0))
475 return -EINVAL;
476
477 if (timeout == 0) {
478 for (i = 0; i < count; ++i)
7392b4bb 479 if (dma_fence_is_signaled(fences[i])) {
480 if (idx)
481 *idx = i;
a519435a 482 return 1;
7392b4bb 483 }
a519435a
CK
484
485 return 0;
486 }
487
488 cb = kcalloc(count, sizeof(struct default_wait_cb), GFP_KERNEL);
489 if (cb == NULL) {
490 ret = -ENOMEM;
491 goto err_free_cb;
492 }
493
494 for (i = 0; i < count; ++i) {
f54d1867 495 struct dma_fence *fence = fences[i];
a519435a 496
f54d1867 497 if (fence->ops->wait != dma_fence_default_wait) {
a519435a
CK
498 ret = -EINVAL;
499 goto fence_rm_cb;
500 }
501
502 cb[i].task = current;
f54d1867
CW
503 if (dma_fence_add_callback(fence, &cb[i].base,
504 dma_fence_default_wait_cb)) {
a519435a 505 /* This fence is already signaled */
7392b4bb 506 if (idx)
507 *idx = i;
a519435a
CK
508 goto fence_rm_cb;
509 }
510 }
511
512 while (ret > 0) {
513 if (intr)
514 set_current_state(TASK_INTERRUPTIBLE);
515 else
516 set_current_state(TASK_UNINTERRUPTIBLE);
517
7392b4bb 518 if (dma_fence_test_signaled_any(fences, count, idx))
a519435a
CK
519 break;
520
521 ret = schedule_timeout(ret);
522
523 if (ret > 0 && intr && signal_pending(current))
524 ret = -ERESTARTSYS;
525 }
526
527 __set_current_state(TASK_RUNNING);
528
529fence_rm_cb:
530 while (i-- > 0)
f54d1867 531 dma_fence_remove_callback(fences[i], &cb[i].base);
a519435a
CK
532
533err_free_cb:
534 kfree(cb);
535
536 return ret;
537}
f54d1867 538EXPORT_SYMBOL(dma_fence_wait_any_timeout);
a519435a 539
e941759c 540/**
f54d1867 541 * dma_fence_init - Initialize a custom fence.
e941759c 542 * @fence: [in] the fence to initialize
f54d1867 543 * @ops: [in] the dma_fence_ops for operations on this fence
e941759c
ML
544 * @lock: [in] the irqsafe spinlock to use for locking this fence
545 * @context: [in] the execution context this fence is run on
546 * @seqno: [in] a linear increasing sequence number for this context
547 *
548 * Initializes an allocated fence, the caller doesn't have to keep its
549 * refcount after committing with this fence, but it will need to hold a
f54d1867 550 * refcount again if dma_fence_ops.enable_signaling gets called. This can
e941759c
ML
551 * be used for other implementing other types of fence.
552 *
553 * context and seqno are used for easy comparison between fences, allowing
f54d1867 554 * to check which fence is later by simply using dma_fence_later.
e941759c
ML
555 */
556void
f54d1867
CW
557dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops,
558 spinlock_t *lock, u64 context, unsigned seqno)
e941759c
ML
559{
560 BUG_ON(!lock);
561 BUG_ON(!ops || !ops->wait || !ops->enable_signaling ||
562 !ops->get_driver_name || !ops->get_timeline_name);
563
564 kref_init(&fence->refcount);
565 fence->ops = ops;
566 INIT_LIST_HEAD(&fence->cb_list);
567 fence->lock = lock;
568 fence->context = context;
569 fence->seqno = seqno;
570 fence->flags = 0UL;
a009e975 571 fence->error = 0;
e941759c 572
f54d1867 573 trace_dma_fence_init(fence);
e941759c 574}
f54d1867 575EXPORT_SYMBOL(dma_fence_init);