[mirror_ubuntu-bionic-kernel.git] / drivers / edac / Kconfig

#
#	EDAC Kconfig
#	Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
#	Licensed and distributed under the GPL

config EDAC_ATOMIC_SCRUB
	bool

config EDAC_SUPPORT
	bool

menuconfig EDAC
	bool "EDAC (Error Detection And Correction) reporting"
	depends on HAS_IOMEM && EDAC_SUPPORT
	help
	  EDAC is designed to report errors in the core system.
	  These are low-level errors that are reported in the CPU or
	  supporting chipset or other subsystems:
	  memory errors, cache errors, PCI errors, thermal throttling, etc..
	  If unsure, select 'Y'.

	  If this code is reporting problems on your system, please
	  see the EDAC project web pages for more information at:

	  <http://bluesmoke.sourceforge.net/>

	  and:

	  <http://buttersideup.com/edacwiki>

	  There is also a mailing list for the EDAC project, which can
	  be found via the sourceforge page.

if EDAC

config EDAC_LEGACY_SYSFS
	bool "EDAC legacy sysfs"
	default y
	help
	  Enable the compatibility sysfs nodes.
	  Use 'Y' if your edac utilities aren't ported to work with the newer
	  structures.

config EDAC_DEBUG
	bool "Debugging"
	select DEBUG_FS
	help
	  This turns on debugging information for the entire EDAC subsystem.
	  You do so by inserting edac_module with "edac_debug_level=x." Valid
	  levels are 0-4 (from low to high) and by default it is set to 2.
	  Usually you should select 'N' here.

config EDAC_DECODE_MCE
	tristate "Decode MCEs in human-readable form (only on AMD for now)"
	depends on CPU_SUP_AMD && X86_MCE_AMD
	default y
	---help---
	  Enable this option if you want to decode Machine Check Exceptions
	  occurring on your machine in human-readable form.

	  You should definitely say Y here in case you want to decode MCEs
	  which occur really early upon boot, before the module infrastructure
	  has been initialized.

config EDAC_MM_EDAC
	tristate "Main Memory EDAC (Error Detection And Correction) reporting"
	select RAS
	help
	  Some systems are able to detect and correct errors in main
	  memory.  EDAC can report statistics on memory error
	  detection and correction (EDAC - or commonly referred to ECC
	  errors).  EDAC will also try to decode where these errors
	  occurred so that a particular failing memory module can be
	  replaced.  If unsure, select 'Y'.

config EDAC_GHES
	bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
	depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
	default y
	help
	  Not all machines support hardware-driven error report. Some of those
	  provide a BIOS-driven error report mechanism via ACPI, using the
	  APEI/GHES driver. By enabling this option, the error reports provided
	  by GHES are sent to userspace via the EDAC API.

	  When this option is enabled, it will disable the hardware-driven
	  mechanisms, if a GHES BIOS is detected, entering into the
	  "Firmware First" mode.

	  It should be noticed that keeping both GHES and a hardware-driven
	  error mechanism won't work well, as BIOS will race with OS, while
	  reading the error registers. So, if you want to not use "Firmware
	  first" GHES error mechanism, you should disable GHES either at
	  compilation time or by passing "ghes.disable=1" Kernel parameter
	  at boot time.

	  In doubt, say 'Y'.

config EDAC_AMD64
	tristate "AMD64 (Opteron, Athlon64)"
	depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE
	help
	  Support for error detection and correction of DRAM ECC errors on
	  the AMD64 families (>= K8) of memory controllers.

config EDAC_AMD64_ERROR_INJECTION
	bool "Sysfs HW Error injection facilities"
	depends on EDAC_AMD64
	help
	  Recent Opterons (Family 10h and later) provide for Memory Error
	  Injection into the ECC detection circuits. The amd64_edac module
	  allows the operator/user to inject Uncorrectable and Correctable
	  errors into DRAM.

	  When enabled, in each of the respective memory controller directories
	  (/sys/devices/system/edac/mc/mcX), there are 3 input files:

	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
	  - inject_word (0..8, 16-bit word of 16-byte section),
	  - inject_ecc_vector (hex ecc vector: select bits of inject word)

	  In addition, there are two control files, inject_read and inject_write,
	  which trigger the DRAM ECC Read and Write respectively.

config EDAC_AMD76X
	tristate "AMD 76x (760, 762, 768)"
	depends on EDAC_MM_EDAC && PCI && X86_32
	help
	  Support for error detection and correction on the AMD 76x
	  series of chipsets used with the Athlon processor.

config EDAC_E7XXX
	tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
	depends on EDAC_MM_EDAC && PCI && X86_32
	help
	  Support for error detection and correction on the Intel
	  E7205, E7500, E7501 and E7505 server chipsets.

config EDAC_E752X
	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  E7520, E7525, E7320 server chipsets.

config EDAC_I82443BXGX
	tristate "Intel 82443BX/GX (440BX/GX)"
	depends on EDAC_MM_EDAC && PCI && X86_32
	depends on BROKEN
	help
	  Support for error detection and correction on the Intel
	  82443BX/GX memory controllers (440BX/GX chipsets).

config EDAC_I82875P
	tristate "Intel 82875p (D82875P, E7210)"
	depends on EDAC_MM_EDAC && PCI && X86_32
	help
	  Support for error detection and correction on the Intel
	  DP82785P and E7210 server chipsets.

config EDAC_I82975X
	tristate "Intel 82975x (D82975x)"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  DP82975x server chipsets.

config EDAC_I3000
	tristate "Intel 3000/3010"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  3000 and 3010 server chipsets.

config EDAC_I3200
	tristate "Intel 3200"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  3200 and 3210 server chipsets.

config EDAC_IE31200
	tristate "Intel e312xx"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  E3-1200 based DRAM controllers.

config EDAC_X38
	tristate "Intel X38"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction on the Intel
	  X38 server chipsets.

config EDAC_I5400
	tristate "Intel 5400 (Seaburg) chipsets"
	depends on EDAC_MM_EDAC && PCI && X86
	help
	  Support for error detection and correction the Intel
	  i5400 MCH chipset (Seaburg).

config EDAC_I7CORE
	tristate "Intel i7 Core (Nehalem) processors"
	depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
	help
	  Support for error detection and correction the Intel
	  i7 Core (Nehalem) Integrated Memory Controller that exists on
	  newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
	  and Xeon 55xx processors.

config EDAC_I82860
	tristate "Intel 82860"
	depends on EDAC_MM_EDAC && PCI && X86_32
	help
	  Support for error detection and correction on the Intel
	  82860 chipset.

config EDAC_R82600
	tristate "Radisys 82600 embedded chipset"
	depends on EDAC_MM_EDAC && PCI && X86_32
	help
	  Support for error detection and correction on the Radisys
	  82600 embedded chipset.

config EDAC_I5000
	tristate "Intel Greencreek/Blackford chipset"
	depends on EDAC_MM_EDAC && X86 && PCI
	help
	  Support for error detection and correction the Intel
	  Greekcreek/Blackford chipsets.

config EDAC_I5100
	tristate "Intel San Clemente MCH"
	depends on EDAC_MM_EDAC && X86 && PCI
	help
	  Support for error detection and correction the Intel
	  San Clemente MCH.

config EDAC_I7300
	tristate "Intel Clarksboro MCH"
	depends on EDAC_MM_EDAC && X86 && PCI
	help
	  Support for error detection and correction the Intel
	  Clarksboro MCH (Intel 7300 chipset).

config EDAC_SBRIDGE
	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
	depends on PCI_MMCONFIG
	help
	  Support for error detection and correction the Intel
	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.

config EDAC_SKX
	tristate "Intel Skylake server Integrated MC"
	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
	depends on PCI_MMCONFIG
	help
	  Support for error detection and correction the Intel
	  Skylake server Integrated Memory Controllers.

config EDAC_PND2
	tristate "Intel Pondicherry2"
	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
	help
	  Support for error detection and correction on the Intel
	  Pondicherry2 Integrated Memory Controller. This SoC IP is
	  first used on the Apollo Lake platform and Denverton
	  micro-server but may appear on others in the future.

config EDAC_MPC85XX
	tristate "Freescale MPC83xx / MPC85xx"
	depends on EDAC_MM_EDAC && FSL_SOC
	help
	  Support for error detection and correction on the Freescale
	  MPC8349, MPC8560, MPC8540, MPC8548, T4240

config EDAC_LAYERSCAPE
	tristate "Freescale Layerscape DDR"
	depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
	help
	  Support for error detection and correction on Freescale memory
	  controllers on Layerscape SoCs.

config EDAC_MV64X60
	tristate "Marvell MV64x60"
	depends on EDAC_MM_EDAC && MV64X60
	help
	  Support for error detection and correction on the Marvell
	  MV64360 and MV64460 chipsets.

config EDAC_PASEMI
	tristate "PA Semi PWRficient"
	depends on EDAC_MM_EDAC && PCI
	depends on PPC_PASEMI
	help
	  Support for error detection and correction on PA Semi
	  PWRficient.

config EDAC_CELL
	tristate "Cell Broadband Engine memory controller"
	depends on EDAC_MM_EDAC && PPC_CELL_COMMON
	help
	  Support for error detection and correction on the
	  Cell Broadband Engine internal memory controller
	  on platform without a hypervisor

config EDAC_PPC4XX
	tristate "PPC4xx IBM DDR2 Memory Controller"
	depends on EDAC_MM_EDAC && 4xx
	help
	  This enables support for EDAC on the ECC memory used
	  with the IBM DDR2 memory controller found in various
	  PowerPC 4xx embedded processors such as the 405EX[r],
	  440SP, 440SPe, 460EX, 460GT and 460SX.

config EDAC_AMD8131
	tristate "AMD8131 HyperTransport PCI-X Tunnel"
	depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
	help
	  Support for error detection and correction on the
	  AMD8131 HyperTransport PCI-X Tunnel chip.
	  Note, add more Kconfig dependency if it's adopted
	  on some machine other than Maple.

config EDAC_AMD8111
	tristate "AMD8111 HyperTransport I/O Hub"
	depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
	help
	  Support for error detection and correction on the
	  AMD8111 HyperTransport I/O Hub chip.
	  Note, add more Kconfig dependency if it's adopted
	  on some machine other than Maple.

config EDAC_CPC925
	tristate "IBM CPC925 Memory Controller (PPC970FX)"
	depends on EDAC_MM_EDAC && PPC64
	help
	  Support for error detection and correction on the
	  IBM CPC925 Bridge and Memory Controller, which is
	  a companion chip to the PowerPC 970 family of
	  processors.

config EDAC_TILE
	tristate "Tilera Memory Controller"
	depends on EDAC_MM_EDAC && TILE
	default y
	help
	  Support for error detection and correction on the
	  Tilera memory controller.

config EDAC_HIGHBANK_MC
	tristate "Highbank Memory Controller"
	depends on EDAC_MM_EDAC && ARCH_HIGHBANK
	help
	  Support for error detection and correction on the
	  Calxeda Highbank memory controller.

config EDAC_HIGHBANK_L2
	tristate "Highbank L2 Cache"
	depends on EDAC_MM_EDAC && ARCH_HIGHBANK
	help
	  Support for error detection and correction on the
	  Calxeda Highbank memory controller.

config EDAC_OCTEON_PC
	tristate "Cavium Octeon Primary Caches"
	depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
	help
	  Support for error detection and correction on the primary caches of
	  the cnMIPS cores of Cavium Octeon family SOCs.

config EDAC_OCTEON_L2C
	tristate "Cavium Octeon Secondary Caches (L2C)"
	depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
	help
	  Support for error detection and correction on the
	  Cavium Octeon family of SOCs.

config EDAC_OCTEON_LMC
	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
	depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
	help
	  Support for error detection and correction on the
	  Cavium Octeon family of SOCs.

config EDAC_OCTEON_PCI
	tristate "Cavium Octeon PCI Controller"
	depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
	help
	  Support for error detection and correction on the
	  Cavium Octeon family of SOCs.

config EDAC_ALTERA
	bool "Altera SOCFPGA ECC"
	depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
	help
	  Support for error detection and correction on the
	  Altera SOCs. This must be selected for SDRAM ECC.
	  Note that the preloader must initialize the SDRAM
	  before loading the kernel.

config EDAC_ALTERA_L2C
	bool "Altera L2 Cache ECC"
	depends on EDAC_ALTERA=y && CACHE_L2X0
	help
	  Support for error detection and correction on the
	  Altera L2 cache Memory for Altera SoCs. This option
	  requires L2 cache.

config EDAC_ALTERA_OCRAM
	bool "Altera On-Chip RAM ECC"
	depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
	help
	  Support for error detection and correction on the
	  Altera On-Chip RAM Memory for Altera SoCs.

config EDAC_ALTERA_ETHERNET
	bool "Altera Ethernet FIFO ECC"
	depends on EDAC_ALTERA=y
	help
	  Support for error detection and correction on the
	  Altera Ethernet FIFO Memory for Altera SoCs.

config EDAC_ALTERA_NAND
	bool "Altera NAND FIFO ECC"
	depends on EDAC_ALTERA=y && MTD_NAND_DENALI
	help
	  Support for error detection and correction on the
	  Altera NAND FIFO Memory for Altera SoCs.

config EDAC_ALTERA_DMA
	bool "Altera DMA FIFO ECC"
	depends on EDAC_ALTERA=y && PL330_DMA=y
	help
	  Support for error detection and correction on the
	  Altera DMA FIFO Memory for Altera SoCs.

config EDAC_ALTERA_USB
	bool "Altera USB FIFO ECC"
	depends on EDAC_ALTERA=y && USB_DWC2
	help
	  Support for error detection and correction on the
	  Altera USB FIFO Memory for Altera SoCs.

config EDAC_ALTERA_QSPI
	bool "Altera QSPI FIFO ECC"
	depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
	help
	  Support for error detection and correction on the
	  Altera QSPI FIFO Memory for Altera SoCs.

config EDAC_ALTERA_SDMMC
	bool "Altera SDMMC FIFO ECC"
	depends on EDAC_ALTERA=y && MMC_DW
	help
	  Support for error detection and correction on the
	  Altera SDMMC FIFO Memory for Altera SoCs.

config EDAC_SYNOPSYS
	tristate "Synopsys DDR Memory Controller"
	depends on EDAC_MM_EDAC && ARCH_ZYNQ
	help
	  Support for error detection and correction on the Synopsys DDR
	  memory controller.

config EDAC_XGENE
	tristate "APM X-Gene SoC"
	depends on EDAC_MM_EDAC && (ARM64 || COMPILE_TEST)
	help
	  Support for error detection and correction on the
	  APM X-Gene family of SOCs.

endif # EDAC
Commit	Line	Data
da9bb1d2 AC	1	#
da9bb1d2 AC	2	# EDAC Kconfig
4577ca55	3	# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
da9bb1d2	4	# Licensed and distributed under the GPL
b01aec9b BP	5
	6	config EDAC_ATOMIC_SCRUB
	7	bool
da9bb1d2	8
54451663 BP	9	config EDAC_SUPPORT
	10	bool
	11
751cb5e5	12	menuconfig EDAC
e24aca67	13	bool "EDAC (Error Detection And Correction) reporting"
b01aec9b	14	depends on HAS_IOMEM && EDAC_SUPPORT
da9bb1d2 AC	15	help
	16	EDAC is designed to report errors in the core system.
	17	These are low-level errors that are reported in the CPU or
8cb2a398 DT	18	supporting chipset or other subsystems:
	19	memory errors, cache errors, PCI errors, thermal throttling, etc..
	20	If unsure, select 'Y'.
da9bb1d2	21
57c432b5 TS	22	If this code is reporting problems on your system, please
	23	see the EDAC project web pages for more information at:
	24
	25	<http://bluesmoke.sourceforge.net/>
	26
	27	and:
	28
	29	<http://buttersideup.com/edacwiki>
	30
	31	There is also a mailing list for the EDAC project, which can
	32	be found via the sourceforge page.
	33
751cb5e5	34	if EDAC
da9bb1d2	35
19974710 MCC	36	config EDAC_LEGACY_SYSFS
	37	bool "EDAC legacy sysfs"
	38	default y
	39	help
	40	Enable the compatibility sysfs nodes.
	41	Use 'Y' if your edac utilities aren't ported to work with the newer
	42	structures.
	43
da9bb1d2 AC	44	config EDAC_DEBUG
da9bb1d2 AC	45	bool "Debugging"
1c5bf781	46	select DEBUG_FS
da9bb1d2	47	help
37929874 BP	48	This turns on debugging information for the entire EDAC subsystem.
	49	You do so by inserting edac_module with "edac_debug_level=x." Valid
	50	levels are 0-4 (from low to high) and by default it is set to 2.
	51	Usually you should select 'N' here.
da9bb1d2	52
9cdeb404	53	config EDAC_DECODE_MCE
0d18b2e3	54	tristate "Decode MCEs in human-readable form (only on AMD for now)"
168eb34d	55	depends on CPU_SUP_AMD && X86_MCE_AMD
0d18b2e3 BP	56	default y
	57	---help---
	58	Enable this option if you want to decode Machine Check Exceptions
25985edc	59	occurring on your machine in human-readable form.
0d18b2e3 BP	60
	61	You should definitely say Y here in case you want to decode MCEs
	62	which occur really early upon boot, before the module infrastructure
	63	has been initialized.
	64
da9bb1d2 AC	65	config EDAC_MM_EDAC
da9bb1d2 AC	66	tristate "Main Memory EDAC (Error Detection And Correction) reporting"
76ac8275	67	select RAS
da9bb1d2 AC	68	help
	69	Some systems are able to detect and correct errors in main
	70	memory. EDAC can report statistics on memory error
	71	detection and correction (EDAC - or commonly referred to ECC
	72	errors). EDAC will also try to decode where these errors
	73	occurred so that a particular failing memory module can be
	74	replaced. If unsure, select 'Y'.
	75
77c5f5d2 MCC	76	config EDAC_GHES
	77	bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
	78	depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
	79	default y
	80	help
	81	Not all machines support hardware-driven error report. Some of those
	82	provide a BIOS-driven error report mechanism via ACPI, using the
	83	APEI/GHES driver. By enabling this option, the error reports provided
	84	by GHES are sent to userspace via the EDAC API.
	85
	86	When this option is enabled, it will disable the hardware-driven
	87	mechanisms, if a GHES BIOS is detected, entering into the
	88	"Firmware First" mode.
	89
	90	It should be noticed that keeping both GHES and a hardware-driven
	91	error mechanism won't work well, as BIOS will race with OS, while
	92	reading the error registers. So, if you want to not use "Firmware
	93	first" GHES error mechanism, you should disable GHES either at
	94	compilation time or by passing "ghes.disable=1" Kernel parameter
	95	at boot time.
	96
	97	In doubt, say 'Y'.
	98
7d6034d3	99	config EDAC_AMD64
f5b10c45 TP	100	tristate "AMD64 (Opteron, Athlon64)"
f5b10c45 TP	101	depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE
7d6034d3	102	help
027dbd6f	103	Support for error detection and correction of DRAM ECC errors on
f5b10c45	104	the AMD64 families (>= K8) of memory controllers.
7d6034d3 DT	105
7d6034d3 DT	106	config EDAC_AMD64_ERROR_INJECTION
9cdeb404	107	bool "Sysfs HW Error injection facilities"
7d6034d3 DT	108	depends on EDAC_AMD64
	109	help
	110	Recent Opterons (Family 10h and later) provide for Memory Error
	111	Injection into the ECC detection circuits. The amd64_edac module
	112	allows the operator/user to inject Uncorrectable and Correctable
	113	errors into DRAM.
	114
	115	When enabled, in each of the respective memory controller directories
	116	(/sys/devices/system/edac/mc/mcX), there are 3 input files:
	117
	118	- inject_section (0..3, 16-byte section of 64-byte cacheline),
	119	- inject_word (0..8, 16-bit word of 16-byte section),
	120	- inject_ecc_vector (hex ecc vector: select bits of inject word)
	121
	122	In addition, there are two control files, inject_read and inject_write,
	123	which trigger the DRAM ECC Read and Write respectively.
da9bb1d2 AC	124
	125	config EDAC_AMD76X
	126	tristate "AMD 76x (760, 762, 768)"
90cbc45b	127	depends on EDAC_MM_EDAC && PCI && X86_32
da9bb1d2 AC	128	help
	129	Support for error detection and correction on the AMD 76x
	130	series of chipsets used with the Athlon processor.
	131
	132	config EDAC_E7XXX
	133	tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
39f1d8d3	134	depends on EDAC_MM_EDAC && PCI && X86_32
da9bb1d2 AC	135	help
	136	Support for error detection and correction on the Intel
	137	E7205, E7500, E7501 and E7505 server chipsets.
	138
	139	config EDAC_E752X
5135b797	140	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
40b31360	141	depends on EDAC_MM_EDAC && PCI && X86
da9bb1d2 AC	142	help
	143	Support for error detection and correction on the Intel
	144	E7520, E7525, E7320 server chipsets.
	145
5a2c675c TS	146	config EDAC_I82443BXGX
	147	tristate "Intel 82443BX/GX (440BX/GX)"
	148	depends on EDAC_MM_EDAC && PCI && X86_32
28f96eea	149	depends on BROKEN
5a2c675c TS	150	help
	151	Support for error detection and correction on the Intel
	152	82443BX/GX memory controllers (440BX/GX chipsets).
	153
da9bb1d2 AC	154	config EDAC_I82875P
da9bb1d2 AC	155	tristate "Intel 82875p (D82875P, E7210)"
39f1d8d3	156	depends on EDAC_MM_EDAC && PCI && X86_32
da9bb1d2 AC	157	help
	158	Support for error detection and correction on the Intel
	159	DP82785P and E7210 server chipsets.
	160
420390f0 RD	161	config EDAC_I82975X
	162	tristate "Intel 82975x (D82975x)"
	163	depends on EDAC_MM_EDAC && PCI && X86
	164	help
	165	Support for error detection and correction on the Intel
	166	DP82975x server chipsets.
	167
535c6a53 JU	168	config EDAC_I3000
535c6a53 JU	169	tristate "Intel 3000/3010"
f5c0454c	170	depends on EDAC_MM_EDAC && PCI && X86
535c6a53 JU	171	help
	172	Support for error detection and correction on the Intel
	173	3000 and 3010 server chipsets.
	174
dd8ef1db JU	175	config EDAC_I3200
dd8ef1db JU	176	tristate "Intel 3200"
053417a5	177	depends on EDAC_MM_EDAC && PCI && X86
dd8ef1db JU	178	help
	179	Support for error detection and correction on the Intel
	180	3200 and 3210 server chipsets.
	181
7ee40b89 JB	182	config EDAC_IE31200
	183	tristate "Intel e312xx"
	184	depends on EDAC_MM_EDAC && PCI && X86
	185	help
	186	Support for error detection and correction on the Intel
	187	E3-1200 based DRAM controllers.
	188
df8bc08c HM	189	config EDAC_X38
	190	tristate "Intel X38"
	191	depends on EDAC_MM_EDAC && PCI && X86
	192	help
	193	Support for error detection and correction on the Intel
	194	X38 server chipsets.
	195
920c8df6 MCC	196	config EDAC_I5400
	197	tristate "Intel 5400 (Seaburg) chipsets"
	198	depends on EDAC_MM_EDAC && PCI && X86
	199	help
	200	Support for error detection and correction the Intel
	201	i5400 MCH chipset (Seaburg).
	202
a0c36a1f MCC	203	config EDAC_I7CORE
a0c36a1f MCC	204	tristate "Intel i7 Core (Nehalem) processors"
168eb34d	205	depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
a0c36a1f MCC	206	help
a0c36a1f MCC	207	Support for error detection and correction the Intel
696e409d MCC	208	i7 Core (Nehalem) Integrated Memory Controller that exists on
	209	newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
	210	and Xeon 55xx processors.
a0c36a1f	211
da9bb1d2 AC	212	config EDAC_I82860
da9bb1d2 AC	213	tristate "Intel 82860"
39f1d8d3	214	depends on EDAC_MM_EDAC && PCI && X86_32
da9bb1d2 AC	215	help
	216	Support for error detection and correction on the Intel
	217	82860 chipset.
	218
	219	config EDAC_R82600
	220	tristate "Radisys 82600 embedded chipset"
39f1d8d3	221	depends on EDAC_MM_EDAC && PCI && X86_32
da9bb1d2 AC	222	help
	223	Support for error detection and correction on the Radisys
	224	82600 embedded chipset.
	225
eb60705a EW	226	config EDAC_I5000
	227	tristate "Intel Greencreek/Blackford chipset"
	228	depends on EDAC_MM_EDAC && X86 && PCI
	229	help
	230	Support for error detection and correction the Intel
	231	Greekcreek/Blackford chipsets.
	232
8f421c59 AJ	233	config EDAC_I5100
	234	tristate "Intel San Clemente MCH"
	235	depends on EDAC_MM_EDAC && X86 && PCI
	236	help
	237	Support for error detection and correction the Intel
	238	San Clemente MCH.
	239
fcaf780b MCC	240	config EDAC_I7300
	241	tristate "Intel Clarksboro MCH"
	242	depends on EDAC_MM_EDAC && X86 && PCI
	243	help
	244	Support for error detection and correction the Intel
	245	Clarksboro MCH (Intel 7300 chipset).
	246
3d78c9af	247	config EDAC_SBRIDGE
50d1bb93	248	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
22a5c27b	249	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
053417a5	250	depends on PCI_MMCONFIG
3d78c9af MCC	251	help
3d78c9af MCC	252	Support for error detection and correction the Intel
50d1bb93	253	Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
3d78c9af	254
4ec656bd TL	255	config EDAC_SKX
	256	tristate "Intel Skylake server Integrated MC"
	257	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
	258	depends on PCI_MMCONFIG
	259	help
	260	Support for error detection and correction the Intel
	261	Skylake server Integrated Memory Controllers.
	262
5c71ad17 TL	263	config EDAC_PND2
	264	tristate "Intel Pondicherry2"
	265	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
	266	help
	267	Support for error detection and correction on the Intel
	268	Pondicherry2 Integrated Memory Controller. This SoC IP is
	269	first used on the Apollo Lake platform and Denverton
	270	micro-server but may appear on others in the future.
	271
a9a753d5	272	config EDAC_MPC85XX
b4846251	273	tristate "Freescale MPC83xx / MPC85xx"
74210267	274	depends on EDAC_MM_EDAC && FSL_SOC
a9a753d5 DJ	275	help
a9a753d5 DJ	276	Support for error detection and correction on the Freescale
74210267	277	MPC8349, MPC8560, MPC8540, MPC8548, T4240
a9a753d5	278
eeb3d68b YS	279	config EDAC_LAYERSCAPE
	280	tristate "Freescale Layerscape DDR"
	281	depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
	282	help
	283	Support for error detection and correction on Freescale memory
	284	controllers on Layerscape SoCs.
	285
4f4aeeab DJ	286	config EDAC_MV64X60
	287	tristate "Marvell MV64x60"
	288	depends on EDAC_MM_EDAC && MV64X60
	289	help
	290	Support for error detection and correction on the Marvell
	291	MV64360 and MV64460 chipsets.
	292
7d8536fb EM	293	config EDAC_PASEMI
	294	tristate "PA Semi PWRficient"
	295	depends on EDAC_MM_EDAC && PCI
ddcc3050	296	depends on PPC_PASEMI
7d8536fb EM	297	help
	298	Support for error detection and correction on PA Semi
	299	PWRficient.
	300
48764e41 BH	301	config EDAC_CELL
48764e41 BH	302	tristate "Cell Broadband Engine memory controller"
def434c2	303	depends on EDAC_MM_EDAC && PPC_CELL_COMMON
48764e41 BH	304	help
	305	Support for error detection and correction on the
	306	Cell Broadband Engine internal memory controller
	307	on platform without a hypervisor
7d8536fb	308
dba7a77c GE	309	config EDAC_PPC4XX
	310	tristate "PPC4xx IBM DDR2 Memory Controller"
	311	depends on EDAC_MM_EDAC && 4xx
	312	help
	313	This enables support for EDAC on the ECC memory used
	314	with the IBM DDR2 memory controller found in various
	315	PowerPC 4xx embedded processors such as the 405EX[r],
	316	440SP, 440SPe, 460EX, 460GT and 460SX.
	317
e8765584 HC	318	config EDAC_AMD8131
e8765584 HC	319	tristate "AMD8131 HyperTransport PCI-X Tunnel"
715fe7af	320	depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
e8765584 HC	321	help
	322	Support for error detection and correction on the
	323	AMD8131 HyperTransport PCI-X Tunnel chip.
715fe7af HC	324	Note, add more Kconfig dependency if it's adopted
715fe7af HC	325	on some machine other than Maple.
e8765584	326
58b4ce6f HC	327	config EDAC_AMD8111
58b4ce6f HC	328	tristate "AMD8111 HyperTransport I/O Hub"
715fe7af	329	depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
58b4ce6f HC	330	help
	331	Support for error detection and correction on the
	332	AMD8111 HyperTransport I/O Hub chip.
715fe7af HC	333	Note, add more Kconfig dependency if it's adopted
715fe7af HC	334	on some machine other than Maple.
58b4ce6f	335
2a9036af HC	336	config EDAC_CPC925
	337	tristate "IBM CPC925 Memory Controller (PPC970FX)"
	338	depends on EDAC_MM_EDAC && PPC64
	339	help
	340	Support for error detection and correction on the
	341	IBM CPC925 Bridge and Memory Controller, which is
	342	a companion chip to the PowerPC 970 family of
	343	processors.
	344
5c770755 CM	345	config EDAC_TILE
	346	tristate "Tilera Memory Controller"
	347	depends on EDAC_MM_EDAC && TILE
	348	default y
	349	help
	350	Support for error detection and correction on the
	351	Tilera memory controller.
	352
a1b01edb RH	353	config EDAC_HIGHBANK_MC
	354	tristate "Highbank Memory Controller"
	355	depends on EDAC_MM_EDAC && ARCH_HIGHBANK
	356	help
	357	Support for error detection and correction on the
	358	Calxeda Highbank memory controller.
	359
69154d06 RH	360	config EDAC_HIGHBANK_L2
	361	tristate "Highbank L2 Cache"
	362	depends on EDAC_MM_EDAC && ARCH_HIGHBANK
	363	help
	364	Support for error detection and correction on the
	365	Calxeda Highbank memory controller.
	366
f65aad41 RB	367	config EDAC_OCTEON_PC
	368	tristate "Cavium Octeon Primary Caches"
	369	depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
	370	help
	371	Support for error detection and correction on the primary caches of
	372	the cnMIPS cores of Cavium Octeon family SOCs.
	373
	374	config EDAC_OCTEON_L2C
	375	tristate "Cavium Octeon Secondary Caches (L2C)"
9ddebc46	376	depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
f65aad41 RB	377	help
	378	Support for error detection and correction on the
	379	Cavium Octeon family of SOCs.
	380
	381	config EDAC_OCTEON_LMC
	382	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
9ddebc46	383	depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
f65aad41 RB	384	help
	385	Support for error detection and correction on the
	386	Cavium Octeon family of SOCs.
	387
	388	config EDAC_OCTEON_PCI
	389	tristate "Cavium Octeon PCI Controller"
9ddebc46	390	depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
f65aad41 RB	391	help
	392	Support for error detection and correction on the
	393	Cavium Octeon family of SOCs.
	394
c3eea194 TT	395	config EDAC_ALTERA
c3eea194 TT	396	bool "Altera SOCFPGA ECC"
7e52a036	397	depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
71bcada8 TT	398	help
71bcada8 TT	399	Support for error detection and correction on the
c3eea194 TT	400	Altera SOCs. This must be selected for SDRAM ECC.
	401	Note that the preloader must initialize the SDRAM
	402	before loading the kernel.
	403
	404	config EDAC_ALTERA_L2C
	405	bool "Altera L2 Cache ECC"
3a8f21f1	406	depends on EDAC_ALTERA=y && CACHE_L2X0
c3eea194 TT	407	help
	408	Support for error detection and correction on the
	409	Altera L2 cache Memory for Altera SoCs. This option
3a8f21f1	410	requires L2 cache.
c3eea194 TT	411
	412	config EDAC_ALTERA_OCRAM
	413	bool "Altera On-Chip RAM ECC"
	414	depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
	415	help
	416	Support for error detection and correction on the
	417	Altera On-Chip RAM Memory for Altera SoCs.
71bcada8	418
ab8c1e0f TT	419	config EDAC_ALTERA_ETHERNET
	420	bool "Altera Ethernet FIFO ECC"
	421	depends on EDAC_ALTERA=y
	422	help
	423	Support for error detection and correction on the
	424	Altera Ethernet FIFO Memory for Altera SoCs.
	425
c6882fb2 TT	426	config EDAC_ALTERA_NAND
	427	bool "Altera NAND FIFO ECC"
	428	depends on EDAC_ALTERA=y && MTD_NAND_DENALI
	429	help
	430	Support for error detection and correction on the
	431	Altera NAND FIFO Memory for Altera SoCs.
	432
e8263793 TT	433	config EDAC_ALTERA_DMA
	434	bool "Altera DMA FIFO ECC"
	435	depends on EDAC_ALTERA=y && PL330_DMA=y
	436	help
	437	Support for error detection and correction on the
	438	Altera DMA FIFO Memory for Altera SoCs.
	439
c609581d TT	440	config EDAC_ALTERA_USB
	441	bool "Altera USB FIFO ECC"
	442	depends on EDAC_ALTERA=y && USB_DWC2
	443	help
	444	Support for error detection and correction on the
	445	Altera USB FIFO Memory for Altera SoCs.
	446
485fe9e2 TT	447	config EDAC_ALTERA_QSPI
	448	bool "Altera QSPI FIFO ECC"
	449	depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
	450	help
	451	Support for error detection and correction on the
	452	Altera QSPI FIFO Memory for Altera SoCs.
	453
91104984 TT	454	config EDAC_ALTERA_SDMMC
	455	bool "Altera SDMMC FIFO ECC"
	456	depends on EDAC_ALTERA=y && MMC_DW
	457	help
	458	Support for error detection and correction on the
	459	Altera SDMMC FIFO Memory for Altera SoCs.
	460
ae9b56e3 PCK	461	config EDAC_SYNOPSYS
	462	tristate "Synopsys DDR Memory Controller"
	463	depends on EDAC_MM_EDAC && ARCH_ZYNQ
	464	help
	465	Support for error detection and correction on the Synopsys DDR
	466	memory controller.
	467
0d442930 LH	468	config EDAC_XGENE
	469	tristate "APM X-Gene SoC"
	470	depends on EDAC_MM_EDAC && (ARM64 \|\| COMPILE_TEST)
	471	help
	472	Support for error detection and correction on the
	473	APM X-Gene family of SOCs.
	474
751cb5e5	475	endif # EDAC