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da9bb1d2 AC |
1 | # |
2 | # EDAC Kconfig | |
4577ca55 | 3 | # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com |
da9bb1d2 AC |
4 | # Licensed and distributed under the GPL |
5 | # | |
da9bb1d2 | 6 | |
751cb5e5 | 7 | menuconfig EDAC |
e24aca67 | 8 | bool "EDAC (Error Detection And Correction) reporting" |
e25df120 | 9 | depends on HAS_IOMEM |
4c6a1c13 | 10 | depends on X86 || PPC |
da9bb1d2 AC |
11 | help |
12 | EDAC is designed to report errors in the core system. | |
13 | These are low-level errors that are reported in the CPU or | |
8cb2a398 DT |
14 | supporting chipset or other subsystems: |
15 | memory errors, cache errors, PCI errors, thermal throttling, etc.. | |
16 | If unsure, select 'Y'. | |
da9bb1d2 | 17 | |
57c432b5 TS |
18 | If this code is reporting problems on your system, please |
19 | see the EDAC project web pages for more information at: | |
20 | ||
21 | <http://bluesmoke.sourceforge.net/> | |
22 | ||
23 | and: | |
24 | ||
25 | <http://buttersideup.com/edacwiki> | |
26 | ||
27 | There is also a mailing list for the EDAC project, which can | |
28 | be found via the sourceforge page. | |
29 | ||
751cb5e5 | 30 | if EDAC |
da9bb1d2 AC |
31 | |
32 | comment "Reporting subsystems" | |
da9bb1d2 AC |
33 | |
34 | config EDAC_DEBUG | |
35 | bool "Debugging" | |
da9bb1d2 AC |
36 | help |
37 | This turns on debugging information for the entire EDAC | |
38 | sub-system. You can insert module with "debug_level=x", current | |
39 | there're four debug levels (x=0,1,2,3 from low to high). | |
40 | Usually you should select 'N'. | |
41 | ||
cc18e3cd HM |
42 | config EDAC_DEBUG_VERBOSE |
43 | bool "More verbose debugging" | |
44 | depends on EDAC_DEBUG | |
45 | help | |
46 | This option makes debugging information more verbose. | |
47 | Source file name and line number where debugging message | |
48 | printed will be added to debugging message. | |
49 | ||
0d18b2e3 BP |
50 | config EDAC_DECODE_MCE |
51 | tristate "Decode MCEs in human-readable form (only on AMD for now)" | |
52 | depends on CPU_SUP_AMD && X86_MCE | |
53 | default y | |
54 | ---help--- | |
55 | Enable this option if you want to decode Machine Check Exceptions | |
56 | occuring on your machine in human-readable form. | |
57 | ||
58 | You should definitely say Y here in case you want to decode MCEs | |
59 | which occur really early upon boot, before the module infrastructure | |
60 | has been initialized. | |
61 | ||
da9bb1d2 AC |
62 | config EDAC_MM_EDAC |
63 | tristate "Main Memory EDAC (Error Detection And Correction) reporting" | |
da9bb1d2 AC |
64 | help |
65 | Some systems are able to detect and correct errors in main | |
66 | memory. EDAC can report statistics on memory error | |
67 | detection and correction (EDAC - or commonly referred to ECC | |
68 | errors). EDAC will also try to decode where these errors | |
69 | occurred so that a particular failing memory module can be | |
70 | replaced. If unsure, select 'Y'. | |
71 | ||
7d6034d3 DT |
72 | config EDAC_AMD64 |
73 | tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h" | |
0d18b2e3 | 74 | depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE |
7d6034d3 | 75 | help |
3d373290 BP |
76 | Support for error detection and correction on the AMD 64 |
77 | Families of Memory Controllers (K8, F10h and F11h) | |
7d6034d3 DT |
78 | |
79 | config EDAC_AMD64_ERROR_INJECTION | |
80 | bool "Sysfs Error Injection facilities" | |
81 | depends on EDAC_AMD64 | |
82 | help | |
83 | Recent Opterons (Family 10h and later) provide for Memory Error | |
84 | Injection into the ECC detection circuits. The amd64_edac module | |
85 | allows the operator/user to inject Uncorrectable and Correctable | |
86 | errors into DRAM. | |
87 | ||
88 | When enabled, in each of the respective memory controller directories | |
89 | (/sys/devices/system/edac/mc/mcX), there are 3 input files: | |
90 | ||
91 | - inject_section (0..3, 16-byte section of 64-byte cacheline), | |
92 | - inject_word (0..8, 16-bit word of 16-byte section), | |
93 | - inject_ecc_vector (hex ecc vector: select bits of inject word) | |
94 | ||
95 | In addition, there are two control files, inject_read and inject_write, | |
96 | which trigger the DRAM ECC Read and Write respectively. | |
da9bb1d2 AC |
97 | |
98 | config EDAC_AMD76X | |
99 | tristate "AMD 76x (760, 762, 768)" | |
90cbc45b | 100 | depends on EDAC_MM_EDAC && PCI && X86_32 |
da9bb1d2 AC |
101 | help |
102 | Support for error detection and correction on the AMD 76x | |
103 | series of chipsets used with the Athlon processor. | |
104 | ||
105 | config EDAC_E7XXX | |
106 | tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" | |
39f1d8d3 | 107 | depends on EDAC_MM_EDAC && PCI && X86_32 |
da9bb1d2 AC |
108 | help |
109 | Support for error detection and correction on the Intel | |
110 | E7205, E7500, E7501 and E7505 server chipsets. | |
111 | ||
112 | config EDAC_E752X | |
5135b797 | 113 | tristate "Intel e752x (e7520, e7525, e7320) and 3100" |
da960a6a | 114 | depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG |
da9bb1d2 AC |
115 | help |
116 | Support for error detection and correction on the Intel | |
117 | E7520, E7525, E7320 server chipsets. | |
118 | ||
5a2c675c TS |
119 | config EDAC_I82443BXGX |
120 | tristate "Intel 82443BX/GX (440BX/GX)" | |
121 | depends on EDAC_MM_EDAC && PCI && X86_32 | |
28f96eea | 122 | depends on BROKEN |
5a2c675c TS |
123 | help |
124 | Support for error detection and correction on the Intel | |
125 | 82443BX/GX memory controllers (440BX/GX chipsets). | |
126 | ||
da9bb1d2 AC |
127 | config EDAC_I82875P |
128 | tristate "Intel 82875p (D82875P, E7210)" | |
39f1d8d3 | 129 | depends on EDAC_MM_EDAC && PCI && X86_32 |
da9bb1d2 AC |
130 | help |
131 | Support for error detection and correction on the Intel | |
132 | DP82785P and E7210 server chipsets. | |
133 | ||
420390f0 RD |
134 | config EDAC_I82975X |
135 | tristate "Intel 82975x (D82975x)" | |
136 | depends on EDAC_MM_EDAC && PCI && X86 | |
137 | help | |
138 | Support for error detection and correction on the Intel | |
139 | DP82975x server chipsets. | |
140 | ||
535c6a53 JU |
141 | config EDAC_I3000 |
142 | tristate "Intel 3000/3010" | |
f5c0454c | 143 | depends on EDAC_MM_EDAC && PCI && X86 |
535c6a53 JU |
144 | help |
145 | Support for error detection and correction on the Intel | |
146 | 3000 and 3010 server chipsets. | |
147 | ||
dd8ef1db JU |
148 | config EDAC_I3200 |
149 | tristate "Intel 3200" | |
150 | depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL | |
151 | help | |
152 | Support for error detection and correction on the Intel | |
153 | 3200 and 3210 server chipsets. | |
154 | ||
df8bc08c HM |
155 | config EDAC_X38 |
156 | tristate "Intel X38" | |
157 | depends on EDAC_MM_EDAC && PCI && X86 | |
158 | help | |
159 | Support for error detection and correction on the Intel | |
160 | X38 server chipsets. | |
161 | ||
920c8df6 MCC |
162 | config EDAC_I5400 |
163 | tristate "Intel 5400 (Seaburg) chipsets" | |
164 | depends on EDAC_MM_EDAC && PCI && X86 | |
165 | help | |
166 | Support for error detection and correction the Intel | |
167 | i5400 MCH chipset (Seaburg). | |
168 | ||
da9bb1d2 AC |
169 | config EDAC_I82860 |
170 | tristate "Intel 82860" | |
39f1d8d3 | 171 | depends on EDAC_MM_EDAC && PCI && X86_32 |
da9bb1d2 AC |
172 | help |
173 | Support for error detection and correction on the Intel | |
174 | 82860 chipset. | |
175 | ||
176 | config EDAC_R82600 | |
177 | tristate "Radisys 82600 embedded chipset" | |
39f1d8d3 | 178 | depends on EDAC_MM_EDAC && PCI && X86_32 |
da9bb1d2 AC |
179 | help |
180 | Support for error detection and correction on the Radisys | |
181 | 82600 embedded chipset. | |
182 | ||
eb60705a EW |
183 | config EDAC_I5000 |
184 | tristate "Intel Greencreek/Blackford chipset" | |
185 | depends on EDAC_MM_EDAC && X86 && PCI | |
186 | help | |
187 | Support for error detection and correction the Intel | |
188 | Greekcreek/Blackford chipsets. | |
189 | ||
8f421c59 AJ |
190 | config EDAC_I5100 |
191 | tristate "Intel San Clemente MCH" | |
192 | depends on EDAC_MM_EDAC && X86 && PCI | |
193 | help | |
194 | Support for error detection and correction the Intel | |
195 | San Clemente MCH. | |
196 | ||
a9a753d5 | 197 | config EDAC_MPC85XX |
b4846251 IS |
198 | tristate "Freescale MPC83xx / MPC85xx" |
199 | depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || MPC85xx) | |
a9a753d5 DJ |
200 | help |
201 | Support for error detection and correction on the Freescale | |
b4846251 | 202 | MPC8349, MPC8560, MPC8540, MPC8548 |
a9a753d5 | 203 | |
4f4aeeab DJ |
204 | config EDAC_MV64X60 |
205 | tristate "Marvell MV64x60" | |
206 | depends on EDAC_MM_EDAC && MV64X60 | |
207 | help | |
208 | Support for error detection and correction on the Marvell | |
209 | MV64360 and MV64460 chipsets. | |
210 | ||
7d8536fb EM |
211 | config EDAC_PASEMI |
212 | tristate "PA Semi PWRficient" | |
213 | depends on EDAC_MM_EDAC && PCI | |
ddcc3050 | 214 | depends on PPC_PASEMI |
7d8536fb EM |
215 | help |
216 | Support for error detection and correction on PA Semi | |
217 | PWRficient. | |
218 | ||
48764e41 BH |
219 | config EDAC_CELL |
220 | tristate "Cell Broadband Engine memory controller" | |
def434c2 | 221 | depends on EDAC_MM_EDAC && PPC_CELL_COMMON |
48764e41 BH |
222 | help |
223 | Support for error detection and correction on the | |
224 | Cell Broadband Engine internal memory controller | |
225 | on platform without a hypervisor | |
7d8536fb | 226 | |
dba7a77c GE |
227 | config EDAC_PPC4XX |
228 | tristate "PPC4xx IBM DDR2 Memory Controller" | |
229 | depends on EDAC_MM_EDAC && 4xx | |
230 | help | |
231 | This enables support for EDAC on the ECC memory used | |
232 | with the IBM DDR2 memory controller found in various | |
233 | PowerPC 4xx embedded processors such as the 405EX[r], | |
234 | 440SP, 440SPe, 460EX, 460GT and 460SX. | |
235 | ||
e8765584 HC |
236 | config EDAC_AMD8131 |
237 | tristate "AMD8131 HyperTransport PCI-X Tunnel" | |
715fe7af | 238 | depends on EDAC_MM_EDAC && PCI && PPC_MAPLE |
e8765584 HC |
239 | help |
240 | Support for error detection and correction on the | |
241 | AMD8131 HyperTransport PCI-X Tunnel chip. | |
715fe7af HC |
242 | Note, add more Kconfig dependency if it's adopted |
243 | on some machine other than Maple. | |
e8765584 | 244 | |
58b4ce6f HC |
245 | config EDAC_AMD8111 |
246 | tristate "AMD8111 HyperTransport I/O Hub" | |
715fe7af | 247 | depends on EDAC_MM_EDAC && PCI && PPC_MAPLE |
58b4ce6f HC |
248 | help |
249 | Support for error detection and correction on the | |
250 | AMD8111 HyperTransport I/O Hub chip. | |
715fe7af HC |
251 | Note, add more Kconfig dependency if it's adopted |
252 | on some machine other than Maple. | |
58b4ce6f | 253 | |
2a9036af HC |
254 | config EDAC_CPC925 |
255 | tristate "IBM CPC925 Memory Controller (PPC970FX)" | |
256 | depends on EDAC_MM_EDAC && PPC64 | |
257 | help | |
258 | Support for error detection and correction on the | |
259 | IBM CPC925 Bridge and Memory Controller, which is | |
260 | a companion chip to the PowerPC 970 family of | |
261 | processors. | |
262 | ||
751cb5e5 | 263 | endif # EDAC |