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71bcada8 | 1 | /* |
c3eea194 | 2 | * Copyright Altera Corporation (C) 2014-2016. All rights reserved. |
71bcada8 TT |
3 | * Copyright 2011-2012 Calxeda, Inc. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | * | |
17 | * Adapted from the highbank_mc_edac driver. | |
18 | */ | |
19 | ||
c3eea194 | 20 | #include <asm/cacheflush.h> |
71bcada8 | 21 | #include <linux/ctype.h> |
1166fde9 | 22 | #include <linux/delay.h> |
71bcada8 | 23 | #include <linux/edac.h> |
c3eea194 | 24 | #include <linux/genalloc.h> |
71bcada8 | 25 | #include <linux/interrupt.h> |
13ab8448 | 26 | #include <linux/irqchip/chained_irq.h> |
71bcada8 TT |
27 | #include <linux/kernel.h> |
28 | #include <linux/mfd/syscon.h> | |
588cb03e | 29 | #include <linux/of_address.h> |
13ab8448 | 30 | #include <linux/of_irq.h> |
71bcada8 TT |
31 | #include <linux/of_platform.h> |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/regmap.h> | |
34 | #include <linux/types.h> | |
35 | #include <linux/uaccess.h> | |
36 | ||
143f4a5a | 37 | #include "altera_edac.h" |
71bcada8 TT |
38 | #include "edac_module.h" |
39 | ||
40 | #define EDAC_MOD_STR "altera_edac" | |
41 | #define EDAC_VERSION "1" | |
c3eea194 | 42 | #define EDAC_DEVICE "Altera" |
71bcada8 | 43 | |
143f4a5a TT |
44 | static const struct altr_sdram_prv_data c5_data = { |
45 | .ecc_ctrl_offset = CV_CTLCFG_OFST, | |
46 | .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, | |
47 | .ecc_stat_offset = CV_DRAMSTS_OFST, | |
48 | .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, | |
49 | .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, | |
50 | .ecc_saddr_offset = CV_ERRADDR_OFST, | |
73bcc942 | 51 | .ecc_daddr_offset = CV_ERRADDR_OFST, |
143f4a5a TT |
52 | .ecc_cecnt_offset = CV_SBECOUNT_OFST, |
53 | .ecc_uecnt_offset = CV_DBECOUNT_OFST, | |
54 | .ecc_irq_en_offset = CV_DRAMINTR_OFST, | |
55 | .ecc_irq_en_mask = CV_DRAMINTR_INTREN, | |
56 | .ecc_irq_clr_offset = CV_DRAMINTR_OFST, | |
57 | .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), | |
58 | .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, | |
59 | .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, | |
143f4a5a TT |
60 | .ce_ue_trgr_offset = CV_CTLCFG_OFST, |
61 | .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, | |
62 | .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, | |
71bcada8 TT |
63 | }; |
64 | ||
73bcc942 TT |
65 | static const struct altr_sdram_prv_data a10_data = { |
66 | .ecc_ctrl_offset = A10_ECCCTRL1_OFST, | |
67 | .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, | |
68 | .ecc_stat_offset = A10_INTSTAT_OFST, | |
69 | .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, | |
70 | .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, | |
71 | .ecc_saddr_offset = A10_SERRADDR_OFST, | |
72 | .ecc_daddr_offset = A10_DERRADDR_OFST, | |
73 | .ecc_irq_en_offset = A10_ERRINTEN_OFST, | |
74 | .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, | |
75 | .ecc_irq_clr_offset = A10_INTSTAT_OFST, | |
76 | .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), | |
77 | .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, | |
78 | .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, | |
73bcc942 TT |
79 | .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, |
80 | .ce_set_mask = A10_DIAGINT_TSERRA_MASK, | |
81 | .ue_set_mask = A10_DIAGINT_TDERRA_MASK, | |
73bcc942 TT |
82 | }; |
83 | ||
c3eea194 TT |
84 | /*********************** EDAC Memory Controller Functions ****************/ |
85 | ||
86 | /* The SDRAM controller uses the EDAC Memory Controller framework. */ | |
87 | ||
71bcada8 TT |
88 | static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) |
89 | { | |
90 | struct mem_ctl_info *mci = dev_id; | |
91 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
143f4a5a | 92 | const struct altr_sdram_prv_data *priv = drvdata->data; |
73bcc942 | 93 | u32 status, err_count = 1, err_addr; |
71bcada8 | 94 | |
143f4a5a | 95 | regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); |
71bcada8 | 96 | |
143f4a5a | 97 | if (status & priv->ecc_stat_ue_mask) { |
73bcc942 TT |
98 | regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, |
99 | &err_addr); | |
100 | if (priv->ecc_uecnt_offset) | |
101 | regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, | |
102 | &err_count); | |
71bcada8 TT |
103 | panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", |
104 | err_count, err_addr); | |
105 | } | |
143f4a5a | 106 | if (status & priv->ecc_stat_ce_mask) { |
73bcc942 TT |
107 | regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, |
108 | &err_addr); | |
109 | if (priv->ecc_uecnt_offset) | |
110 | regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, | |
111 | &err_count); | |
71bcada8 TT |
112 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, |
113 | err_addr >> PAGE_SHIFT, | |
114 | err_addr & ~PAGE_MASK, 0, | |
115 | 0, 0, -1, mci->ctl_name, ""); | |
73bcc942 TT |
116 | /* Clear IRQ to resume */ |
117 | regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, | |
118 | priv->ecc_irq_clr_mask); | |
71bcada8 | 119 | |
73bcc942 TT |
120 | return IRQ_HANDLED; |
121 | } | |
122 | return IRQ_NONE; | |
71bcada8 TT |
123 | } |
124 | ||
71bcada8 TT |
125 | static ssize_t altr_sdr_mc_err_inject_write(struct file *file, |
126 | const char __user *data, | |
127 | size_t count, loff_t *ppos) | |
128 | { | |
129 | struct mem_ctl_info *mci = file->private_data; | |
130 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
143f4a5a | 131 | const struct altr_sdram_prv_data *priv = drvdata->data; |
71bcada8 TT |
132 | u32 *ptemp; |
133 | dma_addr_t dma_handle; | |
134 | u32 reg, read_reg; | |
135 | ||
136 | ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); | |
137 | if (!ptemp) { | |
138 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
139 | edac_printk(KERN_ERR, EDAC_MC, | |
140 | "Inject: Buffer Allocation error\n"); | |
141 | return -ENOMEM; | |
142 | } | |
143 | ||
143f4a5a TT |
144 | regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
145 | &read_reg); | |
146 | read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); | |
71bcada8 TT |
147 | |
148 | /* Error are injected by writing a word while the SBE or DBE | |
149 | * bit in the CTLCFG register is set. Reading the word will | |
150 | * trigger the SBE or DBE error and the corresponding IRQ. | |
151 | */ | |
152 | if (count == 3) { | |
153 | edac_printk(KERN_ALERT, EDAC_MC, | |
154 | "Inject Double bit error\n"); | |
90e493d7 | 155 | local_irq_disable(); |
143f4a5a TT |
156 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
157 | (read_reg | priv->ue_set_mask)); | |
90e493d7 | 158 | local_irq_enable(); |
71bcada8 TT |
159 | } else { |
160 | edac_printk(KERN_ALERT, EDAC_MC, | |
161 | "Inject Single bit error\n"); | |
90e493d7 | 162 | local_irq_disable(); |
143f4a5a TT |
163 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
164 | (read_reg | priv->ce_set_mask)); | |
90e493d7 | 165 | local_irq_enable(); |
71bcada8 TT |
166 | } |
167 | ||
168 | ptemp[0] = 0x5A5A5A5A; | |
169 | ptemp[1] = 0xA5A5A5A5; | |
170 | ||
171 | /* Clear the error injection bits */ | |
143f4a5a | 172 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); |
71bcada8 TT |
173 | /* Ensure it has been written out */ |
174 | wmb(); | |
175 | ||
176 | /* | |
177 | * To trigger the error, we need to read the data back | |
178 | * (the data was written with errors above). | |
179 | * The ACCESS_ONCE macros and printk are used to prevent the | |
180 | * the compiler optimizing these reads out. | |
181 | */ | |
182 | reg = ACCESS_ONCE(ptemp[0]); | |
183 | read_reg = ACCESS_ONCE(ptemp[1]); | |
184 | /* Force Read */ | |
185 | rmb(); | |
186 | ||
187 | edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", | |
188 | reg, read_reg); | |
189 | ||
190 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
191 | ||
192 | return count; | |
193 | } | |
194 | ||
195 | static const struct file_operations altr_sdr_mc_debug_inject_fops = { | |
196 | .open = simple_open, | |
197 | .write = altr_sdr_mc_err_inject_write, | |
198 | .llseek = generic_file_llseek, | |
199 | }; | |
200 | ||
201 | static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) | |
202 | { | |
bba3b31e BP |
203 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) |
204 | return; | |
205 | ||
206 | if (!mci->debugfs) | |
207 | return; | |
208 | ||
b8978bad | 209 | edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci, |
bba3b31e | 210 | &altr_sdr_mc_debug_inject_fops); |
71bcada8 | 211 | } |
71bcada8 | 212 | |
f9ae487e TT |
213 | /* Get total memory size from Open Firmware DTB */ |
214 | static unsigned long get_total_mem(void) | |
71bcada8 | 215 | { |
f9ae487e TT |
216 | struct device_node *np = NULL; |
217 | const unsigned int *reg, *reg_end; | |
218 | int len, sw, aw; | |
219 | unsigned long start, size, total_mem = 0; | |
220 | ||
221 | for_each_node_by_type(np, "memory") { | |
222 | aw = of_n_addr_cells(np); | |
223 | sw = of_n_size_cells(np); | |
224 | reg = (const unsigned int *)of_get_property(np, "reg", &len); | |
225 | reg_end = reg + (len / sizeof(u32)); | |
226 | ||
227 | total_mem = 0; | |
228 | do { | |
229 | start = of_read_number(reg, aw); | |
230 | reg += aw; | |
231 | size = of_read_number(reg, sw); | |
232 | reg += sw; | |
233 | total_mem += size; | |
234 | } while (reg < reg_end); | |
235 | } | |
236 | edac_dbg(0, "total_mem 0x%lx\n", total_mem); | |
237 | return total_mem; | |
71bcada8 TT |
238 | } |
239 | ||
143f4a5a | 240 | static const struct of_device_id altr_sdram_ctrl_of_match[] = { |
2c911f6c AB |
241 | { .compatible = "altr,sdram-edac", .data = &c5_data}, |
242 | { .compatible = "altr,sdram-edac-a10", .data = &a10_data}, | |
143f4a5a TT |
243 | {}, |
244 | }; | |
245 | MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); | |
246 | ||
73bcc942 TT |
247 | static int a10_init(struct regmap *mc_vbase) |
248 | { | |
249 | if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, | |
250 | A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { | |
251 | edac_printk(KERN_ERR, EDAC_MC, | |
252 | "Error setting SB IRQ mode\n"); | |
253 | return -ENODEV; | |
254 | } | |
255 | ||
256 | if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { | |
257 | edac_printk(KERN_ERR, EDAC_MC, | |
258 | "Error setting trigger count\n"); | |
259 | return -ENODEV; | |
260 | } | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static int a10_unmask_irq(struct platform_device *pdev, u32 mask) | |
266 | { | |
267 | void __iomem *sm_base; | |
268 | int ret = 0; | |
269 | ||
270 | if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), | |
271 | dev_name(&pdev->dev))) { | |
272 | edac_printk(KERN_ERR, EDAC_MC, | |
273 | "Unable to request mem region\n"); | |
274 | return -EBUSY; | |
275 | } | |
276 | ||
277 | sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
278 | if (!sm_base) { | |
279 | edac_printk(KERN_ERR, EDAC_MC, | |
280 | "Unable to ioremap device\n"); | |
281 | ||
282 | ret = -ENOMEM; | |
283 | goto release; | |
284 | } | |
285 | ||
286 | iowrite32(mask, sm_base); | |
287 | ||
288 | iounmap(sm_base); | |
289 | ||
290 | release: | |
291 | release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
292 | ||
293 | return ret; | |
294 | } | |
295 | ||
71bcada8 TT |
296 | static int altr_sdram_probe(struct platform_device *pdev) |
297 | { | |
143f4a5a | 298 | const struct of_device_id *id; |
71bcada8 TT |
299 | struct edac_mc_layer layers[2]; |
300 | struct mem_ctl_info *mci; | |
301 | struct altr_sdram_mc_data *drvdata; | |
143f4a5a | 302 | const struct altr_sdram_prv_data *priv; |
71bcada8 TT |
303 | struct regmap *mc_vbase; |
304 | struct dimm_info *dimm; | |
143f4a5a | 305 | u32 read_reg; |
73bcc942 TT |
306 | int irq, irq2, res = 0; |
307 | unsigned long mem_size, irqflags = 0; | |
143f4a5a TT |
308 | |
309 | id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); | |
310 | if (!id) | |
311 | return -ENODEV; | |
71bcada8 | 312 | |
71bcada8 TT |
313 | /* Grab the register range from the sdr controller in device tree */ |
314 | mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
315 | "altr,sdr-syscon"); | |
316 | if (IS_ERR(mc_vbase)) { | |
317 | edac_printk(KERN_ERR, EDAC_MC, | |
318 | "regmap for altr,sdr-syscon lookup failed.\n"); | |
319 | return -ENODEV; | |
320 | } | |
321 | ||
143f4a5a TT |
322 | /* Check specific dependencies for the module */ |
323 | priv = of_match_node(altr_sdram_ctrl_of_match, | |
324 | pdev->dev.of_node)->data; | |
325 | ||
326 | /* Validate the SDRAM controller has ECC enabled */ | |
327 | if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || | |
328 | ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { | |
71bcada8 TT |
329 | edac_printk(KERN_ERR, EDAC_MC, |
330 | "No ECC/ECC disabled [0x%08X]\n", read_reg); | |
331 | return -ENODEV; | |
332 | } | |
333 | ||
334 | /* Grab memory size from device tree. */ | |
f9ae487e | 335 | mem_size = get_total_mem(); |
71bcada8 | 336 | if (!mem_size) { |
f9ae487e | 337 | edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); |
71bcada8 TT |
338 | return -ENODEV; |
339 | } | |
340 | ||
143f4a5a TT |
341 | /* Ensure the SDRAM Interrupt is disabled */ |
342 | if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, | |
343 | priv->ecc_irq_en_mask, 0)) { | |
344 | edac_printk(KERN_ERR, EDAC_MC, | |
345 | "Error disabling SDRAM ECC IRQ\n"); | |
346 | return -ENODEV; | |
347 | } | |
348 | ||
349 | /* Toggle to clear the SDRAM Error count */ | |
350 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
351 | priv->ecc_cnt_rst_mask, | |
352 | priv->ecc_cnt_rst_mask)) { | |
353 | edac_printk(KERN_ERR, EDAC_MC, | |
354 | "Error clearing SDRAM ECC count\n"); | |
355 | return -ENODEV; | |
356 | } | |
357 | ||
358 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
359 | priv->ecc_cnt_rst_mask, 0)) { | |
71bcada8 | 360 | edac_printk(KERN_ERR, EDAC_MC, |
143f4a5a | 361 | "Error clearing SDRAM ECC count\n"); |
71bcada8 TT |
362 | return -ENODEV; |
363 | } | |
364 | ||
365 | irq = platform_get_irq(pdev, 0); | |
366 | if (irq < 0) { | |
367 | edac_printk(KERN_ERR, EDAC_MC, | |
368 | "No irq %d in DT\n", irq); | |
369 | return -ENODEV; | |
370 | } | |
371 | ||
73bcc942 TT |
372 | /* Arria10 has a 2nd IRQ */ |
373 | irq2 = platform_get_irq(pdev, 1); | |
374 | ||
71bcada8 TT |
375 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
376 | layers[0].size = 1; | |
377 | layers[0].is_virt_csrow = true; | |
378 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
379 | layers[1].size = 1; | |
380 | layers[1].is_virt_csrow = false; | |
381 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | |
382 | sizeof(struct altr_sdram_mc_data)); | |
383 | if (!mci) | |
384 | return -ENOMEM; | |
385 | ||
386 | mci->pdev = &pdev->dev; | |
387 | drvdata = mci->pvt_info; | |
388 | drvdata->mc_vbase = mc_vbase; | |
143f4a5a | 389 | drvdata->data = priv; |
71bcada8 TT |
390 | platform_set_drvdata(pdev, mci); |
391 | ||
392 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
143f4a5a TT |
393 | edac_printk(KERN_ERR, EDAC_MC, |
394 | "Unable to get managed device resource\n"); | |
71bcada8 TT |
395 | res = -ENOMEM; |
396 | goto free; | |
397 | } | |
398 | ||
399 | mci->mtype_cap = MEM_FLAG_DDR3; | |
400 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
401 | mci->edac_cap = EDAC_FLAG_SECDED; | |
402 | mci->mod_name = EDAC_MOD_STR; | |
403 | mci->mod_ver = EDAC_VERSION; | |
404 | mci->ctl_name = dev_name(&pdev->dev); | |
405 | mci->scrub_mode = SCRUB_SW_SRC; | |
406 | mci->dev_name = dev_name(&pdev->dev); | |
407 | ||
408 | dimm = *mci->dimms; | |
409 | dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; | |
410 | dimm->grain = 8; | |
411 | dimm->dtype = DEV_X8; | |
412 | dimm->mtype = MEM_DDR3; | |
413 | dimm->edac_mode = EDAC_SECDED; | |
414 | ||
415 | res = edac_mc_add_mc(mci); | |
416 | if (res < 0) | |
417 | goto err; | |
418 | ||
73bcc942 TT |
419 | /* Only the Arria10 has separate IRQs */ |
420 | if (irq2 > 0) { | |
421 | /* Arria10 specific initialization */ | |
422 | res = a10_init(mc_vbase); | |
423 | if (res < 0) | |
424 | goto err2; | |
425 | ||
426 | res = devm_request_irq(&pdev->dev, irq2, | |
427 | altr_sdram_mc_err_handler, | |
428 | IRQF_SHARED, dev_name(&pdev->dev), mci); | |
429 | if (res < 0) { | |
430 | edac_mc_printk(mci, KERN_ERR, | |
431 | "Unable to request irq %d\n", irq2); | |
432 | res = -ENODEV; | |
433 | goto err2; | |
434 | } | |
435 | ||
436 | res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); | |
437 | if (res < 0) | |
438 | goto err2; | |
439 | ||
440 | irqflags = IRQF_SHARED; | |
441 | } | |
442 | ||
71bcada8 | 443 | res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, |
73bcc942 | 444 | irqflags, dev_name(&pdev->dev), mci); |
71bcada8 TT |
445 | if (res < 0) { |
446 | edac_mc_printk(mci, KERN_ERR, | |
447 | "Unable to request irq %d\n", irq); | |
448 | res = -ENODEV; | |
449 | goto err2; | |
450 | } | |
451 | ||
143f4a5a TT |
452 | /* Infrastructure ready - enable the IRQ */ |
453 | if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, | |
454 | priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { | |
71bcada8 TT |
455 | edac_mc_printk(mci, KERN_ERR, |
456 | "Error enabling SDRAM ECC IRQ\n"); | |
457 | res = -ENODEV; | |
458 | goto err2; | |
459 | } | |
460 | ||
461 | altr_sdr_mc_create_debugfs_nodes(mci); | |
462 | ||
463 | devres_close_group(&pdev->dev, NULL); | |
464 | ||
465 | return 0; | |
466 | ||
467 | err2: | |
468 | edac_mc_del_mc(&pdev->dev); | |
469 | err: | |
470 | devres_release_group(&pdev->dev, NULL); | |
471 | free: | |
472 | edac_mc_free(mci); | |
473 | edac_printk(KERN_ERR, EDAC_MC, | |
474 | "EDAC Probe Failed; Error %d\n", res); | |
475 | ||
476 | return res; | |
477 | } | |
478 | ||
479 | static int altr_sdram_remove(struct platform_device *pdev) | |
480 | { | |
481 | struct mem_ctl_info *mci = platform_get_drvdata(pdev); | |
482 | ||
483 | edac_mc_del_mc(&pdev->dev); | |
484 | edac_mc_free(mci); | |
485 | platform_set_drvdata(pdev, NULL); | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
6f2b6422 AT |
490 | /* |
491 | * If you want to suspend, need to disable EDAC by removing it | |
492 | * from the device tree or defconfig. | |
493 | */ | |
494 | #ifdef CONFIG_PM | |
495 | static int altr_sdram_prepare(struct device *dev) | |
496 | { | |
497 | pr_err("Suspend not allowed when EDAC is enabled.\n"); | |
498 | ||
499 | return -EPERM; | |
500 | } | |
501 | ||
502 | static const struct dev_pm_ops altr_sdram_pm_ops = { | |
503 | .prepare = altr_sdram_prepare, | |
504 | }; | |
505 | #endif | |
506 | ||
71bcada8 TT |
507 | static struct platform_driver altr_sdram_edac_driver = { |
508 | .probe = altr_sdram_probe, | |
509 | .remove = altr_sdram_remove, | |
510 | .driver = { | |
511 | .name = "altr_sdram_edac", | |
6f2b6422 AT |
512 | #ifdef CONFIG_PM |
513 | .pm = &altr_sdram_pm_ops, | |
514 | #endif | |
71bcada8 TT |
515 | .of_match_table = altr_sdram_ctrl_of_match, |
516 | }, | |
517 | }; | |
518 | ||
519 | module_platform_driver(altr_sdram_edac_driver); | |
520 | ||
c3eea194 TT |
521 | /************************* EDAC Parent Probe *************************/ |
522 | ||
523 | static const struct of_device_id altr_edac_device_of_match[]; | |
524 | ||
525 | static const struct of_device_id altr_edac_of_match[] = { | |
526 | { .compatible = "altr,socfpga-ecc-manager" }, | |
527 | {}, | |
528 | }; | |
529 | MODULE_DEVICE_TABLE(of, altr_edac_of_match); | |
530 | ||
531 | static int altr_edac_probe(struct platform_device *pdev) | |
532 | { | |
533 | of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, | |
534 | NULL, &pdev->dev); | |
535 | return 0; | |
536 | } | |
537 | ||
538 | static struct platform_driver altr_edac_driver = { | |
539 | .probe = altr_edac_probe, | |
540 | .driver = { | |
541 | .name = "socfpga_ecc_manager", | |
542 | .of_match_table = altr_edac_of_match, | |
543 | }, | |
544 | }; | |
545 | module_platform_driver(altr_edac_driver); | |
546 | ||
547 | /************************* EDAC Device Functions *************************/ | |
548 | ||
549 | /* | |
550 | * EDAC Device Functions (shared between various IPs). | |
551 | * The discrete memories use the EDAC Device framework. The probe | |
552 | * and error handling functions are very similar between memories | |
553 | * so they are shared. The memory allocation and freeing for EDAC | |
554 | * trigger testing are different for each memory. | |
555 | */ | |
556 | ||
1cf70377 TT |
557 | static const struct edac_device_prv_data ocramecc_data; |
558 | static const struct edac_device_prv_data l2ecc_data; | |
559 | static const struct edac_device_prv_data a10_ocramecc_data; | |
560 | static const struct edac_device_prv_data a10_l2ecc_data; | |
c3eea194 | 561 | |
c3eea194 TT |
562 | static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) |
563 | { | |
564 | irqreturn_t ret_value = IRQ_NONE; | |
565 | struct edac_device_ctl_info *dci = dev_id; | |
566 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
567 | const struct edac_device_prv_data *priv = drvdata->data; | |
568 | ||
569 | if (irq == drvdata->sb_irq) { | |
570 | if (priv->ce_clear_mask) | |
571 | writel(priv->ce_clear_mask, drvdata->base); | |
572 | edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); | |
573 | ret_value = IRQ_HANDLED; | |
574 | } else if (irq == drvdata->db_irq) { | |
575 | if (priv->ue_clear_mask) | |
576 | writel(priv->ue_clear_mask, drvdata->base); | |
577 | edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); | |
578 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
579 | ret_value = IRQ_HANDLED; | |
580 | } else { | |
581 | WARN_ON(1); | |
582 | } | |
583 | ||
584 | return ret_value; | |
585 | } | |
586 | ||
587 | static ssize_t altr_edac_device_trig(struct file *file, | |
588 | const char __user *user_buf, | |
589 | size_t count, loff_t *ppos) | |
590 | ||
591 | { | |
592 | u32 *ptemp, i, error_mask; | |
593 | int result = 0; | |
594 | u8 trig_type; | |
595 | unsigned long flags; | |
596 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
597 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
598 | const struct edac_device_prv_data *priv = drvdata->data; | |
599 | void *generic_ptr = edac_dci->dev; | |
600 | ||
601 | if (!user_buf || get_user(trig_type, user_buf)) | |
602 | return -EFAULT; | |
603 | ||
604 | if (!priv->alloc_mem) | |
605 | return -ENOMEM; | |
606 | ||
607 | /* | |
608 | * Note that generic_ptr is initialized to the device * but in | |
609 | * some alloc_functions, this is overridden and returns data. | |
610 | */ | |
611 | ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); | |
612 | if (!ptemp) { | |
613 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
614 | "Inject: Buffer Allocation error\n"); | |
615 | return -ENOMEM; | |
616 | } | |
617 | ||
618 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
619 | error_mask = priv->ue_set_mask; | |
620 | else | |
621 | error_mask = priv->ce_set_mask; | |
622 | ||
623 | edac_printk(KERN_ALERT, EDAC_DEVICE, | |
624 | "Trigger Error Mask (0x%X)\n", error_mask); | |
625 | ||
626 | local_irq_save(flags); | |
627 | /* write ECC corrupted data out. */ | |
628 | for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { | |
629 | /* Read data so we're in the correct state */ | |
630 | rmb(); | |
631 | if (ACCESS_ONCE(ptemp[i])) | |
632 | result = -1; | |
633 | /* Toggle Error bit (it is latched), leave ECC enabled */ | |
811fce4f TT |
634 | writel(error_mask, (drvdata->base + priv->set_err_ofst)); |
635 | writel(priv->ecc_enable_mask, (drvdata->base + | |
636 | priv->set_err_ofst)); | |
c3eea194 TT |
637 | ptemp[i] = i; |
638 | } | |
639 | /* Ensure it has been written out */ | |
640 | wmb(); | |
641 | local_irq_restore(flags); | |
642 | ||
643 | if (result) | |
644 | edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); | |
645 | ||
646 | /* Read out written data. ECC error caused here */ | |
647 | for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) | |
648 | if (ACCESS_ONCE(ptemp[i]) != i) | |
649 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
650 | "Read doesn't match written data\n"); | |
651 | ||
652 | if (priv->free_mem) | |
653 | priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); | |
654 | ||
655 | return count; | |
656 | } | |
657 | ||
658 | static const struct file_operations altr_edac_device_inject_fops = { | |
659 | .open = simple_open, | |
660 | .write = altr_edac_device_trig, | |
661 | .llseek = generic_file_llseek, | |
662 | }; | |
663 | ||
c7b4be8d TT |
664 | static ssize_t altr_edac_a10_device_trig(struct file *file, |
665 | const char __user *user_buf, | |
666 | size_t count, loff_t *ppos); | |
667 | ||
668 | static const struct file_operations altr_edac_a10_device_inject_fops = { | |
669 | .open = simple_open, | |
670 | .write = altr_edac_a10_device_trig, | |
671 | .llseek = generic_file_llseek, | |
672 | }; | |
673 | ||
c3eea194 TT |
674 | static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, |
675 | const struct edac_device_prv_data *priv) | |
676 | { | |
677 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
678 | ||
679 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) | |
680 | return; | |
681 | ||
682 | drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); | |
683 | if (!drvdata->debugfs_dir) | |
684 | return; | |
685 | ||
f399f34b | 686 | if (!edac_debugfs_create_file("altr_trigger", S_IWUSR, |
c3eea194 | 687 | drvdata->debugfs_dir, edac_dci, |
e17ced2c | 688 | priv->inject_fops)) |
c3eea194 TT |
689 | debugfs_remove_recursive(drvdata->debugfs_dir); |
690 | } | |
691 | ||
692 | static const struct of_device_id altr_edac_device_of_match[] = { | |
693 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
2c911f6c | 694 | { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data }, |
c3eea194 TT |
695 | #endif |
696 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
2c911f6c | 697 | { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, |
c3eea194 TT |
698 | #endif |
699 | {}, | |
700 | }; | |
701 | MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); | |
702 | ||
703 | /* | |
704 | * altr_edac_device_probe() | |
705 | * This is a generic EDAC device driver that will support | |
706 | * various Altera memory devices such as the L2 cache ECC and | |
707 | * OCRAM ECC as well as the memories for other peripherals. | |
708 | * Module specific initialization is done by passing the | |
709 | * function index in the device tree. | |
710 | */ | |
711 | static int altr_edac_device_probe(struct platform_device *pdev) | |
712 | { | |
713 | struct edac_device_ctl_info *dci; | |
714 | struct altr_edac_device_dev *drvdata; | |
715 | struct resource *r; | |
716 | int res = 0; | |
717 | struct device_node *np = pdev->dev.of_node; | |
718 | char *ecc_name = (char *)np->name; | |
719 | static int dev_instance; | |
720 | ||
721 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
722 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
723 | "Unable to open devm\n"); | |
724 | return -ENOMEM; | |
725 | } | |
726 | ||
727 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
728 | if (!r) { | |
729 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
730 | "Unable to get mem resource\n"); | |
731 | res = -ENODEV; | |
732 | goto fail; | |
733 | } | |
734 | ||
735 | if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), | |
736 | dev_name(&pdev->dev))) { | |
737 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
738 | "%s:Error requesting mem region\n", ecc_name); | |
739 | res = -EBUSY; | |
740 | goto fail; | |
741 | } | |
742 | ||
743 | dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, | |
744 | 1, ecc_name, 1, 0, NULL, 0, | |
745 | dev_instance++); | |
746 | ||
747 | if (!dci) { | |
748 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
749 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
750 | res = -ENOMEM; | |
751 | goto fail; | |
752 | } | |
753 | ||
754 | drvdata = dci->pvt_info; | |
755 | dci->dev = &pdev->dev; | |
756 | platform_set_drvdata(pdev, dci); | |
757 | drvdata->edac_dev_name = ecc_name; | |
758 | ||
759 | drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); | |
760 | if (!drvdata->base) | |
761 | goto fail1; | |
762 | ||
763 | /* Get driver specific data for this EDAC device */ | |
764 | drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; | |
765 | ||
766 | /* Check specific dependencies for the module */ | |
767 | if (drvdata->data->setup) { | |
328ca7ae | 768 | res = drvdata->data->setup(drvdata); |
c3eea194 TT |
769 | if (res) |
770 | goto fail1; | |
771 | } | |
772 | ||
773 | drvdata->sb_irq = platform_get_irq(pdev, 0); | |
774 | res = devm_request_irq(&pdev->dev, drvdata->sb_irq, | |
775 | altr_edac_device_handler, | |
776 | 0, dev_name(&pdev->dev), dci); | |
777 | if (res) | |
778 | goto fail1; | |
779 | ||
780 | drvdata->db_irq = platform_get_irq(pdev, 1); | |
781 | res = devm_request_irq(&pdev->dev, drvdata->db_irq, | |
782 | altr_edac_device_handler, | |
783 | 0, dev_name(&pdev->dev), dci); | |
784 | if (res) | |
785 | goto fail1; | |
786 | ||
787 | dci->mod_name = "Altera ECC Manager"; | |
788 | dci->dev_name = drvdata->edac_dev_name; | |
789 | ||
790 | res = edac_device_add_device(dci); | |
791 | if (res) | |
792 | goto fail1; | |
793 | ||
794 | altr_create_edacdev_dbgfs(dci, drvdata->data); | |
795 | ||
796 | devres_close_group(&pdev->dev, NULL); | |
797 | ||
798 | return 0; | |
799 | ||
800 | fail1: | |
801 | edac_device_free_ctl_info(dci); | |
802 | fail: | |
803 | devres_release_group(&pdev->dev, NULL); | |
804 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
805 | "%s:Error setting up EDAC device: %d\n", ecc_name, res); | |
806 | ||
807 | return res; | |
808 | } | |
809 | ||
810 | static int altr_edac_device_remove(struct platform_device *pdev) | |
811 | { | |
812 | struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); | |
813 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
814 | ||
815 | debugfs_remove_recursive(drvdata->debugfs_dir); | |
816 | edac_device_del_device(&pdev->dev); | |
817 | edac_device_free_ctl_info(dci); | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
822 | static struct platform_driver altr_edac_device_driver = { | |
823 | .probe = altr_edac_device_probe, | |
824 | .remove = altr_edac_device_remove, | |
825 | .driver = { | |
826 | .name = "altr_edac_device", | |
827 | .of_match_table = altr_edac_device_of_match, | |
828 | }, | |
829 | }; | |
830 | module_platform_driver(altr_edac_device_driver); | |
831 | ||
6b300fb9 | 832 | /******************* Arria10 Device ECC Shared Functions *****************/ |
c3eea194 | 833 | |
1aa6eb5c AB |
834 | /* |
835 | * Test for memory's ECC dependencies upon entry because platform specific | |
836 | * startup should have initialized the memory and enabled the ECC. | |
837 | * Can't turn on ECC here because accessing un-initialized memory will | |
838 | * cause CE/UE errors possibly causing an ABORT. | |
839 | */ | |
6b300fb9 TT |
840 | static int __maybe_unused |
841 | altr_check_ecc_deps(struct altr_edac_device_dev *device) | |
1aa6eb5c AB |
842 | { |
843 | void __iomem *base = device->base; | |
844 | const struct edac_device_prv_data *prv = device->data; | |
845 | ||
846 | if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) | |
847 | return 0; | |
848 | ||
849 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
850 | "%s: No ECC present or ECC disabled.\n", | |
851 | device->edac_dev_name); | |
852 | return -ENODEV; | |
853 | } | |
c3eea194 | 854 | |
6b300fb9 TT |
855 | static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id) |
856 | { | |
857 | struct altr_edac_device_dev *dci = dev_id; | |
858 | void __iomem *base = dci->base; | |
859 | ||
860 | if (irq == dci->sb_irq) { | |
861 | writel(ALTR_A10_ECC_SERRPENA, | |
862 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
863 | edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
864 | ||
865 | return IRQ_HANDLED; | |
866 | } else if (irq == dci->db_irq) { | |
867 | writel(ALTR_A10_ECC_DERRPENA, | |
868 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
869 | edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
870 | if (dci->data->panic) | |
871 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
872 | ||
873 | return IRQ_HANDLED; | |
874 | } | |
875 | ||
876 | WARN_ON(1); | |
877 | ||
878 | return IRQ_NONE; | |
879 | } | |
880 | ||
1166fde9 TT |
881 | /******************* Arria10 Memory Buffer Functions *********************/ |
882 | ||
883 | static inline int a10_get_irq_mask(struct device_node *np) | |
884 | { | |
885 | int irq; | |
886 | const u32 *handle = of_get_property(np, "interrupts", NULL); | |
887 | ||
888 | if (!handle) | |
889 | return -ENODEV; | |
890 | irq = be32_to_cpup(handle); | |
891 | return irq; | |
892 | } | |
893 | ||
894 | static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) | |
895 | { | |
896 | u32 value = readl(ioaddr); | |
897 | ||
898 | value |= bit_mask; | |
899 | writel(value, ioaddr); | |
900 | } | |
901 | ||
902 | static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) | |
903 | { | |
904 | u32 value = readl(ioaddr); | |
905 | ||
906 | value &= ~bit_mask; | |
907 | writel(value, ioaddr); | |
908 | } | |
909 | ||
910 | static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) | |
911 | { | |
912 | u32 value = readl(ioaddr); | |
913 | ||
914 | return (value & bit_mask) ? 1 : 0; | |
915 | } | |
916 | ||
917 | /* | |
918 | * This function uses the memory initialization block in the Arria10 ECC | |
919 | * controller to initialize/clear the entire memory data and ECC data. | |
920 | */ | |
921 | static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port) | |
922 | { | |
923 | int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US; | |
924 | u32 init_mask, stat_mask, clear_mask; | |
925 | int ret = 0; | |
926 | ||
927 | if (port) { | |
928 | init_mask = ALTR_A10_ECC_INITB; | |
929 | stat_mask = ALTR_A10_ECC_INITCOMPLETEB; | |
930 | clear_mask = ALTR_A10_ECC_ERRPENB_MASK; | |
931 | } else { | |
932 | init_mask = ALTR_A10_ECC_INITA; | |
933 | stat_mask = ALTR_A10_ECC_INITCOMPLETEA; | |
934 | clear_mask = ALTR_A10_ECC_ERRPENA_MASK; | |
935 | } | |
936 | ||
937 | ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST)); | |
938 | while (limit--) { | |
939 | if (ecc_test_bits(stat_mask, | |
940 | (ioaddr + ALTR_A10_ECC_INITSTAT_OFST))) | |
941 | break; | |
942 | udelay(1); | |
943 | } | |
944 | if (limit < 0) | |
945 | ret = -EBUSY; | |
946 | ||
947 | /* Clear any pending ECC interrupts */ | |
948 | writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST)); | |
949 | ||
950 | return ret; | |
951 | } | |
952 | ||
953 | static __init int __maybe_unused | |
954 | altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, | |
955 | u32 ecc_ctrl_en_mask, bool dual_port) | |
956 | { | |
957 | int ret = 0; | |
958 | void __iomem *ecc_block_base; | |
959 | struct regmap *ecc_mgr_map; | |
960 | char *ecc_name; | |
961 | struct device_node *np_eccmgr; | |
962 | ||
963 | ecc_name = (char *)np->name; | |
964 | ||
965 | /* Get the ECC Manager - parent of the device EDACs */ | |
966 | np_eccmgr = of_get_parent(np); | |
967 | ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr, | |
968 | "altr,sysmgr-syscon"); | |
969 | of_node_put(np_eccmgr); | |
970 | if (IS_ERR(ecc_mgr_map)) { | |
971 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
972 | "Unable to get syscon altr,sysmgr-syscon\n"); | |
973 | return -ENODEV; | |
974 | } | |
975 | ||
976 | /* Map the ECC Block */ | |
977 | ecc_block_base = of_iomap(np, 0); | |
978 | if (!ecc_block_base) { | |
979 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
980 | "Unable to map %s ECC block\n", ecc_name); | |
981 | return -ENODEV; | |
982 | } | |
983 | ||
984 | /* Disable ECC */ | |
985 | regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask); | |
986 | writel(ALTR_A10_ECC_SERRINTEN, | |
987 | (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST)); | |
988 | ecc_clear_bits(ecc_ctrl_en_mask, | |
989 | (ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); | |
990 | /* Ensure all writes complete */ | |
991 | wmb(); | |
992 | /* Use HW initialization block to initialize memory for ECC */ | |
993 | ret = altr_init_memory_port(ecc_block_base, 0); | |
994 | if (ret) { | |
995 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
996 | "ECC: cannot init %s PORTA memory\n", ecc_name); | |
997 | goto out; | |
998 | } | |
999 | ||
1000 | if (dual_port) { | |
1001 | ret = altr_init_memory_port(ecc_block_base, 1); | |
1002 | if (ret) { | |
1003 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1004 | "ECC: cannot init %s PORTB memory\n", | |
1005 | ecc_name); | |
1006 | goto out; | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | /* Interrupt mode set to every SBERR */ | |
1011 | regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST, | |
1012 | ALTR_A10_ECC_INTMODE); | |
1013 | /* Enable ECC */ | |
1014 | ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base + | |
1015 | ALTR_A10_ECC_CTRL_OFST)); | |
1016 | writel(ALTR_A10_ECC_SERRINTEN, | |
1017 | (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST)); | |
1018 | regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask); | |
1019 | /* Ensure all writes complete */ | |
1020 | wmb(); | |
1021 | out: | |
1022 | iounmap(ecc_block_base); | |
1023 | return ret; | |
1024 | } | |
1025 | ||
1026 | static int validate_parent_available(struct device_node *np); | |
1027 | static const struct of_device_id altr_edac_a10_device_of_match[]; | |
1028 | static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat) | |
1029 | { | |
1030 | int irq; | |
1031 | struct device_node *child, *np = of_find_compatible_node(NULL, NULL, | |
1032 | "altr,socfpga-a10-ecc-manager"); | |
1033 | if (!np) { | |
1034 | edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n"); | |
1035 | return -ENODEV; | |
1036 | } | |
1037 | ||
1038 | for_each_child_of_node(np, child) { | |
1039 | const struct of_device_id *pdev_id; | |
1040 | const struct edac_device_prv_data *prv; | |
1041 | ||
1042 | if (!of_device_is_available(child)) | |
1043 | continue; | |
1044 | if (!of_device_is_compatible(child, compat)) | |
1045 | continue; | |
1046 | ||
1047 | if (validate_parent_available(child)) | |
1048 | continue; | |
1049 | ||
1050 | irq = a10_get_irq_mask(child); | |
1051 | if (irq < 0) | |
1052 | continue; | |
1053 | ||
1054 | /* Get matching node and check for valid result */ | |
1055 | pdev_id = of_match_node(altr_edac_a10_device_of_match, child); | |
1056 | if (IS_ERR_OR_NULL(pdev_id)) | |
1057 | continue; | |
1058 | ||
1059 | /* Validate private data pointer before dereferencing */ | |
1060 | prv = pdev_id->data; | |
1061 | if (!prv) | |
1062 | continue; | |
1063 | ||
1064 | altr_init_a10_ecc_block(child, BIT(irq), | |
1065 | prv->ecc_enable_mask, 0); | |
1066 | } | |
1067 | ||
1068 | of_node_put(np); | |
1069 | return 0; | |
1070 | } | |
1071 | ||
6b300fb9 TT |
1072 | /*********************** OCRAM EDAC Device Functions *********************/ |
1073 | ||
1074 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
1075 | ||
c3eea194 TT |
1076 | static void *ocram_alloc_mem(size_t size, void **other) |
1077 | { | |
1078 | struct device_node *np; | |
1079 | struct gen_pool *gp; | |
1080 | void *sram_addr; | |
1081 | ||
1082 | np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); | |
1083 | if (!np) | |
1084 | return NULL; | |
1085 | ||
1086 | gp = of_gen_pool_get(np, "iram", 0); | |
1087 | of_node_put(np); | |
1088 | if (!gp) | |
1089 | return NULL; | |
1090 | ||
1091 | sram_addr = (void *)gen_pool_alloc(gp, size); | |
1092 | if (!sram_addr) | |
1093 | return NULL; | |
1094 | ||
1095 | memset(sram_addr, 0, size); | |
1096 | /* Ensure data is written out */ | |
1097 | wmb(); | |
1098 | ||
1099 | /* Remember this handle for freeing later */ | |
1100 | *other = gp; | |
1101 | ||
1102 | return sram_addr; | |
1103 | } | |
1104 | ||
1105 | static void ocram_free_mem(void *p, size_t size, void *other) | |
1106 | { | |
1107 | gen_pool_free((struct gen_pool *)other, (u32)p, size); | |
1108 | } | |
1109 | ||
1cf70377 | 1110 | static const struct edac_device_prv_data ocramecc_data = { |
aa1f06dc | 1111 | .setup = altr_check_ecc_deps, |
c3eea194 TT |
1112 | .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), |
1113 | .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), | |
c3eea194 TT |
1114 | .alloc_mem = ocram_alloc_mem, |
1115 | .free_mem = ocram_free_mem, | |
1116 | .ecc_enable_mask = ALTR_OCR_ECC_EN, | |
943ad917 | 1117 | .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET, |
c3eea194 TT |
1118 | .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), |
1119 | .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), | |
811fce4f | 1120 | .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, |
c3eea194 | 1121 | .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, |
e17ced2c | 1122 | .inject_fops = &altr_edac_device_inject_fops, |
c3eea194 TT |
1123 | }; |
1124 | ||
1cf70377 | 1125 | static const struct edac_device_prv_data a10_ocramecc_data = { |
c7b4be8d TT |
1126 | .setup = altr_check_ecc_deps, |
1127 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1128 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
1129 | .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM, | |
c7b4be8d TT |
1130 | .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL, |
1131 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1132 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1133 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1134 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1135 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1136 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
2b083d65 TT |
1137 | /* |
1138 | * OCRAM panic on uncorrectable error because sleep/resume | |
1139 | * functions and FPGA contents are stored in OCRAM. Prefer | |
1140 | * a kernel panic over executing/loading corrupted data. | |
1141 | */ | |
1142 | .panic = true, | |
c7b4be8d TT |
1143 | }; |
1144 | ||
c3eea194 TT |
1145 | #endif /* CONFIG_EDAC_ALTERA_OCRAM */ |
1146 | ||
1147 | /********************* L2 Cache EDAC Device Functions ********************/ | |
1148 | ||
1149 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
1150 | ||
1151 | static void *l2_alloc_mem(size_t size, void **other) | |
1152 | { | |
1153 | struct device *dev = *other; | |
1154 | void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); | |
1155 | ||
1156 | if (!ptemp) | |
1157 | return NULL; | |
1158 | ||
1159 | /* Make sure everything is written out */ | |
1160 | wmb(); | |
1161 | ||
1162 | /* | |
1163 | * Clean all cache levels up to LoC (includes L2) | |
1164 | * This ensures the corrupted data is written into | |
1165 | * L2 cache for readback test (which causes ECC error). | |
1166 | */ | |
1167 | flush_cache_all(); | |
1168 | ||
1169 | return ptemp; | |
1170 | } | |
1171 | ||
1172 | static void l2_free_mem(void *p, size_t size, void *other) | |
1173 | { | |
1174 | struct device *dev = other; | |
1175 | ||
1176 | if (dev && p) | |
1177 | devm_kfree(dev, p); | |
1178 | } | |
1179 | ||
1180 | /* | |
1181 | * altr_l2_check_deps() | |
1182 | * Test for L2 cache ECC dependencies upon entry because | |
1183 | * platform specific startup should have initialized the L2 | |
1184 | * memory and enabled the ECC. | |
1185 | * Bail if ECC is not enabled. | |
1186 | * Note that L2 Cache Enable is forced at build time. | |
1187 | */ | |
328ca7ae | 1188 | static int altr_l2_check_deps(struct altr_edac_device_dev *device) |
c3eea194 | 1189 | { |
328ca7ae | 1190 | void __iomem *base = device->base; |
27439a1a TT |
1191 | const struct edac_device_prv_data *prv = device->data; |
1192 | ||
1193 | if ((readl(base) & prv->ecc_enable_mask) == | |
1194 | prv->ecc_enable_mask) | |
c3eea194 TT |
1195 | return 0; |
1196 | ||
1197 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1198 | "L2: No ECC present, or ECC disabled\n"); | |
1199 | return -ENODEV; | |
1200 | } | |
1201 | ||
13ab8448 | 1202 | static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id) |
588cb03e | 1203 | { |
13ab8448 TT |
1204 | struct altr_edac_device_dev *dci = dev_id; |
1205 | ||
1206 | if (irq == dci->sb_irq) { | |
588cb03e TT |
1207 | regmap_write(dci->edac->ecc_mgr_map, |
1208 | A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, | |
1209 | A10_SYSGMR_MPU_CLEAR_L2_ECC_SB); | |
1210 | edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
13ab8448 TT |
1211 | |
1212 | return IRQ_HANDLED; | |
1213 | } else if (irq == dci->db_irq) { | |
588cb03e TT |
1214 | regmap_write(dci->edac->ecc_mgr_map, |
1215 | A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, | |
1216 | A10_SYSGMR_MPU_CLEAR_L2_ECC_MB); | |
1217 | edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
1218 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
13ab8448 TT |
1219 | |
1220 | return IRQ_HANDLED; | |
588cb03e | 1221 | } |
13ab8448 TT |
1222 | |
1223 | WARN_ON(1); | |
1224 | ||
1225 | return IRQ_NONE; | |
588cb03e TT |
1226 | } |
1227 | ||
1cf70377 | 1228 | static const struct edac_device_prv_data l2ecc_data = { |
c3eea194 TT |
1229 | .setup = altr_l2_check_deps, |
1230 | .ce_clear_mask = 0, | |
1231 | .ue_clear_mask = 0, | |
c3eea194 TT |
1232 | .alloc_mem = l2_alloc_mem, |
1233 | .free_mem = l2_free_mem, | |
1234 | .ecc_enable_mask = ALTR_L2_ECC_EN, | |
1235 | .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), | |
1236 | .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), | |
811fce4f | 1237 | .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, |
c3eea194 | 1238 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, |
e17ced2c | 1239 | .inject_fops = &altr_edac_device_inject_fops, |
c3eea194 TT |
1240 | }; |
1241 | ||
1cf70377 | 1242 | static const struct edac_device_prv_data a10_l2ecc_data = { |
588cb03e TT |
1243 | .setup = altr_l2_check_deps, |
1244 | .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR, | |
1245 | .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR, | |
1246 | .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2, | |
588cb03e TT |
1247 | .alloc_mem = l2_alloc_mem, |
1248 | .free_mem = l2_free_mem, | |
1249 | .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL, | |
1250 | .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK, | |
1251 | .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK, | |
1252 | .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST, | |
1253 | .ecc_irq_handler = altr_edac_a10_l2_irq, | |
1254 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, | |
e17ced2c | 1255 | .inject_fops = &altr_edac_device_inject_fops, |
588cb03e TT |
1256 | }; |
1257 | ||
c3eea194 TT |
1258 | #endif /* CONFIG_EDAC_ALTERA_L2C */ |
1259 | ||
ab8c1e0f TT |
1260 | /********************* Ethernet Device Functions ********************/ |
1261 | ||
1262 | #ifdef CONFIG_EDAC_ALTERA_ETHERNET | |
1263 | ||
1264 | static const struct edac_device_prv_data a10_enetecc_data = { | |
1265 | .setup = altr_check_ecc_deps, | |
1266 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1267 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
ab8c1e0f TT |
1268 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1269 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1270 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1271 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1272 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1273 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1274 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1275 | }; | |
1276 | ||
1277 | static int __init socfpga_init_ethernet_ecc(void) | |
1278 | { | |
1279 | return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); | |
1280 | } | |
1281 | ||
1282 | early_initcall(socfpga_init_ethernet_ecc); | |
1283 | ||
1284 | #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ | |
1285 | ||
c6882fb2 TT |
1286 | /********************** NAND Device Functions **********************/ |
1287 | ||
1288 | #ifdef CONFIG_EDAC_ALTERA_NAND | |
1289 | ||
1290 | static const struct edac_device_prv_data a10_nandecc_data = { | |
1291 | .setup = altr_check_ecc_deps, | |
1292 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1293 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
c6882fb2 TT |
1294 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1295 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1296 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1297 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1298 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1299 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1300 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1301 | }; | |
1302 | ||
1303 | static int __init socfpga_init_nand_ecc(void) | |
1304 | { | |
1305 | return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc"); | |
1306 | } | |
1307 | ||
1308 | early_initcall(socfpga_init_nand_ecc); | |
1309 | ||
1310 | #endif /* CONFIG_EDAC_ALTERA_NAND */ | |
1311 | ||
e8263793 TT |
1312 | /********************** DMA Device Functions **********************/ |
1313 | ||
1314 | #ifdef CONFIG_EDAC_ALTERA_DMA | |
1315 | ||
1316 | static const struct edac_device_prv_data a10_dmaecc_data = { | |
1317 | .setup = altr_check_ecc_deps, | |
1318 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1319 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
e8263793 TT |
1320 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1321 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1322 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1323 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1324 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1325 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1326 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1327 | }; | |
1328 | ||
1329 | static int __init socfpga_init_dma_ecc(void) | |
1330 | { | |
1331 | return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); | |
1332 | } | |
1333 | ||
1334 | early_initcall(socfpga_init_dma_ecc); | |
1335 | ||
1336 | #endif /* CONFIG_EDAC_ALTERA_DMA */ | |
1337 | ||
c609581d TT |
1338 | /********************** USB Device Functions **********************/ |
1339 | ||
1340 | #ifdef CONFIG_EDAC_ALTERA_USB | |
1341 | ||
1342 | static const struct edac_device_prv_data a10_usbecc_data = { | |
1343 | .setup = altr_check_ecc_deps, | |
1344 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1345 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
c609581d TT |
1346 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1347 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1348 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1349 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1350 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1351 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1352 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1353 | }; | |
1354 | ||
1355 | static int __init socfpga_init_usb_ecc(void) | |
1356 | { | |
1357 | return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc"); | |
1358 | } | |
1359 | ||
1360 | early_initcall(socfpga_init_usb_ecc); | |
1361 | ||
1362 | #endif /* CONFIG_EDAC_ALTERA_USB */ | |
1363 | ||
485fe9e2 TT |
1364 | /********************** QSPI Device Functions **********************/ |
1365 | ||
1366 | #ifdef CONFIG_EDAC_ALTERA_QSPI | |
1367 | ||
1368 | static const struct edac_device_prv_data a10_qspiecc_data = { | |
1369 | .setup = altr_check_ecc_deps, | |
1370 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1371 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
485fe9e2 TT |
1372 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1373 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1374 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1375 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1376 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1377 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1378 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1379 | }; | |
1380 | ||
1381 | static int __init socfpga_init_qspi_ecc(void) | |
1382 | { | |
1383 | return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc"); | |
1384 | } | |
1385 | ||
1386 | early_initcall(socfpga_init_qspi_ecc); | |
1387 | ||
1388 | #endif /* CONFIG_EDAC_ALTERA_QSPI */ | |
1389 | ||
91104984 TT |
1390 | /********************* SDMMC Device Functions **********************/ |
1391 | ||
1392 | #ifdef CONFIG_EDAC_ALTERA_SDMMC | |
1393 | ||
1394 | static const struct edac_device_prv_data a10_sdmmceccb_data; | |
1395 | static int altr_portb_setup(struct altr_edac_device_dev *device) | |
1396 | { | |
1397 | struct edac_device_ctl_info *dci; | |
1398 | struct altr_edac_device_dev *altdev; | |
1399 | char *ecc_name = "sdmmcb-ecc"; | |
1400 | int edac_idx, rc; | |
1401 | struct device_node *np; | |
1402 | const struct edac_device_prv_data *prv = &a10_sdmmceccb_data; | |
1403 | ||
1404 | rc = altr_check_ecc_deps(device); | |
1405 | if (rc) | |
1406 | return rc; | |
1407 | ||
1408 | np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); | |
1409 | if (!np) { | |
1410 | edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); | |
1411 | return -ENODEV; | |
1412 | } | |
1413 | ||
1414 | /* Create the PortB EDAC device */ | |
1415 | edac_idx = edac_device_alloc_index(); | |
1416 | dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1, | |
1417 | ecc_name, 1, 0, NULL, 0, edac_idx); | |
1418 | if (!dci) { | |
1419 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1420 | "%s: Unable to allocate PortB EDAC device\n", | |
1421 | ecc_name); | |
1422 | return -ENOMEM; | |
1423 | } | |
1424 | ||
1425 | /* Initialize the PortB EDAC device structure from PortA structure */ | |
1426 | altdev = dci->pvt_info; | |
1427 | *altdev = *device; | |
1428 | ||
1429 | if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL)) | |
1430 | return -ENOMEM; | |
1431 | ||
1432 | /* Update PortB specific values */ | |
1433 | altdev->edac_dev_name = ecc_name; | |
1434 | altdev->edac_idx = edac_idx; | |
1435 | altdev->edac_dev = dci; | |
1436 | altdev->data = prv; | |
1437 | dci->dev = &altdev->ddev; | |
1438 | dci->ctl_name = "Altera ECC Manager"; | |
1439 | dci->mod_name = ecc_name; | |
1440 | dci->dev_name = ecc_name; | |
1441 | ||
1442 | /* Update the IRQs for PortB */ | |
1443 | altdev->sb_irq = irq_of_parse_and_map(np, 2); | |
1444 | if (!altdev->sb_irq) { | |
1445 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n"); | |
1446 | rc = -ENODEV; | |
1447 | goto err_release_group_1; | |
1448 | } | |
1449 | rc = devm_request_irq(&altdev->ddev, altdev->sb_irq, | |
1450 | prv->ecc_irq_handler, | |
a29d64a4 TT |
1451 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, |
1452 | ecc_name, altdev); | |
91104984 TT |
1453 | if (rc) { |
1454 | edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n"); | |
1455 | goto err_release_group_1; | |
1456 | } | |
1457 | ||
1458 | altdev->db_irq = irq_of_parse_and_map(np, 3); | |
1459 | if (!altdev->db_irq) { | |
1460 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); | |
1461 | rc = -ENODEV; | |
1462 | goto err_release_group_1; | |
1463 | } | |
1464 | rc = devm_request_irq(&altdev->ddev, altdev->db_irq, | |
1465 | prv->ecc_irq_handler, | |
a29d64a4 TT |
1466 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, |
1467 | ecc_name, altdev); | |
91104984 TT |
1468 | if (rc) { |
1469 | edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n"); | |
1470 | goto err_release_group_1; | |
1471 | } | |
1472 | ||
1473 | rc = edac_device_add_device(dci); | |
1474 | if (rc) { | |
1475 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1476 | "edac_device_add_device portB failed\n"); | |
1477 | rc = -ENOMEM; | |
1478 | goto err_release_group_1; | |
1479 | } | |
1480 | altr_create_edacdev_dbgfs(dci, prv); | |
1481 | ||
1482 | list_add(&altdev->next, &altdev->edac->a10_ecc_devices); | |
1483 | ||
1484 | devres_remove_group(&altdev->ddev, altr_portb_setup); | |
1485 | ||
1486 | return 0; | |
1487 | ||
1488 | err_release_group_1: | |
1489 | edac_device_free_ctl_info(dci); | |
1490 | devres_release_group(&altdev->ddev, altr_portb_setup); | |
1491 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1492 | "%s:Error setting up EDAC device: %d\n", ecc_name, rc); | |
1493 | return rc; | |
1494 | } | |
1495 | ||
1496 | static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id) | |
1497 | { | |
1498 | struct altr_edac_device_dev *ad = dev_id; | |
1499 | void __iomem *base = ad->base; | |
1500 | const struct edac_device_prv_data *priv = ad->data; | |
1501 | ||
1502 | if (irq == ad->sb_irq) { | |
1503 | writel(priv->ce_clear_mask, | |
1504 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
1505 | edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name); | |
1506 | return IRQ_HANDLED; | |
1507 | } else if (irq == ad->db_irq) { | |
1508 | writel(priv->ue_clear_mask, | |
1509 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
1510 | edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name); | |
1511 | return IRQ_HANDLED; | |
1512 | } | |
1513 | ||
1514 | WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq); | |
1515 | ||
1516 | return IRQ_NONE; | |
1517 | } | |
1518 | ||
1519 | static const struct edac_device_prv_data a10_sdmmcecca_data = { | |
1520 | .setup = altr_portb_setup, | |
1521 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
1522 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
91104984 TT |
1523 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1524 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1525 | .ce_set_mask = ALTR_A10_ECC_SERRPENA, | |
1526 | .ue_set_mask = ALTR_A10_ECC_DERRPENA, | |
1527 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1528 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1529 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1530 | }; | |
1531 | ||
1532 | static const struct edac_device_prv_data a10_sdmmceccb_data = { | |
1533 | .setup = altr_portb_setup, | |
1534 | .ce_clear_mask = ALTR_A10_ECC_SERRPENB, | |
1535 | .ue_clear_mask = ALTR_A10_ECC_DERRPENB, | |
91104984 TT |
1536 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1537 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1538 | .ce_set_mask = ALTR_A10_ECC_TSERRB, | |
1539 | .ue_set_mask = ALTR_A10_ECC_TDERRB, | |
1540 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1541 | .ecc_irq_handler = altr_edac_a10_ecc_irq_portb, | |
1542 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1543 | }; | |
1544 | ||
1545 | static int __init socfpga_init_sdmmc_ecc(void) | |
1546 | { | |
1547 | int rc = -ENODEV; | |
1548 | struct device_node *child = of_find_compatible_node(NULL, NULL, | |
1549 | "altr,socfpga-sdmmc-ecc"); | |
1550 | if (!child) { | |
1551 | edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); | |
1552 | return -ENODEV; | |
1553 | } | |
1554 | ||
1555 | if (!of_device_is_available(child)) | |
1556 | goto exit; | |
1557 | ||
1558 | if (validate_parent_available(child)) | |
1559 | goto exit; | |
1560 | ||
1561 | rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK, | |
1562 | a10_sdmmcecca_data.ecc_enable_mask, 1); | |
1563 | exit: | |
1564 | of_node_put(child); | |
1565 | return rc; | |
1566 | } | |
1567 | ||
1568 | early_initcall(socfpga_init_sdmmc_ecc); | |
1569 | ||
1570 | #endif /* CONFIG_EDAC_ALTERA_SDMMC */ | |
1571 | ||
588cb03e | 1572 | /********************* Arria10 EDAC Device Functions *************************/ |
ab564cb5 TT |
1573 | static const struct of_device_id altr_edac_a10_device_of_match[] = { |
1574 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
1575 | { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, | |
1576 | #endif | |
1577 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
1578 | { .compatible = "altr,socfpga-a10-ocram-ecc", | |
1579 | .data = &a10_ocramecc_data }, | |
ab8c1e0f TT |
1580 | #endif |
1581 | #ifdef CONFIG_EDAC_ALTERA_ETHERNET | |
1582 | { .compatible = "altr,socfpga-eth-mac-ecc", | |
1583 | .data = &a10_enetecc_data }, | |
c6882fb2 TT |
1584 | #endif |
1585 | #ifdef CONFIG_EDAC_ALTERA_NAND | |
1586 | { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, | |
e8263793 TT |
1587 | #endif |
1588 | #ifdef CONFIG_EDAC_ALTERA_DMA | |
1589 | { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, | |
c609581d TT |
1590 | #endif |
1591 | #ifdef CONFIG_EDAC_ALTERA_USB | |
1592 | { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, | |
485fe9e2 TT |
1593 | #endif |
1594 | #ifdef CONFIG_EDAC_ALTERA_QSPI | |
1595 | { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data }, | |
91104984 TT |
1596 | #endif |
1597 | #ifdef CONFIG_EDAC_ALTERA_SDMMC | |
1598 | { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data }, | |
ab564cb5 TT |
1599 | #endif |
1600 | {}, | |
1601 | }; | |
1602 | MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); | |
588cb03e TT |
1603 | |
1604 | /* | |
1605 | * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 | |
1606 | * because 2 IRQs are shared among the all ECC peripherals. The ECC | |
1607 | * manager manages the IRQs and the children. | |
1608 | * Based on xgene_edac.c peripheral code. | |
1609 | */ | |
1610 | ||
c7b4be8d TT |
1611 | static ssize_t altr_edac_a10_device_trig(struct file *file, |
1612 | const char __user *user_buf, | |
1613 | size_t count, loff_t *ppos) | |
1614 | { | |
1615 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
1616 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
1617 | const struct edac_device_prv_data *priv = drvdata->data; | |
1618 | void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); | |
1619 | unsigned long flags; | |
1620 | u8 trig_type; | |
1621 | ||
1622 | if (!user_buf || get_user(trig_type, user_buf)) | |
1623 | return -EFAULT; | |
1624 | ||
1625 | local_irq_save(flags); | |
1626 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
1627 | writel(priv->ue_set_mask, set_addr); | |
1628 | else | |
1629 | writel(priv->ce_set_mask, set_addr); | |
1630 | /* Ensure the interrupt test bits are set */ | |
1631 | wmb(); | |
1632 | local_irq_restore(flags); | |
1633 | ||
1634 | return count; | |
1635 | } | |
1636 | ||
13ab8448 | 1637 | static void altr_edac_a10_irq_handler(struct irq_desc *desc) |
588cb03e | 1638 | { |
13ab8448 TT |
1639 | int dberr, bit, sm_offset, irq_status; |
1640 | struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc); | |
1641 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
1642 | int irq = irq_desc_get_irq(desc); | |
1643 | ||
1644 | dberr = (irq == edac->db_irq) ? 1 : 0; | |
1645 | sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST : | |
1646 | A10_SYSMGR_ECC_INTSTAT_SERR_OFST; | |
1647 | ||
1648 | chained_irq_enter(chip, desc); | |
588cb03e TT |
1649 | |
1650 | regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status); | |
1651 | ||
13ab8448 TT |
1652 | for_each_set_bit(bit, (unsigned long *)&irq_status, 32) { |
1653 | irq = irq_linear_revmap(edac->domain, dberr * 32 + bit); | |
1654 | if (irq) | |
1655 | generic_handle_irq(irq); | |
588cb03e TT |
1656 | } |
1657 | ||
13ab8448 | 1658 | chained_irq_exit(chip, desc); |
588cb03e TT |
1659 | } |
1660 | ||
44ec9b30 TT |
1661 | static int validate_parent_available(struct device_node *np) |
1662 | { | |
1663 | struct device_node *parent; | |
1664 | int ret = 0; | |
1665 | ||
1666 | /* Ensure parent device is enabled if parent node exists */ | |
1667 | parent = of_parse_phandle(np, "altr,ecc-parent", 0); | |
1668 | if (parent && !of_device_is_available(parent)) | |
1669 | ret = -ENODEV; | |
1670 | ||
1671 | of_node_put(parent); | |
1672 | return ret; | |
1673 | } | |
1674 | ||
588cb03e TT |
1675 | static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, |
1676 | struct device_node *np) | |
1677 | { | |
1678 | struct edac_device_ctl_info *dci; | |
1679 | struct altr_edac_device_dev *altdev; | |
1680 | char *ecc_name = (char *)np->name; | |
1681 | struct resource res; | |
1682 | int edac_idx; | |
1683 | int rc = 0; | |
1684 | const struct edac_device_prv_data *prv; | |
1685 | /* Get matching node and check for valid result */ | |
1686 | const struct of_device_id *pdev_id = | |
ab564cb5 | 1687 | of_match_node(altr_edac_a10_device_of_match, np); |
588cb03e TT |
1688 | if (IS_ERR_OR_NULL(pdev_id)) |
1689 | return -ENODEV; | |
1690 | ||
1691 | /* Get driver specific data for this EDAC device */ | |
1692 | prv = pdev_id->data; | |
1693 | if (IS_ERR_OR_NULL(prv)) | |
1694 | return -ENODEV; | |
1695 | ||
44ec9b30 TT |
1696 | if (validate_parent_available(np)) |
1697 | return -ENODEV; | |
1698 | ||
588cb03e TT |
1699 | if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL)) |
1700 | return -ENOMEM; | |
1701 | ||
1702 | rc = of_address_to_resource(np, 0, &res); | |
1703 | if (rc < 0) { | |
1704 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1705 | "%s: no resource address\n", ecc_name); | |
1706 | goto err_release_group; | |
1707 | } | |
1708 | ||
1709 | edac_idx = edac_device_alloc_index(); | |
1710 | dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, | |
1711 | 1, ecc_name, 1, 0, NULL, 0, | |
1712 | edac_idx); | |
1713 | ||
1714 | if (!dci) { | |
1715 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1716 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
1717 | rc = -ENOMEM; | |
1718 | goto err_release_group; | |
1719 | } | |
1720 | ||
1721 | altdev = dci->pvt_info; | |
1722 | dci->dev = edac->dev; | |
1723 | altdev->edac_dev_name = ecc_name; | |
1724 | altdev->edac_idx = edac_idx; | |
1725 | altdev->edac = edac; | |
1726 | altdev->edac_dev = dci; | |
1727 | altdev->data = prv; | |
1728 | altdev->ddev = *edac->dev; | |
1729 | dci->dev = &altdev->ddev; | |
1730 | dci->ctl_name = "Altera ECC Manager"; | |
1731 | dci->mod_name = ecc_name; | |
1732 | dci->dev_name = ecc_name; | |
1733 | ||
1734 | altdev->base = devm_ioremap_resource(edac->dev, &res); | |
1735 | if (IS_ERR(altdev->base)) { | |
1736 | rc = PTR_ERR(altdev->base); | |
1737 | goto err_release_group1; | |
1738 | } | |
1739 | ||
1740 | /* Check specific dependencies for the module */ | |
1741 | if (altdev->data->setup) { | |
1742 | rc = altdev->data->setup(altdev); | |
1743 | if (rc) | |
1744 | goto err_release_group1; | |
1745 | } | |
1746 | ||
13ab8448 TT |
1747 | altdev->sb_irq = irq_of_parse_and_map(np, 0); |
1748 | if (!altdev->sb_irq) { | |
1749 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n"); | |
1750 | rc = -ENODEV; | |
1751 | goto err_release_group1; | |
1752 | } | |
a29d64a4 TT |
1753 | rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler, |
1754 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
1755 | ecc_name, altdev); | |
13ab8448 | 1756 | if (rc) { |
3763569f | 1757 | edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n"); |
13ab8448 TT |
1758 | goto err_release_group1; |
1759 | } | |
1760 | ||
1761 | altdev->db_irq = irq_of_parse_and_map(np, 1); | |
1762 | if (!altdev->db_irq) { | |
1763 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n"); | |
1764 | rc = -ENODEV; | |
1765 | goto err_release_group1; | |
1766 | } | |
a29d64a4 TT |
1767 | rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler, |
1768 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
1769 | ecc_name, altdev); | |
13ab8448 TT |
1770 | if (rc) { |
1771 | edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); | |
1772 | goto err_release_group1; | |
1773 | } | |
1774 | ||
588cb03e TT |
1775 | rc = edac_device_add_device(dci); |
1776 | if (rc) { | |
1777 | dev_err(edac->dev, "edac_device_add_device failed\n"); | |
1778 | rc = -ENOMEM; | |
1779 | goto err_release_group1; | |
1780 | } | |
1781 | ||
1782 | altr_create_edacdev_dbgfs(dci, prv); | |
1783 | ||
1784 | list_add(&altdev->next, &edac->a10_ecc_devices); | |
1785 | ||
1786 | devres_remove_group(edac->dev, altr_edac_a10_device_add); | |
1787 | ||
1788 | return 0; | |
1789 | ||
1790 | err_release_group1: | |
1791 | edac_device_free_ctl_info(dci); | |
1792 | err_release_group: | |
588cb03e TT |
1793 | devres_release_group(edac->dev, NULL); |
1794 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1795 | "%s:Error setting up EDAC device: %d\n", ecc_name, rc); | |
1796 | ||
1797 | return rc; | |
1798 | } | |
1799 | ||
13ab8448 TT |
1800 | static void a10_eccmgr_irq_mask(struct irq_data *d) |
1801 | { | |
1802 | struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); | |
1803 | ||
1804 | regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, | |
1805 | BIT(d->hwirq)); | |
1806 | } | |
1807 | ||
1808 | static void a10_eccmgr_irq_unmask(struct irq_data *d) | |
1809 | { | |
1810 | struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); | |
1811 | ||
1812 | regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, | |
1813 | BIT(d->hwirq)); | |
1814 | } | |
1815 | ||
1816 | static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
1817 | irq_hw_number_t hwirq) | |
1818 | { | |
1819 | struct altr_arria10_edac *edac = d->host_data; | |
1820 | ||
1821 | irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); | |
1822 | irq_set_chip_data(irq, edac); | |
1823 | irq_set_noprobe(irq); | |
1824 | ||
1825 | return 0; | |
1826 | } | |
1827 | ||
9bcd919e | 1828 | static struct irq_domain_ops a10_eccmgr_ic_ops = { |
13ab8448 TT |
1829 | .map = a10_eccmgr_irqdomain_map, |
1830 | .xlate = irq_domain_xlate_twocell, | |
1831 | }; | |
1832 | ||
588cb03e TT |
1833 | static int altr_edac_a10_probe(struct platform_device *pdev) |
1834 | { | |
1835 | struct altr_arria10_edac *edac; | |
1836 | struct device_node *child; | |
588cb03e TT |
1837 | |
1838 | edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); | |
1839 | if (!edac) | |
1840 | return -ENOMEM; | |
1841 | ||
1842 | edac->dev = &pdev->dev; | |
1843 | platform_set_drvdata(pdev, edac); | |
1844 | INIT_LIST_HEAD(&edac->a10_ecc_devices); | |
1845 | ||
1846 | edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
1847 | "altr,sysmgr-syscon"); | |
1848 | if (IS_ERR(edac->ecc_mgr_map)) { | |
1849 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1850 | "Unable to get syscon altr,sysmgr-syscon\n"); | |
1851 | return PTR_ERR(edac->ecc_mgr_map); | |
1852 | } | |
1853 | ||
13ab8448 TT |
1854 | edac->irq_chip.name = pdev->dev.of_node->name; |
1855 | edac->irq_chip.irq_mask = a10_eccmgr_irq_mask; | |
1856 | edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask; | |
1857 | edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64, | |
1858 | &a10_eccmgr_ic_ops, edac); | |
1859 | if (!edac->domain) { | |
1860 | dev_err(&pdev->dev, "Error adding IRQ domain\n"); | |
1861 | return -ENOMEM; | |
1862 | } | |
1863 | ||
588cb03e | 1864 | edac->sb_irq = platform_get_irq(pdev, 0); |
13ab8448 TT |
1865 | if (edac->sb_irq < 0) { |
1866 | dev_err(&pdev->dev, "No SBERR IRQ resource\n"); | |
1867 | return edac->sb_irq; | |
588cb03e TT |
1868 | } |
1869 | ||
13ab8448 TT |
1870 | irq_set_chained_handler_and_data(edac->sb_irq, |
1871 | altr_edac_a10_irq_handler, | |
1872 | edac); | |
1873 | ||
588cb03e | 1874 | edac->db_irq = platform_get_irq(pdev, 1); |
13ab8448 TT |
1875 | if (edac->db_irq < 0) { |
1876 | dev_err(&pdev->dev, "No DBERR IRQ resource\n"); | |
1877 | return edac->db_irq; | |
588cb03e | 1878 | } |
13ab8448 TT |
1879 | irq_set_chained_handler_and_data(edac->db_irq, |
1880 | altr_edac_a10_irq_handler, | |
1881 | edac); | |
588cb03e TT |
1882 | |
1883 | for_each_child_of_node(pdev->dev.of_node, child) { | |
1884 | if (!of_device_is_available(child)) | |
1885 | continue; | |
c6882fb2 TT |
1886 | |
1887 | if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") || | |
1888 | of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") || | |
1889 | of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") || | |
e8263793 | 1890 | of_device_is_compatible(child, "altr,socfpga-nand-ecc") || |
c609581d | 1891 | of_device_is_compatible(child, "altr,socfpga-dma-ecc") || |
485fe9e2 | 1892 | of_device_is_compatible(child, "altr,socfpga-usb-ecc") || |
91104984 TT |
1893 | of_device_is_compatible(child, "altr,socfpga-qspi-ecc") || |
1894 | of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc")) | |
c6882fb2 | 1895 | |
c7b4be8d | 1896 | altr_edac_a10_device_add(edac, child); |
c6882fb2 TT |
1897 | |
1898 | else if (of_device_is_compatible(child, "altr,sdram-edac-a10")) | |
ab564cb5 TT |
1899 | of_platform_populate(pdev->dev.of_node, |
1900 | altr_sdram_ctrl_of_match, | |
1901 | NULL, &pdev->dev); | |
588cb03e TT |
1902 | } |
1903 | ||
1904 | return 0; | |
1905 | } | |
1906 | ||
1907 | static const struct of_device_id altr_edac_a10_of_match[] = { | |
1908 | { .compatible = "altr,socfpga-a10-ecc-manager" }, | |
1909 | {}, | |
1910 | }; | |
1911 | MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); | |
1912 | ||
1913 | static struct platform_driver altr_edac_a10_driver = { | |
1914 | .probe = altr_edac_a10_probe, | |
1915 | .driver = { | |
1916 | .name = "socfpga_a10_ecc_manager", | |
1917 | .of_match_table = altr_edac_a10_of_match, | |
1918 | }, | |
1919 | }; | |
1920 | module_platform_driver(altr_edac_a10_driver); | |
1921 | ||
71bcada8 TT |
1922 | MODULE_LICENSE("GPL v2"); |
1923 | MODULE_AUTHOR("Thor Thayer"); | |
c3eea194 | 1924 | MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); |