[mirror_ubuntu-hirsute-kernel.git] / drivers / edac / altera_edac.c

/*
 *  Copyright Altera Corporation (C) 2014-2015. All rights reserved.
 *  Copyright 2011-2012 Calxeda, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Adapted from the highbank_mc_edac driver.
 */

#include <linux/ctype.h>
#include <linux/edac.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/types.h>
#include <linux/uaccess.h>

#include "altera_edac.h"
#include "edac_core.h"
#include "edac_module.h"

#define EDAC_MOD_STR		"altera_edac"
#define EDAC_VERSION		"1"

static const struct altr_sdram_prv_data c5_data = {
	.ecc_ctrl_offset    = CV_CTLCFG_OFST,
	.ecc_ctl_en_mask    = CV_CTLCFG_ECC_AUTO_EN,
	.ecc_stat_offset    = CV_DRAMSTS_OFST,
	.ecc_stat_ce_mask   = CV_DRAMSTS_SBEERR,
	.ecc_stat_ue_mask   = CV_DRAMSTS_DBEERR,
	.ecc_saddr_offset   = CV_ERRADDR_OFST,
	.ecc_cecnt_offset   = CV_SBECOUNT_OFST,
	.ecc_uecnt_offset   = CV_DBECOUNT_OFST,
	.ecc_irq_en_offset  = CV_DRAMINTR_OFST,
	.ecc_irq_en_mask    = CV_DRAMINTR_INTREN,
	.ecc_irq_clr_offset = CV_DRAMINTR_OFST,
	.ecc_irq_clr_mask   = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
	.ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
	.ecc_cnt_rst_mask   = CV_DRAMINTR_INTRCLR,
#ifdef CONFIG_EDAC_DEBUG
	.ce_ue_trgr_offset  = CV_CTLCFG_OFST,
	.ce_set_mask        = CV_CTLCFG_GEN_SB_ERR,
	.ue_set_mask        = CV_CTLCFG_GEN_DB_ERR,
#endif
};

static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
{
	struct mem_ctl_info *mci = dev_id;
	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
	const struct altr_sdram_prv_data *priv = drvdata->data;
	u32 status, err_count, err_addr;

	/* Error Address is shared by both SBE & DBE */
	regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, &err_addr);

	regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);

	if (status & priv->ecc_stat_ue_mask) {
		regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
			    &err_count);
		panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
		      err_count, err_addr);
	}
	if (status & priv->ecc_stat_ce_mask) {
		regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
			    &err_count);
		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
				     err_addr >> PAGE_SHIFT,
				     err_addr & ~PAGE_MASK, 0,
				     0, 0, -1, mci->ctl_name, "");
	}

	regmap_write(drvdata->mc_vbase,	priv->ecc_irq_clr_offset,
		     priv->ecc_irq_clr_mask);

	return IRQ_HANDLED;
}

#ifdef CONFIG_EDAC_DEBUG
static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
					    const char __user *data,
					    size_t count, loff_t *ppos)
{
	struct mem_ctl_info *mci = file->private_data;
	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
	const struct altr_sdram_prv_data *priv = drvdata->data;
	u32 *ptemp;
	dma_addr_t dma_handle;
	u32 reg, read_reg;

	ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
	if (!ptemp) {
		dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
		edac_printk(KERN_ERR, EDAC_MC,
			    "Inject: Buffer Allocation error\n");
		return -ENOMEM;
	}

	regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
		    &read_reg);
	read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);

	/* Error are injected by writing a word while the SBE or DBE
	 * bit in the CTLCFG register is set. Reading the word will
	 * trigger the SBE or DBE error and the corresponding IRQ.
	 */
	if (count == 3) {
		edac_printk(KERN_ALERT, EDAC_MC,
			    "Inject Double bit error\n");
		regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
			     (read_reg | priv->ue_set_mask));
	} else {
		edac_printk(KERN_ALERT, EDAC_MC,
			    "Inject Single bit error\n");
		regmap_write(drvdata->mc_vbase,	priv->ce_ue_trgr_offset,
			     (read_reg | priv->ce_set_mask));
	}

	ptemp[0] = 0x5A5A5A5A;
	ptemp[1] = 0xA5A5A5A5;

	/* Clear the error injection bits */
	regmap_write(drvdata->mc_vbase,	priv->ce_ue_trgr_offset, read_reg);
	/* Ensure it has been written out */
	wmb();

	/*
	 * To trigger the error, we need to read the data back
	 * (the data was written with errors above).
	 * The ACCESS_ONCE macros and printk are used to prevent the
	 * the compiler optimizing these reads out.
	 */
	reg = ACCESS_ONCE(ptemp[0]);
	read_reg = ACCESS_ONCE(ptemp[1]);
	/* Force Read */
	rmb();

	edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
		    reg, read_reg);

	dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);

	return count;
}

static const struct file_operations altr_sdr_mc_debug_inject_fops = {
	.open = simple_open,
	.write = altr_sdr_mc_err_inject_write,
	.llseek = generic_file_llseek,
};

static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
{
	if (mci->debugfs)
		debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
				    &altr_sdr_mc_debug_inject_fops);
}
#else
static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
{}
#endif

/* Get total memory size from Open Firmware DTB */
static unsigned long get_total_mem(void)
{
	struct device_node *np = NULL;
	const unsigned int *reg, *reg_end;
	int len, sw, aw;
	unsigned long start, size, total_mem = 0;

	for_each_node_by_type(np, "memory") {
		aw = of_n_addr_cells(np);
		sw = of_n_size_cells(np);
		reg = (const unsigned int *)of_get_property(np, "reg", &len);
		reg_end = reg + (len / sizeof(u32));

		total_mem = 0;
		do {
			start = of_read_number(reg, aw);
			reg += aw;
			size = of_read_number(reg, sw);
			reg += sw;
			total_mem += size;
		} while (reg < reg_end);
	}
	edac_dbg(0, "total_mem 0x%lx\n", total_mem);
	return total_mem;
}

static const struct of_device_id altr_sdram_ctrl_of_match[] = {
	{ .compatible = "altr,sdram-edac", .data = (void *)&c5_data},
	{},
};
MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);

static int altr_sdram_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	struct edac_mc_layer layers[2];
	struct mem_ctl_info *mci;
	struct altr_sdram_mc_data *drvdata;
	const struct altr_sdram_prv_data *priv;
	struct regmap *mc_vbase;
	struct dimm_info *dimm;
	u32 read_reg;
	int irq, res = 0;
	unsigned long mem_size;

	id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
	if (!id)
		return -ENODEV;

	/* Grab the register range from the sdr controller in device tree */
	mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
						   "altr,sdr-syscon");
	if (IS_ERR(mc_vbase)) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "regmap for altr,sdr-syscon lookup failed.\n");
		return -ENODEV;
	}

	/* Check specific dependencies for the module */
	priv = of_match_node(altr_sdram_ctrl_of_match,
			     pdev->dev.of_node)->data;

	/* Validate the SDRAM controller has ECC enabled */
	if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
	    ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "No ECC/ECC disabled [0x%08X]\n", read_reg);
		return -ENODEV;
	}

	/* Grab memory size from device tree. */
	mem_size = get_total_mem();
	if (!mem_size) {
		edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
		return -ENODEV;
	}

	/* Ensure the SDRAM Interrupt is disabled */
	if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
			       priv->ecc_irq_en_mask, 0)) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "Error disabling SDRAM ECC IRQ\n");
		return -ENODEV;
	}

	/* Toggle to clear the SDRAM Error count */
	if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
			       priv->ecc_cnt_rst_mask,
			       priv->ecc_cnt_rst_mask)) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "Error clearing SDRAM ECC count\n");
		return -ENODEV;
	}

	if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
			       priv->ecc_cnt_rst_mask, 0)) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "Error clearing SDRAM ECC count\n");
		return -ENODEV;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "No irq %d in DT\n", irq);
		return -ENODEV;
	}

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = 1;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = 1;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
			    sizeof(struct altr_sdram_mc_data));
	if (!mci)
		return -ENOMEM;

	mci->pdev = &pdev->dev;
	drvdata = mci->pvt_info;
	drvdata->mc_vbase = mc_vbase;
	drvdata->data = priv;
	platform_set_drvdata(pdev, mci);

	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "Unable to get managed device resource\n");
		res = -ENOMEM;
		goto free;
	}

	mci->mtype_cap = MEM_FLAG_DDR3;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;
	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = EDAC_VERSION;
	mci->ctl_name = dev_name(&pdev->dev);
	mci->scrub_mode = SCRUB_SW_SRC;
	mci->dev_name = dev_name(&pdev->dev);

	dimm = *mci->dimms;
	dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
	dimm->grain = 8;
	dimm->dtype = DEV_X8;
	dimm->mtype = MEM_DDR3;
	dimm->edac_mode = EDAC_SECDED;

	res = edac_mc_add_mc(mci);
	if (res < 0)
		goto err;

	res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
			       0, dev_name(&pdev->dev), mci);
	if (res < 0) {
		edac_mc_printk(mci, KERN_ERR,
			       "Unable to request irq %d\n", irq);
		res = -ENODEV;
		goto err2;
	}

	/* Infrastructure ready - enable the IRQ */
	if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
			       priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
		edac_mc_printk(mci, KERN_ERR,
			       "Error enabling SDRAM ECC IRQ\n");
		res = -ENODEV;
		goto err2;
	}

	altr_sdr_mc_create_debugfs_nodes(mci);

	devres_close_group(&pdev->dev, NULL);

	return 0;

err2:
	edac_mc_del_mc(&pdev->dev);
err:
	devres_release_group(&pdev->dev, NULL);
free:
	edac_mc_free(mci);
	edac_printk(KERN_ERR, EDAC_MC,
		    "EDAC Probe Failed; Error %d\n", res);

	return res;
}

static int altr_sdram_remove(struct platform_device *pdev)
{
	struct mem_ctl_info *mci = platform_get_drvdata(pdev);

	edac_mc_del_mc(&pdev->dev);
	edac_mc_free(mci);
	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver altr_sdram_edac_driver = {
	.probe = altr_sdram_probe,
	.remove = altr_sdram_remove,
	.driver = {
		.name = "altr_sdram_edac",
		.of_match_table = altr_sdram_ctrl_of_match,
	},
};

module_platform_driver(altr_sdram_edac_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Thor Thayer");
MODULE_DESCRIPTION("EDAC Driver for Altera SDRAM Controller");
Commit	Line	Data
71bcada8	1	/*
143f4a5a	2	* Copyright Altera Corporation (C) 2014-2015. All rights reserved.
71bcada8 TT	3	* Copyright 2011-2012 Calxeda, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*
	17	* Adapted from the highbank_mc_edac driver.
	18	*/
	19
	20	#include <linux/ctype.h>
	21	#include <linux/edac.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/kernel.h>
	24	#include <linux/mfd/syscon.h>
	25	#include <linux/of_platform.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/regmap.h>
	28	#include <linux/types.h>
	29	#include <linux/uaccess.h>
	30
143f4a5a	31	#include "altera_edac.h"
71bcada8 TT	32	#include "edac_core.h"
	33	#include "edac_module.h"
	34
	35	#define EDAC_MOD_STR "altera_edac"
	36	#define EDAC_VERSION "1"
	37
143f4a5a TT	38	static const struct altr_sdram_prv_data c5_data = {
	39	.ecc_ctrl_offset = CV_CTLCFG_OFST,
	40	.ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
	41	.ecc_stat_offset = CV_DRAMSTS_OFST,
	42	.ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
	43	.ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
	44	.ecc_saddr_offset = CV_ERRADDR_OFST,
	45	.ecc_cecnt_offset = CV_SBECOUNT_OFST,
	46	.ecc_uecnt_offset = CV_DBECOUNT_OFST,
	47	.ecc_irq_en_offset = CV_DRAMINTR_OFST,
	48	.ecc_irq_en_mask = CV_DRAMINTR_INTREN,
	49	.ecc_irq_clr_offset = CV_DRAMINTR_OFST,
	50	.ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR \| CV_DRAMINTR_INTREN),
	51	.ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
	52	.ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
	53	#ifdef CONFIG_EDAC_DEBUG
	54	.ce_ue_trgr_offset = CV_CTLCFG_OFST,
	55	.ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
	56	.ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
	57	#endif
71bcada8 TT	58	};
	59
	60	static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
	61	{
	62	struct mem_ctl_info *mci = dev_id;
	63	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
143f4a5a	64	const struct altr_sdram_prv_data *priv = drvdata->data;
71bcada8 TT	65	u32 status, err_count, err_addr;
	66
	67	/* Error Address is shared by both SBE & DBE */
143f4a5a	68	regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, &err_addr);
71bcada8	69
143f4a5a	70	regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
71bcada8	71
143f4a5a TT	72	if (status & priv->ecc_stat_ue_mask) {
	73	regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
	74	&err_count);
71bcada8 TT	75	panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
	76	err_count, err_addr);
	77	}
143f4a5a TT	78	if (status & priv->ecc_stat_ce_mask) {
	79	regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
	80	&err_count);
71bcada8 TT	81	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
	82	err_addr >> PAGE_SHIFT,
	83	err_addr & ~PAGE_MASK, 0,
	84	0, 0, -1, mci->ctl_name, "");
	85	}
	86
143f4a5a TT	87	regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
143f4a5a TT	88	priv->ecc_irq_clr_mask);
71bcada8 TT	89
	90	return IRQ_HANDLED;
	91	}
	92
	93	#ifdef CONFIG_EDAC_DEBUG
	94	static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
	95	const char __user *data,
	96	size_t count, loff_t *ppos)
	97	{
	98	struct mem_ctl_info *mci = file->private_data;
	99	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
143f4a5a	100	const struct altr_sdram_prv_data *priv = drvdata->data;
71bcada8 TT	101	u32 *ptemp;
	102	dma_addr_t dma_handle;
	103	u32 reg, read_reg;
	104
	105	ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
	106	if (!ptemp) {
	107	dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
	108	edac_printk(KERN_ERR, EDAC_MC,
	109	"Inject: Buffer Allocation error\n");
	110	return -ENOMEM;
	111	}
	112
143f4a5a TT	113	regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
	114	&read_reg);
	115	read_reg &= ~(priv->ce_set_mask \| priv->ue_set_mask);
71bcada8 TT	116
	117	/* Error are injected by writing a word while the SBE or DBE
	118	* bit in the CTLCFG register is set. Reading the word will
	119	* trigger the SBE or DBE error and the corresponding IRQ.
	120	*/
	121	if (count == 3) {
	122	edac_printk(KERN_ALERT, EDAC_MC,
	123	"Inject Double bit error\n");
143f4a5a TT	124	regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
143f4a5a TT	125	(read_reg \| priv->ue_set_mask));
71bcada8 TT	126	} else {
	127	edac_printk(KERN_ALERT, EDAC_MC,
	128	"Inject Single bit error\n");
143f4a5a TT	129	regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
143f4a5a TT	130	(read_reg \| priv->ce_set_mask));
71bcada8 TT	131	}
	132
	133	ptemp[0] = 0x5A5A5A5A;
	134	ptemp[1] = 0xA5A5A5A5;
	135
	136	/* Clear the error injection bits */
143f4a5a	137	regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
71bcada8 TT	138	/* Ensure it has been written out */
	139	wmb();
	140
	141	/*
	142	* To trigger the error, we need to read the data back
	143	* (the data was written with errors above).
	144	* The ACCESS_ONCE macros and printk are used to prevent the
	145	* the compiler optimizing these reads out.
	146	*/
	147	reg = ACCESS_ONCE(ptemp[0]);
	148	read_reg = ACCESS_ONCE(ptemp[1]);
	149	/* Force Read */
	150	rmb();
	151
	152	edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
	153	reg, read_reg);
	154
	155	dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
	156
	157	return count;
	158	}
	159
	160	static const struct file_operations altr_sdr_mc_debug_inject_fops = {
	161	.open = simple_open,
	162	.write = altr_sdr_mc_err_inject_write,
	163	.llseek = generic_file_llseek,
	164	};
	165
	166	static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
	167	{
	168	if (mci->debugfs)
	169	debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
	170	&altr_sdr_mc_debug_inject_fops);
	171	}
	172	#else
	173	static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
	174	{}
	175	#endif
	176
f9ae487e TT	177	/* Get total memory size from Open Firmware DTB */
f9ae487e TT	178	static unsigned long get_total_mem(void)
71bcada8	179	{
f9ae487e TT	180	struct device_node *np = NULL;
	181	const unsigned int reg, reg_end;
	182	int len, sw, aw;
	183	unsigned long start, size, total_mem = 0;
	184
	185	for_each_node_by_type(np, "memory") {
	186	aw = of_n_addr_cells(np);
	187	sw = of_n_size_cells(np);
	188	reg = (const unsigned int *)of_get_property(np, "reg", &len);
	189	reg_end = reg + (len / sizeof(u32));
	190
	191	total_mem = 0;
	192	do {
	193	start = of_read_number(reg, aw);
	194	reg += aw;
	195	size = of_read_number(reg, sw);
	196	reg += sw;
	197	total_mem += size;
	198	} while (reg < reg_end);
	199	}
	200	edac_dbg(0, "total_mem 0x%lx\n", total_mem);
	201	return total_mem;
71bcada8 TT	202	}
71bcada8 TT	203
143f4a5a TT	204	static const struct of_device_id altr_sdram_ctrl_of_match[] = {
	205	{ .compatible = "altr,sdram-edac", .data = (void *)&c5_data},
	206	{},
	207	};
	208	MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
	209
71bcada8 TT	210	static int altr_sdram_probe(struct platform_device *pdev)
71bcada8 TT	211	{
143f4a5a	212	const struct of_device_id *id;
71bcada8 TT	213	struct edac_mc_layer layers[2];
	214	struct mem_ctl_info *mci;
	215	struct altr_sdram_mc_data *drvdata;
143f4a5a	216	const struct altr_sdram_prv_data *priv;
71bcada8 TT	217	struct regmap *mc_vbase;
71bcada8 TT	218	struct dimm_info *dimm;
143f4a5a TT	219	u32 read_reg;
	220	int irq, res = 0;
	221	unsigned long mem_size;
	222
	223	id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
	224	if (!id)
	225	return -ENODEV;
71bcada8	226
71bcada8 TT	227	/* Grab the register range from the sdr controller in device tree */
	228	mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
	229	"altr,sdr-syscon");
	230	if (IS_ERR(mc_vbase)) {
	231	edac_printk(KERN_ERR, EDAC_MC,
	232	"regmap for altr,sdr-syscon lookup failed.\n");
	233	return -ENODEV;
	234	}
	235
143f4a5a TT	236	/* Check specific dependencies for the module */
	237	priv = of_match_node(altr_sdram_ctrl_of_match,
	238	pdev->dev.of_node)->data;
	239
	240	/* Validate the SDRAM controller has ECC enabled */
	241	if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) \|\|
	242	((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
71bcada8 TT	243	edac_printk(KERN_ERR, EDAC_MC,
	244	"No ECC/ECC disabled [0x%08X]\n", read_reg);
	245	return -ENODEV;
	246	}
	247
	248	/* Grab memory size from device tree. */
f9ae487e	249	mem_size = get_total_mem();
71bcada8	250	if (!mem_size) {
f9ae487e	251	edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
71bcada8 TT	252	return -ENODEV;
	253	}
	254
143f4a5a TT	255	/* Ensure the SDRAM Interrupt is disabled */
	256	if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
	257	priv->ecc_irq_en_mask, 0)) {
	258	edac_printk(KERN_ERR, EDAC_MC,
	259	"Error disabling SDRAM ECC IRQ\n");
	260	return -ENODEV;
	261	}
	262
	263	/* Toggle to clear the SDRAM Error count */
	264	if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
	265	priv->ecc_cnt_rst_mask,
	266	priv->ecc_cnt_rst_mask)) {
	267	edac_printk(KERN_ERR, EDAC_MC,
	268	"Error clearing SDRAM ECC count\n");
	269	return -ENODEV;
	270	}
	271
	272	if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
	273	priv->ecc_cnt_rst_mask, 0)) {
71bcada8	274	edac_printk(KERN_ERR, EDAC_MC,
143f4a5a	275	"Error clearing SDRAM ECC count\n");
71bcada8 TT	276	return -ENODEV;
	277	}
	278
	279	irq = platform_get_irq(pdev, 0);
	280	if (irq < 0) {
	281	edac_printk(KERN_ERR, EDAC_MC,
	282	"No irq %d in DT\n", irq);
	283	return -ENODEV;
	284	}
	285
	286	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	287	layers[0].size = 1;
	288	layers[0].is_virt_csrow = true;
	289	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	290	layers[1].size = 1;
	291	layers[1].is_virt_csrow = false;
	292	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
	293	sizeof(struct altr_sdram_mc_data));
	294	if (!mci)
	295	return -ENOMEM;
	296
	297	mci->pdev = &pdev->dev;
	298	drvdata = mci->pvt_info;
	299	drvdata->mc_vbase = mc_vbase;
143f4a5a	300	drvdata->data = priv;
71bcada8 TT	301	platform_set_drvdata(pdev, mci);
	302
	303	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
143f4a5a TT	304	edac_printk(KERN_ERR, EDAC_MC,
143f4a5a TT	305	"Unable to get managed device resource\n");
71bcada8 TT	306	res = -ENOMEM;
	307	goto free;
	308	}
	309
	310	mci->mtype_cap = MEM_FLAG_DDR3;
	311	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	312	mci->edac_cap = EDAC_FLAG_SECDED;
	313	mci->mod_name = EDAC_MOD_STR;
	314	mci->mod_ver = EDAC_VERSION;
	315	mci->ctl_name = dev_name(&pdev->dev);
	316	mci->scrub_mode = SCRUB_SW_SRC;
	317	mci->dev_name = dev_name(&pdev->dev);
	318
	319	dimm = *mci->dimms;
	320	dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
	321	dimm->grain = 8;
	322	dimm->dtype = DEV_X8;
	323	dimm->mtype = MEM_DDR3;
	324	dimm->edac_mode = EDAC_SECDED;
	325
	326	res = edac_mc_add_mc(mci);
	327	if (res < 0)
	328	goto err;
	329
	330	res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
	331	0, dev_name(&pdev->dev), mci);
	332	if (res < 0) {
	333	edac_mc_printk(mci, KERN_ERR,
	334	"Unable to request irq %d\n", irq);
	335	res = -ENODEV;
	336	goto err2;
	337	}
	338
143f4a5a TT	339	/* Infrastructure ready - enable the IRQ */
	340	if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
	341	priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
71bcada8 TT	342	edac_mc_printk(mci, KERN_ERR,
	343	"Error enabling SDRAM ECC IRQ\n");
	344	res = -ENODEV;
	345	goto err2;
	346	}
	347
	348	altr_sdr_mc_create_debugfs_nodes(mci);
	349
	350	devres_close_group(&pdev->dev, NULL);
	351
	352	return 0;
	353
	354	err2:
	355	edac_mc_del_mc(&pdev->dev);
	356	err:
	357	devres_release_group(&pdev->dev, NULL);
	358	free:
	359	edac_mc_free(mci);
	360	edac_printk(KERN_ERR, EDAC_MC,
	361	"EDAC Probe Failed; Error %d\n", res);
	362
	363	return res;
	364	}
	365
	366	static int altr_sdram_remove(struct platform_device *pdev)
	367	{
	368	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
	369
	370	edac_mc_del_mc(&pdev->dev);
	371	edac_mc_free(mci);
	372	platform_set_drvdata(pdev, NULL);
	373
	374	return 0;
	375	}
	376
71bcada8 TT	377	static struct platform_driver altr_sdram_edac_driver = {
	378	.probe = altr_sdram_probe,
	379	.remove = altr_sdram_remove,
	380	.driver = {
	381	.name = "altr_sdram_edac",
	382	.of_match_table = altr_sdram_ctrl_of_match,
	383	},
	384	};
	385
	386	module_platform_driver(altr_sdram_edac_driver);
	387
	388	MODULE_LICENSE("GPL v2");
	389	MODULE_AUTHOR("Thor Thayer");
	390	MODULE_DESCRIPTION("EDAC Driver for Altera SDRAM Controller");