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Commit | Line | Data |
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2bc65418 | 1 | #include "amd64_edac.h" |
23ac4ae8 | 2 | #include <asm/amd_nb.h> |
2bc65418 DT |
3 | |
4 | static struct edac_pci_ctl_info *amd64_ctl_pci; | |
5 | ||
6 | static int report_gart_errors; | |
7 | module_param(report_gart_errors, int, 0644); | |
8 | ||
9 | /* | |
10 | * Set by command line parameter. If BIOS has enabled the ECC, this override is | |
11 | * cleared to prevent re-enabling the hardware by this driver. | |
12 | */ | |
13 | static int ecc_enable_override; | |
14 | module_param(ecc_enable_override, int, 0644); | |
15 | ||
a29d8b8e | 16 | static struct msr __percpu *msrs; |
50542251 | 17 | |
360b7f3c BP |
18 | /* |
19 | * count successfully initialized driver instances for setup_pci_device() | |
20 | */ | |
21 | static atomic_t drv_instances = ATOMIC_INIT(0); | |
22 | ||
cc4d8860 BP |
23 | /* Per-node driver instances */ |
24 | static struct mem_ctl_info **mcis; | |
ae7bb7c6 | 25 | static struct ecc_settings **ecc_stngs; |
2bc65418 | 26 | |
b70ef010 BP |
27 | /* |
28 | * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing | |
29 | * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching- | |
30 | * or higher value'. | |
31 | * | |
32 | *FIXME: Produce a better mapping/linearisation. | |
33 | */ | |
39094443 BP |
34 | struct scrubrate { |
35 | u32 scrubval; /* bit pattern for scrub rate */ | |
36 | u32 bandwidth; /* bandwidth consumed (bytes/sec) */ | |
37 | } scrubrates[] = { | |
b70ef010 BP |
38 | { 0x01, 1600000000UL}, |
39 | { 0x02, 800000000UL}, | |
40 | { 0x03, 400000000UL}, | |
41 | { 0x04, 200000000UL}, | |
42 | { 0x05, 100000000UL}, | |
43 | { 0x06, 50000000UL}, | |
44 | { 0x07, 25000000UL}, | |
45 | { 0x08, 12284069UL}, | |
46 | { 0x09, 6274509UL}, | |
47 | { 0x0A, 3121951UL}, | |
48 | { 0x0B, 1560975UL}, | |
49 | { 0x0C, 781440UL}, | |
50 | { 0x0D, 390720UL}, | |
51 | { 0x0E, 195300UL}, | |
52 | { 0x0F, 97650UL}, | |
53 | { 0x10, 48854UL}, | |
54 | { 0x11, 24427UL}, | |
55 | { 0x12, 12213UL}, | |
56 | { 0x13, 6101UL}, | |
57 | { 0x14, 3051UL}, | |
58 | { 0x15, 1523UL}, | |
59 | { 0x16, 761UL}, | |
60 | { 0x00, 0UL}, /* scrubbing off */ | |
61 | }; | |
62 | ||
66fed2d4 BP |
63 | int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, |
64 | u32 *val, const char *func) | |
b2b0c605 BP |
65 | { |
66 | int err = 0; | |
67 | ||
68 | err = pci_read_config_dword(pdev, offset, val); | |
69 | if (err) | |
70 | amd64_warn("%s: error reading F%dx%03x.\n", | |
71 | func, PCI_FUNC(pdev->devfn), offset); | |
72 | ||
73 | return err; | |
74 | } | |
75 | ||
76 | int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, | |
77 | u32 val, const char *func) | |
78 | { | |
79 | int err = 0; | |
80 | ||
81 | err = pci_write_config_dword(pdev, offset, val); | |
82 | if (err) | |
83 | amd64_warn("%s: error writing to F%dx%03x.\n", | |
84 | func, PCI_FUNC(pdev->devfn), offset); | |
85 | ||
86 | return err; | |
87 | } | |
88 | ||
89 | /* | |
90 | * | |
91 | * Depending on the family, F2 DCT reads need special handling: | |
92 | * | |
93 | * K8: has a single DCT only | |
94 | * | |
95 | * F10h: each DCT has its own set of regs | |
96 | * DCT0 -> F2x040.. | |
97 | * DCT1 -> F2x140.. | |
98 | * | |
99 | * F15h: we select which DCT we access using F1x10C[DctCfgSel] | |
100 | * | |
101 | */ | |
102 | static int k8_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val, | |
103 | const char *func) | |
104 | { | |
105 | if (addr >= 0x100) | |
106 | return -EINVAL; | |
107 | ||
108 | return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); | |
109 | } | |
110 | ||
111 | static int f10_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val, | |
112 | const char *func) | |
113 | { | |
114 | return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); | |
115 | } | |
116 | ||
73ba8593 BP |
117 | /* |
118 | * Select DCT to which PCI cfg accesses are routed | |
119 | */ | |
120 | static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) | |
121 | { | |
122 | u32 reg = 0; | |
123 | ||
124 | amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); | |
125 | reg &= 0xfffffffe; | |
126 | reg |= dct; | |
127 | amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); | |
128 | } | |
129 | ||
b2b0c605 BP |
130 | static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val, |
131 | const char *func) | |
132 | { | |
b2b0c605 BP |
133 | u8 dct = 0; |
134 | ||
135 | if (addr >= 0x140 && addr <= 0x1a0) { | |
136 | dct = 1; | |
137 | addr -= 0x100; | |
138 | } | |
139 | ||
73ba8593 | 140 | f15h_select_dct(pvt, dct); |
b2b0c605 BP |
141 | |
142 | return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); | |
143 | } | |
144 | ||
2bc65418 DT |
145 | /* |
146 | * Memory scrubber control interface. For K8, memory scrubbing is handled by | |
147 | * hardware and can involve L2 cache, dcache as well as the main memory. With | |
148 | * F10, this is extended to L3 cache scrubbing on CPU models sporting that | |
149 | * functionality. | |
150 | * | |
151 | * This causes the "units" for the scrubbing speed to vary from 64 byte blocks | |
152 | * (dram) over to cache lines. This is nasty, so we will use bandwidth in | |
153 | * bytes/sec for the setting. | |
154 | * | |
155 | * Currently, we only do dram scrubbing. If the scrubbing is done in software on | |
156 | * other archs, we might not have access to the caches directly. | |
157 | */ | |
158 | ||
159 | /* | |
160 | * scan the scrub rate mapping table for a close or matching bandwidth value to | |
161 | * issue. If requested is too big, then use last maximum value found. | |
162 | */ | |
395ae783 | 163 | static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate) |
2bc65418 DT |
164 | { |
165 | u32 scrubval; | |
166 | int i; | |
167 | ||
168 | /* | |
169 | * map the configured rate (new_bw) to a value specific to the AMD64 | |
170 | * memory controller and apply to register. Search for the first | |
171 | * bandwidth entry that is greater or equal than the setting requested | |
172 | * and program that. If at last entry, turn off DRAM scrubbing. | |
168bfeef AM |
173 | * |
174 | * If no suitable bandwidth is found, turn off DRAM scrubbing entirely | |
175 | * by falling back to the last element in scrubrates[]. | |
2bc65418 | 176 | */ |
168bfeef | 177 | for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) { |
2bc65418 DT |
178 | /* |
179 | * skip scrub rates which aren't recommended | |
180 | * (see F10 BKDG, F3x58) | |
181 | */ | |
395ae783 | 182 | if (scrubrates[i].scrubval < min_rate) |
2bc65418 DT |
183 | continue; |
184 | ||
185 | if (scrubrates[i].bandwidth <= new_bw) | |
186 | break; | |
2bc65418 DT |
187 | } |
188 | ||
189 | scrubval = scrubrates[i].scrubval; | |
2bc65418 | 190 | |
5980bb9c | 191 | pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F); |
2bc65418 | 192 | |
39094443 BP |
193 | if (scrubval) |
194 | return scrubrates[i].bandwidth; | |
195 | ||
2bc65418 DT |
196 | return 0; |
197 | } | |
198 | ||
395ae783 | 199 | static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw) |
2bc65418 DT |
200 | { |
201 | struct amd64_pvt *pvt = mci->pvt_info; | |
87b3e0e6 | 202 | u32 min_scrubrate = 0x5; |
2bc65418 | 203 | |
87b3e0e6 BP |
204 | if (boot_cpu_data.x86 == 0xf) |
205 | min_scrubrate = 0x0; | |
206 | ||
73ba8593 BP |
207 | /* F15h Erratum #505 */ |
208 | if (boot_cpu_data.x86 == 0x15) | |
209 | f15h_select_dct(pvt, 0); | |
210 | ||
87b3e0e6 | 211 | return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate); |
2bc65418 DT |
212 | } |
213 | ||
39094443 | 214 | static int amd64_get_scrub_rate(struct mem_ctl_info *mci) |
2bc65418 DT |
215 | { |
216 | struct amd64_pvt *pvt = mci->pvt_info; | |
217 | u32 scrubval = 0; | |
39094443 | 218 | int i, retval = -EINVAL; |
2bc65418 | 219 | |
73ba8593 BP |
220 | /* F15h Erratum #505 */ |
221 | if (boot_cpu_data.x86 == 0x15) | |
222 | f15h_select_dct(pvt, 0); | |
223 | ||
5980bb9c | 224 | amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); |
2bc65418 DT |
225 | |
226 | scrubval = scrubval & 0x001F; | |
227 | ||
926311fd | 228 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { |
2bc65418 | 229 | if (scrubrates[i].scrubval == scrubval) { |
39094443 | 230 | retval = scrubrates[i].bandwidth; |
2bc65418 DT |
231 | break; |
232 | } | |
233 | } | |
39094443 | 234 | return retval; |
2bc65418 DT |
235 | } |
236 | ||
6775763a | 237 | /* |
7f19bf75 BP |
238 | * returns true if the SysAddr given by sys_addr matches the |
239 | * DRAM base/limit associated with node_id | |
6775763a | 240 | */ |
b487c33e BP |
241 | static bool amd64_base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, |
242 | unsigned nid) | |
6775763a | 243 | { |
7f19bf75 | 244 | u64 addr; |
6775763a DT |
245 | |
246 | /* The K8 treats this as a 40-bit value. However, bits 63-40 will be | |
247 | * all ones if the most significant implemented address bit is 1. | |
248 | * Here we discard bits 63-40. See section 3.4.2 of AMD publication | |
249 | * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 | |
250 | * Application Programming. | |
251 | */ | |
252 | addr = sys_addr & 0x000000ffffffffffull; | |
253 | ||
7f19bf75 BP |
254 | return ((addr >= get_dram_base(pvt, nid)) && |
255 | (addr <= get_dram_limit(pvt, nid))); | |
6775763a DT |
256 | } |
257 | ||
258 | /* | |
259 | * Attempt to map a SysAddr to a node. On success, return a pointer to the | |
260 | * mem_ctl_info structure for the node that the SysAddr maps to. | |
261 | * | |
262 | * On failure, return NULL. | |
263 | */ | |
264 | static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, | |
265 | u64 sys_addr) | |
266 | { | |
267 | struct amd64_pvt *pvt; | |
b487c33e | 268 | unsigned node_id; |
6775763a DT |
269 | u32 intlv_en, bits; |
270 | ||
271 | /* | |
272 | * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section | |
273 | * 3.4.4.2) registers to map the SysAddr to a node ID. | |
274 | */ | |
275 | pvt = mci->pvt_info; | |
276 | ||
277 | /* | |
278 | * The value of this field should be the same for all DRAM Base | |
279 | * registers. Therefore we arbitrarily choose to read it from the | |
280 | * register for node 0. | |
281 | */ | |
7f19bf75 | 282 | intlv_en = dram_intlv_en(pvt, 0); |
6775763a DT |
283 | |
284 | if (intlv_en == 0) { | |
7f19bf75 | 285 | for (node_id = 0; node_id < DRAM_RANGES; node_id++) { |
6775763a | 286 | if (amd64_base_limit_match(pvt, sys_addr, node_id)) |
8edc5445 | 287 | goto found; |
6775763a | 288 | } |
8edc5445 | 289 | goto err_no_match; |
6775763a DT |
290 | } |
291 | ||
72f158fe BP |
292 | if (unlikely((intlv_en != 0x01) && |
293 | (intlv_en != 0x03) && | |
294 | (intlv_en != 0x07))) { | |
24f9a7fe | 295 | amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en); |
6775763a DT |
296 | return NULL; |
297 | } | |
298 | ||
299 | bits = (((u32) sys_addr) >> 12) & intlv_en; | |
300 | ||
301 | for (node_id = 0; ; ) { | |
7f19bf75 | 302 | if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) |
6775763a DT |
303 | break; /* intlv_sel field matches */ |
304 | ||
7f19bf75 | 305 | if (++node_id >= DRAM_RANGES) |
6775763a DT |
306 | goto err_no_match; |
307 | } | |
308 | ||
309 | /* sanity test for sys_addr */ | |
310 | if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) { | |
24f9a7fe BP |
311 | amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address" |
312 | "range for node %d with node interleaving enabled.\n", | |
313 | __func__, sys_addr, node_id); | |
6775763a DT |
314 | return NULL; |
315 | } | |
316 | ||
317 | found: | |
b487c33e | 318 | return edac_mc_find((int)node_id); |
6775763a DT |
319 | |
320 | err_no_match: | |
956b9ba1 JP |
321 | edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n", |
322 | (unsigned long)sys_addr); | |
6775763a DT |
323 | |
324 | return NULL; | |
325 | } | |
e2ce7255 DT |
326 | |
327 | /* | |
11c75ead BP |
328 | * compute the CS base address of the @csrow on the DRAM controller @dct. |
329 | * For details see F2x[5C:40] in the processor's BKDG | |
e2ce7255 | 330 | */ |
11c75ead BP |
331 | static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, |
332 | u64 *base, u64 *mask) | |
e2ce7255 | 333 | { |
11c75ead BP |
334 | u64 csbase, csmask, base_bits, mask_bits; |
335 | u8 addr_shift; | |
e2ce7255 | 336 | |
11c75ead BP |
337 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) { |
338 | csbase = pvt->csels[dct].csbases[csrow]; | |
339 | csmask = pvt->csels[dct].csmasks[csrow]; | |
340 | base_bits = GENMASK(21, 31) | GENMASK(9, 15); | |
341 | mask_bits = GENMASK(21, 29) | GENMASK(9, 15); | |
342 | addr_shift = 4; | |
343 | } else { | |
344 | csbase = pvt->csels[dct].csbases[csrow]; | |
345 | csmask = pvt->csels[dct].csmasks[csrow >> 1]; | |
346 | addr_shift = 8; | |
e2ce7255 | 347 | |
11c75ead BP |
348 | if (boot_cpu_data.x86 == 0x15) |
349 | base_bits = mask_bits = GENMASK(19,30) | GENMASK(5,13); | |
350 | else | |
351 | base_bits = mask_bits = GENMASK(19,28) | GENMASK(5,13); | |
352 | } | |
e2ce7255 | 353 | |
11c75ead | 354 | *base = (csbase & base_bits) << addr_shift; |
e2ce7255 | 355 | |
11c75ead BP |
356 | *mask = ~0ULL; |
357 | /* poke holes for the csmask */ | |
358 | *mask &= ~(mask_bits << addr_shift); | |
359 | /* OR them in */ | |
360 | *mask |= (csmask & mask_bits) << addr_shift; | |
e2ce7255 DT |
361 | } |
362 | ||
11c75ead BP |
363 | #define for_each_chip_select(i, dct, pvt) \ |
364 | for (i = 0; i < pvt->csels[dct].b_cnt; i++) | |
365 | ||
614ec9d8 BP |
366 | #define chip_select_base(i, dct, pvt) \ |
367 | pvt->csels[dct].csbases[i] | |
368 | ||
11c75ead BP |
369 | #define for_each_chip_select_mask(i, dct, pvt) \ |
370 | for (i = 0; i < pvt->csels[dct].m_cnt; i++) | |
371 | ||
e2ce7255 DT |
372 | /* |
373 | * @input_addr is an InputAddr associated with the node given by mci. Return the | |
374 | * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). | |
375 | */ | |
376 | static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) | |
377 | { | |
378 | struct amd64_pvt *pvt; | |
379 | int csrow; | |
380 | u64 base, mask; | |
381 | ||
382 | pvt = mci->pvt_info; | |
383 | ||
11c75ead BP |
384 | for_each_chip_select(csrow, 0, pvt) { |
385 | if (!csrow_enabled(csrow, 0, pvt)) | |
e2ce7255 DT |
386 | continue; |
387 | ||
11c75ead BP |
388 | get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); |
389 | ||
390 | mask = ~mask; | |
e2ce7255 DT |
391 | |
392 | if ((input_addr & mask) == (base & mask)) { | |
956b9ba1 JP |
393 | edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n", |
394 | (unsigned long)input_addr, csrow, | |
395 | pvt->mc_node_id); | |
e2ce7255 DT |
396 | |
397 | return csrow; | |
398 | } | |
399 | } | |
956b9ba1 JP |
400 | edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n", |
401 | (unsigned long)input_addr, pvt->mc_node_id); | |
e2ce7255 DT |
402 | |
403 | return -1; | |
404 | } | |
405 | ||
e2ce7255 DT |
406 | /* |
407 | * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) | |
408 | * for the node represented by mci. Info is passed back in *hole_base, | |
409 | * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if | |
410 | * info is invalid. Info may be invalid for either of the following reasons: | |
411 | * | |
412 | * - The revision of the node is not E or greater. In this case, the DRAM Hole | |
413 | * Address Register does not exist. | |
414 | * | |
415 | * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, | |
416 | * indicating that its contents are not valid. | |
417 | * | |
418 | * The values passed back in *hole_base, *hole_offset, and *hole_size are | |
419 | * complete 32-bit values despite the fact that the bitfields in the DHAR | |
420 | * only represent bits 31-24 of the base and offset values. | |
421 | */ | |
422 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, | |
423 | u64 *hole_offset, u64 *hole_size) | |
424 | { | |
425 | struct amd64_pvt *pvt = mci->pvt_info; | |
e2ce7255 DT |
426 | |
427 | /* only revE and later have the DRAM Hole Address Register */ | |
1433eb99 | 428 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) { |
956b9ba1 JP |
429 | edac_dbg(1, " revision %d for node %d does not support DHAR\n", |
430 | pvt->ext_model, pvt->mc_node_id); | |
e2ce7255 DT |
431 | return 1; |
432 | } | |
433 | ||
bc21fa57 | 434 | /* valid for Fam10h and above */ |
c8e518d5 | 435 | if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) { |
956b9ba1 | 436 | edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n"); |
e2ce7255 DT |
437 | return 1; |
438 | } | |
439 | ||
c8e518d5 | 440 | if (!dhar_valid(pvt)) { |
956b9ba1 JP |
441 | edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n", |
442 | pvt->mc_node_id); | |
e2ce7255 DT |
443 | return 1; |
444 | } | |
445 | ||
446 | /* This node has Memory Hoisting */ | |
447 | ||
448 | /* +------------------+--------------------+--------------------+----- | |
449 | * | memory | DRAM hole | relocated | | |
450 | * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | | |
451 | * | | | DRAM hole | | |
452 | * | | | [0x100000000, | | |
453 | * | | | (0x100000000+ | | |
454 | * | | | (0xffffffff-x))] | | |
455 | * +------------------+--------------------+--------------------+----- | |
456 | * | |
457 | * Above is a diagram of physical memory showing the DRAM hole and the | |
458 | * relocated addresses from the DRAM hole. As shown, the DRAM hole | |
459 | * starts at address x (the base address) and extends through address | |
460 | * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the | |
461 | * addresses in the hole so that they start at 0x100000000. | |
462 | */ | |
463 | ||
1f31677e BP |
464 | *hole_base = dhar_base(pvt); |
465 | *hole_size = (1ULL << 32) - *hole_base; | |
e2ce7255 DT |
466 | |
467 | if (boot_cpu_data.x86 > 0xf) | |
bc21fa57 | 468 | *hole_offset = f10_dhar_offset(pvt); |
e2ce7255 | 469 | else |
bc21fa57 | 470 | *hole_offset = k8_dhar_offset(pvt); |
e2ce7255 | 471 | |
956b9ba1 JP |
472 | edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", |
473 | pvt->mc_node_id, (unsigned long)*hole_base, | |
474 | (unsigned long)*hole_offset, (unsigned long)*hole_size); | |
e2ce7255 DT |
475 | |
476 | return 0; | |
477 | } | |
478 | EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); | |
479 | ||
93c2df58 DT |
480 | /* |
481 | * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is | |
482 | * assumed that sys_addr maps to the node given by mci. | |
483 | * | |
484 | * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section | |
485 | * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a | |
486 | * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, | |
487 | * then it is also involved in translating a SysAddr to a DramAddr. Sections | |
488 | * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. | |
489 | * These parts of the documentation are unclear. I interpret them as follows: | |
490 | * | |
491 | * When node n receives a SysAddr, it processes the SysAddr as follows: | |
492 | * | |
493 | * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM | |
494 | * Limit registers for node n. If the SysAddr is not within the range | |
495 | * specified by the base and limit values, then node n ignores the Sysaddr | |
496 | * (since it does not map to node n). Otherwise continue to step 2 below. | |
497 | * | |
498 | * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is | |
499 | * disabled so skip to step 3 below. Otherwise see if the SysAddr is within | |
500 | * the range of relocated addresses (starting at 0x100000000) from the DRAM | |
501 | * hole. If not, skip to step 3 below. Else get the value of the | |
502 | * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the | |
503 | * offset defined by this value from the SysAddr. | |
504 | * | |
505 | * 3. Obtain the base address for node n from the DRAMBase field of the DRAM | |
506 | * Base register for node n. To obtain the DramAddr, subtract the base | |
507 | * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). | |
508 | */ | |
509 | static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
510 | { | |
7f19bf75 | 511 | struct amd64_pvt *pvt = mci->pvt_info; |
93c2df58 | 512 | u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; |
1f31677e | 513 | int ret; |
93c2df58 | 514 | |
7f19bf75 | 515 | dram_base = get_dram_base(pvt, pvt->mc_node_id); |
93c2df58 DT |
516 | |
517 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
518 | &hole_size); | |
519 | if (!ret) { | |
1f31677e BP |
520 | if ((sys_addr >= (1ULL << 32)) && |
521 | (sys_addr < ((1ULL << 32) + hole_size))) { | |
93c2df58 DT |
522 | /* use DHAR to translate SysAddr to DramAddr */ |
523 | dram_addr = sys_addr - hole_offset; | |
524 | ||
956b9ba1 JP |
525 | edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n", |
526 | (unsigned long)sys_addr, | |
527 | (unsigned long)dram_addr); | |
93c2df58 DT |
528 | |
529 | return dram_addr; | |
530 | } | |
531 | } | |
532 | ||
533 | /* | |
534 | * Translate the SysAddr to a DramAddr as shown near the start of | |
535 | * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 | |
536 | * only deals with 40-bit values. Therefore we discard bits 63-40 of | |
537 | * sys_addr below. If bit 39 of sys_addr is 1 then the bits we | |
538 | * discard are all 1s. Otherwise the bits we discard are all 0s. See | |
539 | * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture | |
540 | * Programmer's Manual Volume 1 Application Programming. | |
541 | */ | |
f678b8cc | 542 | dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base; |
93c2df58 | 543 | |
956b9ba1 JP |
544 | edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n", |
545 | (unsigned long)sys_addr, (unsigned long)dram_addr); | |
93c2df58 DT |
546 | return dram_addr; |
547 | } | |
548 | ||
549 | /* | |
550 | * @intlv_en is the value of the IntlvEn field from a DRAM Base register | |
551 | * (section 3.4.4.1). Return the number of bits from a SysAddr that are used | |
552 | * for node interleaving. | |
553 | */ | |
554 | static int num_node_interleave_bits(unsigned intlv_en) | |
555 | { | |
556 | static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; | |
557 | int n; | |
558 | ||
559 | BUG_ON(intlv_en > 7); | |
560 | n = intlv_shift_table[intlv_en]; | |
561 | return n; | |
562 | } | |
563 | ||
564 | /* Translate the DramAddr given by @dram_addr to an InputAddr. */ | |
565 | static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
566 | { | |
567 | struct amd64_pvt *pvt; | |
568 | int intlv_shift; | |
569 | u64 input_addr; | |
570 | ||
571 | pvt = mci->pvt_info; | |
572 | ||
573 | /* | |
574 | * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
575 | * concerning translating a DramAddr to an InputAddr. | |
576 | */ | |
7f19bf75 | 577 | intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); |
f678b8cc BP |
578 | input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) + |
579 | (dram_addr & 0xfff); | |
93c2df58 | 580 | |
956b9ba1 JP |
581 | edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", |
582 | intlv_shift, (unsigned long)dram_addr, | |
583 | (unsigned long)input_addr); | |
93c2df58 DT |
584 | |
585 | return input_addr; | |
586 | } | |
587 | ||
588 | /* | |
589 | * Translate the SysAddr represented by @sys_addr to an InputAddr. It is | |
590 | * assumed that @sys_addr maps to the node given by mci. | |
591 | */ | |
592 | static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
593 | { | |
594 | u64 input_addr; | |
595 | ||
596 | input_addr = | |
597 | dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); | |
598 | ||
956b9ba1 JP |
599 | edac_dbg(2, "SysAdddr 0x%lx translates to InputAddr 0x%lx\n", |
600 | (unsigned long)sys_addr, (unsigned long)input_addr); | |
93c2df58 DT |
601 | |
602 | return input_addr; | |
603 | } | |
604 | ||
605 | ||
606 | /* | |
607 | * @input_addr is an InputAddr associated with the node represented by mci. | |
608 | * Translate @input_addr to a DramAddr and return the result. | |
609 | */ | |
610 | static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr) | |
611 | { | |
612 | struct amd64_pvt *pvt; | |
b487c33e | 613 | unsigned node_id, intlv_shift; |
93c2df58 DT |
614 | u64 bits, dram_addr; |
615 | u32 intlv_sel; | |
616 | ||
617 | /* | |
618 | * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
619 | * shows how to translate a DramAddr to an InputAddr. Here we reverse | |
620 | * this procedure. When translating from a DramAddr to an InputAddr, the | |
621 | * bits used for node interleaving are discarded. Here we recover these | |
622 | * bits from the IntlvSel field of the DRAM Limit register (section | |
623 | * 3.4.4.2) for the node that input_addr is associated with. | |
624 | */ | |
625 | pvt = mci->pvt_info; | |
626 | node_id = pvt->mc_node_id; | |
b487c33e BP |
627 | |
628 | BUG_ON(node_id > 7); | |
93c2df58 | 629 | |
7f19bf75 | 630 | intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); |
93c2df58 | 631 | if (intlv_shift == 0) { |
956b9ba1 JP |
632 | edac_dbg(1, " InputAddr 0x%lx translates to DramAddr of same value\n", |
633 | (unsigned long)input_addr); | |
93c2df58 DT |
634 | |
635 | return input_addr; | |
636 | } | |
637 | ||
f678b8cc BP |
638 | bits = ((input_addr & GENMASK(12, 35)) << intlv_shift) + |
639 | (input_addr & 0xfff); | |
93c2df58 | 640 | |
7f19bf75 | 641 | intlv_sel = dram_intlv_sel(pvt, node_id) & ((1 << intlv_shift) - 1); |
93c2df58 DT |
642 | dram_addr = bits + (intlv_sel << 12); |
643 | ||
956b9ba1 JP |
644 | edac_dbg(1, "InputAddr 0x%lx translates to DramAddr 0x%lx (%d node interleave bits)\n", |
645 | (unsigned long)input_addr, | |
646 | (unsigned long)dram_addr, intlv_shift); | |
93c2df58 DT |
647 | |
648 | return dram_addr; | |
649 | } | |
650 | ||
651 | /* | |
652 | * @dram_addr is a DramAddr that maps to the node represented by mci. Convert | |
653 | * @dram_addr to a SysAddr. | |
654 | */ | |
655 | static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
656 | { | |
657 | struct amd64_pvt *pvt = mci->pvt_info; | |
7f19bf75 | 658 | u64 hole_base, hole_offset, hole_size, base, sys_addr; |
93c2df58 DT |
659 | int ret = 0; |
660 | ||
661 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
662 | &hole_size); | |
663 | if (!ret) { | |
664 | if ((dram_addr >= hole_base) && | |
665 | (dram_addr < (hole_base + hole_size))) { | |
666 | sys_addr = dram_addr + hole_offset; | |
667 | ||
956b9ba1 JP |
668 | edac_dbg(1, "using DHAR to translate DramAddr 0x%lx to SysAddr 0x%lx\n", |
669 | (unsigned long)dram_addr, | |
670 | (unsigned long)sys_addr); | |
93c2df58 DT |
671 | |
672 | return sys_addr; | |
673 | } | |
674 | } | |
675 | ||
7f19bf75 | 676 | base = get_dram_base(pvt, pvt->mc_node_id); |
93c2df58 DT |
677 | sys_addr = dram_addr + base; |
678 | ||
679 | /* | |
680 | * The sys_addr we have computed up to this point is a 40-bit value | |
681 | * because the k8 deals with 40-bit values. However, the value we are | |
682 | * supposed to return is a full 64-bit physical address. The AMD | |
683 | * x86-64 architecture specifies that the most significant implemented | |
684 | * address bit through bit 63 of a physical address must be either all | |
685 | * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a | |
686 | * 64-bit value below. See section 3.4.2 of AMD publication 24592: | |
687 | * AMD x86-64 Architecture Programmer's Manual Volume 1 Application | |
688 | * Programming. | |
689 | */ | |
690 | sys_addr |= ~((sys_addr & (1ull << 39)) - 1); | |
691 | ||
956b9ba1 JP |
692 | edac_dbg(1, " Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", |
693 | pvt->mc_node_id, (unsigned long)dram_addr, | |
694 | (unsigned long)sys_addr); | |
93c2df58 DT |
695 | |
696 | return sys_addr; | |
697 | } | |
698 | ||
699 | /* | |
700 | * @input_addr is an InputAddr associated with the node given by mci. Translate | |
701 | * @input_addr to a SysAddr. | |
702 | */ | |
703 | static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci, | |
704 | u64 input_addr) | |
705 | { | |
706 | return dram_addr_to_sys_addr(mci, | |
707 | input_addr_to_dram_addr(mci, input_addr)); | |
708 | } | |
709 | ||
93c2df58 DT |
710 | /* Map the Error address to a PAGE and PAGE OFFSET. */ |
711 | static inline void error_address_to_page_and_offset(u64 error_address, | |
33ca0643 | 712 | struct err_info *err) |
93c2df58 | 713 | { |
33ca0643 BP |
714 | err->page = (u32) (error_address >> PAGE_SHIFT); |
715 | err->offset = ((u32) error_address) & ~PAGE_MASK; | |
93c2df58 DT |
716 | } |
717 | ||
718 | /* | |
719 | * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address | |
720 | * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers | |
721 | * of a node that detected an ECC memory error. mci represents the node that | |
722 | * the error address maps to (possibly different from the node that detected | |
723 | * the error). Return the number of the csrow that sys_addr maps to, or -1 on | |
724 | * error. | |
725 | */ | |
726 | static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) | |
727 | { | |
728 | int csrow; | |
729 | ||
730 | csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); | |
731 | ||
732 | if (csrow == -1) | |
24f9a7fe BP |
733 | amd64_mc_err(mci, "Failed to translate InputAddr to csrow for " |
734 | "address 0x%lx\n", (unsigned long)sys_addr); | |
93c2df58 DT |
735 | return csrow; |
736 | } | |
e2ce7255 | 737 | |
bfc04aec | 738 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); |
2da11654 | 739 | |
2da11654 DT |
740 | /* |
741 | * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs | |
742 | * are ECC capable. | |
743 | */ | |
1f6189ed | 744 | static unsigned long amd64_determine_edac_cap(struct amd64_pvt *pvt) |
2da11654 | 745 | { |
cb328507 | 746 | u8 bit; |
1f6189ed | 747 | unsigned long edac_cap = EDAC_FLAG_NONE; |
2da11654 | 748 | |
1433eb99 | 749 | bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F) |
2da11654 DT |
750 | ? 19 |
751 | : 17; | |
752 | ||
584fcff4 | 753 | if (pvt->dclr0 & BIT(bit)) |
2da11654 DT |
754 | edac_cap = EDAC_FLAG_SECDED; |
755 | ||
756 | return edac_cap; | |
757 | } | |
758 | ||
8c671751 | 759 | static void amd64_debug_display_dimm_sizes(struct amd64_pvt *, u8); |
2da11654 | 760 | |
68798e17 BP |
761 | static void amd64_dump_dramcfg_low(u32 dclr, int chan) |
762 | { | |
956b9ba1 | 763 | edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr); |
68798e17 | 764 | |
956b9ba1 JP |
765 | edac_dbg(1, " DIMM type: %sbuffered; all DIMMs support ECC: %s\n", |
766 | (dclr & BIT(16)) ? "un" : "", | |
767 | (dclr & BIT(19)) ? "yes" : "no"); | |
68798e17 | 768 | |
956b9ba1 JP |
769 | edac_dbg(1, " PAR/ERR parity: %s\n", |
770 | (dclr & BIT(8)) ? "enabled" : "disabled"); | |
68798e17 | 771 | |
cb328507 | 772 | if (boot_cpu_data.x86 == 0x10) |
956b9ba1 JP |
773 | edac_dbg(1, " DCT 128bit mode width: %s\n", |
774 | (dclr & BIT(11)) ? "128b" : "64b"); | |
68798e17 | 775 | |
956b9ba1 JP |
776 | edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", |
777 | (dclr & BIT(12)) ? "yes" : "no", | |
778 | (dclr & BIT(13)) ? "yes" : "no", | |
779 | (dclr & BIT(14)) ? "yes" : "no", | |
780 | (dclr & BIT(15)) ? "yes" : "no"); | |
68798e17 BP |
781 | } |
782 | ||
2da11654 | 783 | /* Display and decode various NB registers for debug purposes. */ |
b2b0c605 | 784 | static void dump_misc_regs(struct amd64_pvt *pvt) |
2da11654 | 785 | { |
956b9ba1 | 786 | edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); |
68798e17 | 787 | |
956b9ba1 JP |
788 | edac_dbg(1, " NB two channel DRAM capable: %s\n", |
789 | (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); | |
2da11654 | 790 | |
956b9ba1 JP |
791 | edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n", |
792 | (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", | |
793 | (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); | |
68798e17 BP |
794 | |
795 | amd64_dump_dramcfg_low(pvt->dclr0, 0); | |
2da11654 | 796 | |
956b9ba1 | 797 | edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); |
2da11654 | 798 | |
956b9ba1 JP |
799 | edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n", |
800 | pvt->dhar, dhar_base(pvt), | |
801 | (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt) | |
802 | : f10_dhar_offset(pvt)); | |
2da11654 | 803 | |
956b9ba1 | 804 | edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); |
2da11654 | 805 | |
8c671751 | 806 | amd64_debug_display_dimm_sizes(pvt, 0); |
4d796364 | 807 | |
8de1d91e | 808 | /* everything below this point is Fam10h and above */ |
4d796364 | 809 | if (boot_cpu_data.x86 == 0xf) |
2da11654 | 810 | return; |
4d796364 | 811 | |
8c671751 | 812 | amd64_debug_display_dimm_sizes(pvt, 1); |
2da11654 | 813 | |
a3b7db09 | 814 | amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4")); |
ad6a32e9 | 815 | |
8de1d91e | 816 | /* Only if NOT ganged does dclr1 have valid info */ |
68798e17 BP |
817 | if (!dct_ganging_enabled(pvt)) |
818 | amd64_dump_dramcfg_low(pvt->dclr1, 1); | |
2da11654 DT |
819 | } |
820 | ||
94be4bff | 821 | /* |
11c75ead | 822 | * see BKDG, F2x[1,0][5C:40], F2[1,0][6C:60] |
94be4bff | 823 | */ |
11c75ead | 824 | static void prep_chip_selects(struct amd64_pvt *pvt) |
94be4bff | 825 | { |
1433eb99 | 826 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) { |
11c75ead BP |
827 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; |
828 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; | |
9d858bb1 | 829 | } else { |
11c75ead BP |
830 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; |
831 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; | |
94be4bff DT |
832 | } |
833 | } | |
834 | ||
835 | /* | |
11c75ead | 836 | * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers |
94be4bff | 837 | */ |
b2b0c605 | 838 | static void read_dct_base_mask(struct amd64_pvt *pvt) |
94be4bff | 839 | { |
11c75ead | 840 | int cs; |
94be4bff | 841 | |
11c75ead | 842 | prep_chip_selects(pvt); |
94be4bff | 843 | |
11c75ead | 844 | for_each_chip_select(cs, 0, pvt) { |
71d2a32e BP |
845 | int reg0 = DCSB0 + (cs * 4); |
846 | int reg1 = DCSB1 + (cs * 4); | |
11c75ead BP |
847 | u32 *base0 = &pvt->csels[0].csbases[cs]; |
848 | u32 *base1 = &pvt->csels[1].csbases[cs]; | |
b2b0c605 | 849 | |
11c75ead | 850 | if (!amd64_read_dct_pci_cfg(pvt, reg0, base0)) |
956b9ba1 JP |
851 | edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n", |
852 | cs, *base0, reg0); | |
94be4bff | 853 | |
11c75ead BP |
854 | if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt)) |
855 | continue; | |
b2b0c605 | 856 | |
11c75ead | 857 | if (!amd64_read_dct_pci_cfg(pvt, reg1, base1)) |
956b9ba1 JP |
858 | edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n", |
859 | cs, *base1, reg1); | |
94be4bff DT |
860 | } |
861 | ||
11c75ead | 862 | for_each_chip_select_mask(cs, 0, pvt) { |
71d2a32e BP |
863 | int reg0 = DCSM0 + (cs * 4); |
864 | int reg1 = DCSM1 + (cs * 4); | |
11c75ead BP |
865 | u32 *mask0 = &pvt->csels[0].csmasks[cs]; |
866 | u32 *mask1 = &pvt->csels[1].csmasks[cs]; | |
b2b0c605 | 867 | |
11c75ead | 868 | if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0)) |
956b9ba1 JP |
869 | edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n", |
870 | cs, *mask0, reg0); | |
94be4bff | 871 | |
11c75ead BP |
872 | if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt)) |
873 | continue; | |
b2b0c605 | 874 | |
11c75ead | 875 | if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1)) |
956b9ba1 JP |
876 | edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n", |
877 | cs, *mask1, reg1); | |
94be4bff DT |
878 | } |
879 | } | |
880 | ||
24f9a7fe | 881 | static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt, int cs) |
94be4bff DT |
882 | { |
883 | enum mem_type type; | |
884 | ||
cb328507 BP |
885 | /* F15h supports only DDR3 */ |
886 | if (boot_cpu_data.x86 >= 0x15) | |
887 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; | |
888 | else if (boot_cpu_data.x86 == 0x10 || pvt->ext_model >= K8_REV_F) { | |
6b4c0bde BP |
889 | if (pvt->dchr0 & DDR3_MODE) |
890 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; | |
891 | else | |
892 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; | |
94be4bff | 893 | } else { |
94be4bff DT |
894 | type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; |
895 | } | |
896 | ||
24f9a7fe | 897 | amd64_info("CS%d: %s\n", cs, edac_mem_types[type]); |
94be4bff DT |
898 | |
899 | return type; | |
900 | } | |
901 | ||
cb328507 | 902 | /* Get the number of DCT channels the memory controller is using. */ |
ddff876d DT |
903 | static int k8_early_channel_count(struct amd64_pvt *pvt) |
904 | { | |
cb328507 | 905 | int flag; |
ddff876d | 906 | |
9f56da0e | 907 | if (pvt->ext_model >= K8_REV_F) |
ddff876d | 908 | /* RevF (NPT) and later */ |
41d8bfab | 909 | flag = pvt->dclr0 & WIDTH_128; |
9f56da0e | 910 | else |
ddff876d DT |
911 | /* RevE and earlier */ |
912 | flag = pvt->dclr0 & REVE_WIDTH_128; | |
ddff876d DT |
913 | |
914 | /* not used */ | |
915 | pvt->dclr1 = 0; | |
916 | ||
917 | return (flag) ? 2 : 1; | |
918 | } | |
919 | ||
70046624 BP |
920 | /* On F10h and later ErrAddr is MC4_ADDR[47:1] */ |
921 | static u64 get_error_address(struct mce *m) | |
ddff876d | 922 | { |
c1ae6830 BP |
923 | struct cpuinfo_x86 *c = &boot_cpu_data; |
924 | u64 addr; | |
70046624 BP |
925 | u8 start_bit = 1; |
926 | u8 end_bit = 47; | |
927 | ||
c1ae6830 | 928 | if (c->x86 == 0xf) { |
70046624 BP |
929 | start_bit = 3; |
930 | end_bit = 39; | |
931 | } | |
932 | ||
c1ae6830 BP |
933 | addr = m->addr & GENMASK(start_bit, end_bit); |
934 | ||
935 | /* | |
936 | * Erratum 637 workaround | |
937 | */ | |
938 | if (c->x86 == 0x15) { | |
939 | struct amd64_pvt *pvt; | |
940 | u64 cc6_base, tmp_addr; | |
941 | u32 tmp; | |
942 | u8 mce_nid, intlv_en; | |
943 | ||
944 | if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7) | |
945 | return addr; | |
946 | ||
947 | mce_nid = amd_get_nb_id(m->extcpu); | |
948 | pvt = mcis[mce_nid]->pvt_info; | |
949 | ||
950 | amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); | |
951 | intlv_en = tmp >> 21 & 0x7; | |
952 | ||
953 | /* add [47:27] + 3 trailing bits */ | |
954 | cc6_base = (tmp & GENMASK(0, 20)) << 3; | |
955 | ||
956 | /* reverse and add DramIntlvEn */ | |
957 | cc6_base |= intlv_en ^ 0x7; | |
958 | ||
959 | /* pin at [47:24] */ | |
960 | cc6_base <<= 24; | |
961 | ||
962 | if (!intlv_en) | |
963 | return cc6_base | (addr & GENMASK(0, 23)); | |
964 | ||
965 | amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); | |
966 | ||
967 | /* faster log2 */ | |
968 | tmp_addr = (addr & GENMASK(12, 23)) << __fls(intlv_en + 1); | |
969 | ||
970 | /* OR DramIntlvSel into bits [14:12] */ | |
971 | tmp_addr |= (tmp & GENMASK(21, 23)) >> 9; | |
972 | ||
973 | /* add remaining [11:0] bits from original MC4_ADDR */ | |
974 | tmp_addr |= addr & GENMASK(0, 11); | |
975 | ||
976 | return cc6_base | tmp_addr; | |
977 | } | |
978 | ||
979 | return addr; | |
ddff876d DT |
980 | } |
981 | ||
7f19bf75 | 982 | static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) |
ddff876d | 983 | { |
f08e457c | 984 | struct cpuinfo_x86 *c = &boot_cpu_data; |
71d2a32e | 985 | int off = range << 3; |
ddff876d | 986 | |
7f19bf75 BP |
987 | amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); |
988 | amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); | |
ddff876d | 989 | |
f08e457c | 990 | if (c->x86 == 0xf) |
7f19bf75 | 991 | return; |
ddff876d | 992 | |
7f19bf75 BP |
993 | if (!dram_rw(pvt, range)) |
994 | return; | |
ddff876d | 995 | |
7f19bf75 BP |
996 | amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); |
997 | amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); | |
f08e457c BP |
998 | |
999 | /* Factor in CC6 save area by reading dst node's limit reg */ | |
1000 | if (c->x86 == 0x15) { | |
1001 | struct pci_dev *f1 = NULL; | |
1002 | u8 nid = dram_dst_node(pvt, range); | |
1003 | u32 llim; | |
1004 | ||
1005 | f1 = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0x18 + nid, 1)); | |
1006 | if (WARN_ON(!f1)) | |
1007 | return; | |
1008 | ||
1009 | amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim); | |
1010 | ||
1011 | pvt->ranges[range].lim.lo &= GENMASK(0, 15); | |
1012 | ||
1013 | /* {[39:27],111b} */ | |
1014 | pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; | |
1015 | ||
1016 | pvt->ranges[range].lim.hi &= GENMASK(0, 7); | |
1017 | ||
1018 | /* [47:40] */ | |
1019 | pvt->ranges[range].lim.hi |= llim >> 13; | |
1020 | ||
1021 | pci_dev_put(f1); | |
1022 | } | |
ddff876d DT |
1023 | } |
1024 | ||
f192c7b1 | 1025 | static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, |
33ca0643 | 1026 | struct err_info *err) |
ddff876d | 1027 | { |
f192c7b1 | 1028 | struct amd64_pvt *pvt = mci->pvt_info; |
ddff876d | 1029 | |
33ca0643 | 1030 | error_address_to_page_and_offset(sys_addr, err); |
ab5a503c MCC |
1031 | |
1032 | /* | |
1033 | * Find out which node the error address belongs to. This may be | |
1034 | * different from the node that detected the error. | |
1035 | */ | |
33ca0643 BP |
1036 | err->src_mci = find_mc_by_sys_addr(mci, sys_addr); |
1037 | if (!err->src_mci) { | |
ab5a503c MCC |
1038 | amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n", |
1039 | (unsigned long)sys_addr); | |
33ca0643 | 1040 | err->err_code = ERR_NODE; |
ab5a503c MCC |
1041 | return; |
1042 | } | |
1043 | ||
1044 | /* Now map the sys_addr to a CSROW */ | |
33ca0643 BP |
1045 | err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr); |
1046 | if (err->csrow < 0) { | |
1047 | err->err_code = ERR_CSROW; | |
ab5a503c MCC |
1048 | return; |
1049 | } | |
1050 | ||
ddff876d | 1051 | /* CHIPKILL enabled */ |
f192c7b1 | 1052 | if (pvt->nbcfg & NBCFG_CHIPKILL) { |
33ca0643 BP |
1053 | err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); |
1054 | if (err->channel < 0) { | |
ddff876d DT |
1055 | /* |
1056 | * Syndrome didn't map, so we don't know which of the | |
1057 | * 2 DIMMs is in error. So we need to ID 'both' of them | |
1058 | * as suspect. | |
1059 | */ | |
33ca0643 | 1060 | amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - " |
ab5a503c | 1061 | "possible error reporting race\n", |
33ca0643 BP |
1062 | err->syndrome); |
1063 | err->err_code = ERR_CHANNEL; | |
ddff876d DT |
1064 | return; |
1065 | } | |
1066 | } else { | |
1067 | /* | |
1068 | * non-chipkill ecc mode | |
1069 | * | |
1070 | * The k8 documentation is unclear about how to determine the | |
1071 | * channel number when using non-chipkill memory. This method | |
1072 | * was obtained from email communication with someone at AMD. | |
1073 | * (Wish the email was placed in this comment - norsk) | |
1074 | */ | |
33ca0643 | 1075 | err->channel = ((sys_addr & BIT(3)) != 0); |
ddff876d | 1076 | } |
ddff876d DT |
1077 | } |
1078 | ||
41d8bfab | 1079 | static int ddr2_cs_size(unsigned i, bool dct_width) |
ddff876d | 1080 | { |
41d8bfab | 1081 | unsigned shift = 0; |
ddff876d | 1082 | |
41d8bfab BP |
1083 | if (i <= 2) |
1084 | shift = i; | |
1085 | else if (!(i & 0x1)) | |
1086 | shift = i >> 1; | |
1433eb99 | 1087 | else |
41d8bfab | 1088 | shift = (i + 1) >> 1; |
ddff876d | 1089 | |
41d8bfab BP |
1090 | return 128 << (shift + !!dct_width); |
1091 | } | |
1092 | ||
1093 | static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
1094 | unsigned cs_mode) | |
1095 | { | |
1096 | u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; | |
1097 | ||
1098 | if (pvt->ext_model >= K8_REV_F) { | |
1099 | WARN_ON(cs_mode > 11); | |
1100 | return ddr2_cs_size(cs_mode, dclr & WIDTH_128); | |
1101 | } | |
1102 | else if (pvt->ext_model >= K8_REV_D) { | |
11b0a314 | 1103 | unsigned diff; |
41d8bfab BP |
1104 | WARN_ON(cs_mode > 10); |
1105 | ||
11b0a314 BP |
1106 | /* |
1107 | * the below calculation, besides trying to win an obfuscated C | |
1108 | * contest, maps cs_mode values to DIMM chip select sizes. The | |
1109 | * mappings are: | |
1110 | * | |
1111 | * cs_mode CS size (mb) | |
1112 | * ======= ============ | |
1113 | * 0 32 | |
1114 | * 1 64 | |
1115 | * 2 128 | |
1116 | * 3 128 | |
1117 | * 4 256 | |
1118 | * 5 512 | |
1119 | * 6 256 | |
1120 | * 7 512 | |
1121 | * 8 1024 | |
1122 | * 9 1024 | |
1123 | * 10 2048 | |
1124 | * | |
1125 | * Basically, it calculates a value with which to shift the | |
1126 | * smallest CS size of 32MB. | |
1127 | * | |
1128 | * ddr[23]_cs_size have a similar purpose. | |
1129 | */ | |
1130 | diff = cs_mode/3 + (unsigned)(cs_mode > 5); | |
1131 | ||
1132 | return 32 << (cs_mode - diff); | |
41d8bfab BP |
1133 | } |
1134 | else { | |
1135 | WARN_ON(cs_mode > 6); | |
1136 | return 32 << cs_mode; | |
1137 | } | |
ddff876d DT |
1138 | } |
1139 | ||
1afd3c98 DT |
1140 | /* |
1141 | * Get the number of DCT channels in use. | |
1142 | * | |
1143 | * Return: | |
1144 | * number of Memory Channels in operation | |
1145 | * Pass back: | |
1146 | * contents of the DCL0_LOW register | |
1147 | */ | |
7d20d14d | 1148 | static int f1x_early_channel_count(struct amd64_pvt *pvt) |
1afd3c98 | 1149 | { |
6ba5dcdc | 1150 | int i, j, channels = 0; |
1afd3c98 | 1151 | |
7d20d14d | 1152 | /* On F10h, if we are in 128 bit mode, then we are using 2 channels */ |
41d8bfab | 1153 | if (boot_cpu_data.x86 == 0x10 && (pvt->dclr0 & WIDTH_128)) |
7d20d14d | 1154 | return 2; |
1afd3c98 DT |
1155 | |
1156 | /* | |
d16149e8 BP |
1157 | * Need to check if in unganged mode: In such, there are 2 channels, |
1158 | * but they are not in 128 bit mode and thus the above 'dclr0' status | |
1159 | * bit will be OFF. | |
1afd3c98 DT |
1160 | * |
1161 | * Need to check DCT0[0] and DCT1[0] to see if only one of them has | |
1162 | * their CSEnable bit on. If so, then SINGLE DIMM case. | |
1163 | */ | |
956b9ba1 | 1164 | edac_dbg(0, "Data width is not 128 bits - need more decoding\n"); |
ddff876d | 1165 | |
1afd3c98 DT |
1166 | /* |
1167 | * Check DRAM Bank Address Mapping values for each DIMM to see if there | |
1168 | * is more than just one DIMM present in unganged mode. Need to check | |
1169 | * both controllers since DIMMs can be placed in either one. | |
1170 | */ | |
525a1b20 BP |
1171 | for (i = 0; i < 2; i++) { |
1172 | u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); | |
1afd3c98 | 1173 | |
57a30854 WW |
1174 | for (j = 0; j < 4; j++) { |
1175 | if (DBAM_DIMM(j, dbam) > 0) { | |
1176 | channels++; | |
1177 | break; | |
1178 | } | |
1179 | } | |
1afd3c98 DT |
1180 | } |
1181 | ||
d16149e8 BP |
1182 | if (channels > 2) |
1183 | channels = 2; | |
1184 | ||
24f9a7fe | 1185 | amd64_info("MCT channel count: %d\n", channels); |
1afd3c98 DT |
1186 | |
1187 | return channels; | |
1afd3c98 DT |
1188 | } |
1189 | ||
41d8bfab | 1190 | static int ddr3_cs_size(unsigned i, bool dct_width) |
1afd3c98 | 1191 | { |
41d8bfab BP |
1192 | unsigned shift = 0; |
1193 | int cs_size = 0; | |
1194 | ||
1195 | if (i == 0 || i == 3 || i == 4) | |
1196 | cs_size = -1; | |
1197 | else if (i <= 2) | |
1198 | shift = i; | |
1199 | else if (i == 12) | |
1200 | shift = 7; | |
1201 | else if (!(i & 0x1)) | |
1202 | shift = i >> 1; | |
1203 | else | |
1204 | shift = (i + 1) >> 1; | |
1205 | ||
1206 | if (cs_size != -1) | |
1207 | cs_size = (128 * (1 << !!dct_width)) << shift; | |
1208 | ||
1209 | return cs_size; | |
1210 | } | |
1211 | ||
1212 | static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
1213 | unsigned cs_mode) | |
1214 | { | |
1215 | u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; | |
1216 | ||
1217 | WARN_ON(cs_mode > 11); | |
1433eb99 BP |
1218 | |
1219 | if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) | |
41d8bfab | 1220 | return ddr3_cs_size(cs_mode, dclr & WIDTH_128); |
1433eb99 | 1221 | else |
41d8bfab BP |
1222 | return ddr2_cs_size(cs_mode, dclr & WIDTH_128); |
1223 | } | |
1224 | ||
1225 | /* | |
1226 | * F15h supports only 64bit DCT interfaces | |
1227 | */ | |
1228 | static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
1229 | unsigned cs_mode) | |
1230 | { | |
1231 | WARN_ON(cs_mode > 12); | |
1433eb99 | 1232 | |
41d8bfab | 1233 | return ddr3_cs_size(cs_mode, false); |
1afd3c98 DT |
1234 | } |
1235 | ||
5a5d2371 | 1236 | static void read_dram_ctl_register(struct amd64_pvt *pvt) |
6163b5d4 | 1237 | { |
6163b5d4 | 1238 | |
5a5d2371 BP |
1239 | if (boot_cpu_data.x86 == 0xf) |
1240 | return; | |
1241 | ||
78da121e | 1242 | if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) { |
956b9ba1 JP |
1243 | edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n", |
1244 | pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); | |
72381bd5 | 1245 | |
956b9ba1 JP |
1246 | edac_dbg(0, " DCTs operate in %s mode\n", |
1247 | (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); | |
72381bd5 BP |
1248 | |
1249 | if (!dct_ganging_enabled(pvt)) | |
956b9ba1 JP |
1250 | edac_dbg(0, " Address range split per DCT: %s\n", |
1251 | (dct_high_range_enabled(pvt) ? "yes" : "no")); | |
72381bd5 | 1252 | |
956b9ba1 JP |
1253 | edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n", |
1254 | (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), | |
1255 | (dct_memory_cleared(pvt) ? "yes" : "no")); | |
72381bd5 | 1256 | |
956b9ba1 JP |
1257 | edac_dbg(0, " channel interleave: %s, " |
1258 | "interleave bits selector: 0x%x\n", | |
1259 | (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), | |
1260 | dct_sel_interleave_addr(pvt)); | |
6163b5d4 DT |
1261 | } |
1262 | ||
78da121e | 1263 | amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi); |
6163b5d4 DT |
1264 | } |
1265 | ||
f71d0a05 | 1266 | /* |
229a7a11 | 1267 | * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory |
f71d0a05 DT |
1268 | * Interleaving Modes. |
1269 | */ | |
b15f0fca | 1270 | static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, |
229a7a11 | 1271 | bool hi_range_sel, u8 intlv_en) |
6163b5d4 | 1272 | { |
151fa71c | 1273 | u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; |
6163b5d4 DT |
1274 | |
1275 | if (dct_ganging_enabled(pvt)) | |
229a7a11 | 1276 | return 0; |
6163b5d4 | 1277 | |
229a7a11 BP |
1278 | if (hi_range_sel) |
1279 | return dct_sel_high; | |
6163b5d4 | 1280 | |
229a7a11 BP |
1281 | /* |
1282 | * see F2x110[DctSelIntLvAddr] - channel interleave mode | |
1283 | */ | |
1284 | if (dct_interleave_enabled(pvt)) { | |
1285 | u8 intlv_addr = dct_sel_interleave_addr(pvt); | |
1286 | ||
1287 | /* return DCT select function: 0=DCT0, 1=DCT1 */ | |
1288 | if (!intlv_addr) | |
1289 | return sys_addr >> 6 & 1; | |
1290 | ||
1291 | if (intlv_addr & 0x2) { | |
1292 | u8 shift = intlv_addr & 0x1 ? 9 : 6; | |
1293 | u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; | |
1294 | ||
1295 | return ((sys_addr >> shift) & 1) ^ temp; | |
1296 | } | |
1297 | ||
1298 | return (sys_addr >> (12 + hweight8(intlv_en))) & 1; | |
1299 | } | |
1300 | ||
1301 | if (dct_high_range_enabled(pvt)) | |
1302 | return ~dct_sel_high & 1; | |
6163b5d4 DT |
1303 | |
1304 | return 0; | |
1305 | } | |
1306 | ||
c8e518d5 | 1307 | /* Convert the sys_addr to the normalized DCT address */ |
e761359a | 1308 | static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, unsigned range, |
c8e518d5 BP |
1309 | u64 sys_addr, bool hi_rng, |
1310 | u32 dct_sel_base_addr) | |
6163b5d4 DT |
1311 | { |
1312 | u64 chan_off; | |
c8e518d5 BP |
1313 | u64 dram_base = get_dram_base(pvt, range); |
1314 | u64 hole_off = f10_dhar_offset(pvt); | |
c8e518d5 | 1315 | u64 dct_sel_base_off = (pvt->dct_sel_hi & 0xFFFFFC00) << 16; |
6163b5d4 | 1316 | |
c8e518d5 BP |
1317 | if (hi_rng) { |
1318 | /* | |
1319 | * if | |
1320 | * base address of high range is below 4Gb | |
1321 | * (bits [47:27] at [31:11]) | |
1322 | * DRAM address space on this DCT is hoisted above 4Gb && | |
1323 | * sys_addr > 4Gb | |
1324 | * | |
1325 | * remove hole offset from sys_addr | |
1326 | * else | |
1327 | * remove high range offset from sys_addr | |
1328 | */ | |
1329 | if ((!(dct_sel_base_addr >> 16) || | |
1330 | dct_sel_base_addr < dhar_base(pvt)) && | |
972ea17a | 1331 | dhar_valid(pvt) && |
c8e518d5 | 1332 | (sys_addr >= BIT_64(32))) |
bc21fa57 | 1333 | chan_off = hole_off; |
6163b5d4 DT |
1334 | else |
1335 | chan_off = dct_sel_base_off; | |
1336 | } else { | |
c8e518d5 BP |
1337 | /* |
1338 | * if | |
1339 | * we have a valid hole && | |
1340 | * sys_addr > 4Gb | |
1341 | * | |
1342 | * remove hole | |
1343 | * else | |
1344 | * remove dram base to normalize to DCT address | |
1345 | */ | |
972ea17a | 1346 | if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) |
bc21fa57 | 1347 | chan_off = hole_off; |
6163b5d4 | 1348 | else |
c8e518d5 | 1349 | chan_off = dram_base; |
6163b5d4 DT |
1350 | } |
1351 | ||
c8e518d5 | 1352 | return (sys_addr & GENMASK(6,47)) - (chan_off & GENMASK(23,47)); |
6163b5d4 DT |
1353 | } |
1354 | ||
6163b5d4 DT |
1355 | /* |
1356 | * checks if the csrow passed in is marked as SPARED, if so returns the new | |
1357 | * spare row | |
1358 | */ | |
11c75ead | 1359 | static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) |
6163b5d4 | 1360 | { |
614ec9d8 BP |
1361 | int tmp_cs; |
1362 | ||
1363 | if (online_spare_swap_done(pvt, dct) && | |
1364 | csrow == online_spare_bad_dramcs(pvt, dct)) { | |
1365 | ||
1366 | for_each_chip_select(tmp_cs, dct, pvt) { | |
1367 | if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { | |
1368 | csrow = tmp_cs; | |
1369 | break; | |
1370 | } | |
1371 | } | |
6163b5d4 DT |
1372 | } |
1373 | return csrow; | |
1374 | } | |
1375 | ||
1376 | /* | |
1377 | * Iterate over the DRAM DCT "base" and "mask" registers looking for a | |
1378 | * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' | |
1379 | * | |
1380 | * Return: | |
1381 | * -EINVAL: NOT FOUND | |
1382 | * 0..csrow = Chip-Select Row | |
1383 | */ | |
b15f0fca | 1384 | static int f1x_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct) |
6163b5d4 DT |
1385 | { |
1386 | struct mem_ctl_info *mci; | |
1387 | struct amd64_pvt *pvt; | |
11c75ead | 1388 | u64 cs_base, cs_mask; |
6163b5d4 DT |
1389 | int cs_found = -EINVAL; |
1390 | int csrow; | |
1391 | ||
cc4d8860 | 1392 | mci = mcis[nid]; |
6163b5d4 DT |
1393 | if (!mci) |
1394 | return cs_found; | |
1395 | ||
1396 | pvt = mci->pvt_info; | |
1397 | ||
956b9ba1 | 1398 | edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct); |
6163b5d4 | 1399 | |
11c75ead BP |
1400 | for_each_chip_select(csrow, dct, pvt) { |
1401 | if (!csrow_enabled(csrow, dct, pvt)) | |
6163b5d4 DT |
1402 | continue; |
1403 | ||
11c75ead | 1404 | get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); |
6163b5d4 | 1405 | |
956b9ba1 JP |
1406 | edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n", |
1407 | csrow, cs_base, cs_mask); | |
6163b5d4 | 1408 | |
11c75ead | 1409 | cs_mask = ~cs_mask; |
6163b5d4 | 1410 | |
956b9ba1 JP |
1411 | edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n", |
1412 | (in_addr & cs_mask), (cs_base & cs_mask)); | |
6163b5d4 | 1413 | |
11c75ead BP |
1414 | if ((in_addr & cs_mask) == (cs_base & cs_mask)) { |
1415 | cs_found = f10_process_possible_spare(pvt, dct, csrow); | |
6163b5d4 | 1416 | |
956b9ba1 | 1417 | edac_dbg(1, " MATCH csrow=%d\n", cs_found); |
6163b5d4 DT |
1418 | break; |
1419 | } | |
1420 | } | |
1421 | return cs_found; | |
1422 | } | |
1423 | ||
95b0ef55 BP |
1424 | /* |
1425 | * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is | |
1426 | * swapped with a region located at the bottom of memory so that the GPU can use | |
1427 | * the interleaved region and thus two channels. | |
1428 | */ | |
b15f0fca | 1429 | static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) |
95b0ef55 BP |
1430 | { |
1431 | u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr; | |
1432 | ||
1433 | if (boot_cpu_data.x86 == 0x10) { | |
1434 | /* only revC3 and revE have that feature */ | |
1435 | if (boot_cpu_data.x86_model < 4 || | |
1436 | (boot_cpu_data.x86_model < 0xa && | |
1437 | boot_cpu_data.x86_mask < 3)) | |
1438 | return sys_addr; | |
1439 | } | |
1440 | ||
1441 | amd64_read_dct_pci_cfg(pvt, SWAP_INTLV_REG, &swap_reg); | |
1442 | ||
1443 | if (!(swap_reg & 0x1)) | |
1444 | return sys_addr; | |
1445 | ||
1446 | swap_base = (swap_reg >> 3) & 0x7f; | |
1447 | swap_limit = (swap_reg >> 11) & 0x7f; | |
1448 | rgn_size = (swap_reg >> 20) & 0x7f; | |
1449 | tmp_addr = sys_addr >> 27; | |
1450 | ||
1451 | if (!(sys_addr >> 34) && | |
1452 | (((tmp_addr >= swap_base) && | |
1453 | (tmp_addr <= swap_limit)) || | |
1454 | (tmp_addr < rgn_size))) | |
1455 | return sys_addr ^ (u64)swap_base << 27; | |
1456 | ||
1457 | return sys_addr; | |
1458 | } | |
1459 | ||
f71d0a05 | 1460 | /* For a given @dram_range, check if @sys_addr falls within it. */ |
e761359a | 1461 | static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, |
33ca0643 | 1462 | u64 sys_addr, int *chan_sel) |
f71d0a05 | 1463 | { |
229a7a11 | 1464 | int cs_found = -EINVAL; |
c8e518d5 | 1465 | u64 chan_addr; |
5d4b58e8 | 1466 | u32 dct_sel_base; |
11c75ead | 1467 | u8 channel; |
229a7a11 | 1468 | bool high_range = false; |
f71d0a05 | 1469 | |
7f19bf75 | 1470 | u8 node_id = dram_dst_node(pvt, range); |
229a7a11 | 1471 | u8 intlv_en = dram_intlv_en(pvt, range); |
7f19bf75 | 1472 | u32 intlv_sel = dram_intlv_sel(pvt, range); |
f71d0a05 | 1473 | |
956b9ba1 JP |
1474 | edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n", |
1475 | range, sys_addr, get_dram_limit(pvt, range)); | |
f71d0a05 | 1476 | |
355fba60 BP |
1477 | if (dhar_valid(pvt) && |
1478 | dhar_base(pvt) <= sys_addr && | |
1479 | sys_addr < BIT_64(32)) { | |
1480 | amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n", | |
1481 | sys_addr); | |
1482 | return -EINVAL; | |
1483 | } | |
1484 | ||
f030ddfb | 1485 | if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en))) |
f71d0a05 DT |
1486 | return -EINVAL; |
1487 | ||
b15f0fca | 1488 | sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); |
95b0ef55 | 1489 | |
f71d0a05 DT |
1490 | dct_sel_base = dct_sel_baseaddr(pvt); |
1491 | ||
1492 | /* | |
1493 | * check whether addresses >= DctSelBaseAddr[47:27] are to be used to | |
1494 | * select between DCT0 and DCT1. | |
1495 | */ | |
1496 | if (dct_high_range_enabled(pvt) && | |
1497 | !dct_ganging_enabled(pvt) && | |
1498 | ((sys_addr >> 27) >= (dct_sel_base >> 11))) | |
229a7a11 | 1499 | high_range = true; |
f71d0a05 | 1500 | |
b15f0fca | 1501 | channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); |
f71d0a05 | 1502 | |
b15f0fca | 1503 | chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, |
c8e518d5 | 1504 | high_range, dct_sel_base); |
f71d0a05 | 1505 | |
e2f79dbd BP |
1506 | /* Remove node interleaving, see F1x120 */ |
1507 | if (intlv_en) | |
1508 | chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) | | |
1509 | (chan_addr & 0xfff); | |
f71d0a05 | 1510 | |
5d4b58e8 | 1511 | /* remove channel interleave */ |
f71d0a05 DT |
1512 | if (dct_interleave_enabled(pvt) && |
1513 | !dct_high_range_enabled(pvt) && | |
1514 | !dct_ganging_enabled(pvt)) { | |
5d4b58e8 BP |
1515 | |
1516 | if (dct_sel_interleave_addr(pvt) != 1) { | |
1517 | if (dct_sel_interleave_addr(pvt) == 0x3) | |
1518 | /* hash 9 */ | |
1519 | chan_addr = ((chan_addr >> 10) << 9) | | |
1520 | (chan_addr & 0x1ff); | |
1521 | else | |
1522 | /* A[6] or hash 6 */ | |
1523 | chan_addr = ((chan_addr >> 7) << 6) | | |
1524 | (chan_addr & 0x3f); | |
1525 | } else | |
1526 | /* A[12] */ | |
1527 | chan_addr = ((chan_addr >> 13) << 12) | | |
1528 | (chan_addr & 0xfff); | |
f71d0a05 DT |
1529 | } |
1530 | ||
956b9ba1 | 1531 | edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr); |
f71d0a05 | 1532 | |
b15f0fca | 1533 | cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel); |
f71d0a05 | 1534 | |
33ca0643 | 1535 | if (cs_found >= 0) |
f71d0a05 | 1536 | *chan_sel = channel; |
33ca0643 | 1537 | |
f71d0a05 DT |
1538 | return cs_found; |
1539 | } | |
1540 | ||
b15f0fca | 1541 | static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr, |
33ca0643 | 1542 | int *chan_sel) |
f71d0a05 | 1543 | { |
e761359a BP |
1544 | int cs_found = -EINVAL; |
1545 | unsigned range; | |
f71d0a05 | 1546 | |
7f19bf75 | 1547 | for (range = 0; range < DRAM_RANGES; range++) { |
f71d0a05 | 1548 | |
7f19bf75 | 1549 | if (!dram_rw(pvt, range)) |
f71d0a05 DT |
1550 | continue; |
1551 | ||
7f19bf75 BP |
1552 | if ((get_dram_base(pvt, range) <= sys_addr) && |
1553 | (get_dram_limit(pvt, range) >= sys_addr)) { | |
f71d0a05 | 1554 | |
b15f0fca | 1555 | cs_found = f1x_match_to_this_node(pvt, range, |
33ca0643 | 1556 | sys_addr, chan_sel); |
f71d0a05 DT |
1557 | if (cs_found >= 0) |
1558 | break; | |
1559 | } | |
1560 | } | |
1561 | return cs_found; | |
1562 | } | |
1563 | ||
1564 | /* | |
bdc30a0c BP |
1565 | * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps |
1566 | * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW). | |
f71d0a05 | 1567 | * |
bdc30a0c BP |
1568 | * The @sys_addr is usually an error address received from the hardware |
1569 | * (MCX_ADDR). | |
f71d0a05 | 1570 | */ |
b15f0fca | 1571 | static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, |
33ca0643 | 1572 | struct err_info *err) |
f71d0a05 DT |
1573 | { |
1574 | struct amd64_pvt *pvt = mci->pvt_info; | |
f71d0a05 | 1575 | |
33ca0643 | 1576 | error_address_to_page_and_offset(sys_addr, err); |
ab5a503c | 1577 | |
33ca0643 BP |
1578 | err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); |
1579 | if (err->csrow < 0) { | |
1580 | err->err_code = ERR_CSROW; | |
bdc30a0c BP |
1581 | return; |
1582 | } | |
1583 | ||
bdc30a0c BP |
1584 | /* |
1585 | * We need the syndromes for channel detection only when we're | |
1586 | * ganged. Otherwise @chan should already contain the channel at | |
1587 | * this point. | |
1588 | */ | |
a97fa68e | 1589 | if (dct_ganging_enabled(pvt)) |
33ca0643 | 1590 | err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); |
f71d0a05 DT |
1591 | } |
1592 | ||
f71d0a05 | 1593 | /* |
8566c4df | 1594 | * debug routine to display the memory sizes of all logical DIMMs and its |
cb328507 | 1595 | * CSROWs |
f71d0a05 | 1596 | */ |
8c671751 | 1597 | static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) |
f71d0a05 | 1598 | { |
bb89f5a0 | 1599 | int dimm, size0, size1; |
525a1b20 BP |
1600 | u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; |
1601 | u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; | |
f71d0a05 | 1602 | |
8566c4df BP |
1603 | if (boot_cpu_data.x86 == 0xf) { |
1604 | /* K8 families < revF not supported yet */ | |
1433eb99 | 1605 | if (pvt->ext_model < K8_REV_F) |
8566c4df BP |
1606 | return; |
1607 | else | |
1608 | WARN_ON(ctrl != 0); | |
1609 | } | |
1610 | ||
4d796364 | 1611 | dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 : pvt->dbam0; |
11c75ead BP |
1612 | dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases |
1613 | : pvt->csels[0].csbases; | |
f71d0a05 | 1614 | |
956b9ba1 JP |
1615 | edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", |
1616 | ctrl, dbam); | |
f71d0a05 | 1617 | |
8566c4df BP |
1618 | edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl); |
1619 | ||
f71d0a05 DT |
1620 | /* Dump memory sizes for DIMM and its CSROWs */ |
1621 | for (dimm = 0; dimm < 4; dimm++) { | |
1622 | ||
1623 | size0 = 0; | |
11c75ead | 1624 | if (dcsb[dimm*2] & DCSB_CS_ENABLE) |
41d8bfab BP |
1625 | size0 = pvt->ops->dbam_to_cs(pvt, ctrl, |
1626 | DBAM_DIMM(dimm, dbam)); | |
f71d0a05 DT |
1627 | |
1628 | size1 = 0; | |
11c75ead | 1629 | if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE) |
41d8bfab BP |
1630 | size1 = pvt->ops->dbam_to_cs(pvt, ctrl, |
1631 | DBAM_DIMM(dimm, dbam)); | |
f71d0a05 | 1632 | |
24f9a7fe | 1633 | amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n", |
bb89f5a0 BP |
1634 | dimm * 2, size0, |
1635 | dimm * 2 + 1, size1); | |
f71d0a05 DT |
1636 | } |
1637 | } | |
1638 | ||
4d37607a DT |
1639 | static struct amd64_family_type amd64_family_types[] = { |
1640 | [K8_CPUS] = { | |
0092b20d | 1641 | .ctl_name = "K8", |
8d5b5d9c BP |
1642 | .f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, |
1643 | .f3_id = PCI_DEVICE_ID_AMD_K8_NB_MISC, | |
4d37607a | 1644 | .ops = { |
1433eb99 | 1645 | .early_channel_count = k8_early_channel_count, |
1433eb99 BP |
1646 | .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, |
1647 | .dbam_to_cs = k8_dbam_to_chip_select, | |
b2b0c605 | 1648 | .read_dct_pci_cfg = k8_read_dct_pci_cfg, |
4d37607a DT |
1649 | } |
1650 | }, | |
1651 | [F10_CPUS] = { | |
0092b20d | 1652 | .ctl_name = "F10h", |
8d5b5d9c BP |
1653 | .f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP, |
1654 | .f3_id = PCI_DEVICE_ID_AMD_10H_NB_MISC, | |
4d37607a | 1655 | .ops = { |
7d20d14d | 1656 | .early_channel_count = f1x_early_channel_count, |
b15f0fca | 1657 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, |
1433eb99 | 1658 | .dbam_to_cs = f10_dbam_to_chip_select, |
b2b0c605 BP |
1659 | .read_dct_pci_cfg = f10_read_dct_pci_cfg, |
1660 | } | |
1661 | }, | |
1662 | [F15_CPUS] = { | |
1663 | .ctl_name = "F15h", | |
df71a053 BP |
1664 | .f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1, |
1665 | .f3_id = PCI_DEVICE_ID_AMD_15H_NB_F3, | |
b2b0c605 | 1666 | .ops = { |
7d20d14d | 1667 | .early_channel_count = f1x_early_channel_count, |
b15f0fca | 1668 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, |
41d8bfab | 1669 | .dbam_to_cs = f15_dbam_to_chip_select, |
b2b0c605 | 1670 | .read_dct_pci_cfg = f15_read_dct_pci_cfg, |
4d37607a DT |
1671 | } |
1672 | }, | |
4d37607a DT |
1673 | }; |
1674 | ||
1675 | static struct pci_dev *pci_get_related_function(unsigned int vendor, | |
1676 | unsigned int device, | |
1677 | struct pci_dev *related) | |
1678 | { | |
1679 | struct pci_dev *dev = NULL; | |
1680 | ||
1681 | dev = pci_get_device(vendor, device, dev); | |
1682 | while (dev) { | |
1683 | if ((dev->bus->number == related->bus->number) && | |
1684 | (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) | |
1685 | break; | |
1686 | dev = pci_get_device(vendor, device, dev); | |
1687 | } | |
1688 | ||
1689 | return dev; | |
1690 | } | |
1691 | ||
b1289d6f | 1692 | /* |
bfc04aec BP |
1693 | * These are tables of eigenvectors (one per line) which can be used for the |
1694 | * construction of the syndrome tables. The modified syndrome search algorithm | |
1695 | * uses those to find the symbol in error and thus the DIMM. | |
b1289d6f | 1696 | * |
bfc04aec | 1697 | * Algorithm courtesy of Ross LaFetra from AMD. |
b1289d6f | 1698 | */ |
bfc04aec BP |
1699 | static u16 x4_vectors[] = { |
1700 | 0x2f57, 0x1afe, 0x66cc, 0xdd88, | |
1701 | 0x11eb, 0x3396, 0x7f4c, 0xeac8, | |
1702 | 0x0001, 0x0002, 0x0004, 0x0008, | |
1703 | 0x1013, 0x3032, 0x4044, 0x8088, | |
1704 | 0x106b, 0x30d6, 0x70fc, 0xe0a8, | |
1705 | 0x4857, 0xc4fe, 0x13cc, 0x3288, | |
1706 | 0x1ac5, 0x2f4a, 0x5394, 0xa1e8, | |
1707 | 0x1f39, 0x251e, 0xbd6c, 0x6bd8, | |
1708 | 0x15c1, 0x2a42, 0x89ac, 0x4758, | |
1709 | 0x2b03, 0x1602, 0x4f0c, 0xca08, | |
1710 | 0x1f07, 0x3a0e, 0x6b04, 0xbd08, | |
1711 | 0x8ba7, 0x465e, 0x244c, 0x1cc8, | |
1712 | 0x2b87, 0x164e, 0x642c, 0xdc18, | |
1713 | 0x40b9, 0x80de, 0x1094, 0x20e8, | |
1714 | 0x27db, 0x1eb6, 0x9dac, 0x7b58, | |
1715 | 0x11c1, 0x2242, 0x84ac, 0x4c58, | |
1716 | 0x1be5, 0x2d7a, 0x5e34, 0xa718, | |
1717 | 0x4b39, 0x8d1e, 0x14b4, 0x28d8, | |
1718 | 0x4c97, 0xc87e, 0x11fc, 0x33a8, | |
1719 | 0x8e97, 0x497e, 0x2ffc, 0x1aa8, | |
1720 | 0x16b3, 0x3d62, 0x4f34, 0x8518, | |
1721 | 0x1e2f, 0x391a, 0x5cac, 0xf858, | |
1722 | 0x1d9f, 0x3b7a, 0x572c, 0xfe18, | |
1723 | 0x15f5, 0x2a5a, 0x5264, 0xa3b8, | |
1724 | 0x1dbb, 0x3b66, 0x715c, 0xe3f8, | |
1725 | 0x4397, 0xc27e, 0x17fc, 0x3ea8, | |
1726 | 0x1617, 0x3d3e, 0x6464, 0xb8b8, | |
1727 | 0x23ff, 0x12aa, 0xab6c, 0x56d8, | |
1728 | 0x2dfb, 0x1ba6, 0x913c, 0x7328, | |
1729 | 0x185d, 0x2ca6, 0x7914, 0x9e28, | |
1730 | 0x171b, 0x3e36, 0x7d7c, 0xebe8, | |
1731 | 0x4199, 0x82ee, 0x19f4, 0x2e58, | |
1732 | 0x4807, 0xc40e, 0x130c, 0x3208, | |
1733 | 0x1905, 0x2e0a, 0x5804, 0xac08, | |
1734 | 0x213f, 0x132a, 0xadfc, 0x5ba8, | |
1735 | 0x19a9, 0x2efe, 0xb5cc, 0x6f88, | |
b1289d6f DT |
1736 | }; |
1737 | ||
bfc04aec BP |
1738 | static u16 x8_vectors[] = { |
1739 | 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480, | |
1740 | 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80, | |
1741 | 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80, | |
1742 | 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80, | |
1743 | 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780, | |
1744 | 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080, | |
1745 | 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080, | |
1746 | 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080, | |
1747 | 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80, | |
1748 | 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580, | |
1749 | 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880, | |
1750 | 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280, | |
1751 | 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180, | |
1752 | 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580, | |
1753 | 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280, | |
1754 | 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180, | |
1755 | 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080, | |
1756 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
1757 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, | |
1758 | }; | |
1759 | ||
d34a6ecd BP |
1760 | static int decode_syndrome(u16 syndrome, u16 *vectors, unsigned num_vecs, |
1761 | unsigned v_dim) | |
b1289d6f | 1762 | { |
bfc04aec BP |
1763 | unsigned int i, err_sym; |
1764 | ||
1765 | for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) { | |
1766 | u16 s = syndrome; | |
d34a6ecd BP |
1767 | unsigned v_idx = err_sym * v_dim; |
1768 | unsigned v_end = (err_sym + 1) * v_dim; | |
bfc04aec BP |
1769 | |
1770 | /* walk over all 16 bits of the syndrome */ | |
1771 | for (i = 1; i < (1U << 16); i <<= 1) { | |
1772 | ||
1773 | /* if bit is set in that eigenvector... */ | |
1774 | if (v_idx < v_end && vectors[v_idx] & i) { | |
1775 | u16 ev_comp = vectors[v_idx++]; | |
1776 | ||
1777 | /* ... and bit set in the modified syndrome, */ | |
1778 | if (s & i) { | |
1779 | /* remove it. */ | |
1780 | s ^= ev_comp; | |
4d37607a | 1781 | |
bfc04aec BP |
1782 | if (!s) |
1783 | return err_sym; | |
1784 | } | |
b1289d6f | 1785 | |
bfc04aec BP |
1786 | } else if (s & i) |
1787 | /* can't get to zero, move to next symbol */ | |
1788 | break; | |
1789 | } | |
b1289d6f DT |
1790 | } |
1791 | ||
956b9ba1 | 1792 | edac_dbg(0, "syndrome(%x) not found\n", syndrome); |
b1289d6f DT |
1793 | return -1; |
1794 | } | |
d27bf6fa | 1795 | |
bfc04aec BP |
1796 | static int map_err_sym_to_channel(int err_sym, int sym_size) |
1797 | { | |
1798 | if (sym_size == 4) | |
1799 | switch (err_sym) { | |
1800 | case 0x20: | |
1801 | case 0x21: | |
1802 | return 0; | |
1803 | break; | |
1804 | case 0x22: | |
1805 | case 0x23: | |
1806 | return 1; | |
1807 | break; | |
1808 | default: | |
1809 | return err_sym >> 4; | |
1810 | break; | |
1811 | } | |
1812 | /* x8 symbols */ | |
1813 | else | |
1814 | switch (err_sym) { | |
1815 | /* imaginary bits not in a DIMM */ | |
1816 | case 0x10: | |
1817 | WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n", | |
1818 | err_sym); | |
1819 | return -1; | |
1820 | break; | |
1821 | ||
1822 | case 0x11: | |
1823 | return 0; | |
1824 | break; | |
1825 | case 0x12: | |
1826 | return 1; | |
1827 | break; | |
1828 | default: | |
1829 | return err_sym >> 3; | |
1830 | break; | |
1831 | } | |
1832 | return -1; | |
1833 | } | |
1834 | ||
1835 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome) | |
1836 | { | |
1837 | struct amd64_pvt *pvt = mci->pvt_info; | |
ad6a32e9 BP |
1838 | int err_sym = -1; |
1839 | ||
a3b7db09 | 1840 | if (pvt->ecc_sym_sz == 8) |
ad6a32e9 BP |
1841 | err_sym = decode_syndrome(syndrome, x8_vectors, |
1842 | ARRAY_SIZE(x8_vectors), | |
a3b7db09 BP |
1843 | pvt->ecc_sym_sz); |
1844 | else if (pvt->ecc_sym_sz == 4) | |
ad6a32e9 BP |
1845 | err_sym = decode_syndrome(syndrome, x4_vectors, |
1846 | ARRAY_SIZE(x4_vectors), | |
a3b7db09 | 1847 | pvt->ecc_sym_sz); |
ad6a32e9 | 1848 | else { |
a3b7db09 | 1849 | amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); |
ad6a32e9 | 1850 | return err_sym; |
bfc04aec | 1851 | } |
ad6a32e9 | 1852 | |
a3b7db09 | 1853 | return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); |
bfc04aec BP |
1854 | } |
1855 | ||
33ca0643 BP |
1856 | static void __log_bus_error(struct mem_ctl_info *mci, struct err_info *err, |
1857 | u8 ecc_type) | |
d27bf6fa | 1858 | { |
33ca0643 BP |
1859 | enum hw_event_mc_err_type err_type; |
1860 | const char *string; | |
d27bf6fa | 1861 | |
33ca0643 BP |
1862 | if (ecc_type == 2) |
1863 | err_type = HW_EVENT_ERR_CORRECTED; | |
1864 | else if (ecc_type == 1) | |
1865 | err_type = HW_EVENT_ERR_UNCORRECTED; | |
1866 | else { | |
1867 | WARN(1, "Something is rotten in the state of Denmark.\n"); | |
d27bf6fa DT |
1868 | return; |
1869 | } | |
1870 | ||
33ca0643 BP |
1871 | switch (err->err_code) { |
1872 | case DECODE_OK: | |
1873 | string = ""; | |
1874 | break; | |
1875 | case ERR_NODE: | |
1876 | string = "Failed to map error addr to a node"; | |
1877 | break; | |
1878 | case ERR_CSROW: | |
1879 | string = "Failed to map error addr to a csrow"; | |
1880 | break; | |
1881 | case ERR_CHANNEL: | |
1882 | string = "unknown syndrome - possible error reporting race"; | |
1883 | break; | |
1884 | default: | |
1885 | string = "WTF error"; | |
1886 | break; | |
d27bf6fa | 1887 | } |
33ca0643 BP |
1888 | |
1889 | edac_mc_handle_error(err_type, mci, 1, | |
1890 | err->page, err->offset, err->syndrome, | |
1891 | err->csrow, err->channel, -1, | |
1892 | string, ""); | |
d27bf6fa DT |
1893 | } |
1894 | ||
549d042d | 1895 | static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, |
f192c7b1 | 1896 | struct mce *m) |
d27bf6fa | 1897 | { |
33ca0643 | 1898 | struct amd64_pvt *pvt = mci->pvt_info; |
f192c7b1 | 1899 | u8 ecc_type = (m->status >> 45) & 0x3; |
66fed2d4 BP |
1900 | u8 xec = XEC(m->status, 0x1f); |
1901 | u16 ec = EC(m->status); | |
33ca0643 BP |
1902 | u64 sys_addr; |
1903 | struct err_info err; | |
d27bf6fa | 1904 | |
66fed2d4 | 1905 | /* Bail out early if this was an 'observed' error */ |
5980bb9c | 1906 | if (PP(ec) == NBSL_PP_OBS) |
b70ef010 | 1907 | return; |
d27bf6fa | 1908 | |
ecaf5606 BP |
1909 | /* Do only ECC errors */ |
1910 | if (xec && xec != F10_NBSL_EXT_ERR_ECC) | |
d27bf6fa | 1911 | return; |
d27bf6fa | 1912 | |
33ca0643 BP |
1913 | memset(&err, 0, sizeof(err)); |
1914 | ||
1915 | sys_addr = get_error_address(m); | |
1916 | ||
ecaf5606 | 1917 | if (ecc_type == 2) |
33ca0643 BP |
1918 | err.syndrome = extract_syndrome(m->status); |
1919 | ||
1920 | pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); | |
1921 | ||
1922 | __log_bus_error(mci, &err, ecc_type); | |
d27bf6fa DT |
1923 | } |
1924 | ||
b0b07a2b | 1925 | void amd64_decode_bus_error(int node_id, struct mce *m) |
d27bf6fa | 1926 | { |
b0b07a2b | 1927 | __amd64_decode_bus_error(mcis[node_id], m); |
d27bf6fa | 1928 | } |
d27bf6fa | 1929 | |
0ec449ee | 1930 | /* |
8d5b5d9c | 1931 | * Use pvt->F2 which contains the F2 CPU PCI device to get the related |
bbd0c1f6 | 1932 | * F1 (AddrMap) and F3 (Misc) devices. Return negative value on error. |
0ec449ee | 1933 | */ |
360b7f3c | 1934 | static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id) |
0ec449ee | 1935 | { |
0ec449ee | 1936 | /* Reserve the ADDRESS MAP Device */ |
8d5b5d9c BP |
1937 | pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2); |
1938 | if (!pvt->F1) { | |
24f9a7fe BP |
1939 | amd64_err("error address map device not found: " |
1940 | "vendor %x device 0x%x (broken BIOS?)\n", | |
1941 | PCI_VENDOR_ID_AMD, f1_id); | |
bbd0c1f6 | 1942 | return -ENODEV; |
0ec449ee DT |
1943 | } |
1944 | ||
1945 | /* Reserve the MISC Device */ | |
8d5b5d9c BP |
1946 | pvt->F3 = pci_get_related_function(pvt->F2->vendor, f3_id, pvt->F2); |
1947 | if (!pvt->F3) { | |
1948 | pci_dev_put(pvt->F1); | |
1949 | pvt->F1 = NULL; | |
0ec449ee | 1950 | |
24f9a7fe BP |
1951 | amd64_err("error F3 device not found: " |
1952 | "vendor %x device 0x%x (broken BIOS?)\n", | |
1953 | PCI_VENDOR_ID_AMD, f3_id); | |
0ec449ee | 1954 | |
bbd0c1f6 | 1955 | return -ENODEV; |
0ec449ee | 1956 | } |
956b9ba1 JP |
1957 | edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); |
1958 | edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); | |
1959 | edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); | |
0ec449ee DT |
1960 | |
1961 | return 0; | |
1962 | } | |
1963 | ||
360b7f3c | 1964 | static void free_mc_sibling_devs(struct amd64_pvt *pvt) |
0ec449ee | 1965 | { |
8d5b5d9c BP |
1966 | pci_dev_put(pvt->F1); |
1967 | pci_dev_put(pvt->F3); | |
0ec449ee DT |
1968 | } |
1969 | ||
1970 | /* | |
1971 | * Retrieve the hardware registers of the memory controller (this includes the | |
1972 | * 'Address Map' and 'Misc' device regs) | |
1973 | */ | |
360b7f3c | 1974 | static void read_mc_regs(struct amd64_pvt *pvt) |
0ec449ee | 1975 | { |
a3b7db09 | 1976 | struct cpuinfo_x86 *c = &boot_cpu_data; |
0ec449ee | 1977 | u64 msr_val; |
ad6a32e9 | 1978 | u32 tmp; |
e761359a | 1979 | unsigned range; |
0ec449ee DT |
1980 | |
1981 | /* | |
1982 | * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since | |
1983 | * those are Read-As-Zero | |
1984 | */ | |
e97f8bb8 | 1985 | rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); |
956b9ba1 | 1986 | edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); |
0ec449ee DT |
1987 | |
1988 | /* check first whether TOP_MEM2 is enabled */ | |
1989 | rdmsrl(MSR_K8_SYSCFG, msr_val); | |
1990 | if (msr_val & (1U << 21)) { | |
e97f8bb8 | 1991 | rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); |
956b9ba1 | 1992 | edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); |
0ec449ee | 1993 | } else |
956b9ba1 | 1994 | edac_dbg(0, " TOP_MEM2 disabled\n"); |
0ec449ee | 1995 | |
5980bb9c | 1996 | amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); |
0ec449ee | 1997 | |
5a5d2371 | 1998 | read_dram_ctl_register(pvt); |
0ec449ee | 1999 | |
7f19bf75 BP |
2000 | for (range = 0; range < DRAM_RANGES; range++) { |
2001 | u8 rw; | |
0ec449ee | 2002 | |
7f19bf75 BP |
2003 | /* read settings for this DRAM range */ |
2004 | read_dram_base_limit_regs(pvt, range); | |
2005 | ||
2006 | rw = dram_rw(pvt, range); | |
2007 | if (!rw) | |
2008 | continue; | |
2009 | ||
956b9ba1 JP |
2010 | edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n", |
2011 | range, | |
2012 | get_dram_base(pvt, range), | |
2013 | get_dram_limit(pvt, range)); | |
7f19bf75 | 2014 | |
956b9ba1 JP |
2015 | edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n", |
2016 | dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", | |
2017 | (rw & 0x1) ? "R" : "-", | |
2018 | (rw & 0x2) ? "W" : "-", | |
2019 | dram_intlv_sel(pvt, range), | |
2020 | dram_dst_node(pvt, range)); | |
0ec449ee DT |
2021 | } |
2022 | ||
b2b0c605 | 2023 | read_dct_base_mask(pvt); |
0ec449ee | 2024 | |
bc21fa57 | 2025 | amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); |
525a1b20 | 2026 | amd64_read_dct_pci_cfg(pvt, DBAM0, &pvt->dbam0); |
0ec449ee | 2027 | |
8d5b5d9c | 2028 | amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); |
0ec449ee | 2029 | |
cb328507 BP |
2030 | amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0); |
2031 | amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0); | |
0ec449ee | 2032 | |
78da121e | 2033 | if (!dct_ganging_enabled(pvt)) { |
cb328507 BP |
2034 | amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1); |
2035 | amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1); | |
0ec449ee | 2036 | } |
ad6a32e9 | 2037 | |
a3b7db09 BP |
2038 | pvt->ecc_sym_sz = 4; |
2039 | ||
2040 | if (c->x86 >= 0x10) { | |
b2b0c605 | 2041 | amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); |
525a1b20 | 2042 | amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1); |
ad6a32e9 | 2043 | |
a3b7db09 BP |
2044 | /* F10h, revD and later can do x8 ECC too */ |
2045 | if ((c->x86 > 0x10 || c->x86_model > 7) && tmp & BIT(25)) | |
2046 | pvt->ecc_sym_sz = 8; | |
2047 | } | |
b2b0c605 | 2048 | dump_misc_regs(pvt); |
0ec449ee DT |
2049 | } |
2050 | ||
2051 | /* | |
2052 | * NOTE: CPU Revision Dependent code | |
2053 | * | |
2054 | * Input: | |
11c75ead | 2055 | * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1) |
0ec449ee DT |
2056 | * k8 private pointer to --> |
2057 | * DRAM Bank Address mapping register | |
2058 | * node_id | |
2059 | * DCL register where dual_channel_active is | |
2060 | * | |
2061 | * The DBAM register consists of 4 sets of 4 bits each definitions: | |
2062 | * | |
2063 | * Bits: CSROWs | |
2064 | * 0-3 CSROWs 0 and 1 | |
2065 | * 4-7 CSROWs 2 and 3 | |
2066 | * 8-11 CSROWs 4 and 5 | |
2067 | * 12-15 CSROWs 6 and 7 | |
2068 | * | |
2069 | * Values range from: 0 to 15 | |
2070 | * The meaning of the values depends on CPU revision and dual-channel state, | |
2071 | * see relevant BKDG more info. | |
2072 | * | |
2073 | * The memory controller provides for total of only 8 CSROWs in its current | |
2074 | * architecture. Each "pair" of CSROWs normally represents just one DIMM in | |
2075 | * single channel or two (2) DIMMs in dual channel mode. | |
2076 | * | |
2077 | * The following code logic collapses the various tables for CSROW based on CPU | |
2078 | * revision. | |
2079 | * | |
2080 | * Returns: | |
2081 | * The number of PAGE_SIZE pages on the specified CSROW number it | |
2082 | * encompasses | |
2083 | * | |
2084 | */ | |
41d8bfab | 2085 | static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) |
0ec449ee | 2086 | { |
1433eb99 | 2087 | u32 cs_mode, nr_pages; |
f92cae45 | 2088 | u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; |
0ec449ee DT |
2089 | |
2090 | /* | |
2091 | * The math on this doesn't look right on the surface because x/2*4 can | |
2092 | * be simplified to x*2 but this expression makes use of the fact that | |
2093 | * it is integral math where 1/2=0. This intermediate value becomes the | |
2094 | * number of bits to shift the DBAM register to extract the proper CSROW | |
2095 | * field. | |
2096 | */ | |
0a5dfc31 | 2097 | cs_mode = DBAM_DIMM(csrow_nr / 2, dbam); |
0ec449ee | 2098 | |
41d8bfab | 2099 | nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT); |
0ec449ee | 2100 | |
956b9ba1 JP |
2101 | edac_dbg(0, " (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode); |
2102 | edac_dbg(0, " nr_pages/channel= %u channel-count = %d\n", | |
2103 | nr_pages, pvt->channel_count); | |
0ec449ee DT |
2104 | |
2105 | return nr_pages; | |
2106 | } | |
2107 | ||
2108 | /* | |
2109 | * Initialize the array of csrow attribute instances, based on the values | |
2110 | * from pci config hardware registers. | |
2111 | */ | |
360b7f3c | 2112 | static int init_csrows(struct mem_ctl_info *mci) |
0ec449ee DT |
2113 | { |
2114 | struct csrow_info *csrow; | |
de3910eb | 2115 | struct dimm_info *dimm; |
2299ef71 | 2116 | struct amd64_pvt *pvt = mci->pvt_info; |
5e2af0c0 | 2117 | u64 base, mask; |
2299ef71 | 2118 | u32 val; |
084a4fcc MCC |
2119 | int i, j, empty = 1; |
2120 | enum mem_type mtype; | |
2121 | enum edac_type edac_mode; | |
a895bf8b | 2122 | int nr_pages = 0; |
0ec449ee | 2123 | |
a97fa68e | 2124 | amd64_read_pci_cfg(pvt->F3, NBCFG, &val); |
0ec449ee | 2125 | |
2299ef71 | 2126 | pvt->nbcfg = val; |
0ec449ee | 2127 | |
956b9ba1 JP |
2128 | edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n", |
2129 | pvt->mc_node_id, val, | |
2130 | !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE)); | |
0ec449ee | 2131 | |
11c75ead | 2132 | for_each_chip_select(i, 0, pvt) { |
de3910eb | 2133 | csrow = mci->csrows[i]; |
0ec449ee | 2134 | |
f92cae45 | 2135 | if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) { |
956b9ba1 JP |
2136 | edac_dbg(1, "----CSROW %d VALID for MC node %d\n", |
2137 | i, pvt->mc_node_id); | |
0ec449ee DT |
2138 | continue; |
2139 | } | |
2140 | ||
0ec449ee | 2141 | empty = 0; |
f92cae45 | 2142 | if (csrow_enabled(i, 0, pvt)) |
a895bf8b | 2143 | nr_pages = amd64_csrow_nr_pages(pvt, 0, i); |
f92cae45 | 2144 | if (csrow_enabled(i, 1, pvt)) |
a895bf8b | 2145 | nr_pages += amd64_csrow_nr_pages(pvt, 1, i); |
11c75ead BP |
2146 | |
2147 | get_cs_base_and_mask(pvt, i, 0, &base, &mask); | |
0ec449ee DT |
2148 | /* 8 bytes of resolution */ |
2149 | ||
084a4fcc | 2150 | mtype = amd64_determine_memory_type(pvt, i); |
0ec449ee | 2151 | |
956b9ba1 JP |
2152 | edac_dbg(1, " for MC node %d csrow %d:\n", pvt->mc_node_id, i); |
2153 | edac_dbg(1, " nr_pages: %u\n", | |
2154 | nr_pages * pvt->channel_count); | |
0ec449ee DT |
2155 | |
2156 | /* | |
2157 | * determine whether CHIPKILL or JUST ECC or NO ECC is operating | |
2158 | */ | |
a97fa68e | 2159 | if (pvt->nbcfg & NBCFG_ECC_ENABLE) |
084a4fcc MCC |
2160 | edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) ? |
2161 | EDAC_S4ECD4ED : EDAC_SECDED; | |
0ec449ee | 2162 | else |
084a4fcc MCC |
2163 | edac_mode = EDAC_NONE; |
2164 | ||
2165 | for (j = 0; j < pvt->channel_count; j++) { | |
de3910eb MCC |
2166 | dimm = csrow->channels[j]->dimm; |
2167 | dimm->mtype = mtype; | |
2168 | dimm->edac_mode = edac_mode; | |
2169 | dimm->nr_pages = nr_pages; | |
084a4fcc | 2170 | } |
0ec449ee DT |
2171 | } |
2172 | ||
2173 | return empty; | |
2174 | } | |
d27bf6fa | 2175 | |
f6d6ae96 | 2176 | /* get all cores on this DCT */ |
b487c33e | 2177 | static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, unsigned nid) |
f6d6ae96 BP |
2178 | { |
2179 | int cpu; | |
2180 | ||
2181 | for_each_online_cpu(cpu) | |
2182 | if (amd_get_nb_id(cpu) == nid) | |
2183 | cpumask_set_cpu(cpu, mask); | |
2184 | } | |
2185 | ||
2186 | /* check MCG_CTL on all the cpus on this node */ | |
b487c33e | 2187 | static bool amd64_nb_mce_bank_enabled_on_node(unsigned nid) |
f6d6ae96 BP |
2188 | { |
2189 | cpumask_var_t mask; | |
50542251 | 2190 | int cpu, nbe; |
f6d6ae96 BP |
2191 | bool ret = false; |
2192 | ||
2193 | if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { | |
24f9a7fe | 2194 | amd64_warn("%s: Error allocating mask\n", __func__); |
f6d6ae96 BP |
2195 | return false; |
2196 | } | |
2197 | ||
2198 | get_cpus_on_this_dct_cpumask(mask, nid); | |
2199 | ||
f6d6ae96 BP |
2200 | rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs); |
2201 | ||
2202 | for_each_cpu(cpu, mask) { | |
50542251 | 2203 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
5980bb9c | 2204 | nbe = reg->l & MSR_MCGCTL_NBE; |
f6d6ae96 | 2205 | |
956b9ba1 JP |
2206 | edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", |
2207 | cpu, reg->q, | |
2208 | (nbe ? "enabled" : "disabled")); | |
f6d6ae96 BP |
2209 | |
2210 | if (!nbe) | |
2211 | goto out; | |
f6d6ae96 BP |
2212 | } |
2213 | ret = true; | |
2214 | ||
2215 | out: | |
f6d6ae96 BP |
2216 | free_cpumask_var(mask); |
2217 | return ret; | |
2218 | } | |
2219 | ||
2299ef71 | 2220 | static int toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on) |
f6d6ae96 BP |
2221 | { |
2222 | cpumask_var_t cmask; | |
50542251 | 2223 | int cpu; |
f6d6ae96 BP |
2224 | |
2225 | if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) { | |
24f9a7fe | 2226 | amd64_warn("%s: error allocating mask\n", __func__); |
f6d6ae96 BP |
2227 | return false; |
2228 | } | |
2229 | ||
ae7bb7c6 | 2230 | get_cpus_on_this_dct_cpumask(cmask, nid); |
f6d6ae96 | 2231 | |
f6d6ae96 BP |
2232 | rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); |
2233 | ||
2234 | for_each_cpu(cpu, cmask) { | |
2235 | ||
50542251 BP |
2236 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
2237 | ||
f6d6ae96 | 2238 | if (on) { |
5980bb9c | 2239 | if (reg->l & MSR_MCGCTL_NBE) |
ae7bb7c6 | 2240 | s->flags.nb_mce_enable = 1; |
f6d6ae96 | 2241 | |
5980bb9c | 2242 | reg->l |= MSR_MCGCTL_NBE; |
f6d6ae96 BP |
2243 | } else { |
2244 | /* | |
d95cf4de | 2245 | * Turn off NB MCE reporting only when it was off before |
f6d6ae96 | 2246 | */ |
ae7bb7c6 | 2247 | if (!s->flags.nb_mce_enable) |
5980bb9c | 2248 | reg->l &= ~MSR_MCGCTL_NBE; |
f6d6ae96 | 2249 | } |
f6d6ae96 BP |
2250 | } |
2251 | wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); | |
2252 | ||
f6d6ae96 BP |
2253 | free_cpumask_var(cmask); |
2254 | ||
2255 | return 0; | |
2256 | } | |
2257 | ||
2299ef71 BP |
2258 | static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid, |
2259 | struct pci_dev *F3) | |
f9431992 | 2260 | { |
2299ef71 | 2261 | bool ret = true; |
c9f4f26e | 2262 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
f9431992 | 2263 | |
2299ef71 BP |
2264 | if (toggle_ecc_err_reporting(s, nid, ON)) { |
2265 | amd64_warn("Error enabling ECC reporting over MCGCTL!\n"); | |
2266 | return false; | |
2267 | } | |
2268 | ||
c9f4f26e | 2269 | amd64_read_pci_cfg(F3, NBCTL, &value); |
f9431992 | 2270 | |
ae7bb7c6 BP |
2271 | s->old_nbctl = value & mask; |
2272 | s->nbctl_valid = true; | |
f9431992 DT |
2273 | |
2274 | value |= mask; | |
c9f4f26e | 2275 | amd64_write_pci_cfg(F3, NBCTL, value); |
f9431992 | 2276 | |
a97fa68e | 2277 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2278 | |
956b9ba1 JP |
2279 | edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", |
2280 | nid, value, !!(value & NBCFG_ECC_ENABLE)); | |
f9431992 | 2281 | |
a97fa68e | 2282 | if (!(value & NBCFG_ECC_ENABLE)) { |
24f9a7fe | 2283 | amd64_warn("DRAM ECC disabled on this node, enabling...\n"); |
f9431992 | 2284 | |
ae7bb7c6 | 2285 | s->flags.nb_ecc_prev = 0; |
d95cf4de | 2286 | |
f9431992 | 2287 | /* Attempt to turn on DRAM ECC Enable */ |
a97fa68e BP |
2288 | value |= NBCFG_ECC_ENABLE; |
2289 | amd64_write_pci_cfg(F3, NBCFG, value); | |
f9431992 | 2290 | |
a97fa68e | 2291 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2292 | |
a97fa68e | 2293 | if (!(value & NBCFG_ECC_ENABLE)) { |
24f9a7fe BP |
2294 | amd64_warn("Hardware rejected DRAM ECC enable," |
2295 | "check memory DIMM configuration.\n"); | |
2299ef71 | 2296 | ret = false; |
f9431992 | 2297 | } else { |
24f9a7fe | 2298 | amd64_info("Hardware accepted DRAM ECC Enable\n"); |
f9431992 | 2299 | } |
d95cf4de | 2300 | } else { |
ae7bb7c6 | 2301 | s->flags.nb_ecc_prev = 1; |
f9431992 | 2302 | } |
d95cf4de | 2303 | |
956b9ba1 JP |
2304 | edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", |
2305 | nid, value, !!(value & NBCFG_ECC_ENABLE)); | |
f9431992 | 2306 | |
2299ef71 | 2307 | return ret; |
f9431992 DT |
2308 | } |
2309 | ||
360b7f3c BP |
2310 | static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid, |
2311 | struct pci_dev *F3) | |
f9431992 | 2312 | { |
c9f4f26e BP |
2313 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
2314 | ||
f9431992 | 2315 | |
ae7bb7c6 | 2316 | if (!s->nbctl_valid) |
f9431992 DT |
2317 | return; |
2318 | ||
c9f4f26e | 2319 | amd64_read_pci_cfg(F3, NBCTL, &value); |
f9431992 | 2320 | value &= ~mask; |
ae7bb7c6 | 2321 | value |= s->old_nbctl; |
f9431992 | 2322 | |
c9f4f26e | 2323 | amd64_write_pci_cfg(F3, NBCTL, value); |
f9431992 | 2324 | |
ae7bb7c6 BP |
2325 | /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ |
2326 | if (!s->flags.nb_ecc_prev) { | |
a97fa68e BP |
2327 | amd64_read_pci_cfg(F3, NBCFG, &value); |
2328 | value &= ~NBCFG_ECC_ENABLE; | |
2329 | amd64_write_pci_cfg(F3, NBCFG, value); | |
d95cf4de BP |
2330 | } |
2331 | ||
2332 | /* restore the NB Enable MCGCTL bit */ | |
2299ef71 | 2333 | if (toggle_ecc_err_reporting(s, nid, OFF)) |
24f9a7fe | 2334 | amd64_warn("Error restoring NB MCGCTL settings!\n"); |
f9431992 DT |
2335 | } |
2336 | ||
2337 | /* | |
2299ef71 BP |
2338 | * EDAC requires that the BIOS have ECC enabled before |
2339 | * taking over the processing of ECC errors. A command line | |
2340 | * option allows to force-enable hardware ECC later in | |
2341 | * enable_ecc_error_reporting(). | |
f9431992 | 2342 | */ |
cab4d277 BP |
2343 | static const char *ecc_msg = |
2344 | "ECC disabled in the BIOS or no ECC capability, module will not load.\n" | |
2345 | " Either enable ECC checking or force module loading by setting " | |
2346 | "'ecc_enable_override'.\n" | |
2347 | " (Note that use of the override may cause unknown side effects.)\n"; | |
be3468e8 | 2348 | |
2299ef71 | 2349 | static bool ecc_enabled(struct pci_dev *F3, u8 nid) |
f9431992 DT |
2350 | { |
2351 | u32 value; | |
2299ef71 | 2352 | u8 ecc_en = 0; |
06724535 | 2353 | bool nb_mce_en = false; |
f9431992 | 2354 | |
a97fa68e | 2355 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2356 | |
a97fa68e | 2357 | ecc_en = !!(value & NBCFG_ECC_ENABLE); |
2299ef71 | 2358 | amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled")); |
f9431992 | 2359 | |
2299ef71 | 2360 | nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid); |
06724535 | 2361 | if (!nb_mce_en) |
2299ef71 BP |
2362 | amd64_notice("NB MCE bank disabled, set MSR " |
2363 | "0x%08x[4] on node %d to enable.\n", | |
2364 | MSR_IA32_MCG_CTL, nid); | |
f9431992 | 2365 | |
2299ef71 BP |
2366 | if (!ecc_en || !nb_mce_en) { |
2367 | amd64_notice("%s", ecc_msg); | |
2368 | return false; | |
2369 | } | |
2370 | return true; | |
f9431992 DT |
2371 | } |
2372 | ||
c5608759 | 2373 | static int set_mc_sysfs_attrs(struct mem_ctl_info *mci) |
7d6034d3 | 2374 | { |
c5608759 | 2375 | int rc; |
7d6034d3 | 2376 | |
c5608759 MCC |
2377 | rc = amd64_create_sysfs_dbg_files(mci); |
2378 | if (rc < 0) | |
2379 | return rc; | |
7d6034d3 | 2380 | |
c5608759 MCC |
2381 | if (boot_cpu_data.x86 >= 0x10) { |
2382 | rc = amd64_create_sysfs_inject_files(mci); | |
2383 | if (rc < 0) | |
2384 | return rc; | |
2385 | } | |
2386 | ||
2387 | return 0; | |
2388 | } | |
7d6034d3 | 2389 | |
c5608759 MCC |
2390 | static void del_mc_sysfs_attrs(struct mem_ctl_info *mci) |
2391 | { | |
2392 | amd64_remove_sysfs_dbg_files(mci); | |
7d6034d3 | 2393 | |
c5608759 MCC |
2394 | if (boot_cpu_data.x86 >= 0x10) |
2395 | amd64_remove_sysfs_inject_files(mci); | |
7d6034d3 DT |
2396 | } |
2397 | ||
df71a053 BP |
2398 | static void setup_mci_misc_attrs(struct mem_ctl_info *mci, |
2399 | struct amd64_family_type *fam) | |
7d6034d3 DT |
2400 | { |
2401 | struct amd64_pvt *pvt = mci->pvt_info; | |
2402 | ||
2403 | mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; | |
2404 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
7d6034d3 | 2405 | |
5980bb9c | 2406 | if (pvt->nbcap & NBCAP_SECDED) |
7d6034d3 DT |
2407 | mci->edac_ctl_cap |= EDAC_FLAG_SECDED; |
2408 | ||
5980bb9c | 2409 | if (pvt->nbcap & NBCAP_CHIPKILL) |
7d6034d3 DT |
2410 | mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; |
2411 | ||
2412 | mci->edac_cap = amd64_determine_edac_cap(pvt); | |
2413 | mci->mod_name = EDAC_MOD_STR; | |
2414 | mci->mod_ver = EDAC_AMD64_VERSION; | |
df71a053 | 2415 | mci->ctl_name = fam->ctl_name; |
8d5b5d9c | 2416 | mci->dev_name = pci_name(pvt->F2); |
7d6034d3 DT |
2417 | mci->ctl_page_to_phys = NULL; |
2418 | ||
7d6034d3 DT |
2419 | /* memory scrubber interface */ |
2420 | mci->set_sdram_scrub_rate = amd64_set_scrub_rate; | |
2421 | mci->get_sdram_scrub_rate = amd64_get_scrub_rate; | |
2422 | } | |
2423 | ||
0092b20d BP |
2424 | /* |
2425 | * returns a pointer to the family descriptor on success, NULL otherwise. | |
2426 | */ | |
2427 | static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt) | |
395ae783 | 2428 | { |
0092b20d BP |
2429 | u8 fam = boot_cpu_data.x86; |
2430 | struct amd64_family_type *fam_type = NULL; | |
2431 | ||
2432 | switch (fam) { | |
395ae783 | 2433 | case 0xf: |
0092b20d | 2434 | fam_type = &amd64_family_types[K8_CPUS]; |
b8cfa02f | 2435 | pvt->ops = &amd64_family_types[K8_CPUS].ops; |
395ae783 | 2436 | break; |
df71a053 | 2437 | |
395ae783 | 2438 | case 0x10: |
0092b20d | 2439 | fam_type = &amd64_family_types[F10_CPUS]; |
b8cfa02f | 2440 | pvt->ops = &amd64_family_types[F10_CPUS].ops; |
df71a053 BP |
2441 | break; |
2442 | ||
2443 | case 0x15: | |
2444 | fam_type = &amd64_family_types[F15_CPUS]; | |
2445 | pvt->ops = &amd64_family_types[F15_CPUS].ops; | |
395ae783 BP |
2446 | break; |
2447 | ||
2448 | default: | |
24f9a7fe | 2449 | amd64_err("Unsupported family!\n"); |
0092b20d | 2450 | return NULL; |
395ae783 | 2451 | } |
0092b20d | 2452 | |
b8cfa02f BP |
2453 | pvt->ext_model = boot_cpu_data.x86_model >> 4; |
2454 | ||
df71a053 | 2455 | amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name, |
0092b20d | 2456 | (fam == 0xf ? |
24f9a7fe BP |
2457 | (pvt->ext_model >= K8_REV_F ? "revF or later " |
2458 | : "revE or earlier ") | |
2459 | : ""), pvt->mc_node_id); | |
0092b20d | 2460 | return fam_type; |
395ae783 BP |
2461 | } |
2462 | ||
2299ef71 | 2463 | static int amd64_init_one_instance(struct pci_dev *F2) |
7d6034d3 DT |
2464 | { |
2465 | struct amd64_pvt *pvt = NULL; | |
0092b20d | 2466 | struct amd64_family_type *fam_type = NULL; |
360b7f3c | 2467 | struct mem_ctl_info *mci = NULL; |
ab5a503c | 2468 | struct edac_mc_layer layers[2]; |
7d6034d3 | 2469 | int err = 0, ret; |
360b7f3c | 2470 | u8 nid = get_node_id(F2); |
7d6034d3 DT |
2471 | |
2472 | ret = -ENOMEM; | |
2473 | pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); | |
2474 | if (!pvt) | |
360b7f3c | 2475 | goto err_ret; |
7d6034d3 | 2476 | |
360b7f3c | 2477 | pvt->mc_node_id = nid; |
8d5b5d9c | 2478 | pvt->F2 = F2; |
7d6034d3 | 2479 | |
395ae783 | 2480 | ret = -EINVAL; |
0092b20d BP |
2481 | fam_type = amd64_per_family_init(pvt); |
2482 | if (!fam_type) | |
395ae783 BP |
2483 | goto err_free; |
2484 | ||
7d6034d3 | 2485 | ret = -ENODEV; |
360b7f3c | 2486 | err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id); |
7d6034d3 DT |
2487 | if (err) |
2488 | goto err_free; | |
2489 | ||
360b7f3c | 2490 | read_mc_regs(pvt); |
7d6034d3 | 2491 | |
7d6034d3 DT |
2492 | /* |
2493 | * We need to determine how many memory channels there are. Then use | |
2494 | * that information for calculating the size of the dynamic instance | |
360b7f3c | 2495 | * tables in the 'mci' structure. |
7d6034d3 | 2496 | */ |
360b7f3c | 2497 | ret = -EINVAL; |
7d6034d3 DT |
2498 | pvt->channel_count = pvt->ops->early_channel_count(pvt); |
2499 | if (pvt->channel_count < 0) | |
360b7f3c | 2500 | goto err_siblings; |
7d6034d3 DT |
2501 | |
2502 | ret = -ENOMEM; | |
ab5a503c MCC |
2503 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
2504 | layers[0].size = pvt->csels[0].b_cnt; | |
2505 | layers[0].is_virt_csrow = true; | |
2506 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
2507 | layers[1].size = pvt->channel_count; | |
2508 | layers[1].is_virt_csrow = false; | |
ca0907b9 | 2509 | mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0); |
7d6034d3 | 2510 | if (!mci) |
360b7f3c | 2511 | goto err_siblings; |
7d6034d3 DT |
2512 | |
2513 | mci->pvt_info = pvt; | |
fd687502 | 2514 | mci->pdev = &pvt->F2->dev; |
7d6034d3 | 2515 | |
df71a053 | 2516 | setup_mci_misc_attrs(mci, fam_type); |
360b7f3c BP |
2517 | |
2518 | if (init_csrows(mci)) | |
7d6034d3 DT |
2519 | mci->edac_cap = EDAC_FLAG_NONE; |
2520 | ||
7d6034d3 DT |
2521 | ret = -ENODEV; |
2522 | if (edac_mc_add_mc(mci)) { | |
956b9ba1 | 2523 | edac_dbg(1, "failed edac_mc_add_mc()\n"); |
7d6034d3 DT |
2524 | goto err_add_mc; |
2525 | } | |
c5608759 | 2526 | if (set_mc_sysfs_attrs(mci)) { |
956b9ba1 | 2527 | edac_dbg(1, "failed edac_mc_add_mc()\n"); |
c5608759 MCC |
2528 | goto err_add_sysfs; |
2529 | } | |
7d6034d3 | 2530 | |
549d042d BP |
2531 | /* register stuff with EDAC MCE */ |
2532 | if (report_gart_errors) | |
2533 | amd_report_gart_errors(true); | |
2534 | ||
2535 | amd_register_ecc_decoder(amd64_decode_bus_error); | |
2536 | ||
360b7f3c BP |
2537 | mcis[nid] = mci; |
2538 | ||
2539 | atomic_inc(&drv_instances); | |
2540 | ||
7d6034d3 DT |
2541 | return 0; |
2542 | ||
c5608759 MCC |
2543 | err_add_sysfs: |
2544 | edac_mc_del_mc(mci->pdev); | |
7d6034d3 DT |
2545 | err_add_mc: |
2546 | edac_mc_free(mci); | |
2547 | ||
360b7f3c BP |
2548 | err_siblings: |
2549 | free_mc_sibling_devs(pvt); | |
7d6034d3 | 2550 | |
360b7f3c BP |
2551 | err_free: |
2552 | kfree(pvt); | |
7d6034d3 | 2553 | |
360b7f3c | 2554 | err_ret: |
7d6034d3 DT |
2555 | return ret; |
2556 | } | |
2557 | ||
2299ef71 | 2558 | static int __devinit amd64_probe_one_instance(struct pci_dev *pdev, |
b8cfa02f | 2559 | const struct pci_device_id *mc_type) |
7d6034d3 | 2560 | { |
ae7bb7c6 | 2561 | u8 nid = get_node_id(pdev); |
2299ef71 | 2562 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; |
ae7bb7c6 | 2563 | struct ecc_settings *s; |
2299ef71 | 2564 | int ret = 0; |
7d6034d3 | 2565 | |
7d6034d3 | 2566 | ret = pci_enable_device(pdev); |
b8cfa02f | 2567 | if (ret < 0) { |
956b9ba1 | 2568 | edac_dbg(0, "ret=%d\n", ret); |
b8cfa02f BP |
2569 | return -EIO; |
2570 | } | |
7d6034d3 | 2571 | |
ae7bb7c6 BP |
2572 | ret = -ENOMEM; |
2573 | s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL); | |
2574 | if (!s) | |
2299ef71 | 2575 | goto err_out; |
ae7bb7c6 BP |
2576 | |
2577 | ecc_stngs[nid] = s; | |
2578 | ||
2299ef71 BP |
2579 | if (!ecc_enabled(F3, nid)) { |
2580 | ret = -ENODEV; | |
2581 | ||
2582 | if (!ecc_enable_override) | |
2583 | goto err_enable; | |
2584 | ||
2585 | amd64_warn("Forcing ECC on!\n"); | |
2586 | ||
2587 | if (!enable_ecc_error_reporting(s, nid, F3)) | |
2588 | goto err_enable; | |
2589 | } | |
2590 | ||
2591 | ret = amd64_init_one_instance(pdev); | |
360b7f3c | 2592 | if (ret < 0) { |
ae7bb7c6 | 2593 | amd64_err("Error probing instance: %d\n", nid); |
360b7f3c BP |
2594 | restore_ecc_error_reporting(s, nid, F3); |
2595 | } | |
7d6034d3 DT |
2596 | |
2597 | return ret; | |
2299ef71 BP |
2598 | |
2599 | err_enable: | |
2600 | kfree(s); | |
2601 | ecc_stngs[nid] = NULL; | |
2602 | ||
2603 | err_out: | |
2604 | return ret; | |
7d6034d3 DT |
2605 | } |
2606 | ||
2607 | static void __devexit amd64_remove_one_instance(struct pci_dev *pdev) | |
2608 | { | |
2609 | struct mem_ctl_info *mci; | |
2610 | struct amd64_pvt *pvt; | |
360b7f3c BP |
2611 | u8 nid = get_node_id(pdev); |
2612 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; | |
2613 | struct ecc_settings *s = ecc_stngs[nid]; | |
7d6034d3 | 2614 | |
c5608759 MCC |
2615 | mci = find_mci_by_dev(&pdev->dev); |
2616 | del_mc_sysfs_attrs(mci); | |
7d6034d3 DT |
2617 | /* Remove from EDAC CORE tracking list */ |
2618 | mci = edac_mc_del_mc(&pdev->dev); | |
2619 | if (!mci) | |
2620 | return; | |
2621 | ||
2622 | pvt = mci->pvt_info; | |
2623 | ||
360b7f3c | 2624 | restore_ecc_error_reporting(s, nid, F3); |
7d6034d3 | 2625 | |
360b7f3c | 2626 | free_mc_sibling_devs(pvt); |
7d6034d3 | 2627 | |
549d042d BP |
2628 | /* unregister from EDAC MCE */ |
2629 | amd_report_gart_errors(false); | |
2630 | amd_unregister_ecc_decoder(amd64_decode_bus_error); | |
2631 | ||
360b7f3c BP |
2632 | kfree(ecc_stngs[nid]); |
2633 | ecc_stngs[nid] = NULL; | |
ae7bb7c6 | 2634 | |
7d6034d3 | 2635 | /* Free the EDAC CORE resources */ |
8f68ed97 | 2636 | mci->pvt_info = NULL; |
360b7f3c | 2637 | mcis[nid] = NULL; |
8f68ed97 BP |
2638 | |
2639 | kfree(pvt); | |
7d6034d3 DT |
2640 | edac_mc_free(mci); |
2641 | } | |
2642 | ||
2643 | /* | |
2644 | * This table is part of the interface for loading drivers for PCI devices. The | |
2645 | * PCI core identifies what devices are on a system during boot, and then | |
2646 | * inquiry this table to see if this driver is for a given device found. | |
2647 | */ | |
36c46f31 | 2648 | static DEFINE_PCI_DEVICE_TABLE(amd64_pci_table) = { |
7d6034d3 DT |
2649 | { |
2650 | .vendor = PCI_VENDOR_ID_AMD, | |
2651 | .device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL, | |
2652 | .subvendor = PCI_ANY_ID, | |
2653 | .subdevice = PCI_ANY_ID, | |
2654 | .class = 0, | |
2655 | .class_mask = 0, | |
7d6034d3 DT |
2656 | }, |
2657 | { | |
2658 | .vendor = PCI_VENDOR_ID_AMD, | |
2659 | .device = PCI_DEVICE_ID_AMD_10H_NB_DRAM, | |
2660 | .subvendor = PCI_ANY_ID, | |
2661 | .subdevice = PCI_ANY_ID, | |
2662 | .class = 0, | |
2663 | .class_mask = 0, | |
7d6034d3 | 2664 | }, |
df71a053 BP |
2665 | { |
2666 | .vendor = PCI_VENDOR_ID_AMD, | |
2667 | .device = PCI_DEVICE_ID_AMD_15H_NB_F2, | |
2668 | .subvendor = PCI_ANY_ID, | |
2669 | .subdevice = PCI_ANY_ID, | |
2670 | .class = 0, | |
2671 | .class_mask = 0, | |
2672 | }, | |
2673 | ||
7d6034d3 DT |
2674 | {0, } |
2675 | }; | |
2676 | MODULE_DEVICE_TABLE(pci, amd64_pci_table); | |
2677 | ||
2678 | static struct pci_driver amd64_pci_driver = { | |
2679 | .name = EDAC_MOD_STR, | |
2299ef71 | 2680 | .probe = amd64_probe_one_instance, |
7d6034d3 DT |
2681 | .remove = __devexit_p(amd64_remove_one_instance), |
2682 | .id_table = amd64_pci_table, | |
2683 | }; | |
2684 | ||
360b7f3c | 2685 | static void setup_pci_device(void) |
7d6034d3 DT |
2686 | { |
2687 | struct mem_ctl_info *mci; | |
2688 | struct amd64_pvt *pvt; | |
2689 | ||
2690 | if (amd64_ctl_pci) | |
2691 | return; | |
2692 | ||
cc4d8860 | 2693 | mci = mcis[0]; |
7d6034d3 DT |
2694 | if (mci) { |
2695 | ||
2696 | pvt = mci->pvt_info; | |
2697 | amd64_ctl_pci = | |
8d5b5d9c | 2698 | edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR); |
7d6034d3 DT |
2699 | |
2700 | if (!amd64_ctl_pci) { | |
2701 | pr_warning("%s(): Unable to create PCI control\n", | |
2702 | __func__); | |
2703 | ||
2704 | pr_warning("%s(): PCI error report via EDAC not set\n", | |
2705 | __func__); | |
2706 | } | |
2707 | } | |
2708 | } | |
2709 | ||
2710 | static int __init amd64_edac_init(void) | |
2711 | { | |
360b7f3c | 2712 | int err = -ENODEV; |
7d6034d3 | 2713 | |
df71a053 | 2714 | printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION); |
7d6034d3 DT |
2715 | |
2716 | opstate_init(); | |
2717 | ||
9653a5c7 | 2718 | if (amd_cache_northbridges() < 0) |
56b34b91 | 2719 | goto err_ret; |
7d6034d3 | 2720 | |
cc4d8860 | 2721 | err = -ENOMEM; |
ae7bb7c6 BP |
2722 | mcis = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL); |
2723 | ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL); | |
360b7f3c | 2724 | if (!(mcis && ecc_stngs)) |
a9f0fbe2 | 2725 | goto err_free; |
cc4d8860 | 2726 | |
50542251 | 2727 | msrs = msrs_alloc(); |
56b34b91 | 2728 | if (!msrs) |
360b7f3c | 2729 | goto err_free; |
50542251 | 2730 | |
7d6034d3 DT |
2731 | err = pci_register_driver(&amd64_pci_driver); |
2732 | if (err) | |
56b34b91 | 2733 | goto err_pci; |
7d6034d3 | 2734 | |
56b34b91 | 2735 | err = -ENODEV; |
360b7f3c BP |
2736 | if (!atomic_read(&drv_instances)) |
2737 | goto err_no_instances; | |
7d6034d3 | 2738 | |
360b7f3c BP |
2739 | setup_pci_device(); |
2740 | return 0; | |
7d6034d3 | 2741 | |
360b7f3c | 2742 | err_no_instances: |
7d6034d3 | 2743 | pci_unregister_driver(&amd64_pci_driver); |
cc4d8860 | 2744 | |
56b34b91 BP |
2745 | err_pci: |
2746 | msrs_free(msrs); | |
2747 | msrs = NULL; | |
cc4d8860 | 2748 | |
360b7f3c BP |
2749 | err_free: |
2750 | kfree(mcis); | |
2751 | mcis = NULL; | |
2752 | ||
2753 | kfree(ecc_stngs); | |
2754 | ecc_stngs = NULL; | |
2755 | ||
56b34b91 | 2756 | err_ret: |
7d6034d3 DT |
2757 | return err; |
2758 | } | |
2759 | ||
2760 | static void __exit amd64_edac_exit(void) | |
2761 | { | |
2762 | if (amd64_ctl_pci) | |
2763 | edac_pci_release_generic_ctl(amd64_ctl_pci); | |
2764 | ||
2765 | pci_unregister_driver(&amd64_pci_driver); | |
50542251 | 2766 | |
ae7bb7c6 BP |
2767 | kfree(ecc_stngs); |
2768 | ecc_stngs = NULL; | |
2769 | ||
cc4d8860 BP |
2770 | kfree(mcis); |
2771 | mcis = NULL; | |
2772 | ||
50542251 BP |
2773 | msrs_free(msrs); |
2774 | msrs = NULL; | |
7d6034d3 DT |
2775 | } |
2776 | ||
2777 | module_init(amd64_edac_init); | |
2778 | module_exit(amd64_edac_exit); | |
2779 | ||
2780 | MODULE_LICENSE("GPL"); | |
2781 | MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, " | |
2782 | "Dave Peterson, Thayne Harbaugh"); | |
2783 | MODULE_DESCRIPTION("MC support for AMD64 memory controllers - " | |
2784 | EDAC_AMD64_VERSION); | |
2785 | ||
2786 | module_param(edac_op_state, int, 0444); | |
2787 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |