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Commit | Line | Data |
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2bc65418 | 1 | #include "amd64_edac.h" |
23ac4ae8 | 2 | #include <asm/amd_nb.h> |
2bc65418 DT |
3 | |
4 | static struct edac_pci_ctl_info *amd64_ctl_pci; | |
5 | ||
6 | static int report_gart_errors; | |
7 | module_param(report_gart_errors, int, 0644); | |
8 | ||
9 | /* | |
10 | * Set by command line parameter. If BIOS has enabled the ECC, this override is | |
11 | * cleared to prevent re-enabling the hardware by this driver. | |
12 | */ | |
13 | static int ecc_enable_override; | |
14 | module_param(ecc_enable_override, int, 0644); | |
15 | ||
a29d8b8e | 16 | static struct msr __percpu *msrs; |
50542251 | 17 | |
360b7f3c BP |
18 | /* |
19 | * count successfully initialized driver instances for setup_pci_device() | |
20 | */ | |
21 | static atomic_t drv_instances = ATOMIC_INIT(0); | |
22 | ||
cc4d8860 BP |
23 | /* Per-node driver instances */ |
24 | static struct mem_ctl_info **mcis; | |
ae7bb7c6 | 25 | static struct ecc_settings **ecc_stngs; |
2bc65418 | 26 | |
b70ef010 BP |
27 | /* |
28 | * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing | |
29 | * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching- | |
30 | * or higher value'. | |
31 | * | |
32 | *FIXME: Produce a better mapping/linearisation. | |
33 | */ | |
39094443 BP |
34 | struct scrubrate { |
35 | u32 scrubval; /* bit pattern for scrub rate */ | |
36 | u32 bandwidth; /* bandwidth consumed (bytes/sec) */ | |
37 | } scrubrates[] = { | |
b70ef010 BP |
38 | { 0x01, 1600000000UL}, |
39 | { 0x02, 800000000UL}, | |
40 | { 0x03, 400000000UL}, | |
41 | { 0x04, 200000000UL}, | |
42 | { 0x05, 100000000UL}, | |
43 | { 0x06, 50000000UL}, | |
44 | { 0x07, 25000000UL}, | |
45 | { 0x08, 12284069UL}, | |
46 | { 0x09, 6274509UL}, | |
47 | { 0x0A, 3121951UL}, | |
48 | { 0x0B, 1560975UL}, | |
49 | { 0x0C, 781440UL}, | |
50 | { 0x0D, 390720UL}, | |
51 | { 0x0E, 195300UL}, | |
52 | { 0x0F, 97650UL}, | |
53 | { 0x10, 48854UL}, | |
54 | { 0x11, 24427UL}, | |
55 | { 0x12, 12213UL}, | |
56 | { 0x13, 6101UL}, | |
57 | { 0x14, 3051UL}, | |
58 | { 0x15, 1523UL}, | |
59 | { 0x16, 761UL}, | |
60 | { 0x00, 0UL}, /* scrubbing off */ | |
61 | }; | |
62 | ||
b2b0c605 BP |
63 | static int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, |
64 | u32 *val, const char *func) | |
65 | { | |
66 | int err = 0; | |
67 | ||
68 | err = pci_read_config_dword(pdev, offset, val); | |
69 | if (err) | |
70 | amd64_warn("%s: error reading F%dx%03x.\n", | |
71 | func, PCI_FUNC(pdev->devfn), offset); | |
72 | ||
73 | return err; | |
74 | } | |
75 | ||
76 | int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, | |
77 | u32 val, const char *func) | |
78 | { | |
79 | int err = 0; | |
80 | ||
81 | err = pci_write_config_dword(pdev, offset, val); | |
82 | if (err) | |
83 | amd64_warn("%s: error writing to F%dx%03x.\n", | |
84 | func, PCI_FUNC(pdev->devfn), offset); | |
85 | ||
86 | return err; | |
87 | } | |
88 | ||
89 | /* | |
90 | * | |
91 | * Depending on the family, F2 DCT reads need special handling: | |
92 | * | |
93 | * K8: has a single DCT only | |
94 | * | |
95 | * F10h: each DCT has its own set of regs | |
96 | * DCT0 -> F2x040.. | |
97 | * DCT1 -> F2x140.. | |
98 | * | |
99 | * F15h: we select which DCT we access using F1x10C[DctCfgSel] | |
100 | * | |
101 | */ | |
102 | static int k8_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val, | |
103 | const char *func) | |
104 | { | |
105 | if (addr >= 0x100) | |
106 | return -EINVAL; | |
107 | ||
108 | return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); | |
109 | } | |
110 | ||
111 | static int f10_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val, | |
112 | const char *func) | |
113 | { | |
114 | return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); | |
115 | } | |
116 | ||
117 | static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val, | |
118 | const char *func) | |
119 | { | |
120 | u32 reg = 0; | |
121 | u8 dct = 0; | |
122 | ||
123 | if (addr >= 0x140 && addr <= 0x1a0) { | |
124 | dct = 1; | |
125 | addr -= 0x100; | |
126 | } | |
127 | ||
128 | amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); | |
129 | reg &= 0xfffffffe; | |
130 | reg |= dct; | |
131 | amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); | |
132 | ||
133 | return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); | |
134 | } | |
135 | ||
2bc65418 DT |
136 | /* |
137 | * Memory scrubber control interface. For K8, memory scrubbing is handled by | |
138 | * hardware and can involve L2 cache, dcache as well as the main memory. With | |
139 | * F10, this is extended to L3 cache scrubbing on CPU models sporting that | |
140 | * functionality. | |
141 | * | |
142 | * This causes the "units" for the scrubbing speed to vary from 64 byte blocks | |
143 | * (dram) over to cache lines. This is nasty, so we will use bandwidth in | |
144 | * bytes/sec for the setting. | |
145 | * | |
146 | * Currently, we only do dram scrubbing. If the scrubbing is done in software on | |
147 | * other archs, we might not have access to the caches directly. | |
148 | */ | |
149 | ||
150 | /* | |
151 | * scan the scrub rate mapping table for a close or matching bandwidth value to | |
152 | * issue. If requested is too big, then use last maximum value found. | |
153 | */ | |
395ae783 | 154 | static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate) |
2bc65418 DT |
155 | { |
156 | u32 scrubval; | |
157 | int i; | |
158 | ||
159 | /* | |
160 | * map the configured rate (new_bw) to a value specific to the AMD64 | |
161 | * memory controller and apply to register. Search for the first | |
162 | * bandwidth entry that is greater or equal than the setting requested | |
163 | * and program that. If at last entry, turn off DRAM scrubbing. | |
164 | */ | |
165 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { | |
166 | /* | |
167 | * skip scrub rates which aren't recommended | |
168 | * (see F10 BKDG, F3x58) | |
169 | */ | |
395ae783 | 170 | if (scrubrates[i].scrubval < min_rate) |
2bc65418 DT |
171 | continue; |
172 | ||
173 | if (scrubrates[i].bandwidth <= new_bw) | |
174 | break; | |
175 | ||
176 | /* | |
177 | * if no suitable bandwidth found, turn off DRAM scrubbing | |
178 | * entirely by falling back to the last element in the | |
179 | * scrubrates array. | |
180 | */ | |
181 | } | |
182 | ||
183 | scrubval = scrubrates[i].scrubval; | |
2bc65418 | 184 | |
5980bb9c | 185 | pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F); |
2bc65418 | 186 | |
39094443 BP |
187 | if (scrubval) |
188 | return scrubrates[i].bandwidth; | |
189 | ||
2bc65418 DT |
190 | return 0; |
191 | } | |
192 | ||
395ae783 | 193 | static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw) |
2bc65418 DT |
194 | { |
195 | struct amd64_pvt *pvt = mci->pvt_info; | |
87b3e0e6 | 196 | u32 min_scrubrate = 0x5; |
2bc65418 | 197 | |
87b3e0e6 BP |
198 | if (boot_cpu_data.x86 == 0xf) |
199 | min_scrubrate = 0x0; | |
200 | ||
201 | return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate); | |
2bc65418 DT |
202 | } |
203 | ||
39094443 | 204 | static int amd64_get_scrub_rate(struct mem_ctl_info *mci) |
2bc65418 DT |
205 | { |
206 | struct amd64_pvt *pvt = mci->pvt_info; | |
207 | u32 scrubval = 0; | |
39094443 | 208 | int i, retval = -EINVAL; |
2bc65418 | 209 | |
5980bb9c | 210 | amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); |
2bc65418 DT |
211 | |
212 | scrubval = scrubval & 0x001F; | |
213 | ||
24f9a7fe | 214 | amd64_debug("pci-read, sdram scrub control value: %d\n", scrubval); |
2bc65418 | 215 | |
926311fd | 216 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { |
2bc65418 | 217 | if (scrubrates[i].scrubval == scrubval) { |
39094443 | 218 | retval = scrubrates[i].bandwidth; |
2bc65418 DT |
219 | break; |
220 | } | |
221 | } | |
39094443 | 222 | return retval; |
2bc65418 DT |
223 | } |
224 | ||
6775763a | 225 | /* |
7f19bf75 BP |
226 | * returns true if the SysAddr given by sys_addr matches the |
227 | * DRAM base/limit associated with node_id | |
6775763a | 228 | */ |
b487c33e BP |
229 | static bool amd64_base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, |
230 | unsigned nid) | |
6775763a | 231 | { |
7f19bf75 | 232 | u64 addr; |
6775763a DT |
233 | |
234 | /* The K8 treats this as a 40-bit value. However, bits 63-40 will be | |
235 | * all ones if the most significant implemented address bit is 1. | |
236 | * Here we discard bits 63-40. See section 3.4.2 of AMD publication | |
237 | * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 | |
238 | * Application Programming. | |
239 | */ | |
240 | addr = sys_addr & 0x000000ffffffffffull; | |
241 | ||
7f19bf75 BP |
242 | return ((addr >= get_dram_base(pvt, nid)) && |
243 | (addr <= get_dram_limit(pvt, nid))); | |
6775763a DT |
244 | } |
245 | ||
246 | /* | |
247 | * Attempt to map a SysAddr to a node. On success, return a pointer to the | |
248 | * mem_ctl_info structure for the node that the SysAddr maps to. | |
249 | * | |
250 | * On failure, return NULL. | |
251 | */ | |
252 | static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, | |
253 | u64 sys_addr) | |
254 | { | |
255 | struct amd64_pvt *pvt; | |
b487c33e | 256 | unsigned node_id; |
6775763a DT |
257 | u32 intlv_en, bits; |
258 | ||
259 | /* | |
260 | * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section | |
261 | * 3.4.4.2) registers to map the SysAddr to a node ID. | |
262 | */ | |
263 | pvt = mci->pvt_info; | |
264 | ||
265 | /* | |
266 | * The value of this field should be the same for all DRAM Base | |
267 | * registers. Therefore we arbitrarily choose to read it from the | |
268 | * register for node 0. | |
269 | */ | |
7f19bf75 | 270 | intlv_en = dram_intlv_en(pvt, 0); |
6775763a DT |
271 | |
272 | if (intlv_en == 0) { | |
7f19bf75 | 273 | for (node_id = 0; node_id < DRAM_RANGES; node_id++) { |
6775763a | 274 | if (amd64_base_limit_match(pvt, sys_addr, node_id)) |
8edc5445 | 275 | goto found; |
6775763a | 276 | } |
8edc5445 | 277 | goto err_no_match; |
6775763a DT |
278 | } |
279 | ||
72f158fe BP |
280 | if (unlikely((intlv_en != 0x01) && |
281 | (intlv_en != 0x03) && | |
282 | (intlv_en != 0x07))) { | |
24f9a7fe | 283 | amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en); |
6775763a DT |
284 | return NULL; |
285 | } | |
286 | ||
287 | bits = (((u32) sys_addr) >> 12) & intlv_en; | |
288 | ||
289 | for (node_id = 0; ; ) { | |
7f19bf75 | 290 | if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) |
6775763a DT |
291 | break; /* intlv_sel field matches */ |
292 | ||
7f19bf75 | 293 | if (++node_id >= DRAM_RANGES) |
6775763a DT |
294 | goto err_no_match; |
295 | } | |
296 | ||
297 | /* sanity test for sys_addr */ | |
298 | if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) { | |
24f9a7fe BP |
299 | amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address" |
300 | "range for node %d with node interleaving enabled.\n", | |
301 | __func__, sys_addr, node_id); | |
6775763a DT |
302 | return NULL; |
303 | } | |
304 | ||
305 | found: | |
b487c33e | 306 | return edac_mc_find((int)node_id); |
6775763a DT |
307 | |
308 | err_no_match: | |
309 | debugf2("sys_addr 0x%lx doesn't match any node\n", | |
310 | (unsigned long)sys_addr); | |
311 | ||
312 | return NULL; | |
313 | } | |
e2ce7255 DT |
314 | |
315 | /* | |
11c75ead BP |
316 | * compute the CS base address of the @csrow on the DRAM controller @dct. |
317 | * For details see F2x[5C:40] in the processor's BKDG | |
e2ce7255 | 318 | */ |
11c75ead BP |
319 | static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, |
320 | u64 *base, u64 *mask) | |
e2ce7255 | 321 | { |
11c75ead BP |
322 | u64 csbase, csmask, base_bits, mask_bits; |
323 | u8 addr_shift; | |
e2ce7255 | 324 | |
11c75ead BP |
325 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) { |
326 | csbase = pvt->csels[dct].csbases[csrow]; | |
327 | csmask = pvt->csels[dct].csmasks[csrow]; | |
328 | base_bits = GENMASK(21, 31) | GENMASK(9, 15); | |
329 | mask_bits = GENMASK(21, 29) | GENMASK(9, 15); | |
330 | addr_shift = 4; | |
331 | } else { | |
332 | csbase = pvt->csels[dct].csbases[csrow]; | |
333 | csmask = pvt->csels[dct].csmasks[csrow >> 1]; | |
334 | addr_shift = 8; | |
e2ce7255 | 335 | |
11c75ead BP |
336 | if (boot_cpu_data.x86 == 0x15) |
337 | base_bits = mask_bits = GENMASK(19,30) | GENMASK(5,13); | |
338 | else | |
339 | base_bits = mask_bits = GENMASK(19,28) | GENMASK(5,13); | |
340 | } | |
e2ce7255 | 341 | |
11c75ead | 342 | *base = (csbase & base_bits) << addr_shift; |
e2ce7255 | 343 | |
11c75ead BP |
344 | *mask = ~0ULL; |
345 | /* poke holes for the csmask */ | |
346 | *mask &= ~(mask_bits << addr_shift); | |
347 | /* OR them in */ | |
348 | *mask |= (csmask & mask_bits) << addr_shift; | |
e2ce7255 DT |
349 | } |
350 | ||
11c75ead BP |
351 | #define for_each_chip_select(i, dct, pvt) \ |
352 | for (i = 0; i < pvt->csels[dct].b_cnt; i++) | |
353 | ||
614ec9d8 BP |
354 | #define chip_select_base(i, dct, pvt) \ |
355 | pvt->csels[dct].csbases[i] | |
356 | ||
11c75ead BP |
357 | #define for_each_chip_select_mask(i, dct, pvt) \ |
358 | for (i = 0; i < pvt->csels[dct].m_cnt; i++) | |
359 | ||
e2ce7255 DT |
360 | /* |
361 | * @input_addr is an InputAddr associated with the node given by mci. Return the | |
362 | * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). | |
363 | */ | |
364 | static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) | |
365 | { | |
366 | struct amd64_pvt *pvt; | |
367 | int csrow; | |
368 | u64 base, mask; | |
369 | ||
370 | pvt = mci->pvt_info; | |
371 | ||
11c75ead BP |
372 | for_each_chip_select(csrow, 0, pvt) { |
373 | if (!csrow_enabled(csrow, 0, pvt)) | |
e2ce7255 DT |
374 | continue; |
375 | ||
11c75ead BP |
376 | get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); |
377 | ||
378 | mask = ~mask; | |
e2ce7255 DT |
379 | |
380 | if ((input_addr & mask) == (base & mask)) { | |
381 | debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n", | |
382 | (unsigned long)input_addr, csrow, | |
383 | pvt->mc_node_id); | |
384 | ||
385 | return csrow; | |
386 | } | |
387 | } | |
e2ce7255 DT |
388 | debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n", |
389 | (unsigned long)input_addr, pvt->mc_node_id); | |
390 | ||
391 | return -1; | |
392 | } | |
393 | ||
e2ce7255 DT |
394 | /* |
395 | * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) | |
396 | * for the node represented by mci. Info is passed back in *hole_base, | |
397 | * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if | |
398 | * info is invalid. Info may be invalid for either of the following reasons: | |
399 | * | |
400 | * - The revision of the node is not E or greater. In this case, the DRAM Hole | |
401 | * Address Register does not exist. | |
402 | * | |
403 | * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, | |
404 | * indicating that its contents are not valid. | |
405 | * | |
406 | * The values passed back in *hole_base, *hole_offset, and *hole_size are | |
407 | * complete 32-bit values despite the fact that the bitfields in the DHAR | |
408 | * only represent bits 31-24 of the base and offset values. | |
409 | */ | |
410 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, | |
411 | u64 *hole_offset, u64 *hole_size) | |
412 | { | |
413 | struct amd64_pvt *pvt = mci->pvt_info; | |
414 | u64 base; | |
415 | ||
416 | /* only revE and later have the DRAM Hole Address Register */ | |
1433eb99 | 417 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) { |
e2ce7255 DT |
418 | debugf1(" revision %d for node %d does not support DHAR\n", |
419 | pvt->ext_model, pvt->mc_node_id); | |
420 | return 1; | |
421 | } | |
422 | ||
bc21fa57 | 423 | /* valid for Fam10h and above */ |
c8e518d5 | 424 | if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) { |
e2ce7255 DT |
425 | debugf1(" Dram Memory Hoisting is DISABLED on this system\n"); |
426 | return 1; | |
427 | } | |
428 | ||
c8e518d5 | 429 | if (!dhar_valid(pvt)) { |
e2ce7255 DT |
430 | debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n", |
431 | pvt->mc_node_id); | |
432 | return 1; | |
433 | } | |
434 | ||
435 | /* This node has Memory Hoisting */ | |
436 | ||
437 | /* +------------------+--------------------+--------------------+----- | |
438 | * | memory | DRAM hole | relocated | | |
439 | * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | | |
440 | * | | | DRAM hole | | |
441 | * | | | [0x100000000, | | |
442 | * | | | (0x100000000+ | | |
443 | * | | | (0xffffffff-x))] | | |
444 | * +------------------+--------------------+--------------------+----- | |
445 | * | |
446 | * Above is a diagram of physical memory showing the DRAM hole and the | |
447 | * relocated addresses from the DRAM hole. As shown, the DRAM hole | |
448 | * starts at address x (the base address) and extends through address | |
449 | * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the | |
450 | * addresses in the hole so that they start at 0x100000000. | |
451 | */ | |
452 | ||
bc21fa57 | 453 | base = dhar_base(pvt); |
e2ce7255 DT |
454 | |
455 | *hole_base = base; | |
456 | *hole_size = (0x1ull << 32) - base; | |
457 | ||
458 | if (boot_cpu_data.x86 > 0xf) | |
bc21fa57 | 459 | *hole_offset = f10_dhar_offset(pvt); |
e2ce7255 | 460 | else |
bc21fa57 | 461 | *hole_offset = k8_dhar_offset(pvt); |
e2ce7255 DT |
462 | |
463 | debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", | |
464 | pvt->mc_node_id, (unsigned long)*hole_base, | |
465 | (unsigned long)*hole_offset, (unsigned long)*hole_size); | |
466 | ||
467 | return 0; | |
468 | } | |
469 | EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); | |
470 | ||
93c2df58 DT |
471 | /* |
472 | * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is | |
473 | * assumed that sys_addr maps to the node given by mci. | |
474 | * | |
475 | * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section | |
476 | * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a | |
477 | * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, | |
478 | * then it is also involved in translating a SysAddr to a DramAddr. Sections | |
479 | * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. | |
480 | * These parts of the documentation are unclear. I interpret them as follows: | |
481 | * | |
482 | * When node n receives a SysAddr, it processes the SysAddr as follows: | |
483 | * | |
484 | * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM | |
485 | * Limit registers for node n. If the SysAddr is not within the range | |
486 | * specified by the base and limit values, then node n ignores the Sysaddr | |
487 | * (since it does not map to node n). Otherwise continue to step 2 below. | |
488 | * | |
489 | * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is | |
490 | * disabled so skip to step 3 below. Otherwise see if the SysAddr is within | |
491 | * the range of relocated addresses (starting at 0x100000000) from the DRAM | |
492 | * hole. If not, skip to step 3 below. Else get the value of the | |
493 | * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the | |
494 | * offset defined by this value from the SysAddr. | |
495 | * | |
496 | * 3. Obtain the base address for node n from the DRAMBase field of the DRAM | |
497 | * Base register for node n. To obtain the DramAddr, subtract the base | |
498 | * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). | |
499 | */ | |
500 | static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
501 | { | |
7f19bf75 | 502 | struct amd64_pvt *pvt = mci->pvt_info; |
93c2df58 DT |
503 | u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; |
504 | int ret = 0; | |
505 | ||
7f19bf75 | 506 | dram_base = get_dram_base(pvt, pvt->mc_node_id); |
93c2df58 DT |
507 | |
508 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
509 | &hole_size); | |
510 | if (!ret) { | |
511 | if ((sys_addr >= (1ull << 32)) && | |
512 | (sys_addr < ((1ull << 32) + hole_size))) { | |
513 | /* use DHAR to translate SysAddr to DramAddr */ | |
514 | dram_addr = sys_addr - hole_offset; | |
515 | ||
516 | debugf2("using DHAR to translate SysAddr 0x%lx to " | |
517 | "DramAddr 0x%lx\n", | |
518 | (unsigned long)sys_addr, | |
519 | (unsigned long)dram_addr); | |
520 | ||
521 | return dram_addr; | |
522 | } | |
523 | } | |
524 | ||
525 | /* | |
526 | * Translate the SysAddr to a DramAddr as shown near the start of | |
527 | * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 | |
528 | * only deals with 40-bit values. Therefore we discard bits 63-40 of | |
529 | * sys_addr below. If bit 39 of sys_addr is 1 then the bits we | |
530 | * discard are all 1s. Otherwise the bits we discard are all 0s. See | |
531 | * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture | |
532 | * Programmer's Manual Volume 1 Application Programming. | |
533 | */ | |
f678b8cc | 534 | dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base; |
93c2df58 DT |
535 | |
536 | debugf2("using DRAM Base register to translate SysAddr 0x%lx to " | |
537 | "DramAddr 0x%lx\n", (unsigned long)sys_addr, | |
538 | (unsigned long)dram_addr); | |
539 | return dram_addr; | |
540 | } | |
541 | ||
542 | /* | |
543 | * @intlv_en is the value of the IntlvEn field from a DRAM Base register | |
544 | * (section 3.4.4.1). Return the number of bits from a SysAddr that are used | |
545 | * for node interleaving. | |
546 | */ | |
547 | static int num_node_interleave_bits(unsigned intlv_en) | |
548 | { | |
549 | static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; | |
550 | int n; | |
551 | ||
552 | BUG_ON(intlv_en > 7); | |
553 | n = intlv_shift_table[intlv_en]; | |
554 | return n; | |
555 | } | |
556 | ||
557 | /* Translate the DramAddr given by @dram_addr to an InputAddr. */ | |
558 | static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
559 | { | |
560 | struct amd64_pvt *pvt; | |
561 | int intlv_shift; | |
562 | u64 input_addr; | |
563 | ||
564 | pvt = mci->pvt_info; | |
565 | ||
566 | /* | |
567 | * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
568 | * concerning translating a DramAddr to an InputAddr. | |
569 | */ | |
7f19bf75 | 570 | intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); |
f678b8cc BP |
571 | input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) + |
572 | (dram_addr & 0xfff); | |
93c2df58 DT |
573 | |
574 | debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", | |
575 | intlv_shift, (unsigned long)dram_addr, | |
576 | (unsigned long)input_addr); | |
577 | ||
578 | return input_addr; | |
579 | } | |
580 | ||
581 | /* | |
582 | * Translate the SysAddr represented by @sys_addr to an InputAddr. It is | |
583 | * assumed that @sys_addr maps to the node given by mci. | |
584 | */ | |
585 | static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
586 | { | |
587 | u64 input_addr; | |
588 | ||
589 | input_addr = | |
590 | dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); | |
591 | ||
592 | debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n", | |
593 | (unsigned long)sys_addr, (unsigned long)input_addr); | |
594 | ||
595 | return input_addr; | |
596 | } | |
597 | ||
598 | ||
599 | /* | |
600 | * @input_addr is an InputAddr associated with the node represented by mci. | |
601 | * Translate @input_addr to a DramAddr and return the result. | |
602 | */ | |
603 | static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr) | |
604 | { | |
605 | struct amd64_pvt *pvt; | |
b487c33e | 606 | unsigned node_id, intlv_shift; |
93c2df58 DT |
607 | u64 bits, dram_addr; |
608 | u32 intlv_sel; | |
609 | ||
610 | /* | |
611 | * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
612 | * shows how to translate a DramAddr to an InputAddr. Here we reverse | |
613 | * this procedure. When translating from a DramAddr to an InputAddr, the | |
614 | * bits used for node interleaving are discarded. Here we recover these | |
615 | * bits from the IntlvSel field of the DRAM Limit register (section | |
616 | * 3.4.4.2) for the node that input_addr is associated with. | |
617 | */ | |
618 | pvt = mci->pvt_info; | |
619 | node_id = pvt->mc_node_id; | |
b487c33e BP |
620 | |
621 | BUG_ON(node_id > 7); | |
93c2df58 | 622 | |
7f19bf75 | 623 | intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); |
93c2df58 DT |
624 | if (intlv_shift == 0) { |
625 | debugf1(" InputAddr 0x%lx translates to DramAddr of " | |
626 | "same value\n", (unsigned long)input_addr); | |
627 | ||
628 | return input_addr; | |
629 | } | |
630 | ||
f678b8cc BP |
631 | bits = ((input_addr & GENMASK(12, 35)) << intlv_shift) + |
632 | (input_addr & 0xfff); | |
93c2df58 | 633 | |
7f19bf75 | 634 | intlv_sel = dram_intlv_sel(pvt, node_id) & ((1 << intlv_shift) - 1); |
93c2df58 DT |
635 | dram_addr = bits + (intlv_sel << 12); |
636 | ||
637 | debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx " | |
638 | "(%d node interleave bits)\n", (unsigned long)input_addr, | |
639 | (unsigned long)dram_addr, intlv_shift); | |
640 | ||
641 | return dram_addr; | |
642 | } | |
643 | ||
644 | /* | |
645 | * @dram_addr is a DramAddr that maps to the node represented by mci. Convert | |
646 | * @dram_addr to a SysAddr. | |
647 | */ | |
648 | static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
649 | { | |
650 | struct amd64_pvt *pvt = mci->pvt_info; | |
7f19bf75 | 651 | u64 hole_base, hole_offset, hole_size, base, sys_addr; |
93c2df58 DT |
652 | int ret = 0; |
653 | ||
654 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
655 | &hole_size); | |
656 | if (!ret) { | |
657 | if ((dram_addr >= hole_base) && | |
658 | (dram_addr < (hole_base + hole_size))) { | |
659 | sys_addr = dram_addr + hole_offset; | |
660 | ||
661 | debugf1("using DHAR to translate DramAddr 0x%lx to " | |
662 | "SysAddr 0x%lx\n", (unsigned long)dram_addr, | |
663 | (unsigned long)sys_addr); | |
664 | ||
665 | return sys_addr; | |
666 | } | |
667 | } | |
668 | ||
7f19bf75 | 669 | base = get_dram_base(pvt, pvt->mc_node_id); |
93c2df58 DT |
670 | sys_addr = dram_addr + base; |
671 | ||
672 | /* | |
673 | * The sys_addr we have computed up to this point is a 40-bit value | |
674 | * because the k8 deals with 40-bit values. However, the value we are | |
675 | * supposed to return is a full 64-bit physical address. The AMD | |
676 | * x86-64 architecture specifies that the most significant implemented | |
677 | * address bit through bit 63 of a physical address must be either all | |
678 | * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a | |
679 | * 64-bit value below. See section 3.4.2 of AMD publication 24592: | |
680 | * AMD x86-64 Architecture Programmer's Manual Volume 1 Application | |
681 | * Programming. | |
682 | */ | |
683 | sys_addr |= ~((sys_addr & (1ull << 39)) - 1); | |
684 | ||
685 | debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", | |
686 | pvt->mc_node_id, (unsigned long)dram_addr, | |
687 | (unsigned long)sys_addr); | |
688 | ||
689 | return sys_addr; | |
690 | } | |
691 | ||
692 | /* | |
693 | * @input_addr is an InputAddr associated with the node given by mci. Translate | |
694 | * @input_addr to a SysAddr. | |
695 | */ | |
696 | static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci, | |
697 | u64 input_addr) | |
698 | { | |
699 | return dram_addr_to_sys_addr(mci, | |
700 | input_addr_to_dram_addr(mci, input_addr)); | |
701 | } | |
702 | ||
703 | /* | |
704 | * Find the minimum and maximum InputAddr values that map to the given @csrow. | |
705 | * Pass back these values in *input_addr_min and *input_addr_max. | |
706 | */ | |
707 | static void find_csrow_limits(struct mem_ctl_info *mci, int csrow, | |
708 | u64 *input_addr_min, u64 *input_addr_max) | |
709 | { | |
710 | struct amd64_pvt *pvt; | |
711 | u64 base, mask; | |
712 | ||
713 | pvt = mci->pvt_info; | |
11c75ead | 714 | BUG_ON((csrow < 0) || (csrow >= pvt->csels[0].b_cnt)); |
93c2df58 | 715 | |
11c75ead | 716 | get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); |
93c2df58 DT |
717 | |
718 | *input_addr_min = base & ~mask; | |
11c75ead | 719 | *input_addr_max = base | mask; |
93c2df58 DT |
720 | } |
721 | ||
93c2df58 DT |
722 | /* Map the Error address to a PAGE and PAGE OFFSET. */ |
723 | static inline void error_address_to_page_and_offset(u64 error_address, | |
724 | u32 *page, u32 *offset) | |
725 | { | |
726 | *page = (u32) (error_address >> PAGE_SHIFT); | |
727 | *offset = ((u32) error_address) & ~PAGE_MASK; | |
728 | } | |
729 | ||
730 | /* | |
731 | * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address | |
732 | * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers | |
733 | * of a node that detected an ECC memory error. mci represents the node that | |
734 | * the error address maps to (possibly different from the node that detected | |
735 | * the error). Return the number of the csrow that sys_addr maps to, or -1 on | |
736 | * error. | |
737 | */ | |
738 | static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) | |
739 | { | |
740 | int csrow; | |
741 | ||
742 | csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); | |
743 | ||
744 | if (csrow == -1) | |
24f9a7fe BP |
745 | amd64_mc_err(mci, "Failed to translate InputAddr to csrow for " |
746 | "address 0x%lx\n", (unsigned long)sys_addr); | |
93c2df58 DT |
747 | return csrow; |
748 | } | |
e2ce7255 | 749 | |
bfc04aec | 750 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); |
2da11654 | 751 | |
2da11654 DT |
752 | /* |
753 | * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs | |
754 | * are ECC capable. | |
755 | */ | |
756 | static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt) | |
757 | { | |
cb328507 | 758 | u8 bit; |
584fcff4 | 759 | enum dev_type edac_cap = EDAC_FLAG_NONE; |
2da11654 | 760 | |
1433eb99 | 761 | bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F) |
2da11654 DT |
762 | ? 19 |
763 | : 17; | |
764 | ||
584fcff4 | 765 | if (pvt->dclr0 & BIT(bit)) |
2da11654 DT |
766 | edac_cap = EDAC_FLAG_SECDED; |
767 | ||
768 | return edac_cap; | |
769 | } | |
770 | ||
771 | ||
8566c4df | 772 | static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt); |
2da11654 | 773 | |
68798e17 BP |
774 | static void amd64_dump_dramcfg_low(u32 dclr, int chan) |
775 | { | |
776 | debugf1("F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr); | |
777 | ||
778 | debugf1(" DIMM type: %sbuffered; all DIMMs support ECC: %s\n", | |
779 | (dclr & BIT(16)) ? "un" : "", | |
780 | (dclr & BIT(19)) ? "yes" : "no"); | |
781 | ||
782 | debugf1(" PAR/ERR parity: %s\n", | |
783 | (dclr & BIT(8)) ? "enabled" : "disabled"); | |
784 | ||
cb328507 BP |
785 | if (boot_cpu_data.x86 == 0x10) |
786 | debugf1(" DCT 128bit mode width: %s\n", | |
787 | (dclr & BIT(11)) ? "128b" : "64b"); | |
68798e17 BP |
788 | |
789 | debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", | |
790 | (dclr & BIT(12)) ? "yes" : "no", | |
791 | (dclr & BIT(13)) ? "yes" : "no", | |
792 | (dclr & BIT(14)) ? "yes" : "no", | |
793 | (dclr & BIT(15)) ? "yes" : "no"); | |
794 | } | |
795 | ||
2da11654 | 796 | /* Display and decode various NB registers for debug purposes. */ |
b2b0c605 | 797 | static void dump_misc_regs(struct amd64_pvt *pvt) |
2da11654 | 798 | { |
68798e17 BP |
799 | debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); |
800 | ||
801 | debugf1(" NB two channel DRAM capable: %s\n", | |
5980bb9c | 802 | (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); |
2da11654 | 803 | |
68798e17 | 804 | debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n", |
5980bb9c BP |
805 | (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", |
806 | (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); | |
68798e17 BP |
807 | |
808 | amd64_dump_dramcfg_low(pvt->dclr0, 0); | |
2da11654 | 809 | |
8de1d91e | 810 | debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); |
2da11654 | 811 | |
8de1d91e BP |
812 | debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, " |
813 | "offset: 0x%08x\n", | |
bc21fa57 BP |
814 | pvt->dhar, dhar_base(pvt), |
815 | (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt) | |
816 | : f10_dhar_offset(pvt)); | |
2da11654 | 817 | |
c8e518d5 | 818 | debugf1(" DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); |
2da11654 | 819 | |
4d796364 BP |
820 | amd64_debug_display_dimm_sizes(0, pvt); |
821 | ||
8de1d91e | 822 | /* everything below this point is Fam10h and above */ |
4d796364 | 823 | if (boot_cpu_data.x86 == 0xf) |
2da11654 | 824 | return; |
4d796364 BP |
825 | |
826 | amd64_debug_display_dimm_sizes(1, pvt); | |
2da11654 | 827 | |
a3b7db09 | 828 | amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4")); |
ad6a32e9 | 829 | |
8de1d91e | 830 | /* Only if NOT ganged does dclr1 have valid info */ |
68798e17 BP |
831 | if (!dct_ganging_enabled(pvt)) |
832 | amd64_dump_dramcfg_low(pvt->dclr1, 1); | |
2da11654 DT |
833 | } |
834 | ||
94be4bff | 835 | /* |
11c75ead | 836 | * see BKDG, F2x[1,0][5C:40], F2[1,0][6C:60] |
94be4bff | 837 | */ |
11c75ead | 838 | static void prep_chip_selects(struct amd64_pvt *pvt) |
94be4bff | 839 | { |
1433eb99 | 840 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) { |
11c75ead BP |
841 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; |
842 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; | |
9d858bb1 | 843 | } else { |
11c75ead BP |
844 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; |
845 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; | |
94be4bff DT |
846 | } |
847 | } | |
848 | ||
849 | /* | |
11c75ead | 850 | * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers |
94be4bff | 851 | */ |
b2b0c605 | 852 | static void read_dct_base_mask(struct amd64_pvt *pvt) |
94be4bff | 853 | { |
11c75ead | 854 | int cs; |
94be4bff | 855 | |
11c75ead | 856 | prep_chip_selects(pvt); |
94be4bff | 857 | |
11c75ead BP |
858 | for_each_chip_select(cs, 0, pvt) { |
859 | u32 reg0 = DCSB0 + (cs * 4); | |
860 | u32 reg1 = DCSB1 + (cs * 4); | |
861 | u32 *base0 = &pvt->csels[0].csbases[cs]; | |
862 | u32 *base1 = &pvt->csels[1].csbases[cs]; | |
b2b0c605 | 863 | |
11c75ead | 864 | if (!amd64_read_dct_pci_cfg(pvt, reg0, base0)) |
94be4bff | 865 | debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n", |
11c75ead | 866 | cs, *base0, reg0); |
94be4bff | 867 | |
11c75ead BP |
868 | if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt)) |
869 | continue; | |
b2b0c605 | 870 | |
11c75ead BP |
871 | if (!amd64_read_dct_pci_cfg(pvt, reg1, base1)) |
872 | debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n", | |
873 | cs, *base1, reg1); | |
94be4bff DT |
874 | } |
875 | ||
11c75ead BP |
876 | for_each_chip_select_mask(cs, 0, pvt) { |
877 | u32 reg0 = DCSM0 + (cs * 4); | |
878 | u32 reg1 = DCSM1 + (cs * 4); | |
879 | u32 *mask0 = &pvt->csels[0].csmasks[cs]; | |
880 | u32 *mask1 = &pvt->csels[1].csmasks[cs]; | |
b2b0c605 | 881 | |
11c75ead | 882 | if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0)) |
94be4bff | 883 | debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n", |
11c75ead | 884 | cs, *mask0, reg0); |
94be4bff | 885 | |
11c75ead BP |
886 | if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt)) |
887 | continue; | |
b2b0c605 | 888 | |
11c75ead BP |
889 | if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1)) |
890 | debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n", | |
891 | cs, *mask1, reg1); | |
94be4bff DT |
892 | } |
893 | } | |
894 | ||
24f9a7fe | 895 | static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt, int cs) |
94be4bff DT |
896 | { |
897 | enum mem_type type; | |
898 | ||
cb328507 BP |
899 | /* F15h supports only DDR3 */ |
900 | if (boot_cpu_data.x86 >= 0x15) | |
901 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; | |
902 | else if (boot_cpu_data.x86 == 0x10 || pvt->ext_model >= K8_REV_F) { | |
6b4c0bde BP |
903 | if (pvt->dchr0 & DDR3_MODE) |
904 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; | |
905 | else | |
906 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; | |
94be4bff | 907 | } else { |
94be4bff DT |
908 | type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; |
909 | } | |
910 | ||
24f9a7fe | 911 | amd64_info("CS%d: %s\n", cs, edac_mem_types[type]); |
94be4bff DT |
912 | |
913 | return type; | |
914 | } | |
915 | ||
cb328507 | 916 | /* Get the number of DCT channels the memory controller is using. */ |
ddff876d DT |
917 | static int k8_early_channel_count(struct amd64_pvt *pvt) |
918 | { | |
cb328507 | 919 | int flag; |
ddff876d | 920 | |
9f56da0e | 921 | if (pvt->ext_model >= K8_REV_F) |
ddff876d | 922 | /* RevF (NPT) and later */ |
41d8bfab | 923 | flag = pvt->dclr0 & WIDTH_128; |
9f56da0e | 924 | else |
ddff876d DT |
925 | /* RevE and earlier */ |
926 | flag = pvt->dclr0 & REVE_WIDTH_128; | |
ddff876d DT |
927 | |
928 | /* not used */ | |
929 | pvt->dclr1 = 0; | |
930 | ||
931 | return (flag) ? 2 : 1; | |
932 | } | |
933 | ||
70046624 BP |
934 | /* On F10h and later ErrAddr is MC4_ADDR[47:1] */ |
935 | static u64 get_error_address(struct mce *m) | |
ddff876d | 936 | { |
70046624 BP |
937 | u8 start_bit = 1; |
938 | u8 end_bit = 47; | |
939 | ||
940 | if (boot_cpu_data.x86 == 0xf) { | |
941 | start_bit = 3; | |
942 | end_bit = 39; | |
943 | } | |
944 | ||
945 | return m->addr & GENMASK(start_bit, end_bit); | |
ddff876d DT |
946 | } |
947 | ||
7f19bf75 | 948 | static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) |
ddff876d | 949 | { |
7f19bf75 | 950 | u32 off = range << 3; |
ddff876d | 951 | |
7f19bf75 BP |
952 | amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); |
953 | amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); | |
ddff876d | 954 | |
7f19bf75 BP |
955 | if (boot_cpu_data.x86 == 0xf) |
956 | return; | |
ddff876d | 957 | |
7f19bf75 BP |
958 | if (!dram_rw(pvt, range)) |
959 | return; | |
ddff876d | 960 | |
7f19bf75 BP |
961 | amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); |
962 | amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); | |
ddff876d DT |
963 | } |
964 | ||
f192c7b1 BP |
965 | static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, |
966 | u16 syndrome) | |
ddff876d DT |
967 | { |
968 | struct mem_ctl_info *src_mci; | |
f192c7b1 | 969 | struct amd64_pvt *pvt = mci->pvt_info; |
ddff876d DT |
970 | int channel, csrow; |
971 | u32 page, offset; | |
ddff876d DT |
972 | |
973 | /* CHIPKILL enabled */ | |
f192c7b1 | 974 | if (pvt->nbcfg & NBCFG_CHIPKILL) { |
bfc04aec | 975 | channel = get_channel_from_ecc_syndrome(mci, syndrome); |
ddff876d DT |
976 | if (channel < 0) { |
977 | /* | |
978 | * Syndrome didn't map, so we don't know which of the | |
979 | * 2 DIMMs is in error. So we need to ID 'both' of them | |
980 | * as suspect. | |
981 | */ | |
24f9a7fe BP |
982 | amd64_mc_warn(mci, "unknown syndrome 0x%04x - possible " |
983 | "error reporting race\n", syndrome); | |
ddff876d DT |
984 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); |
985 | return; | |
986 | } | |
987 | } else { | |
988 | /* | |
989 | * non-chipkill ecc mode | |
990 | * | |
991 | * The k8 documentation is unclear about how to determine the | |
992 | * channel number when using non-chipkill memory. This method | |
993 | * was obtained from email communication with someone at AMD. | |
994 | * (Wish the email was placed in this comment - norsk) | |
995 | */ | |
44e9e2ee | 996 | channel = ((sys_addr & BIT(3)) != 0); |
ddff876d DT |
997 | } |
998 | ||
999 | /* | |
1000 | * Find out which node the error address belongs to. This may be | |
1001 | * different from the node that detected the error. | |
1002 | */ | |
44e9e2ee | 1003 | src_mci = find_mc_by_sys_addr(mci, sys_addr); |
2cff18c2 | 1004 | if (!src_mci) { |
24f9a7fe | 1005 | amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n", |
44e9e2ee | 1006 | (unsigned long)sys_addr); |
ddff876d DT |
1007 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); |
1008 | return; | |
1009 | } | |
1010 | ||
44e9e2ee BP |
1011 | /* Now map the sys_addr to a CSROW */ |
1012 | csrow = sys_addr_to_csrow(src_mci, sys_addr); | |
ddff876d DT |
1013 | if (csrow < 0) { |
1014 | edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR); | |
1015 | } else { | |
44e9e2ee | 1016 | error_address_to_page_and_offset(sys_addr, &page, &offset); |
ddff876d DT |
1017 | |
1018 | edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow, | |
1019 | channel, EDAC_MOD_STR); | |
1020 | } | |
1021 | } | |
1022 | ||
41d8bfab | 1023 | static int ddr2_cs_size(unsigned i, bool dct_width) |
ddff876d | 1024 | { |
41d8bfab | 1025 | unsigned shift = 0; |
ddff876d | 1026 | |
41d8bfab BP |
1027 | if (i <= 2) |
1028 | shift = i; | |
1029 | else if (!(i & 0x1)) | |
1030 | shift = i >> 1; | |
1433eb99 | 1031 | else |
41d8bfab | 1032 | shift = (i + 1) >> 1; |
ddff876d | 1033 | |
41d8bfab BP |
1034 | return 128 << (shift + !!dct_width); |
1035 | } | |
1036 | ||
1037 | static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
1038 | unsigned cs_mode) | |
1039 | { | |
1040 | u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; | |
1041 | ||
1042 | if (pvt->ext_model >= K8_REV_F) { | |
1043 | WARN_ON(cs_mode > 11); | |
1044 | return ddr2_cs_size(cs_mode, dclr & WIDTH_128); | |
1045 | } | |
1046 | else if (pvt->ext_model >= K8_REV_D) { | |
1047 | WARN_ON(cs_mode > 10); | |
1048 | ||
1049 | if (cs_mode == 3 || cs_mode == 8) | |
1050 | return 32 << (cs_mode - 1); | |
1051 | else | |
1052 | return 32 << cs_mode; | |
1053 | } | |
1054 | else { | |
1055 | WARN_ON(cs_mode > 6); | |
1056 | return 32 << cs_mode; | |
1057 | } | |
ddff876d DT |
1058 | } |
1059 | ||
1afd3c98 DT |
1060 | /* |
1061 | * Get the number of DCT channels in use. | |
1062 | * | |
1063 | * Return: | |
1064 | * number of Memory Channels in operation | |
1065 | * Pass back: | |
1066 | * contents of the DCL0_LOW register | |
1067 | */ | |
7d20d14d | 1068 | static int f1x_early_channel_count(struct amd64_pvt *pvt) |
1afd3c98 | 1069 | { |
6ba5dcdc | 1070 | int i, j, channels = 0; |
1afd3c98 | 1071 | |
7d20d14d | 1072 | /* On F10h, if we are in 128 bit mode, then we are using 2 channels */ |
41d8bfab | 1073 | if (boot_cpu_data.x86 == 0x10 && (pvt->dclr0 & WIDTH_128)) |
7d20d14d | 1074 | return 2; |
1afd3c98 DT |
1075 | |
1076 | /* | |
d16149e8 BP |
1077 | * Need to check if in unganged mode: In such, there are 2 channels, |
1078 | * but they are not in 128 bit mode and thus the above 'dclr0' status | |
1079 | * bit will be OFF. | |
1afd3c98 DT |
1080 | * |
1081 | * Need to check DCT0[0] and DCT1[0] to see if only one of them has | |
1082 | * their CSEnable bit on. If so, then SINGLE DIMM case. | |
1083 | */ | |
d16149e8 | 1084 | debugf0("Data width is not 128 bits - need more decoding\n"); |
ddff876d | 1085 | |
1afd3c98 DT |
1086 | /* |
1087 | * Check DRAM Bank Address Mapping values for each DIMM to see if there | |
1088 | * is more than just one DIMM present in unganged mode. Need to check | |
1089 | * both controllers since DIMMs can be placed in either one. | |
1090 | */ | |
525a1b20 BP |
1091 | for (i = 0; i < 2; i++) { |
1092 | u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); | |
1afd3c98 | 1093 | |
57a30854 WW |
1094 | for (j = 0; j < 4; j++) { |
1095 | if (DBAM_DIMM(j, dbam) > 0) { | |
1096 | channels++; | |
1097 | break; | |
1098 | } | |
1099 | } | |
1afd3c98 DT |
1100 | } |
1101 | ||
d16149e8 BP |
1102 | if (channels > 2) |
1103 | channels = 2; | |
1104 | ||
24f9a7fe | 1105 | amd64_info("MCT channel count: %d\n", channels); |
1afd3c98 DT |
1106 | |
1107 | return channels; | |
1afd3c98 DT |
1108 | } |
1109 | ||
41d8bfab | 1110 | static int ddr3_cs_size(unsigned i, bool dct_width) |
1afd3c98 | 1111 | { |
41d8bfab BP |
1112 | unsigned shift = 0; |
1113 | int cs_size = 0; | |
1114 | ||
1115 | if (i == 0 || i == 3 || i == 4) | |
1116 | cs_size = -1; | |
1117 | else if (i <= 2) | |
1118 | shift = i; | |
1119 | else if (i == 12) | |
1120 | shift = 7; | |
1121 | else if (!(i & 0x1)) | |
1122 | shift = i >> 1; | |
1123 | else | |
1124 | shift = (i + 1) >> 1; | |
1125 | ||
1126 | if (cs_size != -1) | |
1127 | cs_size = (128 * (1 << !!dct_width)) << shift; | |
1128 | ||
1129 | return cs_size; | |
1130 | } | |
1131 | ||
1132 | static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
1133 | unsigned cs_mode) | |
1134 | { | |
1135 | u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; | |
1136 | ||
1137 | WARN_ON(cs_mode > 11); | |
1433eb99 BP |
1138 | |
1139 | if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) | |
41d8bfab | 1140 | return ddr3_cs_size(cs_mode, dclr & WIDTH_128); |
1433eb99 | 1141 | else |
41d8bfab BP |
1142 | return ddr2_cs_size(cs_mode, dclr & WIDTH_128); |
1143 | } | |
1144 | ||
1145 | /* | |
1146 | * F15h supports only 64bit DCT interfaces | |
1147 | */ | |
1148 | static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
1149 | unsigned cs_mode) | |
1150 | { | |
1151 | WARN_ON(cs_mode > 12); | |
1433eb99 | 1152 | |
41d8bfab | 1153 | return ddr3_cs_size(cs_mode, false); |
1afd3c98 DT |
1154 | } |
1155 | ||
5a5d2371 | 1156 | static void read_dram_ctl_register(struct amd64_pvt *pvt) |
6163b5d4 | 1157 | { |
6163b5d4 | 1158 | |
5a5d2371 BP |
1159 | if (boot_cpu_data.x86 == 0xf) |
1160 | return; | |
1161 | ||
78da121e BP |
1162 | if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) { |
1163 | debugf0("F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n", | |
1164 | pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); | |
72381bd5 | 1165 | |
5a5d2371 BP |
1166 | debugf0(" DCTs operate in %s mode.\n", |
1167 | (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); | |
72381bd5 BP |
1168 | |
1169 | if (!dct_ganging_enabled(pvt)) | |
1170 | debugf0(" Address range split per DCT: %s\n", | |
1171 | (dct_high_range_enabled(pvt) ? "yes" : "no")); | |
1172 | ||
78da121e | 1173 | debugf0(" data interleave for ECC: %s, " |
72381bd5 BP |
1174 | "DRAM cleared since last warm reset: %s\n", |
1175 | (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), | |
1176 | (dct_memory_cleared(pvt) ? "yes" : "no")); | |
1177 | ||
78da121e BP |
1178 | debugf0(" channel interleave: %s, " |
1179 | "interleave bits selector: 0x%x\n", | |
72381bd5 | 1180 | (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), |
6163b5d4 DT |
1181 | dct_sel_interleave_addr(pvt)); |
1182 | } | |
1183 | ||
78da121e | 1184 | amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi); |
6163b5d4 DT |
1185 | } |
1186 | ||
f71d0a05 | 1187 | /* |
229a7a11 | 1188 | * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory |
f71d0a05 DT |
1189 | * Interleaving Modes. |
1190 | */ | |
b15f0fca | 1191 | static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, |
229a7a11 | 1192 | bool hi_range_sel, u8 intlv_en) |
6163b5d4 | 1193 | { |
151fa71c | 1194 | u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; |
6163b5d4 DT |
1195 | |
1196 | if (dct_ganging_enabled(pvt)) | |
229a7a11 | 1197 | return 0; |
6163b5d4 | 1198 | |
229a7a11 BP |
1199 | if (hi_range_sel) |
1200 | return dct_sel_high; | |
6163b5d4 | 1201 | |
229a7a11 BP |
1202 | /* |
1203 | * see F2x110[DctSelIntLvAddr] - channel interleave mode | |
1204 | */ | |
1205 | if (dct_interleave_enabled(pvt)) { | |
1206 | u8 intlv_addr = dct_sel_interleave_addr(pvt); | |
1207 | ||
1208 | /* return DCT select function: 0=DCT0, 1=DCT1 */ | |
1209 | if (!intlv_addr) | |
1210 | return sys_addr >> 6 & 1; | |
1211 | ||
1212 | if (intlv_addr & 0x2) { | |
1213 | u8 shift = intlv_addr & 0x1 ? 9 : 6; | |
1214 | u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; | |
1215 | ||
1216 | return ((sys_addr >> shift) & 1) ^ temp; | |
1217 | } | |
1218 | ||
1219 | return (sys_addr >> (12 + hweight8(intlv_en))) & 1; | |
1220 | } | |
1221 | ||
1222 | if (dct_high_range_enabled(pvt)) | |
1223 | return ~dct_sel_high & 1; | |
6163b5d4 DT |
1224 | |
1225 | return 0; | |
1226 | } | |
1227 | ||
c8e518d5 | 1228 | /* Convert the sys_addr to the normalized DCT address */ |
b15f0fca | 1229 | static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, int range, |
c8e518d5 BP |
1230 | u64 sys_addr, bool hi_rng, |
1231 | u32 dct_sel_base_addr) | |
6163b5d4 DT |
1232 | { |
1233 | u64 chan_off; | |
c8e518d5 BP |
1234 | u64 dram_base = get_dram_base(pvt, range); |
1235 | u64 hole_off = f10_dhar_offset(pvt); | |
1236 | u32 hole_valid = dhar_valid(pvt); | |
1237 | u64 dct_sel_base_off = (pvt->dct_sel_hi & 0xFFFFFC00) << 16; | |
6163b5d4 | 1238 | |
c8e518d5 BP |
1239 | if (hi_rng) { |
1240 | /* | |
1241 | * if | |
1242 | * base address of high range is below 4Gb | |
1243 | * (bits [47:27] at [31:11]) | |
1244 | * DRAM address space on this DCT is hoisted above 4Gb && | |
1245 | * sys_addr > 4Gb | |
1246 | * | |
1247 | * remove hole offset from sys_addr | |
1248 | * else | |
1249 | * remove high range offset from sys_addr | |
1250 | */ | |
1251 | if ((!(dct_sel_base_addr >> 16) || | |
1252 | dct_sel_base_addr < dhar_base(pvt)) && | |
1253 | hole_valid && | |
1254 | (sys_addr >= BIT_64(32))) | |
bc21fa57 | 1255 | chan_off = hole_off; |
6163b5d4 DT |
1256 | else |
1257 | chan_off = dct_sel_base_off; | |
1258 | } else { | |
c8e518d5 BP |
1259 | /* |
1260 | * if | |
1261 | * we have a valid hole && | |
1262 | * sys_addr > 4Gb | |
1263 | * | |
1264 | * remove hole | |
1265 | * else | |
1266 | * remove dram base to normalize to DCT address | |
1267 | */ | |
1268 | if (hole_valid && (sys_addr >= BIT_64(32))) | |
bc21fa57 | 1269 | chan_off = hole_off; |
6163b5d4 | 1270 | else |
c8e518d5 | 1271 | chan_off = dram_base; |
6163b5d4 DT |
1272 | } |
1273 | ||
c8e518d5 | 1274 | return (sys_addr & GENMASK(6,47)) - (chan_off & GENMASK(23,47)); |
6163b5d4 DT |
1275 | } |
1276 | ||
6163b5d4 DT |
1277 | /* |
1278 | * checks if the csrow passed in is marked as SPARED, if so returns the new | |
1279 | * spare row | |
1280 | */ | |
11c75ead | 1281 | static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) |
6163b5d4 | 1282 | { |
614ec9d8 BP |
1283 | int tmp_cs; |
1284 | ||
1285 | if (online_spare_swap_done(pvt, dct) && | |
1286 | csrow == online_spare_bad_dramcs(pvt, dct)) { | |
1287 | ||
1288 | for_each_chip_select(tmp_cs, dct, pvt) { | |
1289 | if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { | |
1290 | csrow = tmp_cs; | |
1291 | break; | |
1292 | } | |
1293 | } | |
6163b5d4 DT |
1294 | } |
1295 | return csrow; | |
1296 | } | |
1297 | ||
1298 | /* | |
1299 | * Iterate over the DRAM DCT "base" and "mask" registers looking for a | |
1300 | * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' | |
1301 | * | |
1302 | * Return: | |
1303 | * -EINVAL: NOT FOUND | |
1304 | * 0..csrow = Chip-Select Row | |
1305 | */ | |
b15f0fca | 1306 | static int f1x_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct) |
6163b5d4 DT |
1307 | { |
1308 | struct mem_ctl_info *mci; | |
1309 | struct amd64_pvt *pvt; | |
11c75ead | 1310 | u64 cs_base, cs_mask; |
6163b5d4 DT |
1311 | int cs_found = -EINVAL; |
1312 | int csrow; | |
1313 | ||
cc4d8860 | 1314 | mci = mcis[nid]; |
6163b5d4 DT |
1315 | if (!mci) |
1316 | return cs_found; | |
1317 | ||
1318 | pvt = mci->pvt_info; | |
1319 | ||
11c75ead | 1320 | debugf1("input addr: 0x%llx, DCT: %d\n", in_addr, dct); |
6163b5d4 | 1321 | |
11c75ead BP |
1322 | for_each_chip_select(csrow, dct, pvt) { |
1323 | if (!csrow_enabled(csrow, dct, pvt)) | |
6163b5d4 DT |
1324 | continue; |
1325 | ||
11c75ead | 1326 | get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); |
6163b5d4 | 1327 | |
11c75ead BP |
1328 | debugf1(" CSROW=%d CSBase=0x%llx CSMask=0x%llx\n", |
1329 | csrow, cs_base, cs_mask); | |
6163b5d4 | 1330 | |
11c75ead | 1331 | cs_mask = ~cs_mask; |
6163b5d4 | 1332 | |
11c75ead BP |
1333 | debugf1(" (InputAddr & ~CSMask)=0x%llx " |
1334 | "(CSBase & ~CSMask)=0x%llx\n", | |
1335 | (in_addr & cs_mask), (cs_base & cs_mask)); | |
6163b5d4 | 1336 | |
11c75ead BP |
1337 | if ((in_addr & cs_mask) == (cs_base & cs_mask)) { |
1338 | cs_found = f10_process_possible_spare(pvt, dct, csrow); | |
6163b5d4 DT |
1339 | |
1340 | debugf1(" MATCH csrow=%d\n", cs_found); | |
1341 | break; | |
1342 | } | |
1343 | } | |
1344 | return cs_found; | |
1345 | } | |
1346 | ||
95b0ef55 BP |
1347 | /* |
1348 | * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is | |
1349 | * swapped with a region located at the bottom of memory so that the GPU can use | |
1350 | * the interleaved region and thus two channels. | |
1351 | */ | |
b15f0fca | 1352 | static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) |
95b0ef55 BP |
1353 | { |
1354 | u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr; | |
1355 | ||
1356 | if (boot_cpu_data.x86 == 0x10) { | |
1357 | /* only revC3 and revE have that feature */ | |
1358 | if (boot_cpu_data.x86_model < 4 || | |
1359 | (boot_cpu_data.x86_model < 0xa && | |
1360 | boot_cpu_data.x86_mask < 3)) | |
1361 | return sys_addr; | |
1362 | } | |
1363 | ||
1364 | amd64_read_dct_pci_cfg(pvt, SWAP_INTLV_REG, &swap_reg); | |
1365 | ||
1366 | if (!(swap_reg & 0x1)) | |
1367 | return sys_addr; | |
1368 | ||
1369 | swap_base = (swap_reg >> 3) & 0x7f; | |
1370 | swap_limit = (swap_reg >> 11) & 0x7f; | |
1371 | rgn_size = (swap_reg >> 20) & 0x7f; | |
1372 | tmp_addr = sys_addr >> 27; | |
1373 | ||
1374 | if (!(sys_addr >> 34) && | |
1375 | (((tmp_addr >= swap_base) && | |
1376 | (tmp_addr <= swap_limit)) || | |
1377 | (tmp_addr < rgn_size))) | |
1378 | return sys_addr ^ (u64)swap_base << 27; | |
1379 | ||
1380 | return sys_addr; | |
1381 | } | |
1382 | ||
f71d0a05 | 1383 | /* For a given @dram_range, check if @sys_addr falls within it. */ |
b15f0fca | 1384 | static int f1x_match_to_this_node(struct amd64_pvt *pvt, int range, |
f71d0a05 DT |
1385 | u64 sys_addr, int *nid, int *chan_sel) |
1386 | { | |
229a7a11 | 1387 | int cs_found = -EINVAL; |
c8e518d5 | 1388 | u64 chan_addr; |
5d4b58e8 | 1389 | u32 dct_sel_base; |
11c75ead | 1390 | u8 channel; |
229a7a11 | 1391 | bool high_range = false; |
f71d0a05 | 1392 | |
7f19bf75 | 1393 | u8 node_id = dram_dst_node(pvt, range); |
229a7a11 | 1394 | u8 intlv_en = dram_intlv_en(pvt, range); |
7f19bf75 | 1395 | u32 intlv_sel = dram_intlv_sel(pvt, range); |
f71d0a05 | 1396 | |
c8e518d5 BP |
1397 | debugf1("(range %d) SystemAddr= 0x%llx Limit=0x%llx\n", |
1398 | range, sys_addr, get_dram_limit(pvt, range)); | |
f71d0a05 | 1399 | |
355fba60 BP |
1400 | if (dhar_valid(pvt) && |
1401 | dhar_base(pvt) <= sys_addr && | |
1402 | sys_addr < BIT_64(32)) { | |
1403 | amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n", | |
1404 | sys_addr); | |
1405 | return -EINVAL; | |
1406 | } | |
1407 | ||
e726f3c3 | 1408 | if (intlv_en && |
355fba60 BP |
1409 | (intlv_sel != ((sys_addr >> 12) & intlv_en))) { |
1410 | amd64_warn("Botched intlv bits, en: 0x%x, sel: 0x%x\n", | |
1411 | intlv_en, intlv_sel); | |
f71d0a05 | 1412 | return -EINVAL; |
355fba60 | 1413 | } |
f71d0a05 | 1414 | |
b15f0fca | 1415 | sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); |
95b0ef55 | 1416 | |
f71d0a05 DT |
1417 | dct_sel_base = dct_sel_baseaddr(pvt); |
1418 | ||
1419 | /* | |
1420 | * check whether addresses >= DctSelBaseAddr[47:27] are to be used to | |
1421 | * select between DCT0 and DCT1. | |
1422 | */ | |
1423 | if (dct_high_range_enabled(pvt) && | |
1424 | !dct_ganging_enabled(pvt) && | |
1425 | ((sys_addr >> 27) >= (dct_sel_base >> 11))) | |
229a7a11 | 1426 | high_range = true; |
f71d0a05 | 1427 | |
b15f0fca | 1428 | channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); |
f71d0a05 | 1429 | |
b15f0fca | 1430 | chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, |
c8e518d5 | 1431 | high_range, dct_sel_base); |
f71d0a05 | 1432 | |
e2f79dbd BP |
1433 | /* Remove node interleaving, see F1x120 */ |
1434 | if (intlv_en) | |
1435 | chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) | | |
1436 | (chan_addr & 0xfff); | |
f71d0a05 | 1437 | |
5d4b58e8 | 1438 | /* remove channel interleave */ |
f71d0a05 DT |
1439 | if (dct_interleave_enabled(pvt) && |
1440 | !dct_high_range_enabled(pvt) && | |
1441 | !dct_ganging_enabled(pvt)) { | |
5d4b58e8 BP |
1442 | |
1443 | if (dct_sel_interleave_addr(pvt) != 1) { | |
1444 | if (dct_sel_interleave_addr(pvt) == 0x3) | |
1445 | /* hash 9 */ | |
1446 | chan_addr = ((chan_addr >> 10) << 9) | | |
1447 | (chan_addr & 0x1ff); | |
1448 | else | |
1449 | /* A[6] or hash 6 */ | |
1450 | chan_addr = ((chan_addr >> 7) << 6) | | |
1451 | (chan_addr & 0x3f); | |
1452 | } else | |
1453 | /* A[12] */ | |
1454 | chan_addr = ((chan_addr >> 13) << 12) | | |
1455 | (chan_addr & 0xfff); | |
f71d0a05 DT |
1456 | } |
1457 | ||
5d4b58e8 | 1458 | debugf1(" Normalized DCT addr: 0x%llx\n", chan_addr); |
f71d0a05 | 1459 | |
b15f0fca | 1460 | cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel); |
f71d0a05 DT |
1461 | |
1462 | if (cs_found >= 0) { | |
1463 | *nid = node_id; | |
1464 | *chan_sel = channel; | |
1465 | } | |
1466 | return cs_found; | |
1467 | } | |
1468 | ||
b15f0fca | 1469 | static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr, |
f71d0a05 DT |
1470 | int *node, int *chan_sel) |
1471 | { | |
7f19bf75 | 1472 | int range, cs_found = -EINVAL; |
f71d0a05 | 1473 | |
7f19bf75 | 1474 | for (range = 0; range < DRAM_RANGES; range++) { |
f71d0a05 | 1475 | |
7f19bf75 | 1476 | if (!dram_rw(pvt, range)) |
f71d0a05 DT |
1477 | continue; |
1478 | ||
7f19bf75 BP |
1479 | if ((get_dram_base(pvt, range) <= sys_addr) && |
1480 | (get_dram_limit(pvt, range) >= sys_addr)) { | |
f71d0a05 | 1481 | |
b15f0fca | 1482 | cs_found = f1x_match_to_this_node(pvt, range, |
f71d0a05 DT |
1483 | sys_addr, node, |
1484 | chan_sel); | |
1485 | if (cs_found >= 0) | |
1486 | break; | |
1487 | } | |
1488 | } | |
1489 | return cs_found; | |
1490 | } | |
1491 | ||
1492 | /* | |
bdc30a0c BP |
1493 | * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps |
1494 | * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW). | |
f71d0a05 | 1495 | * |
bdc30a0c BP |
1496 | * The @sys_addr is usually an error address received from the hardware |
1497 | * (MCX_ADDR). | |
f71d0a05 | 1498 | */ |
b15f0fca | 1499 | static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, |
f192c7b1 | 1500 | u16 syndrome) |
f71d0a05 DT |
1501 | { |
1502 | struct amd64_pvt *pvt = mci->pvt_info; | |
1503 | u32 page, offset; | |
f71d0a05 DT |
1504 | int nid, csrow, chan = 0; |
1505 | ||
b15f0fca | 1506 | csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan); |
f71d0a05 | 1507 | |
bdc30a0c BP |
1508 | if (csrow < 0) { |
1509 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1510 | return; | |
1511 | } | |
1512 | ||
1513 | error_address_to_page_and_offset(sys_addr, &page, &offset); | |
f71d0a05 | 1514 | |
bdc30a0c BP |
1515 | /* |
1516 | * We need the syndromes for channel detection only when we're | |
1517 | * ganged. Otherwise @chan should already contain the channel at | |
1518 | * this point. | |
1519 | */ | |
a97fa68e | 1520 | if (dct_ganging_enabled(pvt)) |
bdc30a0c | 1521 | chan = get_channel_from_ecc_syndrome(mci, syndrome); |
f71d0a05 | 1522 | |
bdc30a0c BP |
1523 | if (chan >= 0) |
1524 | edac_mc_handle_ce(mci, page, offset, syndrome, csrow, chan, | |
1525 | EDAC_MOD_STR); | |
1526 | else | |
f71d0a05 | 1527 | /* |
bdc30a0c | 1528 | * Channel unknown, report all channels on this CSROW as failed. |
f71d0a05 | 1529 | */ |
bdc30a0c | 1530 | for (chan = 0; chan < mci->csrows[csrow].nr_channels; chan++) |
f71d0a05 | 1531 | edac_mc_handle_ce(mci, page, offset, syndrome, |
bdc30a0c | 1532 | csrow, chan, EDAC_MOD_STR); |
f71d0a05 DT |
1533 | } |
1534 | ||
f71d0a05 | 1535 | /* |
8566c4df | 1536 | * debug routine to display the memory sizes of all logical DIMMs and its |
cb328507 | 1537 | * CSROWs |
f71d0a05 | 1538 | */ |
8566c4df | 1539 | static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt) |
f71d0a05 | 1540 | { |
603adaf6 | 1541 | int dimm, size0, size1, factor = 0; |
525a1b20 BP |
1542 | u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; |
1543 | u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; | |
f71d0a05 | 1544 | |
8566c4df | 1545 | if (boot_cpu_data.x86 == 0xf) { |
41d8bfab | 1546 | if (pvt->dclr0 & WIDTH_128) |
603adaf6 BP |
1547 | factor = 1; |
1548 | ||
8566c4df | 1549 | /* K8 families < revF not supported yet */ |
1433eb99 | 1550 | if (pvt->ext_model < K8_REV_F) |
8566c4df BP |
1551 | return; |
1552 | else | |
1553 | WARN_ON(ctrl != 0); | |
1554 | } | |
1555 | ||
4d796364 | 1556 | dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 : pvt->dbam0; |
11c75ead BP |
1557 | dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases |
1558 | : pvt->csels[0].csbases; | |
f71d0a05 | 1559 | |
4d796364 | 1560 | debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", ctrl, dbam); |
f71d0a05 | 1561 | |
8566c4df BP |
1562 | edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl); |
1563 | ||
f71d0a05 DT |
1564 | /* Dump memory sizes for DIMM and its CSROWs */ |
1565 | for (dimm = 0; dimm < 4; dimm++) { | |
1566 | ||
1567 | size0 = 0; | |
11c75ead | 1568 | if (dcsb[dimm*2] & DCSB_CS_ENABLE) |
41d8bfab BP |
1569 | size0 = pvt->ops->dbam_to_cs(pvt, ctrl, |
1570 | DBAM_DIMM(dimm, dbam)); | |
f71d0a05 DT |
1571 | |
1572 | size1 = 0; | |
11c75ead | 1573 | if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE) |
41d8bfab BP |
1574 | size1 = pvt->ops->dbam_to_cs(pvt, ctrl, |
1575 | DBAM_DIMM(dimm, dbam)); | |
f71d0a05 | 1576 | |
24f9a7fe BP |
1577 | amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n", |
1578 | dimm * 2, size0 << factor, | |
1579 | dimm * 2 + 1, size1 << factor); | |
f71d0a05 DT |
1580 | } |
1581 | } | |
1582 | ||
4d37607a DT |
1583 | static struct amd64_family_type amd64_family_types[] = { |
1584 | [K8_CPUS] = { | |
0092b20d | 1585 | .ctl_name = "K8", |
8d5b5d9c BP |
1586 | .f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, |
1587 | .f3_id = PCI_DEVICE_ID_AMD_K8_NB_MISC, | |
4d37607a | 1588 | .ops = { |
1433eb99 | 1589 | .early_channel_count = k8_early_channel_count, |
1433eb99 BP |
1590 | .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, |
1591 | .dbam_to_cs = k8_dbam_to_chip_select, | |
b2b0c605 | 1592 | .read_dct_pci_cfg = k8_read_dct_pci_cfg, |
4d37607a DT |
1593 | } |
1594 | }, | |
1595 | [F10_CPUS] = { | |
0092b20d | 1596 | .ctl_name = "F10h", |
8d5b5d9c BP |
1597 | .f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP, |
1598 | .f3_id = PCI_DEVICE_ID_AMD_10H_NB_MISC, | |
4d37607a | 1599 | .ops = { |
7d20d14d | 1600 | .early_channel_count = f1x_early_channel_count, |
b15f0fca | 1601 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, |
1433eb99 | 1602 | .dbam_to_cs = f10_dbam_to_chip_select, |
b2b0c605 BP |
1603 | .read_dct_pci_cfg = f10_read_dct_pci_cfg, |
1604 | } | |
1605 | }, | |
1606 | [F15_CPUS] = { | |
1607 | .ctl_name = "F15h", | |
df71a053 BP |
1608 | .f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1, |
1609 | .f3_id = PCI_DEVICE_ID_AMD_15H_NB_F3, | |
b2b0c605 | 1610 | .ops = { |
7d20d14d | 1611 | .early_channel_count = f1x_early_channel_count, |
b15f0fca | 1612 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, |
41d8bfab | 1613 | .dbam_to_cs = f15_dbam_to_chip_select, |
b2b0c605 | 1614 | .read_dct_pci_cfg = f15_read_dct_pci_cfg, |
4d37607a DT |
1615 | } |
1616 | }, | |
4d37607a DT |
1617 | }; |
1618 | ||
1619 | static struct pci_dev *pci_get_related_function(unsigned int vendor, | |
1620 | unsigned int device, | |
1621 | struct pci_dev *related) | |
1622 | { | |
1623 | struct pci_dev *dev = NULL; | |
1624 | ||
1625 | dev = pci_get_device(vendor, device, dev); | |
1626 | while (dev) { | |
1627 | if ((dev->bus->number == related->bus->number) && | |
1628 | (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) | |
1629 | break; | |
1630 | dev = pci_get_device(vendor, device, dev); | |
1631 | } | |
1632 | ||
1633 | return dev; | |
1634 | } | |
1635 | ||
b1289d6f | 1636 | /* |
bfc04aec BP |
1637 | * These are tables of eigenvectors (one per line) which can be used for the |
1638 | * construction of the syndrome tables. The modified syndrome search algorithm | |
1639 | * uses those to find the symbol in error and thus the DIMM. | |
b1289d6f | 1640 | * |
bfc04aec | 1641 | * Algorithm courtesy of Ross LaFetra from AMD. |
b1289d6f | 1642 | */ |
bfc04aec BP |
1643 | static u16 x4_vectors[] = { |
1644 | 0x2f57, 0x1afe, 0x66cc, 0xdd88, | |
1645 | 0x11eb, 0x3396, 0x7f4c, 0xeac8, | |
1646 | 0x0001, 0x0002, 0x0004, 0x0008, | |
1647 | 0x1013, 0x3032, 0x4044, 0x8088, | |
1648 | 0x106b, 0x30d6, 0x70fc, 0xe0a8, | |
1649 | 0x4857, 0xc4fe, 0x13cc, 0x3288, | |
1650 | 0x1ac5, 0x2f4a, 0x5394, 0xa1e8, | |
1651 | 0x1f39, 0x251e, 0xbd6c, 0x6bd8, | |
1652 | 0x15c1, 0x2a42, 0x89ac, 0x4758, | |
1653 | 0x2b03, 0x1602, 0x4f0c, 0xca08, | |
1654 | 0x1f07, 0x3a0e, 0x6b04, 0xbd08, | |
1655 | 0x8ba7, 0x465e, 0x244c, 0x1cc8, | |
1656 | 0x2b87, 0x164e, 0x642c, 0xdc18, | |
1657 | 0x40b9, 0x80de, 0x1094, 0x20e8, | |
1658 | 0x27db, 0x1eb6, 0x9dac, 0x7b58, | |
1659 | 0x11c1, 0x2242, 0x84ac, 0x4c58, | |
1660 | 0x1be5, 0x2d7a, 0x5e34, 0xa718, | |
1661 | 0x4b39, 0x8d1e, 0x14b4, 0x28d8, | |
1662 | 0x4c97, 0xc87e, 0x11fc, 0x33a8, | |
1663 | 0x8e97, 0x497e, 0x2ffc, 0x1aa8, | |
1664 | 0x16b3, 0x3d62, 0x4f34, 0x8518, | |
1665 | 0x1e2f, 0x391a, 0x5cac, 0xf858, | |
1666 | 0x1d9f, 0x3b7a, 0x572c, 0xfe18, | |
1667 | 0x15f5, 0x2a5a, 0x5264, 0xa3b8, | |
1668 | 0x1dbb, 0x3b66, 0x715c, 0xe3f8, | |
1669 | 0x4397, 0xc27e, 0x17fc, 0x3ea8, | |
1670 | 0x1617, 0x3d3e, 0x6464, 0xb8b8, | |
1671 | 0x23ff, 0x12aa, 0xab6c, 0x56d8, | |
1672 | 0x2dfb, 0x1ba6, 0x913c, 0x7328, | |
1673 | 0x185d, 0x2ca6, 0x7914, 0x9e28, | |
1674 | 0x171b, 0x3e36, 0x7d7c, 0xebe8, | |
1675 | 0x4199, 0x82ee, 0x19f4, 0x2e58, | |
1676 | 0x4807, 0xc40e, 0x130c, 0x3208, | |
1677 | 0x1905, 0x2e0a, 0x5804, 0xac08, | |
1678 | 0x213f, 0x132a, 0xadfc, 0x5ba8, | |
1679 | 0x19a9, 0x2efe, 0xb5cc, 0x6f88, | |
b1289d6f DT |
1680 | }; |
1681 | ||
bfc04aec BP |
1682 | static u16 x8_vectors[] = { |
1683 | 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480, | |
1684 | 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80, | |
1685 | 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80, | |
1686 | 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80, | |
1687 | 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780, | |
1688 | 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080, | |
1689 | 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080, | |
1690 | 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080, | |
1691 | 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80, | |
1692 | 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580, | |
1693 | 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880, | |
1694 | 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280, | |
1695 | 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180, | |
1696 | 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580, | |
1697 | 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280, | |
1698 | 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180, | |
1699 | 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080, | |
1700 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
1701 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, | |
1702 | }; | |
1703 | ||
1704 | static int decode_syndrome(u16 syndrome, u16 *vectors, int num_vecs, | |
ad6a32e9 | 1705 | int v_dim) |
b1289d6f | 1706 | { |
bfc04aec BP |
1707 | unsigned int i, err_sym; |
1708 | ||
1709 | for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) { | |
1710 | u16 s = syndrome; | |
1711 | int v_idx = err_sym * v_dim; | |
1712 | int v_end = (err_sym + 1) * v_dim; | |
1713 | ||
1714 | /* walk over all 16 bits of the syndrome */ | |
1715 | for (i = 1; i < (1U << 16); i <<= 1) { | |
1716 | ||
1717 | /* if bit is set in that eigenvector... */ | |
1718 | if (v_idx < v_end && vectors[v_idx] & i) { | |
1719 | u16 ev_comp = vectors[v_idx++]; | |
1720 | ||
1721 | /* ... and bit set in the modified syndrome, */ | |
1722 | if (s & i) { | |
1723 | /* remove it. */ | |
1724 | s ^= ev_comp; | |
4d37607a | 1725 | |
bfc04aec BP |
1726 | if (!s) |
1727 | return err_sym; | |
1728 | } | |
b1289d6f | 1729 | |
bfc04aec BP |
1730 | } else if (s & i) |
1731 | /* can't get to zero, move to next symbol */ | |
1732 | break; | |
1733 | } | |
b1289d6f DT |
1734 | } |
1735 | ||
1736 | debugf0("syndrome(%x) not found\n", syndrome); | |
1737 | return -1; | |
1738 | } | |
d27bf6fa | 1739 | |
bfc04aec BP |
1740 | static int map_err_sym_to_channel(int err_sym, int sym_size) |
1741 | { | |
1742 | if (sym_size == 4) | |
1743 | switch (err_sym) { | |
1744 | case 0x20: | |
1745 | case 0x21: | |
1746 | return 0; | |
1747 | break; | |
1748 | case 0x22: | |
1749 | case 0x23: | |
1750 | return 1; | |
1751 | break; | |
1752 | default: | |
1753 | return err_sym >> 4; | |
1754 | break; | |
1755 | } | |
1756 | /* x8 symbols */ | |
1757 | else | |
1758 | switch (err_sym) { | |
1759 | /* imaginary bits not in a DIMM */ | |
1760 | case 0x10: | |
1761 | WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n", | |
1762 | err_sym); | |
1763 | return -1; | |
1764 | break; | |
1765 | ||
1766 | case 0x11: | |
1767 | return 0; | |
1768 | break; | |
1769 | case 0x12: | |
1770 | return 1; | |
1771 | break; | |
1772 | default: | |
1773 | return err_sym >> 3; | |
1774 | break; | |
1775 | } | |
1776 | return -1; | |
1777 | } | |
1778 | ||
1779 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome) | |
1780 | { | |
1781 | struct amd64_pvt *pvt = mci->pvt_info; | |
ad6a32e9 BP |
1782 | int err_sym = -1; |
1783 | ||
a3b7db09 | 1784 | if (pvt->ecc_sym_sz == 8) |
ad6a32e9 BP |
1785 | err_sym = decode_syndrome(syndrome, x8_vectors, |
1786 | ARRAY_SIZE(x8_vectors), | |
a3b7db09 BP |
1787 | pvt->ecc_sym_sz); |
1788 | else if (pvt->ecc_sym_sz == 4) | |
ad6a32e9 BP |
1789 | err_sym = decode_syndrome(syndrome, x4_vectors, |
1790 | ARRAY_SIZE(x4_vectors), | |
a3b7db09 | 1791 | pvt->ecc_sym_sz); |
ad6a32e9 | 1792 | else { |
a3b7db09 | 1793 | amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); |
ad6a32e9 | 1794 | return err_sym; |
bfc04aec | 1795 | } |
ad6a32e9 | 1796 | |
a3b7db09 | 1797 | return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); |
bfc04aec BP |
1798 | } |
1799 | ||
d27bf6fa DT |
1800 | /* |
1801 | * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR | |
1802 | * ADDRESS and process. | |
1803 | */ | |
f192c7b1 | 1804 | static void amd64_handle_ce(struct mem_ctl_info *mci, struct mce *m) |
d27bf6fa DT |
1805 | { |
1806 | struct amd64_pvt *pvt = mci->pvt_info; | |
44e9e2ee | 1807 | u64 sys_addr; |
f192c7b1 | 1808 | u16 syndrome; |
d27bf6fa DT |
1809 | |
1810 | /* Ensure that the Error Address is VALID */ | |
f192c7b1 | 1811 | if (!(m->status & MCI_STATUS_ADDRV)) { |
24f9a7fe | 1812 | amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n"); |
d27bf6fa DT |
1813 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); |
1814 | return; | |
1815 | } | |
1816 | ||
70046624 | 1817 | sys_addr = get_error_address(m); |
f192c7b1 | 1818 | syndrome = extract_syndrome(m->status); |
d27bf6fa | 1819 | |
24f9a7fe | 1820 | amd64_mc_err(mci, "CE ERROR_ADDRESS= 0x%llx\n", sys_addr); |
d27bf6fa | 1821 | |
f192c7b1 | 1822 | pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, syndrome); |
d27bf6fa DT |
1823 | } |
1824 | ||
1825 | /* Handle any Un-correctable Errors (UEs) */ | |
f192c7b1 | 1826 | static void amd64_handle_ue(struct mem_ctl_info *mci, struct mce *m) |
d27bf6fa | 1827 | { |
1f6bcee7 | 1828 | struct mem_ctl_info *log_mci, *src_mci = NULL; |
d27bf6fa | 1829 | int csrow; |
44e9e2ee | 1830 | u64 sys_addr; |
d27bf6fa | 1831 | u32 page, offset; |
d27bf6fa DT |
1832 | |
1833 | log_mci = mci; | |
1834 | ||
f192c7b1 | 1835 | if (!(m->status & MCI_STATUS_ADDRV)) { |
24f9a7fe | 1836 | amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n"); |
d27bf6fa DT |
1837 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); |
1838 | return; | |
1839 | } | |
1840 | ||
70046624 | 1841 | sys_addr = get_error_address(m); |
d27bf6fa DT |
1842 | |
1843 | /* | |
1844 | * Find out which node the error address belongs to. This may be | |
1845 | * different from the node that detected the error. | |
1846 | */ | |
44e9e2ee | 1847 | src_mci = find_mc_by_sys_addr(mci, sys_addr); |
d27bf6fa | 1848 | if (!src_mci) { |
24f9a7fe BP |
1849 | amd64_mc_err(mci, "ERROR ADDRESS (0x%lx) NOT mapped to a MC\n", |
1850 | (unsigned long)sys_addr); | |
d27bf6fa DT |
1851 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); |
1852 | return; | |
1853 | } | |
1854 | ||
1855 | log_mci = src_mci; | |
1856 | ||
44e9e2ee | 1857 | csrow = sys_addr_to_csrow(log_mci, sys_addr); |
d27bf6fa | 1858 | if (csrow < 0) { |
24f9a7fe BP |
1859 | amd64_mc_err(mci, "ERROR_ADDRESS (0x%lx) NOT mapped to CS\n", |
1860 | (unsigned long)sys_addr); | |
d27bf6fa DT |
1861 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); |
1862 | } else { | |
44e9e2ee | 1863 | error_address_to_page_and_offset(sys_addr, &page, &offset); |
d27bf6fa DT |
1864 | edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR); |
1865 | } | |
1866 | } | |
1867 | ||
549d042d | 1868 | static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, |
f192c7b1 | 1869 | struct mce *m) |
d27bf6fa | 1870 | { |
f192c7b1 BP |
1871 | u16 ec = EC(m->status); |
1872 | u8 xec = XEC(m->status, 0x1f); | |
1873 | u8 ecc_type = (m->status >> 45) & 0x3; | |
d27bf6fa | 1874 | |
b70ef010 | 1875 | /* Bail early out if this was an 'observed' error */ |
5980bb9c | 1876 | if (PP(ec) == NBSL_PP_OBS) |
b70ef010 | 1877 | return; |
d27bf6fa | 1878 | |
ecaf5606 BP |
1879 | /* Do only ECC errors */ |
1880 | if (xec && xec != F10_NBSL_EXT_ERR_ECC) | |
d27bf6fa | 1881 | return; |
d27bf6fa | 1882 | |
ecaf5606 | 1883 | if (ecc_type == 2) |
f192c7b1 | 1884 | amd64_handle_ce(mci, m); |
ecaf5606 | 1885 | else if (ecc_type == 1) |
f192c7b1 | 1886 | amd64_handle_ue(mci, m); |
d27bf6fa DT |
1887 | } |
1888 | ||
7cfd4a87 | 1889 | void amd64_decode_bus_error(int node_id, struct mce *m, u32 nbcfg) |
d27bf6fa | 1890 | { |
cc4d8860 | 1891 | struct mem_ctl_info *mci = mcis[node_id]; |
7cfd4a87 | 1892 | |
f192c7b1 | 1893 | __amd64_decode_bus_error(mci, m); |
d27bf6fa | 1894 | } |
d27bf6fa | 1895 | |
0ec449ee | 1896 | /* |
8d5b5d9c | 1897 | * Use pvt->F2 which contains the F2 CPU PCI device to get the related |
bbd0c1f6 | 1898 | * F1 (AddrMap) and F3 (Misc) devices. Return negative value on error. |
0ec449ee | 1899 | */ |
360b7f3c | 1900 | static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id) |
0ec449ee | 1901 | { |
0ec449ee | 1902 | /* Reserve the ADDRESS MAP Device */ |
8d5b5d9c BP |
1903 | pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2); |
1904 | if (!pvt->F1) { | |
24f9a7fe BP |
1905 | amd64_err("error address map device not found: " |
1906 | "vendor %x device 0x%x (broken BIOS?)\n", | |
1907 | PCI_VENDOR_ID_AMD, f1_id); | |
bbd0c1f6 | 1908 | return -ENODEV; |
0ec449ee DT |
1909 | } |
1910 | ||
1911 | /* Reserve the MISC Device */ | |
8d5b5d9c BP |
1912 | pvt->F3 = pci_get_related_function(pvt->F2->vendor, f3_id, pvt->F2); |
1913 | if (!pvt->F3) { | |
1914 | pci_dev_put(pvt->F1); | |
1915 | pvt->F1 = NULL; | |
0ec449ee | 1916 | |
24f9a7fe BP |
1917 | amd64_err("error F3 device not found: " |
1918 | "vendor %x device 0x%x (broken BIOS?)\n", | |
1919 | PCI_VENDOR_ID_AMD, f3_id); | |
0ec449ee | 1920 | |
bbd0c1f6 | 1921 | return -ENODEV; |
0ec449ee | 1922 | } |
8d5b5d9c BP |
1923 | debugf1("F1: %s\n", pci_name(pvt->F1)); |
1924 | debugf1("F2: %s\n", pci_name(pvt->F2)); | |
1925 | debugf1("F3: %s\n", pci_name(pvt->F3)); | |
0ec449ee DT |
1926 | |
1927 | return 0; | |
1928 | } | |
1929 | ||
360b7f3c | 1930 | static void free_mc_sibling_devs(struct amd64_pvt *pvt) |
0ec449ee | 1931 | { |
8d5b5d9c BP |
1932 | pci_dev_put(pvt->F1); |
1933 | pci_dev_put(pvt->F3); | |
0ec449ee DT |
1934 | } |
1935 | ||
1936 | /* | |
1937 | * Retrieve the hardware registers of the memory controller (this includes the | |
1938 | * 'Address Map' and 'Misc' device regs) | |
1939 | */ | |
360b7f3c | 1940 | static void read_mc_regs(struct amd64_pvt *pvt) |
0ec449ee | 1941 | { |
a3b7db09 | 1942 | struct cpuinfo_x86 *c = &boot_cpu_data; |
0ec449ee | 1943 | u64 msr_val; |
ad6a32e9 | 1944 | u32 tmp; |
7f19bf75 | 1945 | int range; |
0ec449ee DT |
1946 | |
1947 | /* | |
1948 | * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since | |
1949 | * those are Read-As-Zero | |
1950 | */ | |
e97f8bb8 BP |
1951 | rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); |
1952 | debugf0(" TOP_MEM: 0x%016llx\n", pvt->top_mem); | |
0ec449ee DT |
1953 | |
1954 | /* check first whether TOP_MEM2 is enabled */ | |
1955 | rdmsrl(MSR_K8_SYSCFG, msr_val); | |
1956 | if (msr_val & (1U << 21)) { | |
e97f8bb8 BP |
1957 | rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); |
1958 | debugf0(" TOP_MEM2: 0x%016llx\n", pvt->top_mem2); | |
0ec449ee DT |
1959 | } else |
1960 | debugf0(" TOP_MEM2 disabled.\n"); | |
1961 | ||
5980bb9c | 1962 | amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); |
0ec449ee | 1963 | |
5a5d2371 | 1964 | read_dram_ctl_register(pvt); |
0ec449ee | 1965 | |
7f19bf75 BP |
1966 | for (range = 0; range < DRAM_RANGES; range++) { |
1967 | u8 rw; | |
0ec449ee | 1968 | |
7f19bf75 BP |
1969 | /* read settings for this DRAM range */ |
1970 | read_dram_base_limit_regs(pvt, range); | |
1971 | ||
1972 | rw = dram_rw(pvt, range); | |
1973 | if (!rw) | |
1974 | continue; | |
1975 | ||
1976 | debugf1(" DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n", | |
1977 | range, | |
1978 | get_dram_base(pvt, range), | |
1979 | get_dram_limit(pvt, range)); | |
1980 | ||
1981 | debugf1(" IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n", | |
1982 | dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", | |
1983 | (rw & 0x1) ? "R" : "-", | |
1984 | (rw & 0x2) ? "W" : "-", | |
1985 | dram_intlv_sel(pvt, range), | |
1986 | dram_dst_node(pvt, range)); | |
0ec449ee DT |
1987 | } |
1988 | ||
b2b0c605 | 1989 | read_dct_base_mask(pvt); |
0ec449ee | 1990 | |
bc21fa57 | 1991 | amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); |
525a1b20 | 1992 | amd64_read_dct_pci_cfg(pvt, DBAM0, &pvt->dbam0); |
0ec449ee | 1993 | |
8d5b5d9c | 1994 | amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); |
0ec449ee | 1995 | |
cb328507 BP |
1996 | amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0); |
1997 | amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0); | |
0ec449ee | 1998 | |
78da121e | 1999 | if (!dct_ganging_enabled(pvt)) { |
cb328507 BP |
2000 | amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1); |
2001 | amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1); | |
0ec449ee | 2002 | } |
ad6a32e9 | 2003 | |
a3b7db09 BP |
2004 | pvt->ecc_sym_sz = 4; |
2005 | ||
2006 | if (c->x86 >= 0x10) { | |
b2b0c605 | 2007 | amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); |
525a1b20 | 2008 | amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1); |
ad6a32e9 | 2009 | |
a3b7db09 BP |
2010 | /* F10h, revD and later can do x8 ECC too */ |
2011 | if ((c->x86 > 0x10 || c->x86_model > 7) && tmp & BIT(25)) | |
2012 | pvt->ecc_sym_sz = 8; | |
2013 | } | |
b2b0c605 | 2014 | dump_misc_regs(pvt); |
0ec449ee DT |
2015 | } |
2016 | ||
2017 | /* | |
2018 | * NOTE: CPU Revision Dependent code | |
2019 | * | |
2020 | * Input: | |
11c75ead | 2021 | * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1) |
0ec449ee DT |
2022 | * k8 private pointer to --> |
2023 | * DRAM Bank Address mapping register | |
2024 | * node_id | |
2025 | * DCL register where dual_channel_active is | |
2026 | * | |
2027 | * The DBAM register consists of 4 sets of 4 bits each definitions: | |
2028 | * | |
2029 | * Bits: CSROWs | |
2030 | * 0-3 CSROWs 0 and 1 | |
2031 | * 4-7 CSROWs 2 and 3 | |
2032 | * 8-11 CSROWs 4 and 5 | |
2033 | * 12-15 CSROWs 6 and 7 | |
2034 | * | |
2035 | * Values range from: 0 to 15 | |
2036 | * The meaning of the values depends on CPU revision and dual-channel state, | |
2037 | * see relevant BKDG more info. | |
2038 | * | |
2039 | * The memory controller provides for total of only 8 CSROWs in its current | |
2040 | * architecture. Each "pair" of CSROWs normally represents just one DIMM in | |
2041 | * single channel or two (2) DIMMs in dual channel mode. | |
2042 | * | |
2043 | * The following code logic collapses the various tables for CSROW based on CPU | |
2044 | * revision. | |
2045 | * | |
2046 | * Returns: | |
2047 | * The number of PAGE_SIZE pages on the specified CSROW number it | |
2048 | * encompasses | |
2049 | * | |
2050 | */ | |
41d8bfab | 2051 | static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) |
0ec449ee | 2052 | { |
1433eb99 | 2053 | u32 cs_mode, nr_pages; |
0ec449ee DT |
2054 | |
2055 | /* | |
2056 | * The math on this doesn't look right on the surface because x/2*4 can | |
2057 | * be simplified to x*2 but this expression makes use of the fact that | |
2058 | * it is integral math where 1/2=0. This intermediate value becomes the | |
2059 | * number of bits to shift the DBAM register to extract the proper CSROW | |
2060 | * field. | |
2061 | */ | |
1433eb99 | 2062 | cs_mode = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF; |
0ec449ee | 2063 | |
41d8bfab | 2064 | nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT); |
0ec449ee DT |
2065 | |
2066 | /* | |
2067 | * If dual channel then double the memory size of single channel. | |
2068 | * Channel count is 1 or 2 | |
2069 | */ | |
2070 | nr_pages <<= (pvt->channel_count - 1); | |
2071 | ||
1433eb99 | 2072 | debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode); |
0ec449ee DT |
2073 | debugf0(" nr_pages= %u channel-count = %d\n", |
2074 | nr_pages, pvt->channel_count); | |
2075 | ||
2076 | return nr_pages; | |
2077 | } | |
2078 | ||
2079 | /* | |
2080 | * Initialize the array of csrow attribute instances, based on the values | |
2081 | * from pci config hardware registers. | |
2082 | */ | |
360b7f3c | 2083 | static int init_csrows(struct mem_ctl_info *mci) |
0ec449ee DT |
2084 | { |
2085 | struct csrow_info *csrow; | |
2299ef71 | 2086 | struct amd64_pvt *pvt = mci->pvt_info; |
11c75ead | 2087 | u64 input_addr_min, input_addr_max, sys_addr, base, mask; |
2299ef71 | 2088 | u32 val; |
6ba5dcdc | 2089 | int i, empty = 1; |
0ec449ee | 2090 | |
a97fa68e | 2091 | amd64_read_pci_cfg(pvt->F3, NBCFG, &val); |
0ec449ee | 2092 | |
2299ef71 | 2093 | pvt->nbcfg = val; |
0ec449ee | 2094 | |
2299ef71 BP |
2095 | debugf0("node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n", |
2096 | pvt->mc_node_id, val, | |
a97fa68e | 2097 | !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE)); |
0ec449ee | 2098 | |
11c75ead | 2099 | for_each_chip_select(i, 0, pvt) { |
0ec449ee DT |
2100 | csrow = &mci->csrows[i]; |
2101 | ||
11c75ead | 2102 | if (!csrow_enabled(i, 0, pvt)) { |
0ec449ee DT |
2103 | debugf1("----CSROW %d EMPTY for node %d\n", i, |
2104 | pvt->mc_node_id); | |
2105 | continue; | |
2106 | } | |
2107 | ||
2108 | debugf1("----CSROW %d VALID for MC node %d\n", | |
2109 | i, pvt->mc_node_id); | |
2110 | ||
2111 | empty = 0; | |
41d8bfab | 2112 | csrow->nr_pages = amd64_csrow_nr_pages(pvt, 0, i); |
0ec449ee DT |
2113 | find_csrow_limits(mci, i, &input_addr_min, &input_addr_max); |
2114 | sys_addr = input_addr_to_sys_addr(mci, input_addr_min); | |
2115 | csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT); | |
2116 | sys_addr = input_addr_to_sys_addr(mci, input_addr_max); | |
2117 | csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT); | |
11c75ead BP |
2118 | |
2119 | get_cs_base_and_mask(pvt, i, 0, &base, &mask); | |
2120 | csrow->page_mask = ~mask; | |
0ec449ee DT |
2121 | /* 8 bytes of resolution */ |
2122 | ||
24f9a7fe | 2123 | csrow->mtype = amd64_determine_memory_type(pvt, i); |
0ec449ee DT |
2124 | |
2125 | debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i); | |
2126 | debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n", | |
2127 | (unsigned long)input_addr_min, | |
2128 | (unsigned long)input_addr_max); | |
2129 | debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n", | |
2130 | (unsigned long)sys_addr, csrow->page_mask); | |
2131 | debugf1(" nr_pages: %u first_page: 0x%lx " | |
2132 | "last_page: 0x%lx\n", | |
2133 | (unsigned)csrow->nr_pages, | |
2134 | csrow->first_page, csrow->last_page); | |
2135 | ||
2136 | /* | |
2137 | * determine whether CHIPKILL or JUST ECC or NO ECC is operating | |
2138 | */ | |
a97fa68e | 2139 | if (pvt->nbcfg & NBCFG_ECC_ENABLE) |
0ec449ee | 2140 | csrow->edac_mode = |
a97fa68e | 2141 | (pvt->nbcfg & NBCFG_CHIPKILL) ? |
0ec449ee DT |
2142 | EDAC_S4ECD4ED : EDAC_SECDED; |
2143 | else | |
2144 | csrow->edac_mode = EDAC_NONE; | |
2145 | } | |
2146 | ||
2147 | return empty; | |
2148 | } | |
d27bf6fa | 2149 | |
f6d6ae96 | 2150 | /* get all cores on this DCT */ |
b487c33e | 2151 | static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, unsigned nid) |
f6d6ae96 BP |
2152 | { |
2153 | int cpu; | |
2154 | ||
2155 | for_each_online_cpu(cpu) | |
2156 | if (amd_get_nb_id(cpu) == nid) | |
2157 | cpumask_set_cpu(cpu, mask); | |
2158 | } | |
2159 | ||
2160 | /* check MCG_CTL on all the cpus on this node */ | |
b487c33e | 2161 | static bool amd64_nb_mce_bank_enabled_on_node(unsigned nid) |
f6d6ae96 BP |
2162 | { |
2163 | cpumask_var_t mask; | |
50542251 | 2164 | int cpu, nbe; |
f6d6ae96 BP |
2165 | bool ret = false; |
2166 | ||
2167 | if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { | |
24f9a7fe | 2168 | amd64_warn("%s: Error allocating mask\n", __func__); |
f6d6ae96 BP |
2169 | return false; |
2170 | } | |
2171 | ||
2172 | get_cpus_on_this_dct_cpumask(mask, nid); | |
2173 | ||
f6d6ae96 BP |
2174 | rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs); |
2175 | ||
2176 | for_each_cpu(cpu, mask) { | |
50542251 | 2177 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
5980bb9c | 2178 | nbe = reg->l & MSR_MCGCTL_NBE; |
f6d6ae96 BP |
2179 | |
2180 | debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", | |
50542251 | 2181 | cpu, reg->q, |
f6d6ae96 BP |
2182 | (nbe ? "enabled" : "disabled")); |
2183 | ||
2184 | if (!nbe) | |
2185 | goto out; | |
f6d6ae96 BP |
2186 | } |
2187 | ret = true; | |
2188 | ||
2189 | out: | |
f6d6ae96 BP |
2190 | free_cpumask_var(mask); |
2191 | return ret; | |
2192 | } | |
2193 | ||
2299ef71 | 2194 | static int toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on) |
f6d6ae96 BP |
2195 | { |
2196 | cpumask_var_t cmask; | |
50542251 | 2197 | int cpu; |
f6d6ae96 BP |
2198 | |
2199 | if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) { | |
24f9a7fe | 2200 | amd64_warn("%s: error allocating mask\n", __func__); |
f6d6ae96 BP |
2201 | return false; |
2202 | } | |
2203 | ||
ae7bb7c6 | 2204 | get_cpus_on_this_dct_cpumask(cmask, nid); |
f6d6ae96 | 2205 | |
f6d6ae96 BP |
2206 | rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); |
2207 | ||
2208 | for_each_cpu(cpu, cmask) { | |
2209 | ||
50542251 BP |
2210 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
2211 | ||
f6d6ae96 | 2212 | if (on) { |
5980bb9c | 2213 | if (reg->l & MSR_MCGCTL_NBE) |
ae7bb7c6 | 2214 | s->flags.nb_mce_enable = 1; |
f6d6ae96 | 2215 | |
5980bb9c | 2216 | reg->l |= MSR_MCGCTL_NBE; |
f6d6ae96 BP |
2217 | } else { |
2218 | /* | |
d95cf4de | 2219 | * Turn off NB MCE reporting only when it was off before |
f6d6ae96 | 2220 | */ |
ae7bb7c6 | 2221 | if (!s->flags.nb_mce_enable) |
5980bb9c | 2222 | reg->l &= ~MSR_MCGCTL_NBE; |
f6d6ae96 | 2223 | } |
f6d6ae96 BP |
2224 | } |
2225 | wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); | |
2226 | ||
f6d6ae96 BP |
2227 | free_cpumask_var(cmask); |
2228 | ||
2229 | return 0; | |
2230 | } | |
2231 | ||
2299ef71 BP |
2232 | static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid, |
2233 | struct pci_dev *F3) | |
f9431992 | 2234 | { |
2299ef71 | 2235 | bool ret = true; |
c9f4f26e | 2236 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
f9431992 | 2237 | |
2299ef71 BP |
2238 | if (toggle_ecc_err_reporting(s, nid, ON)) { |
2239 | amd64_warn("Error enabling ECC reporting over MCGCTL!\n"); | |
2240 | return false; | |
2241 | } | |
2242 | ||
c9f4f26e | 2243 | amd64_read_pci_cfg(F3, NBCTL, &value); |
f9431992 | 2244 | |
ae7bb7c6 BP |
2245 | s->old_nbctl = value & mask; |
2246 | s->nbctl_valid = true; | |
f9431992 DT |
2247 | |
2248 | value |= mask; | |
c9f4f26e | 2249 | amd64_write_pci_cfg(F3, NBCTL, value); |
f9431992 | 2250 | |
a97fa68e | 2251 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2252 | |
a97fa68e BP |
2253 | debugf0("1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", |
2254 | nid, value, !!(value & NBCFG_ECC_ENABLE)); | |
f9431992 | 2255 | |
a97fa68e | 2256 | if (!(value & NBCFG_ECC_ENABLE)) { |
24f9a7fe | 2257 | amd64_warn("DRAM ECC disabled on this node, enabling...\n"); |
f9431992 | 2258 | |
ae7bb7c6 | 2259 | s->flags.nb_ecc_prev = 0; |
d95cf4de | 2260 | |
f9431992 | 2261 | /* Attempt to turn on DRAM ECC Enable */ |
a97fa68e BP |
2262 | value |= NBCFG_ECC_ENABLE; |
2263 | amd64_write_pci_cfg(F3, NBCFG, value); | |
f9431992 | 2264 | |
a97fa68e | 2265 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2266 | |
a97fa68e | 2267 | if (!(value & NBCFG_ECC_ENABLE)) { |
24f9a7fe BP |
2268 | amd64_warn("Hardware rejected DRAM ECC enable," |
2269 | "check memory DIMM configuration.\n"); | |
2299ef71 | 2270 | ret = false; |
f9431992 | 2271 | } else { |
24f9a7fe | 2272 | amd64_info("Hardware accepted DRAM ECC Enable\n"); |
f9431992 | 2273 | } |
d95cf4de | 2274 | } else { |
ae7bb7c6 | 2275 | s->flags.nb_ecc_prev = 1; |
f9431992 | 2276 | } |
d95cf4de | 2277 | |
a97fa68e BP |
2278 | debugf0("2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", |
2279 | nid, value, !!(value & NBCFG_ECC_ENABLE)); | |
f9431992 | 2280 | |
2299ef71 | 2281 | return ret; |
f9431992 DT |
2282 | } |
2283 | ||
360b7f3c BP |
2284 | static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid, |
2285 | struct pci_dev *F3) | |
f9431992 | 2286 | { |
c9f4f26e BP |
2287 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
2288 | ||
f9431992 | 2289 | |
ae7bb7c6 | 2290 | if (!s->nbctl_valid) |
f9431992 DT |
2291 | return; |
2292 | ||
c9f4f26e | 2293 | amd64_read_pci_cfg(F3, NBCTL, &value); |
f9431992 | 2294 | value &= ~mask; |
ae7bb7c6 | 2295 | value |= s->old_nbctl; |
f9431992 | 2296 | |
c9f4f26e | 2297 | amd64_write_pci_cfg(F3, NBCTL, value); |
f9431992 | 2298 | |
ae7bb7c6 BP |
2299 | /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ |
2300 | if (!s->flags.nb_ecc_prev) { | |
a97fa68e BP |
2301 | amd64_read_pci_cfg(F3, NBCFG, &value); |
2302 | value &= ~NBCFG_ECC_ENABLE; | |
2303 | amd64_write_pci_cfg(F3, NBCFG, value); | |
d95cf4de BP |
2304 | } |
2305 | ||
2306 | /* restore the NB Enable MCGCTL bit */ | |
2299ef71 | 2307 | if (toggle_ecc_err_reporting(s, nid, OFF)) |
24f9a7fe | 2308 | amd64_warn("Error restoring NB MCGCTL settings!\n"); |
f9431992 DT |
2309 | } |
2310 | ||
2311 | /* | |
2299ef71 BP |
2312 | * EDAC requires that the BIOS have ECC enabled before |
2313 | * taking over the processing of ECC errors. A command line | |
2314 | * option allows to force-enable hardware ECC later in | |
2315 | * enable_ecc_error_reporting(). | |
f9431992 | 2316 | */ |
cab4d277 BP |
2317 | static const char *ecc_msg = |
2318 | "ECC disabled in the BIOS or no ECC capability, module will not load.\n" | |
2319 | " Either enable ECC checking or force module loading by setting " | |
2320 | "'ecc_enable_override'.\n" | |
2321 | " (Note that use of the override may cause unknown side effects.)\n"; | |
be3468e8 | 2322 | |
2299ef71 | 2323 | static bool ecc_enabled(struct pci_dev *F3, u8 nid) |
f9431992 DT |
2324 | { |
2325 | u32 value; | |
2299ef71 | 2326 | u8 ecc_en = 0; |
06724535 | 2327 | bool nb_mce_en = false; |
f9431992 | 2328 | |
a97fa68e | 2329 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2330 | |
a97fa68e | 2331 | ecc_en = !!(value & NBCFG_ECC_ENABLE); |
2299ef71 | 2332 | amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled")); |
f9431992 | 2333 | |
2299ef71 | 2334 | nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid); |
06724535 | 2335 | if (!nb_mce_en) |
2299ef71 BP |
2336 | amd64_notice("NB MCE bank disabled, set MSR " |
2337 | "0x%08x[4] on node %d to enable.\n", | |
2338 | MSR_IA32_MCG_CTL, nid); | |
f9431992 | 2339 | |
2299ef71 BP |
2340 | if (!ecc_en || !nb_mce_en) { |
2341 | amd64_notice("%s", ecc_msg); | |
2342 | return false; | |
2343 | } | |
2344 | return true; | |
f9431992 DT |
2345 | } |
2346 | ||
7d6034d3 DT |
2347 | struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) + |
2348 | ARRAY_SIZE(amd64_inj_attrs) + | |
2349 | 1]; | |
2350 | ||
2351 | struct mcidev_sysfs_attribute terminator = { .attr = { .name = NULL } }; | |
2352 | ||
360b7f3c | 2353 | static void set_mc_sysfs_attrs(struct mem_ctl_info *mci) |
7d6034d3 DT |
2354 | { |
2355 | unsigned int i = 0, j = 0; | |
2356 | ||
2357 | for (; i < ARRAY_SIZE(amd64_dbg_attrs); i++) | |
2358 | sysfs_attrs[i] = amd64_dbg_attrs[i]; | |
2359 | ||
a135cef7 BP |
2360 | if (boot_cpu_data.x86 >= 0x10) |
2361 | for (j = 0; j < ARRAY_SIZE(amd64_inj_attrs); j++, i++) | |
2362 | sysfs_attrs[i] = amd64_inj_attrs[j]; | |
7d6034d3 DT |
2363 | |
2364 | sysfs_attrs[i] = terminator; | |
2365 | ||
2366 | mci->mc_driver_sysfs_attributes = sysfs_attrs; | |
2367 | } | |
2368 | ||
df71a053 BP |
2369 | static void setup_mci_misc_attrs(struct mem_ctl_info *mci, |
2370 | struct amd64_family_type *fam) | |
7d6034d3 DT |
2371 | { |
2372 | struct amd64_pvt *pvt = mci->pvt_info; | |
2373 | ||
2374 | mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; | |
2375 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
7d6034d3 | 2376 | |
5980bb9c | 2377 | if (pvt->nbcap & NBCAP_SECDED) |
7d6034d3 DT |
2378 | mci->edac_ctl_cap |= EDAC_FLAG_SECDED; |
2379 | ||
5980bb9c | 2380 | if (pvt->nbcap & NBCAP_CHIPKILL) |
7d6034d3 DT |
2381 | mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; |
2382 | ||
2383 | mci->edac_cap = amd64_determine_edac_cap(pvt); | |
2384 | mci->mod_name = EDAC_MOD_STR; | |
2385 | mci->mod_ver = EDAC_AMD64_VERSION; | |
df71a053 | 2386 | mci->ctl_name = fam->ctl_name; |
8d5b5d9c | 2387 | mci->dev_name = pci_name(pvt->F2); |
7d6034d3 DT |
2388 | mci->ctl_page_to_phys = NULL; |
2389 | ||
7d6034d3 DT |
2390 | /* memory scrubber interface */ |
2391 | mci->set_sdram_scrub_rate = amd64_set_scrub_rate; | |
2392 | mci->get_sdram_scrub_rate = amd64_get_scrub_rate; | |
2393 | } | |
2394 | ||
0092b20d BP |
2395 | /* |
2396 | * returns a pointer to the family descriptor on success, NULL otherwise. | |
2397 | */ | |
2398 | static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt) | |
395ae783 | 2399 | { |
0092b20d BP |
2400 | u8 fam = boot_cpu_data.x86; |
2401 | struct amd64_family_type *fam_type = NULL; | |
2402 | ||
2403 | switch (fam) { | |
395ae783 | 2404 | case 0xf: |
0092b20d | 2405 | fam_type = &amd64_family_types[K8_CPUS]; |
b8cfa02f | 2406 | pvt->ops = &amd64_family_types[K8_CPUS].ops; |
395ae783 | 2407 | break; |
df71a053 | 2408 | |
395ae783 | 2409 | case 0x10: |
0092b20d | 2410 | fam_type = &amd64_family_types[F10_CPUS]; |
b8cfa02f | 2411 | pvt->ops = &amd64_family_types[F10_CPUS].ops; |
df71a053 BP |
2412 | break; |
2413 | ||
2414 | case 0x15: | |
2415 | fam_type = &amd64_family_types[F15_CPUS]; | |
2416 | pvt->ops = &amd64_family_types[F15_CPUS].ops; | |
395ae783 BP |
2417 | break; |
2418 | ||
2419 | default: | |
24f9a7fe | 2420 | amd64_err("Unsupported family!\n"); |
0092b20d | 2421 | return NULL; |
395ae783 | 2422 | } |
0092b20d | 2423 | |
b8cfa02f BP |
2424 | pvt->ext_model = boot_cpu_data.x86_model >> 4; |
2425 | ||
df71a053 | 2426 | amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name, |
0092b20d | 2427 | (fam == 0xf ? |
24f9a7fe BP |
2428 | (pvt->ext_model >= K8_REV_F ? "revF or later " |
2429 | : "revE or earlier ") | |
2430 | : ""), pvt->mc_node_id); | |
0092b20d | 2431 | return fam_type; |
395ae783 BP |
2432 | } |
2433 | ||
2299ef71 | 2434 | static int amd64_init_one_instance(struct pci_dev *F2) |
7d6034d3 DT |
2435 | { |
2436 | struct amd64_pvt *pvt = NULL; | |
0092b20d | 2437 | struct amd64_family_type *fam_type = NULL; |
360b7f3c | 2438 | struct mem_ctl_info *mci = NULL; |
7d6034d3 | 2439 | int err = 0, ret; |
360b7f3c | 2440 | u8 nid = get_node_id(F2); |
7d6034d3 DT |
2441 | |
2442 | ret = -ENOMEM; | |
2443 | pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); | |
2444 | if (!pvt) | |
360b7f3c | 2445 | goto err_ret; |
7d6034d3 | 2446 | |
360b7f3c | 2447 | pvt->mc_node_id = nid; |
8d5b5d9c | 2448 | pvt->F2 = F2; |
7d6034d3 | 2449 | |
395ae783 | 2450 | ret = -EINVAL; |
0092b20d BP |
2451 | fam_type = amd64_per_family_init(pvt); |
2452 | if (!fam_type) | |
395ae783 BP |
2453 | goto err_free; |
2454 | ||
7d6034d3 | 2455 | ret = -ENODEV; |
360b7f3c | 2456 | err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id); |
7d6034d3 DT |
2457 | if (err) |
2458 | goto err_free; | |
2459 | ||
360b7f3c | 2460 | read_mc_regs(pvt); |
7d6034d3 | 2461 | |
7d6034d3 DT |
2462 | /* |
2463 | * We need to determine how many memory channels there are. Then use | |
2464 | * that information for calculating the size of the dynamic instance | |
360b7f3c | 2465 | * tables in the 'mci' structure. |
7d6034d3 | 2466 | */ |
360b7f3c | 2467 | ret = -EINVAL; |
7d6034d3 DT |
2468 | pvt->channel_count = pvt->ops->early_channel_count(pvt); |
2469 | if (pvt->channel_count < 0) | |
360b7f3c | 2470 | goto err_siblings; |
7d6034d3 DT |
2471 | |
2472 | ret = -ENOMEM; | |
11c75ead | 2473 | mci = edac_mc_alloc(0, pvt->csels[0].b_cnt, pvt->channel_count, nid); |
7d6034d3 | 2474 | if (!mci) |
360b7f3c | 2475 | goto err_siblings; |
7d6034d3 DT |
2476 | |
2477 | mci->pvt_info = pvt; | |
8d5b5d9c | 2478 | mci->dev = &pvt->F2->dev; |
7d6034d3 | 2479 | |
df71a053 | 2480 | setup_mci_misc_attrs(mci, fam_type); |
360b7f3c BP |
2481 | |
2482 | if (init_csrows(mci)) | |
7d6034d3 DT |
2483 | mci->edac_cap = EDAC_FLAG_NONE; |
2484 | ||
360b7f3c | 2485 | set_mc_sysfs_attrs(mci); |
7d6034d3 DT |
2486 | |
2487 | ret = -ENODEV; | |
2488 | if (edac_mc_add_mc(mci)) { | |
2489 | debugf1("failed edac_mc_add_mc()\n"); | |
2490 | goto err_add_mc; | |
2491 | } | |
2492 | ||
549d042d BP |
2493 | /* register stuff with EDAC MCE */ |
2494 | if (report_gart_errors) | |
2495 | amd_report_gart_errors(true); | |
2496 | ||
2497 | amd_register_ecc_decoder(amd64_decode_bus_error); | |
2498 | ||
360b7f3c BP |
2499 | mcis[nid] = mci; |
2500 | ||
2501 | atomic_inc(&drv_instances); | |
2502 | ||
7d6034d3 DT |
2503 | return 0; |
2504 | ||
2505 | err_add_mc: | |
2506 | edac_mc_free(mci); | |
2507 | ||
360b7f3c BP |
2508 | err_siblings: |
2509 | free_mc_sibling_devs(pvt); | |
7d6034d3 | 2510 | |
360b7f3c BP |
2511 | err_free: |
2512 | kfree(pvt); | |
7d6034d3 | 2513 | |
360b7f3c | 2514 | err_ret: |
7d6034d3 DT |
2515 | return ret; |
2516 | } | |
2517 | ||
2299ef71 | 2518 | static int __devinit amd64_probe_one_instance(struct pci_dev *pdev, |
b8cfa02f | 2519 | const struct pci_device_id *mc_type) |
7d6034d3 | 2520 | { |
ae7bb7c6 | 2521 | u8 nid = get_node_id(pdev); |
2299ef71 | 2522 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; |
ae7bb7c6 | 2523 | struct ecc_settings *s; |
2299ef71 | 2524 | int ret = 0; |
7d6034d3 | 2525 | |
7d6034d3 | 2526 | ret = pci_enable_device(pdev); |
b8cfa02f BP |
2527 | if (ret < 0) { |
2528 | debugf0("ret=%d\n", ret); | |
2529 | return -EIO; | |
2530 | } | |
7d6034d3 | 2531 | |
ae7bb7c6 BP |
2532 | ret = -ENOMEM; |
2533 | s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL); | |
2534 | if (!s) | |
2299ef71 | 2535 | goto err_out; |
ae7bb7c6 BP |
2536 | |
2537 | ecc_stngs[nid] = s; | |
2538 | ||
2299ef71 BP |
2539 | if (!ecc_enabled(F3, nid)) { |
2540 | ret = -ENODEV; | |
2541 | ||
2542 | if (!ecc_enable_override) | |
2543 | goto err_enable; | |
2544 | ||
2545 | amd64_warn("Forcing ECC on!\n"); | |
2546 | ||
2547 | if (!enable_ecc_error_reporting(s, nid, F3)) | |
2548 | goto err_enable; | |
2549 | } | |
2550 | ||
2551 | ret = amd64_init_one_instance(pdev); | |
360b7f3c | 2552 | if (ret < 0) { |
ae7bb7c6 | 2553 | amd64_err("Error probing instance: %d\n", nid); |
360b7f3c BP |
2554 | restore_ecc_error_reporting(s, nid, F3); |
2555 | } | |
7d6034d3 DT |
2556 | |
2557 | return ret; | |
2299ef71 BP |
2558 | |
2559 | err_enable: | |
2560 | kfree(s); | |
2561 | ecc_stngs[nid] = NULL; | |
2562 | ||
2563 | err_out: | |
2564 | return ret; | |
7d6034d3 DT |
2565 | } |
2566 | ||
2567 | static void __devexit amd64_remove_one_instance(struct pci_dev *pdev) | |
2568 | { | |
2569 | struct mem_ctl_info *mci; | |
2570 | struct amd64_pvt *pvt; | |
360b7f3c BP |
2571 | u8 nid = get_node_id(pdev); |
2572 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; | |
2573 | struct ecc_settings *s = ecc_stngs[nid]; | |
7d6034d3 DT |
2574 | |
2575 | /* Remove from EDAC CORE tracking list */ | |
2576 | mci = edac_mc_del_mc(&pdev->dev); | |
2577 | if (!mci) | |
2578 | return; | |
2579 | ||
2580 | pvt = mci->pvt_info; | |
2581 | ||
360b7f3c | 2582 | restore_ecc_error_reporting(s, nid, F3); |
7d6034d3 | 2583 | |
360b7f3c | 2584 | free_mc_sibling_devs(pvt); |
7d6034d3 | 2585 | |
549d042d BP |
2586 | /* unregister from EDAC MCE */ |
2587 | amd_report_gart_errors(false); | |
2588 | amd_unregister_ecc_decoder(amd64_decode_bus_error); | |
2589 | ||
360b7f3c BP |
2590 | kfree(ecc_stngs[nid]); |
2591 | ecc_stngs[nid] = NULL; | |
ae7bb7c6 | 2592 | |
7d6034d3 | 2593 | /* Free the EDAC CORE resources */ |
8f68ed97 | 2594 | mci->pvt_info = NULL; |
360b7f3c | 2595 | mcis[nid] = NULL; |
8f68ed97 BP |
2596 | |
2597 | kfree(pvt); | |
7d6034d3 DT |
2598 | edac_mc_free(mci); |
2599 | } | |
2600 | ||
2601 | /* | |
2602 | * This table is part of the interface for loading drivers for PCI devices. The | |
2603 | * PCI core identifies what devices are on a system during boot, and then | |
2604 | * inquiry this table to see if this driver is for a given device found. | |
2605 | */ | |
2606 | static const struct pci_device_id amd64_pci_table[] __devinitdata = { | |
2607 | { | |
2608 | .vendor = PCI_VENDOR_ID_AMD, | |
2609 | .device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL, | |
2610 | .subvendor = PCI_ANY_ID, | |
2611 | .subdevice = PCI_ANY_ID, | |
2612 | .class = 0, | |
2613 | .class_mask = 0, | |
7d6034d3 DT |
2614 | }, |
2615 | { | |
2616 | .vendor = PCI_VENDOR_ID_AMD, | |
2617 | .device = PCI_DEVICE_ID_AMD_10H_NB_DRAM, | |
2618 | .subvendor = PCI_ANY_ID, | |
2619 | .subdevice = PCI_ANY_ID, | |
2620 | .class = 0, | |
2621 | .class_mask = 0, | |
7d6034d3 | 2622 | }, |
df71a053 BP |
2623 | { |
2624 | .vendor = PCI_VENDOR_ID_AMD, | |
2625 | .device = PCI_DEVICE_ID_AMD_15H_NB_F2, | |
2626 | .subvendor = PCI_ANY_ID, | |
2627 | .subdevice = PCI_ANY_ID, | |
2628 | .class = 0, | |
2629 | .class_mask = 0, | |
2630 | }, | |
2631 | ||
7d6034d3 DT |
2632 | {0, } |
2633 | }; | |
2634 | MODULE_DEVICE_TABLE(pci, amd64_pci_table); | |
2635 | ||
2636 | static struct pci_driver amd64_pci_driver = { | |
2637 | .name = EDAC_MOD_STR, | |
2299ef71 | 2638 | .probe = amd64_probe_one_instance, |
7d6034d3 DT |
2639 | .remove = __devexit_p(amd64_remove_one_instance), |
2640 | .id_table = amd64_pci_table, | |
2641 | }; | |
2642 | ||
360b7f3c | 2643 | static void setup_pci_device(void) |
7d6034d3 DT |
2644 | { |
2645 | struct mem_ctl_info *mci; | |
2646 | struct amd64_pvt *pvt; | |
2647 | ||
2648 | if (amd64_ctl_pci) | |
2649 | return; | |
2650 | ||
cc4d8860 | 2651 | mci = mcis[0]; |
7d6034d3 DT |
2652 | if (mci) { |
2653 | ||
2654 | pvt = mci->pvt_info; | |
2655 | amd64_ctl_pci = | |
8d5b5d9c | 2656 | edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR); |
7d6034d3 DT |
2657 | |
2658 | if (!amd64_ctl_pci) { | |
2659 | pr_warning("%s(): Unable to create PCI control\n", | |
2660 | __func__); | |
2661 | ||
2662 | pr_warning("%s(): PCI error report via EDAC not set\n", | |
2663 | __func__); | |
2664 | } | |
2665 | } | |
2666 | } | |
2667 | ||
2668 | static int __init amd64_edac_init(void) | |
2669 | { | |
360b7f3c | 2670 | int err = -ENODEV; |
7d6034d3 | 2671 | |
df71a053 | 2672 | printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION); |
7d6034d3 DT |
2673 | |
2674 | opstate_init(); | |
2675 | ||
9653a5c7 | 2676 | if (amd_cache_northbridges() < 0) |
56b34b91 | 2677 | goto err_ret; |
7d6034d3 | 2678 | |
cc4d8860 | 2679 | err = -ENOMEM; |
ae7bb7c6 BP |
2680 | mcis = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL); |
2681 | ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL); | |
360b7f3c | 2682 | if (!(mcis && ecc_stngs)) |
cc4d8860 BP |
2683 | goto err_ret; |
2684 | ||
50542251 | 2685 | msrs = msrs_alloc(); |
56b34b91 | 2686 | if (!msrs) |
360b7f3c | 2687 | goto err_free; |
50542251 | 2688 | |
7d6034d3 DT |
2689 | err = pci_register_driver(&amd64_pci_driver); |
2690 | if (err) | |
56b34b91 | 2691 | goto err_pci; |
7d6034d3 | 2692 | |
56b34b91 | 2693 | err = -ENODEV; |
360b7f3c BP |
2694 | if (!atomic_read(&drv_instances)) |
2695 | goto err_no_instances; | |
7d6034d3 | 2696 | |
360b7f3c BP |
2697 | setup_pci_device(); |
2698 | return 0; | |
7d6034d3 | 2699 | |
360b7f3c | 2700 | err_no_instances: |
7d6034d3 | 2701 | pci_unregister_driver(&amd64_pci_driver); |
cc4d8860 | 2702 | |
56b34b91 BP |
2703 | err_pci: |
2704 | msrs_free(msrs); | |
2705 | msrs = NULL; | |
cc4d8860 | 2706 | |
360b7f3c BP |
2707 | err_free: |
2708 | kfree(mcis); | |
2709 | mcis = NULL; | |
2710 | ||
2711 | kfree(ecc_stngs); | |
2712 | ecc_stngs = NULL; | |
2713 | ||
56b34b91 | 2714 | err_ret: |
7d6034d3 DT |
2715 | return err; |
2716 | } | |
2717 | ||
2718 | static void __exit amd64_edac_exit(void) | |
2719 | { | |
2720 | if (amd64_ctl_pci) | |
2721 | edac_pci_release_generic_ctl(amd64_ctl_pci); | |
2722 | ||
2723 | pci_unregister_driver(&amd64_pci_driver); | |
50542251 | 2724 | |
ae7bb7c6 BP |
2725 | kfree(ecc_stngs); |
2726 | ecc_stngs = NULL; | |
2727 | ||
cc4d8860 BP |
2728 | kfree(mcis); |
2729 | mcis = NULL; | |
2730 | ||
50542251 BP |
2731 | msrs_free(msrs); |
2732 | msrs = NULL; | |
7d6034d3 DT |
2733 | } |
2734 | ||
2735 | module_init(amd64_edac_init); | |
2736 | module_exit(amd64_edac_exit); | |
2737 | ||
2738 | MODULE_LICENSE("GPL"); | |
2739 | MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, " | |
2740 | "Dave Peterson, Thayne Harbaugh"); | |
2741 | MODULE_DESCRIPTION("MC support for AMD64 memory controllers - " | |
2742 | EDAC_AMD64_VERSION); | |
2743 | ||
2744 | module_param(edac_op_state, int, 0444); | |
2745 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |