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Commit | Line | Data |
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2bc65418 | 1 | #include "amd64_edac.h" |
7d6034d3 | 2 | #include <asm/k8.h> |
2bc65418 DT |
3 | |
4 | static struct edac_pci_ctl_info *amd64_ctl_pci; | |
5 | ||
6 | static int report_gart_errors; | |
7 | module_param(report_gart_errors, int, 0644); | |
8 | ||
9 | /* | |
10 | * Set by command line parameter. If BIOS has enabled the ECC, this override is | |
11 | * cleared to prevent re-enabling the hardware by this driver. | |
12 | */ | |
13 | static int ecc_enable_override; | |
14 | module_param(ecc_enable_override, int, 0644); | |
15 | ||
16 | /* Lookup table for all possible MC control instances */ | |
17 | struct amd64_pvt; | |
3011b20d BP |
18 | static struct mem_ctl_info *mci_lookup[EDAC_MAX_NUMNODES]; |
19 | static struct amd64_pvt *pvt_lookup[EDAC_MAX_NUMNODES]; | |
2bc65418 | 20 | |
b70ef010 | 21 | /* |
1433eb99 BP |
22 | * Address to DRAM bank mapping: see F2x80 for K8 and F2x[1,0]80 for Fam10 and |
23 | * later. | |
b70ef010 | 24 | */ |
1433eb99 BP |
25 | static int ddr2_dbam_revCG[] = { |
26 | [0] = 32, | |
27 | [1] = 64, | |
28 | [2] = 128, | |
29 | [3] = 256, | |
30 | [4] = 512, | |
31 | [5] = 1024, | |
32 | [6] = 2048, | |
33 | }; | |
34 | ||
35 | static int ddr2_dbam_revD[] = { | |
36 | [0] = 32, | |
37 | [1] = 64, | |
38 | [2 ... 3] = 128, | |
39 | [4] = 256, | |
40 | [5] = 512, | |
41 | [6] = 256, | |
42 | [7] = 512, | |
43 | [8 ... 9] = 1024, | |
44 | [10] = 2048, | |
45 | }; | |
46 | ||
47 | static int ddr2_dbam[] = { [0] = 128, | |
48 | [1] = 256, | |
49 | [2 ... 4] = 512, | |
50 | [5 ... 6] = 1024, | |
51 | [7 ... 8] = 2048, | |
52 | [9 ... 10] = 4096, | |
53 | [11] = 8192, | |
54 | }; | |
55 | ||
56 | static int ddr3_dbam[] = { [0] = -1, | |
57 | [1] = 256, | |
58 | [2] = 512, | |
59 | [3 ... 4] = -1, | |
60 | [5 ... 6] = 1024, | |
61 | [7 ... 8] = 2048, | |
62 | [9 ... 10] = 4096, | |
63 | [11] = 8192, | |
b70ef010 BP |
64 | }; |
65 | ||
66 | /* | |
67 | * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing | |
68 | * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching- | |
69 | * or higher value'. | |
70 | * | |
71 | *FIXME: Produce a better mapping/linearisation. | |
72 | */ | |
73 | ||
74 | struct scrubrate scrubrates[] = { | |
75 | { 0x01, 1600000000UL}, | |
76 | { 0x02, 800000000UL}, | |
77 | { 0x03, 400000000UL}, | |
78 | { 0x04, 200000000UL}, | |
79 | { 0x05, 100000000UL}, | |
80 | { 0x06, 50000000UL}, | |
81 | { 0x07, 25000000UL}, | |
82 | { 0x08, 12284069UL}, | |
83 | { 0x09, 6274509UL}, | |
84 | { 0x0A, 3121951UL}, | |
85 | { 0x0B, 1560975UL}, | |
86 | { 0x0C, 781440UL}, | |
87 | { 0x0D, 390720UL}, | |
88 | { 0x0E, 195300UL}, | |
89 | { 0x0F, 97650UL}, | |
90 | { 0x10, 48854UL}, | |
91 | { 0x11, 24427UL}, | |
92 | { 0x12, 12213UL}, | |
93 | { 0x13, 6101UL}, | |
94 | { 0x14, 3051UL}, | |
95 | { 0x15, 1523UL}, | |
96 | { 0x16, 761UL}, | |
97 | { 0x00, 0UL}, /* scrubbing off */ | |
98 | }; | |
99 | ||
2bc65418 DT |
100 | /* |
101 | * Memory scrubber control interface. For K8, memory scrubbing is handled by | |
102 | * hardware and can involve L2 cache, dcache as well as the main memory. With | |
103 | * F10, this is extended to L3 cache scrubbing on CPU models sporting that | |
104 | * functionality. | |
105 | * | |
106 | * This causes the "units" for the scrubbing speed to vary from 64 byte blocks | |
107 | * (dram) over to cache lines. This is nasty, so we will use bandwidth in | |
108 | * bytes/sec for the setting. | |
109 | * | |
110 | * Currently, we only do dram scrubbing. If the scrubbing is done in software on | |
111 | * other archs, we might not have access to the caches directly. | |
112 | */ | |
113 | ||
114 | /* | |
115 | * scan the scrub rate mapping table for a close or matching bandwidth value to | |
116 | * issue. If requested is too big, then use last maximum value found. | |
117 | */ | |
118 | static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, | |
119 | u32 min_scrubrate) | |
120 | { | |
121 | u32 scrubval; | |
122 | int i; | |
123 | ||
124 | /* | |
125 | * map the configured rate (new_bw) to a value specific to the AMD64 | |
126 | * memory controller and apply to register. Search for the first | |
127 | * bandwidth entry that is greater or equal than the setting requested | |
128 | * and program that. If at last entry, turn off DRAM scrubbing. | |
129 | */ | |
130 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { | |
131 | /* | |
132 | * skip scrub rates which aren't recommended | |
133 | * (see F10 BKDG, F3x58) | |
134 | */ | |
135 | if (scrubrates[i].scrubval < min_scrubrate) | |
136 | continue; | |
137 | ||
138 | if (scrubrates[i].bandwidth <= new_bw) | |
139 | break; | |
140 | ||
141 | /* | |
142 | * if no suitable bandwidth found, turn off DRAM scrubbing | |
143 | * entirely by falling back to the last element in the | |
144 | * scrubrates array. | |
145 | */ | |
146 | } | |
147 | ||
148 | scrubval = scrubrates[i].scrubval; | |
149 | if (scrubval) | |
150 | edac_printk(KERN_DEBUG, EDAC_MC, | |
151 | "Setting scrub rate bandwidth: %u\n", | |
152 | scrubrates[i].bandwidth); | |
153 | else | |
154 | edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n"); | |
155 | ||
156 | pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F); | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 *bandwidth) | |
162 | { | |
163 | struct amd64_pvt *pvt = mci->pvt_info; | |
164 | u32 min_scrubrate = 0x0; | |
165 | ||
166 | switch (boot_cpu_data.x86) { | |
167 | case 0xf: | |
168 | min_scrubrate = K8_MIN_SCRUB_RATE_BITS; | |
169 | break; | |
170 | case 0x10: | |
171 | min_scrubrate = F10_MIN_SCRUB_RATE_BITS; | |
172 | break; | |
173 | case 0x11: | |
174 | min_scrubrate = F11_MIN_SCRUB_RATE_BITS; | |
175 | break; | |
176 | ||
177 | default: | |
178 | amd64_printk(KERN_ERR, "Unsupported family!\n"); | |
179 | break; | |
180 | } | |
181 | return amd64_search_set_scrub_rate(pvt->misc_f3_ctl, *bandwidth, | |
182 | min_scrubrate); | |
183 | } | |
184 | ||
185 | static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw) | |
186 | { | |
187 | struct amd64_pvt *pvt = mci->pvt_info; | |
188 | u32 scrubval = 0; | |
6ba5dcdc | 189 | int status = -1, i; |
2bc65418 | 190 | |
6ba5dcdc | 191 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval); |
2bc65418 DT |
192 | |
193 | scrubval = scrubval & 0x001F; | |
194 | ||
195 | edac_printk(KERN_DEBUG, EDAC_MC, | |
196 | "pci-read, sdram scrub control value: %d \n", scrubval); | |
197 | ||
198 | for (i = 0; ARRAY_SIZE(scrubrates); i++) { | |
199 | if (scrubrates[i].scrubval == scrubval) { | |
200 | *bw = scrubrates[i].bandwidth; | |
201 | status = 0; | |
202 | break; | |
203 | } | |
204 | } | |
205 | ||
206 | return status; | |
207 | } | |
208 | ||
6775763a DT |
209 | /* Map from a CSROW entry to the mask entry that operates on it */ |
210 | static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow) | |
211 | { | |
1433eb99 | 212 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) |
9d858bb1 BP |
213 | return csrow; |
214 | else | |
215 | return csrow >> 1; | |
6775763a DT |
216 | } |
217 | ||
218 | /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */ | |
219 | static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow) | |
220 | { | |
221 | if (dct == 0) | |
222 | return pvt->dcsb0[csrow]; | |
223 | else | |
224 | return pvt->dcsb1[csrow]; | |
225 | } | |
226 | ||
227 | /* | |
228 | * Return the 'mask' address the i'th CS entry. This function is needed because | |
229 | * there number of DCSM registers on Rev E and prior vs Rev F and later is | |
230 | * different. | |
231 | */ | |
232 | static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow) | |
233 | { | |
234 | if (dct == 0) | |
235 | return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)]; | |
236 | else | |
237 | return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)]; | |
238 | } | |
239 | ||
240 | ||
241 | /* | |
242 | * In *base and *limit, pass back the full 40-bit base and limit physical | |
243 | * addresses for the node given by node_id. This information is obtained from | |
244 | * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The | |
245 | * base and limit addresses are of type SysAddr, as defined at the start of | |
246 | * section 3.4.4 (p. 70). They are the lowest and highest physical addresses | |
247 | * in the address range they represent. | |
248 | */ | |
249 | static void amd64_get_base_and_limit(struct amd64_pvt *pvt, int node_id, | |
250 | u64 *base, u64 *limit) | |
251 | { | |
252 | *base = pvt->dram_base[node_id]; | |
253 | *limit = pvt->dram_limit[node_id]; | |
254 | } | |
255 | ||
256 | /* | |
257 | * Return 1 if the SysAddr given by sys_addr matches the base/limit associated | |
258 | * with node_id | |
259 | */ | |
260 | static int amd64_base_limit_match(struct amd64_pvt *pvt, | |
261 | u64 sys_addr, int node_id) | |
262 | { | |
263 | u64 base, limit, addr; | |
264 | ||
265 | amd64_get_base_and_limit(pvt, node_id, &base, &limit); | |
266 | ||
267 | /* The K8 treats this as a 40-bit value. However, bits 63-40 will be | |
268 | * all ones if the most significant implemented address bit is 1. | |
269 | * Here we discard bits 63-40. See section 3.4.2 of AMD publication | |
270 | * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 | |
271 | * Application Programming. | |
272 | */ | |
273 | addr = sys_addr & 0x000000ffffffffffull; | |
274 | ||
275 | return (addr >= base) && (addr <= limit); | |
276 | } | |
277 | ||
278 | /* | |
279 | * Attempt to map a SysAddr to a node. On success, return a pointer to the | |
280 | * mem_ctl_info structure for the node that the SysAddr maps to. | |
281 | * | |
282 | * On failure, return NULL. | |
283 | */ | |
284 | static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, | |
285 | u64 sys_addr) | |
286 | { | |
287 | struct amd64_pvt *pvt; | |
288 | int node_id; | |
289 | u32 intlv_en, bits; | |
290 | ||
291 | /* | |
292 | * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section | |
293 | * 3.4.4.2) registers to map the SysAddr to a node ID. | |
294 | */ | |
295 | pvt = mci->pvt_info; | |
296 | ||
297 | /* | |
298 | * The value of this field should be the same for all DRAM Base | |
299 | * registers. Therefore we arbitrarily choose to read it from the | |
300 | * register for node 0. | |
301 | */ | |
302 | intlv_en = pvt->dram_IntlvEn[0]; | |
303 | ||
304 | if (intlv_en == 0) { | |
8edc5445 | 305 | for (node_id = 0; node_id < DRAM_REG_COUNT; node_id++) { |
6775763a | 306 | if (amd64_base_limit_match(pvt, sys_addr, node_id)) |
8edc5445 | 307 | goto found; |
6775763a | 308 | } |
8edc5445 | 309 | goto err_no_match; |
6775763a DT |
310 | } |
311 | ||
72f158fe BP |
312 | if (unlikely((intlv_en != 0x01) && |
313 | (intlv_en != 0x03) && | |
314 | (intlv_en != 0x07))) { | |
6775763a DT |
315 | amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from " |
316 | "IntlvEn field of DRAM Base Register for node 0: " | |
72f158fe | 317 | "this probably indicates a BIOS bug.\n", intlv_en); |
6775763a DT |
318 | return NULL; |
319 | } | |
320 | ||
321 | bits = (((u32) sys_addr) >> 12) & intlv_en; | |
322 | ||
323 | for (node_id = 0; ; ) { | |
8edc5445 | 324 | if ((pvt->dram_IntlvSel[node_id] & intlv_en) == bits) |
6775763a DT |
325 | break; /* intlv_sel field matches */ |
326 | ||
327 | if (++node_id >= DRAM_REG_COUNT) | |
328 | goto err_no_match; | |
329 | } | |
330 | ||
331 | /* sanity test for sys_addr */ | |
332 | if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) { | |
333 | amd64_printk(KERN_WARNING, | |
8edc5445 BP |
334 | "%s(): sys_addr 0x%llx falls outside base/limit " |
335 | "address range for node %d with node interleaving " | |
336 | "enabled.\n", | |
337 | __func__, sys_addr, node_id); | |
6775763a DT |
338 | return NULL; |
339 | } | |
340 | ||
341 | found: | |
342 | return edac_mc_find(node_id); | |
343 | ||
344 | err_no_match: | |
345 | debugf2("sys_addr 0x%lx doesn't match any node\n", | |
346 | (unsigned long)sys_addr); | |
347 | ||
348 | return NULL; | |
349 | } | |
e2ce7255 DT |
350 | |
351 | /* | |
352 | * Extract the DRAM CS base address from selected csrow register. | |
353 | */ | |
354 | static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow) | |
355 | { | |
356 | return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) << | |
357 | pvt->dcs_shift; | |
358 | } | |
359 | ||
360 | /* | |
361 | * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way. | |
362 | */ | |
363 | static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow) | |
364 | { | |
365 | u64 dcsm_bits, other_bits; | |
366 | u64 mask; | |
367 | ||
368 | /* Extract bits from DRAM CS Mask. */ | |
369 | dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask; | |
370 | ||
371 | other_bits = pvt->dcsm_mask; | |
372 | other_bits = ~(other_bits << pvt->dcs_shift); | |
373 | ||
374 | /* | |
375 | * The extracted bits from DCSM belong in the spaces represented by | |
376 | * the cleared bits in other_bits. | |
377 | */ | |
378 | mask = (dcsm_bits << pvt->dcs_shift) | other_bits; | |
379 | ||
380 | return mask; | |
381 | } | |
382 | ||
383 | /* | |
384 | * @input_addr is an InputAddr associated with the node given by mci. Return the | |
385 | * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). | |
386 | */ | |
387 | static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) | |
388 | { | |
389 | struct amd64_pvt *pvt; | |
390 | int csrow; | |
391 | u64 base, mask; | |
392 | ||
393 | pvt = mci->pvt_info; | |
394 | ||
395 | /* | |
396 | * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS | |
397 | * base/mask register pair, test the condition shown near the start of | |
398 | * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E). | |
399 | */ | |
9d858bb1 | 400 | for (csrow = 0; csrow < pvt->cs_count; csrow++) { |
e2ce7255 DT |
401 | |
402 | /* This DRAM chip select is disabled on this node */ | |
403 | if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0) | |
404 | continue; | |
405 | ||
406 | base = base_from_dct_base(pvt, csrow); | |
407 | mask = ~mask_from_dct_mask(pvt, csrow); | |
408 | ||
409 | if ((input_addr & mask) == (base & mask)) { | |
410 | debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n", | |
411 | (unsigned long)input_addr, csrow, | |
412 | pvt->mc_node_id); | |
413 | ||
414 | return csrow; | |
415 | } | |
416 | } | |
417 | ||
418 | debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n", | |
419 | (unsigned long)input_addr, pvt->mc_node_id); | |
420 | ||
421 | return -1; | |
422 | } | |
423 | ||
424 | /* | |
425 | * Return the base value defined by the DRAM Base register for the node | |
426 | * represented by mci. This function returns the full 40-bit value despite the | |
427 | * fact that the register only stores bits 39-24 of the value. See section | |
428 | * 3.4.4.1 (BKDG #26094, K8, revA-E) | |
429 | */ | |
430 | static inline u64 get_dram_base(struct mem_ctl_info *mci) | |
431 | { | |
432 | struct amd64_pvt *pvt = mci->pvt_info; | |
433 | ||
434 | return pvt->dram_base[pvt->mc_node_id]; | |
435 | } | |
436 | ||
437 | /* | |
438 | * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) | |
439 | * for the node represented by mci. Info is passed back in *hole_base, | |
440 | * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if | |
441 | * info is invalid. Info may be invalid for either of the following reasons: | |
442 | * | |
443 | * - The revision of the node is not E or greater. In this case, the DRAM Hole | |
444 | * Address Register does not exist. | |
445 | * | |
446 | * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, | |
447 | * indicating that its contents are not valid. | |
448 | * | |
449 | * The values passed back in *hole_base, *hole_offset, and *hole_size are | |
450 | * complete 32-bit values despite the fact that the bitfields in the DHAR | |
451 | * only represent bits 31-24 of the base and offset values. | |
452 | */ | |
453 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, | |
454 | u64 *hole_offset, u64 *hole_size) | |
455 | { | |
456 | struct amd64_pvt *pvt = mci->pvt_info; | |
457 | u64 base; | |
458 | ||
459 | /* only revE and later have the DRAM Hole Address Register */ | |
1433eb99 | 460 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) { |
e2ce7255 DT |
461 | debugf1(" revision %d for node %d does not support DHAR\n", |
462 | pvt->ext_model, pvt->mc_node_id); | |
463 | return 1; | |
464 | } | |
465 | ||
466 | /* only valid for Fam10h */ | |
467 | if (boot_cpu_data.x86 == 0x10 && | |
468 | (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) == 0) { | |
469 | debugf1(" Dram Memory Hoisting is DISABLED on this system\n"); | |
470 | return 1; | |
471 | } | |
472 | ||
473 | if ((pvt->dhar & DHAR_VALID) == 0) { | |
474 | debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n", | |
475 | pvt->mc_node_id); | |
476 | return 1; | |
477 | } | |
478 | ||
479 | /* This node has Memory Hoisting */ | |
480 | ||
481 | /* +------------------+--------------------+--------------------+----- | |
482 | * | memory | DRAM hole | relocated | | |
483 | * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | | |
484 | * | | | DRAM hole | | |
485 | * | | | [0x100000000, | | |
486 | * | | | (0x100000000+ | | |
487 | * | | | (0xffffffff-x))] | | |
488 | * +------------------+--------------------+--------------------+----- | |
489 | * | |
490 | * Above is a diagram of physical memory showing the DRAM hole and the | |
491 | * relocated addresses from the DRAM hole. As shown, the DRAM hole | |
492 | * starts at address x (the base address) and extends through address | |
493 | * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the | |
494 | * addresses in the hole so that they start at 0x100000000. | |
495 | */ | |
496 | ||
497 | base = dhar_base(pvt->dhar); | |
498 | ||
499 | *hole_base = base; | |
500 | *hole_size = (0x1ull << 32) - base; | |
501 | ||
502 | if (boot_cpu_data.x86 > 0xf) | |
503 | *hole_offset = f10_dhar_offset(pvt->dhar); | |
504 | else | |
505 | *hole_offset = k8_dhar_offset(pvt->dhar); | |
506 | ||
507 | debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", | |
508 | pvt->mc_node_id, (unsigned long)*hole_base, | |
509 | (unsigned long)*hole_offset, (unsigned long)*hole_size); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); | |
514 | ||
93c2df58 DT |
515 | /* |
516 | * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is | |
517 | * assumed that sys_addr maps to the node given by mci. | |
518 | * | |
519 | * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section | |
520 | * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a | |
521 | * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, | |
522 | * then it is also involved in translating a SysAddr to a DramAddr. Sections | |
523 | * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. | |
524 | * These parts of the documentation are unclear. I interpret them as follows: | |
525 | * | |
526 | * When node n receives a SysAddr, it processes the SysAddr as follows: | |
527 | * | |
528 | * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM | |
529 | * Limit registers for node n. If the SysAddr is not within the range | |
530 | * specified by the base and limit values, then node n ignores the Sysaddr | |
531 | * (since it does not map to node n). Otherwise continue to step 2 below. | |
532 | * | |
533 | * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is | |
534 | * disabled so skip to step 3 below. Otherwise see if the SysAddr is within | |
535 | * the range of relocated addresses (starting at 0x100000000) from the DRAM | |
536 | * hole. If not, skip to step 3 below. Else get the value of the | |
537 | * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the | |
538 | * offset defined by this value from the SysAddr. | |
539 | * | |
540 | * 3. Obtain the base address for node n from the DRAMBase field of the DRAM | |
541 | * Base register for node n. To obtain the DramAddr, subtract the base | |
542 | * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). | |
543 | */ | |
544 | static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
545 | { | |
546 | u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; | |
547 | int ret = 0; | |
548 | ||
549 | dram_base = get_dram_base(mci); | |
550 | ||
551 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
552 | &hole_size); | |
553 | if (!ret) { | |
554 | if ((sys_addr >= (1ull << 32)) && | |
555 | (sys_addr < ((1ull << 32) + hole_size))) { | |
556 | /* use DHAR to translate SysAddr to DramAddr */ | |
557 | dram_addr = sys_addr - hole_offset; | |
558 | ||
559 | debugf2("using DHAR to translate SysAddr 0x%lx to " | |
560 | "DramAddr 0x%lx\n", | |
561 | (unsigned long)sys_addr, | |
562 | (unsigned long)dram_addr); | |
563 | ||
564 | return dram_addr; | |
565 | } | |
566 | } | |
567 | ||
568 | /* | |
569 | * Translate the SysAddr to a DramAddr as shown near the start of | |
570 | * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 | |
571 | * only deals with 40-bit values. Therefore we discard bits 63-40 of | |
572 | * sys_addr below. If bit 39 of sys_addr is 1 then the bits we | |
573 | * discard are all 1s. Otherwise the bits we discard are all 0s. See | |
574 | * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture | |
575 | * Programmer's Manual Volume 1 Application Programming. | |
576 | */ | |
577 | dram_addr = (sys_addr & 0xffffffffffull) - dram_base; | |
578 | ||
579 | debugf2("using DRAM Base register to translate SysAddr 0x%lx to " | |
580 | "DramAddr 0x%lx\n", (unsigned long)sys_addr, | |
581 | (unsigned long)dram_addr); | |
582 | return dram_addr; | |
583 | } | |
584 | ||
585 | /* | |
586 | * @intlv_en is the value of the IntlvEn field from a DRAM Base register | |
587 | * (section 3.4.4.1). Return the number of bits from a SysAddr that are used | |
588 | * for node interleaving. | |
589 | */ | |
590 | static int num_node_interleave_bits(unsigned intlv_en) | |
591 | { | |
592 | static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; | |
593 | int n; | |
594 | ||
595 | BUG_ON(intlv_en > 7); | |
596 | n = intlv_shift_table[intlv_en]; | |
597 | return n; | |
598 | } | |
599 | ||
600 | /* Translate the DramAddr given by @dram_addr to an InputAddr. */ | |
601 | static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
602 | { | |
603 | struct amd64_pvt *pvt; | |
604 | int intlv_shift; | |
605 | u64 input_addr; | |
606 | ||
607 | pvt = mci->pvt_info; | |
608 | ||
609 | /* | |
610 | * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
611 | * concerning translating a DramAddr to an InputAddr. | |
612 | */ | |
613 | intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); | |
614 | input_addr = ((dram_addr >> intlv_shift) & 0xffffff000ull) + | |
615 | (dram_addr & 0xfff); | |
616 | ||
617 | debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", | |
618 | intlv_shift, (unsigned long)dram_addr, | |
619 | (unsigned long)input_addr); | |
620 | ||
621 | return input_addr; | |
622 | } | |
623 | ||
624 | /* | |
625 | * Translate the SysAddr represented by @sys_addr to an InputAddr. It is | |
626 | * assumed that @sys_addr maps to the node given by mci. | |
627 | */ | |
628 | static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
629 | { | |
630 | u64 input_addr; | |
631 | ||
632 | input_addr = | |
633 | dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); | |
634 | ||
635 | debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n", | |
636 | (unsigned long)sys_addr, (unsigned long)input_addr); | |
637 | ||
638 | return input_addr; | |
639 | } | |
640 | ||
641 | ||
642 | /* | |
643 | * @input_addr is an InputAddr associated with the node represented by mci. | |
644 | * Translate @input_addr to a DramAddr and return the result. | |
645 | */ | |
646 | static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr) | |
647 | { | |
648 | struct amd64_pvt *pvt; | |
649 | int node_id, intlv_shift; | |
650 | u64 bits, dram_addr; | |
651 | u32 intlv_sel; | |
652 | ||
653 | /* | |
654 | * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
655 | * shows how to translate a DramAddr to an InputAddr. Here we reverse | |
656 | * this procedure. When translating from a DramAddr to an InputAddr, the | |
657 | * bits used for node interleaving are discarded. Here we recover these | |
658 | * bits from the IntlvSel field of the DRAM Limit register (section | |
659 | * 3.4.4.2) for the node that input_addr is associated with. | |
660 | */ | |
661 | pvt = mci->pvt_info; | |
662 | node_id = pvt->mc_node_id; | |
663 | BUG_ON((node_id < 0) || (node_id > 7)); | |
664 | ||
665 | intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); | |
666 | ||
667 | if (intlv_shift == 0) { | |
668 | debugf1(" InputAddr 0x%lx translates to DramAddr of " | |
669 | "same value\n", (unsigned long)input_addr); | |
670 | ||
671 | return input_addr; | |
672 | } | |
673 | ||
674 | bits = ((input_addr & 0xffffff000ull) << intlv_shift) + | |
675 | (input_addr & 0xfff); | |
676 | ||
677 | intlv_sel = pvt->dram_IntlvSel[node_id] & ((1 << intlv_shift) - 1); | |
678 | dram_addr = bits + (intlv_sel << 12); | |
679 | ||
680 | debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx " | |
681 | "(%d node interleave bits)\n", (unsigned long)input_addr, | |
682 | (unsigned long)dram_addr, intlv_shift); | |
683 | ||
684 | return dram_addr; | |
685 | } | |
686 | ||
687 | /* | |
688 | * @dram_addr is a DramAddr that maps to the node represented by mci. Convert | |
689 | * @dram_addr to a SysAddr. | |
690 | */ | |
691 | static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
692 | { | |
693 | struct amd64_pvt *pvt = mci->pvt_info; | |
694 | u64 hole_base, hole_offset, hole_size, base, limit, sys_addr; | |
695 | int ret = 0; | |
696 | ||
697 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
698 | &hole_size); | |
699 | if (!ret) { | |
700 | if ((dram_addr >= hole_base) && | |
701 | (dram_addr < (hole_base + hole_size))) { | |
702 | sys_addr = dram_addr + hole_offset; | |
703 | ||
704 | debugf1("using DHAR to translate DramAddr 0x%lx to " | |
705 | "SysAddr 0x%lx\n", (unsigned long)dram_addr, | |
706 | (unsigned long)sys_addr); | |
707 | ||
708 | return sys_addr; | |
709 | } | |
710 | } | |
711 | ||
712 | amd64_get_base_and_limit(pvt, pvt->mc_node_id, &base, &limit); | |
713 | sys_addr = dram_addr + base; | |
714 | ||
715 | /* | |
716 | * The sys_addr we have computed up to this point is a 40-bit value | |
717 | * because the k8 deals with 40-bit values. However, the value we are | |
718 | * supposed to return is a full 64-bit physical address. The AMD | |
719 | * x86-64 architecture specifies that the most significant implemented | |
720 | * address bit through bit 63 of a physical address must be either all | |
721 | * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a | |
722 | * 64-bit value below. See section 3.4.2 of AMD publication 24592: | |
723 | * AMD x86-64 Architecture Programmer's Manual Volume 1 Application | |
724 | * Programming. | |
725 | */ | |
726 | sys_addr |= ~((sys_addr & (1ull << 39)) - 1); | |
727 | ||
728 | debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", | |
729 | pvt->mc_node_id, (unsigned long)dram_addr, | |
730 | (unsigned long)sys_addr); | |
731 | ||
732 | return sys_addr; | |
733 | } | |
734 | ||
735 | /* | |
736 | * @input_addr is an InputAddr associated with the node given by mci. Translate | |
737 | * @input_addr to a SysAddr. | |
738 | */ | |
739 | static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci, | |
740 | u64 input_addr) | |
741 | { | |
742 | return dram_addr_to_sys_addr(mci, | |
743 | input_addr_to_dram_addr(mci, input_addr)); | |
744 | } | |
745 | ||
746 | /* | |
747 | * Find the minimum and maximum InputAddr values that map to the given @csrow. | |
748 | * Pass back these values in *input_addr_min and *input_addr_max. | |
749 | */ | |
750 | static void find_csrow_limits(struct mem_ctl_info *mci, int csrow, | |
751 | u64 *input_addr_min, u64 *input_addr_max) | |
752 | { | |
753 | struct amd64_pvt *pvt; | |
754 | u64 base, mask; | |
755 | ||
756 | pvt = mci->pvt_info; | |
9d858bb1 | 757 | BUG_ON((csrow < 0) || (csrow >= pvt->cs_count)); |
93c2df58 DT |
758 | |
759 | base = base_from_dct_base(pvt, csrow); | |
760 | mask = mask_from_dct_mask(pvt, csrow); | |
761 | ||
762 | *input_addr_min = base & ~mask; | |
763 | *input_addr_max = base | mask | pvt->dcs_mask_notused; | |
764 | } | |
765 | ||
766 | /* | |
767 | * Extract error address from MCA NB Address Low (section 3.6.4.5) and MCA NB | |
768 | * Address High (section 3.6.4.6) register values and return the result. Address | |
769 | * is located in the info structure (nbeah and nbeal), the encoding is device | |
770 | * specific. | |
771 | */ | |
772 | static u64 extract_error_address(struct mem_ctl_info *mci, | |
ef44cc4c | 773 | struct err_regs *info) |
93c2df58 DT |
774 | { |
775 | struct amd64_pvt *pvt = mci->pvt_info; | |
776 | ||
777 | return pvt->ops->get_error_address(mci, info); | |
778 | } | |
779 | ||
780 | ||
781 | /* Map the Error address to a PAGE and PAGE OFFSET. */ | |
782 | static inline void error_address_to_page_and_offset(u64 error_address, | |
783 | u32 *page, u32 *offset) | |
784 | { | |
785 | *page = (u32) (error_address >> PAGE_SHIFT); | |
786 | *offset = ((u32) error_address) & ~PAGE_MASK; | |
787 | } | |
788 | ||
789 | /* | |
790 | * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address | |
791 | * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers | |
792 | * of a node that detected an ECC memory error. mci represents the node that | |
793 | * the error address maps to (possibly different from the node that detected | |
794 | * the error). Return the number of the csrow that sys_addr maps to, or -1 on | |
795 | * error. | |
796 | */ | |
797 | static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) | |
798 | { | |
799 | int csrow; | |
800 | ||
801 | csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); | |
802 | ||
803 | if (csrow == -1) | |
804 | amd64_mc_printk(mci, KERN_ERR, | |
805 | "Failed to translate InputAddr to csrow for " | |
806 | "address 0x%lx\n", (unsigned long)sys_addr); | |
807 | return csrow; | |
808 | } | |
e2ce7255 | 809 | |
2da11654 DT |
810 | static int get_channel_from_ecc_syndrome(unsigned short syndrome); |
811 | ||
812 | static void amd64_cpu_display_info(struct amd64_pvt *pvt) | |
813 | { | |
814 | if (boot_cpu_data.x86 == 0x11) | |
815 | edac_printk(KERN_DEBUG, EDAC_MC, "F11h CPU detected\n"); | |
816 | else if (boot_cpu_data.x86 == 0x10) | |
817 | edac_printk(KERN_DEBUG, EDAC_MC, "F10h CPU detected\n"); | |
818 | else if (boot_cpu_data.x86 == 0xf) | |
819 | edac_printk(KERN_DEBUG, EDAC_MC, "%s detected\n", | |
1433eb99 | 820 | (pvt->ext_model >= K8_REV_F) ? |
2da11654 DT |
821 | "Rev F or later" : "Rev E or earlier"); |
822 | else | |
823 | /* we'll hardly ever ever get here */ | |
824 | edac_printk(KERN_ERR, EDAC_MC, "Unknown cpu!\n"); | |
825 | } | |
826 | ||
827 | /* | |
828 | * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs | |
829 | * are ECC capable. | |
830 | */ | |
831 | static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt) | |
832 | { | |
833 | int bit; | |
584fcff4 | 834 | enum dev_type edac_cap = EDAC_FLAG_NONE; |
2da11654 | 835 | |
1433eb99 | 836 | bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F) |
2da11654 DT |
837 | ? 19 |
838 | : 17; | |
839 | ||
584fcff4 | 840 | if (pvt->dclr0 & BIT(bit)) |
2da11654 DT |
841 | edac_cap = EDAC_FLAG_SECDED; |
842 | ||
843 | return edac_cap; | |
844 | } | |
845 | ||
846 | ||
8566c4df | 847 | static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt); |
2da11654 | 848 | |
68798e17 BP |
849 | static void amd64_dump_dramcfg_low(u32 dclr, int chan) |
850 | { | |
851 | debugf1("F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr); | |
852 | ||
853 | debugf1(" DIMM type: %sbuffered; all DIMMs support ECC: %s\n", | |
854 | (dclr & BIT(16)) ? "un" : "", | |
855 | (dclr & BIT(19)) ? "yes" : "no"); | |
856 | ||
857 | debugf1(" PAR/ERR parity: %s\n", | |
858 | (dclr & BIT(8)) ? "enabled" : "disabled"); | |
859 | ||
860 | debugf1(" DCT 128bit mode width: %s\n", | |
861 | (dclr & BIT(11)) ? "128b" : "64b"); | |
862 | ||
863 | debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", | |
864 | (dclr & BIT(12)) ? "yes" : "no", | |
865 | (dclr & BIT(13)) ? "yes" : "no", | |
866 | (dclr & BIT(14)) ? "yes" : "no", | |
867 | (dclr & BIT(15)) ? "yes" : "no"); | |
868 | } | |
869 | ||
2da11654 DT |
870 | /* Display and decode various NB registers for debug purposes. */ |
871 | static void amd64_dump_misc_regs(struct amd64_pvt *pvt) | |
872 | { | |
873 | int ganged; | |
874 | ||
68798e17 BP |
875 | debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); |
876 | ||
877 | debugf1(" NB two channel DRAM capable: %s\n", | |
878 | (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "yes" : "no"); | |
2da11654 | 879 | |
68798e17 BP |
880 | debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n", |
881 | (pvt->nbcap & K8_NBCAP_SECDED) ? "yes" : "no", | |
882 | (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "yes" : "no"); | |
883 | ||
884 | amd64_dump_dramcfg_low(pvt->dclr0, 0); | |
2da11654 | 885 | |
8de1d91e | 886 | debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); |
2da11654 | 887 | |
8de1d91e BP |
888 | debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, " |
889 | "offset: 0x%08x\n", | |
890 | pvt->dhar, | |
891 | dhar_base(pvt->dhar), | |
892 | (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt->dhar) | |
893 | : f10_dhar_offset(pvt->dhar)); | |
2da11654 | 894 | |
8de1d91e BP |
895 | debugf1(" DramHoleValid: %s\n", |
896 | (pvt->dhar & DHAR_VALID) ? "yes" : "no"); | |
2da11654 | 897 | |
8de1d91e | 898 | /* everything below this point is Fam10h and above */ |
8566c4df BP |
899 | if (boot_cpu_data.x86 == 0xf) { |
900 | amd64_debug_display_dimm_sizes(0, pvt); | |
2da11654 | 901 | return; |
8566c4df | 902 | } |
2da11654 | 903 | |
8de1d91e | 904 | /* Only if NOT ganged does dclr1 have valid info */ |
68798e17 BP |
905 | if (!dct_ganging_enabled(pvt)) |
906 | amd64_dump_dramcfg_low(pvt->dclr1, 1); | |
2da11654 DT |
907 | |
908 | /* | |
909 | * Determine if ganged and then dump memory sizes for first controller, | |
910 | * and if NOT ganged dump info for 2nd controller. | |
911 | */ | |
912 | ganged = dct_ganging_enabled(pvt); | |
913 | ||
8566c4df | 914 | amd64_debug_display_dimm_sizes(0, pvt); |
2da11654 DT |
915 | |
916 | if (!ganged) | |
8566c4df | 917 | amd64_debug_display_dimm_sizes(1, pvt); |
2da11654 DT |
918 | } |
919 | ||
920 | /* Read in both of DBAM registers */ | |
921 | static void amd64_read_dbam_reg(struct amd64_pvt *pvt) | |
922 | { | |
6ba5dcdc | 923 | amd64_read_pci_cfg(pvt->dram_f2_ctl, DBAM0, &pvt->dbam0); |
2da11654 | 924 | |
6ba5dcdc BP |
925 | if (boot_cpu_data.x86 >= 0x10) |
926 | amd64_read_pci_cfg(pvt->dram_f2_ctl, DBAM1, &pvt->dbam1); | |
2da11654 DT |
927 | } |
928 | ||
94be4bff DT |
929 | /* |
930 | * NOTE: CPU Revision Dependent code: Rev E and Rev F | |
931 | * | |
932 | * Set the DCSB and DCSM mask values depending on the CPU revision value. Also | |
933 | * set the shift factor for the DCSB and DCSM values. | |
934 | * | |
935 | * ->dcs_mask_notused, RevE: | |
936 | * | |
937 | * To find the max InputAddr for the csrow, start with the base address and set | |
938 | * all bits that are "don't care" bits in the test at the start of section | |
939 | * 3.5.4 (p. 84). | |
940 | * | |
941 | * The "don't care" bits are all set bits in the mask and all bits in the gaps | |
942 | * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS | |
943 | * represents bits [24:20] and [12:0], which are all bits in the above-mentioned | |
944 | * gaps. | |
945 | * | |
946 | * ->dcs_mask_notused, RevF and later: | |
947 | * | |
948 | * To find the max InputAddr for the csrow, start with the base address and set | |
949 | * all bits that are "don't care" bits in the test at the start of NPT section | |
950 | * 4.5.4 (p. 87). | |
951 | * | |
952 | * The "don't care" bits are all set bits in the mask and all bits in the gaps | |
953 | * between bit ranges [36:27] and [21:13]. | |
954 | * | |
955 | * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0], | |
956 | * which are all bits in the above-mentioned gaps. | |
957 | */ | |
958 | static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt) | |
959 | { | |
9d858bb1 | 960 | |
1433eb99 | 961 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) { |
9d858bb1 BP |
962 | pvt->dcsb_base = REV_E_DCSB_BASE_BITS; |
963 | pvt->dcsm_mask = REV_E_DCSM_MASK_BITS; | |
964 | pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS; | |
965 | pvt->dcs_shift = REV_E_DCS_SHIFT; | |
966 | pvt->cs_count = 8; | |
967 | pvt->num_dcsm = 8; | |
968 | } else { | |
94be4bff DT |
969 | pvt->dcsb_base = REV_F_F1Xh_DCSB_BASE_BITS; |
970 | pvt->dcsm_mask = REV_F_F1Xh_DCSM_MASK_BITS; | |
971 | pvt->dcs_mask_notused = REV_F_F1Xh_DCS_NOTUSED_BITS; | |
972 | pvt->dcs_shift = REV_F_F1Xh_DCS_SHIFT; | |
973 | ||
9d858bb1 BP |
974 | if (boot_cpu_data.x86 == 0x11) { |
975 | pvt->cs_count = 4; | |
976 | pvt->num_dcsm = 2; | |
977 | } else { | |
978 | pvt->cs_count = 8; | |
979 | pvt->num_dcsm = 4; | |
94be4bff | 980 | } |
94be4bff DT |
981 | } |
982 | } | |
983 | ||
984 | /* | |
985 | * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers | |
986 | */ | |
987 | static void amd64_read_dct_base_mask(struct amd64_pvt *pvt) | |
988 | { | |
6ba5dcdc | 989 | int cs, reg; |
94be4bff DT |
990 | |
991 | amd64_set_dct_base_and_mask(pvt); | |
992 | ||
9d858bb1 | 993 | for (cs = 0; cs < pvt->cs_count; cs++) { |
94be4bff | 994 | reg = K8_DCSB0 + (cs * 4); |
6ba5dcdc | 995 | if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, &pvt->dcsb0[cs])) |
94be4bff DT |
996 | debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n", |
997 | cs, pvt->dcsb0[cs], reg); | |
998 | ||
999 | /* If DCT are NOT ganged, then read in DCT1's base */ | |
1000 | if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { | |
1001 | reg = F10_DCSB1 + (cs * 4); | |
6ba5dcdc BP |
1002 | if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, |
1003 | &pvt->dcsb1[cs])) | |
94be4bff DT |
1004 | debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n", |
1005 | cs, pvt->dcsb1[cs], reg); | |
1006 | } else { | |
1007 | pvt->dcsb1[cs] = 0; | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | for (cs = 0; cs < pvt->num_dcsm; cs++) { | |
4afcd2dc | 1012 | reg = K8_DCSM0 + (cs * 4); |
6ba5dcdc | 1013 | if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, &pvt->dcsm0[cs])) |
94be4bff DT |
1014 | debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n", |
1015 | cs, pvt->dcsm0[cs], reg); | |
1016 | ||
1017 | /* If DCT are NOT ganged, then read in DCT1's mask */ | |
1018 | if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { | |
1019 | reg = F10_DCSM1 + (cs * 4); | |
6ba5dcdc BP |
1020 | if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, |
1021 | &pvt->dcsm1[cs])) | |
94be4bff DT |
1022 | debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n", |
1023 | cs, pvt->dcsm1[cs], reg); | |
6ba5dcdc | 1024 | } else { |
94be4bff | 1025 | pvt->dcsm1[cs] = 0; |
6ba5dcdc | 1026 | } |
94be4bff DT |
1027 | } |
1028 | } | |
1029 | ||
1030 | static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt) | |
1031 | { | |
1032 | enum mem_type type; | |
1033 | ||
1433eb99 | 1034 | if (boot_cpu_data.x86 >= 0x10 || pvt->ext_model >= K8_REV_F) { |
94be4bff DT |
1035 | /* Rev F and later */ |
1036 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; | |
1037 | } else { | |
1038 | /* Rev E and earlier */ | |
1039 | type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; | |
1040 | } | |
1041 | ||
1042 | debugf1(" Memory type is: %s\n", | |
1043 | (type == MEM_DDR2) ? "MEM_DDR2" : | |
1044 | (type == MEM_RDDR2) ? "MEM_RDDR2" : | |
1045 | (type == MEM_DDR) ? "MEM_DDR" : "MEM_RDDR"); | |
1046 | ||
1047 | return type; | |
1048 | } | |
1049 | ||
ddff876d DT |
1050 | /* |
1051 | * Read the DRAM Configuration Low register. It differs between CG, D & E revs | |
1052 | * and the later RevF memory controllers (DDR vs DDR2) | |
1053 | * | |
1054 | * Return: | |
1055 | * number of memory channels in operation | |
1056 | * Pass back: | |
1057 | * contents of the DCL0_LOW register | |
1058 | */ | |
1059 | static int k8_early_channel_count(struct amd64_pvt *pvt) | |
1060 | { | |
1061 | int flag, err = 0; | |
1062 | ||
6ba5dcdc | 1063 | err = amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); |
ddff876d DT |
1064 | if (err) |
1065 | return err; | |
1066 | ||
1433eb99 | 1067 | if ((boot_cpu_data.x86_model >> 4) >= K8_REV_F) { |
ddff876d DT |
1068 | /* RevF (NPT) and later */ |
1069 | flag = pvt->dclr0 & F10_WIDTH_128; | |
1070 | } else { | |
1071 | /* RevE and earlier */ | |
1072 | flag = pvt->dclr0 & REVE_WIDTH_128; | |
1073 | } | |
1074 | ||
1075 | /* not used */ | |
1076 | pvt->dclr1 = 0; | |
1077 | ||
1078 | return (flag) ? 2 : 1; | |
1079 | } | |
1080 | ||
1081 | /* extract the ERROR ADDRESS for the K8 CPUs */ | |
1082 | static u64 k8_get_error_address(struct mem_ctl_info *mci, | |
ef44cc4c | 1083 | struct err_regs *info) |
ddff876d DT |
1084 | { |
1085 | return (((u64) (info->nbeah & 0xff)) << 32) + | |
1086 | (info->nbeal & ~0x03); | |
1087 | } | |
1088 | ||
1089 | /* | |
1090 | * Read the Base and Limit registers for K8 based Memory controllers; extract | |
1091 | * fields from the 'raw' reg into separate data fields | |
1092 | * | |
1093 | * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN | |
1094 | */ | |
1095 | static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram) | |
1096 | { | |
1097 | u32 low; | |
1098 | u32 off = dram << 3; /* 8 bytes between DRAM entries */ | |
ddff876d | 1099 | |
6ba5dcdc | 1100 | amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DRAM_BASE_LOW + off, &low); |
ddff876d DT |
1101 | |
1102 | /* Extract parts into separate data entries */ | |
4997811e | 1103 | pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8; |
ddff876d DT |
1104 | pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7; |
1105 | pvt->dram_rw_en[dram] = (low & 0x3); | |
1106 | ||
6ba5dcdc | 1107 | amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DRAM_LIMIT_LOW + off, &low); |
ddff876d DT |
1108 | |
1109 | /* | |
1110 | * Extract parts into separate data entries. Limit is the HIGHEST memory | |
1111 | * location of the region, so lower 24 bits need to be all ones | |
1112 | */ | |
4997811e | 1113 | pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF; |
ddff876d DT |
1114 | pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7; |
1115 | pvt->dram_DstNode[dram] = (low & 0x7); | |
1116 | } | |
1117 | ||
1118 | static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, | |
ef44cc4c | 1119 | struct err_regs *info, |
44e9e2ee | 1120 | u64 sys_addr) |
ddff876d DT |
1121 | { |
1122 | struct mem_ctl_info *src_mci; | |
1123 | unsigned short syndrome; | |
1124 | int channel, csrow; | |
1125 | u32 page, offset; | |
1126 | ||
1127 | /* Extract the syndrome parts and form a 16-bit syndrome */ | |
b70ef010 BP |
1128 | syndrome = HIGH_SYNDROME(info->nbsl) << 8; |
1129 | syndrome |= LOW_SYNDROME(info->nbsh); | |
ddff876d DT |
1130 | |
1131 | /* CHIPKILL enabled */ | |
1132 | if (info->nbcfg & K8_NBCFG_CHIPKILL) { | |
1133 | channel = get_channel_from_ecc_syndrome(syndrome); | |
1134 | if (channel < 0) { | |
1135 | /* | |
1136 | * Syndrome didn't map, so we don't know which of the | |
1137 | * 2 DIMMs is in error. So we need to ID 'both' of them | |
1138 | * as suspect. | |
1139 | */ | |
1140 | amd64_mc_printk(mci, KERN_WARNING, | |
1141 | "unknown syndrome 0x%x - possible error " | |
1142 | "reporting race\n", syndrome); | |
1143 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1144 | return; | |
1145 | } | |
1146 | } else { | |
1147 | /* | |
1148 | * non-chipkill ecc mode | |
1149 | * | |
1150 | * The k8 documentation is unclear about how to determine the | |
1151 | * channel number when using non-chipkill memory. This method | |
1152 | * was obtained from email communication with someone at AMD. | |
1153 | * (Wish the email was placed in this comment - norsk) | |
1154 | */ | |
44e9e2ee | 1155 | channel = ((sys_addr & BIT(3)) != 0); |
ddff876d DT |
1156 | } |
1157 | ||
1158 | /* | |
1159 | * Find out which node the error address belongs to. This may be | |
1160 | * different from the node that detected the error. | |
1161 | */ | |
44e9e2ee | 1162 | src_mci = find_mc_by_sys_addr(mci, sys_addr); |
2cff18c2 | 1163 | if (!src_mci) { |
ddff876d DT |
1164 | amd64_mc_printk(mci, KERN_ERR, |
1165 | "failed to map error address 0x%lx to a node\n", | |
44e9e2ee | 1166 | (unsigned long)sys_addr); |
ddff876d DT |
1167 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); |
1168 | return; | |
1169 | } | |
1170 | ||
44e9e2ee BP |
1171 | /* Now map the sys_addr to a CSROW */ |
1172 | csrow = sys_addr_to_csrow(src_mci, sys_addr); | |
ddff876d DT |
1173 | if (csrow < 0) { |
1174 | edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR); | |
1175 | } else { | |
44e9e2ee | 1176 | error_address_to_page_and_offset(sys_addr, &page, &offset); |
ddff876d DT |
1177 | |
1178 | edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow, | |
1179 | channel, EDAC_MOD_STR); | |
1180 | } | |
1181 | } | |
1182 | ||
1433eb99 | 1183 | static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode) |
ddff876d | 1184 | { |
1433eb99 | 1185 | int *dbam_map; |
ddff876d | 1186 | |
1433eb99 BP |
1187 | if (pvt->ext_model >= K8_REV_F) |
1188 | dbam_map = ddr2_dbam; | |
1189 | else if (pvt->ext_model >= K8_REV_D) | |
1190 | dbam_map = ddr2_dbam_revD; | |
1191 | else | |
1192 | dbam_map = ddr2_dbam_revCG; | |
ddff876d | 1193 | |
1433eb99 | 1194 | return dbam_map[cs_mode]; |
ddff876d DT |
1195 | } |
1196 | ||
1afd3c98 DT |
1197 | /* |
1198 | * Get the number of DCT channels in use. | |
1199 | * | |
1200 | * Return: | |
1201 | * number of Memory Channels in operation | |
1202 | * Pass back: | |
1203 | * contents of the DCL0_LOW register | |
1204 | */ | |
1205 | static int f10_early_channel_count(struct amd64_pvt *pvt) | |
1206 | { | |
57a30854 | 1207 | int dbams[] = { DBAM0, DBAM1 }; |
6ba5dcdc | 1208 | int i, j, channels = 0; |
1afd3c98 DT |
1209 | u32 dbam; |
1210 | ||
1afd3c98 DT |
1211 | /* If we are in 128 bit mode, then we are using 2 channels */ |
1212 | if (pvt->dclr0 & F10_WIDTH_128) { | |
1afd3c98 DT |
1213 | channels = 2; |
1214 | return channels; | |
1215 | } | |
1216 | ||
1217 | /* | |
d16149e8 BP |
1218 | * Need to check if in unganged mode: In such, there are 2 channels, |
1219 | * but they are not in 128 bit mode and thus the above 'dclr0' status | |
1220 | * bit will be OFF. | |
1afd3c98 DT |
1221 | * |
1222 | * Need to check DCT0[0] and DCT1[0] to see if only one of them has | |
1223 | * their CSEnable bit on. If so, then SINGLE DIMM case. | |
1224 | */ | |
d16149e8 | 1225 | debugf0("Data width is not 128 bits - need more decoding\n"); |
ddff876d | 1226 | |
1afd3c98 DT |
1227 | /* |
1228 | * Check DRAM Bank Address Mapping values for each DIMM to see if there | |
1229 | * is more than just one DIMM present in unganged mode. Need to check | |
1230 | * both controllers since DIMMs can be placed in either one. | |
1231 | */ | |
57a30854 | 1232 | for (i = 0; i < ARRAY_SIZE(dbams); i++) { |
6ba5dcdc | 1233 | if (amd64_read_pci_cfg(pvt->dram_f2_ctl, dbams[i], &dbam)) |
1afd3c98 DT |
1234 | goto err_reg; |
1235 | ||
57a30854 WW |
1236 | for (j = 0; j < 4; j++) { |
1237 | if (DBAM_DIMM(j, dbam) > 0) { | |
1238 | channels++; | |
1239 | break; | |
1240 | } | |
1241 | } | |
1afd3c98 DT |
1242 | } |
1243 | ||
d16149e8 BP |
1244 | if (channels > 2) |
1245 | channels = 2; | |
1246 | ||
37da0450 | 1247 | debugf0("MCT channel count: %d\n", channels); |
1afd3c98 DT |
1248 | |
1249 | return channels; | |
1250 | ||
1251 | err_reg: | |
1252 | return -1; | |
1253 | ||
1254 | } | |
1255 | ||
1433eb99 | 1256 | static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode) |
1afd3c98 | 1257 | { |
1433eb99 BP |
1258 | int *dbam_map; |
1259 | ||
1260 | if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) | |
1261 | dbam_map = ddr3_dbam; | |
1262 | else | |
1263 | dbam_map = ddr2_dbam; | |
1264 | ||
1265 | return dbam_map[cs_mode]; | |
1afd3c98 DT |
1266 | } |
1267 | ||
1268 | /* Enable extended configuration access via 0xCF8 feature */ | |
1269 | static void amd64_setup(struct amd64_pvt *pvt) | |
1270 | { | |
1271 | u32 reg; | |
1272 | ||
6ba5dcdc | 1273 | amd64_read_pci_cfg(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); |
1afd3c98 DT |
1274 | |
1275 | pvt->flags.cf8_extcfg = !!(reg & F10_NB_CFG_LOW_ENABLE_EXT_CFG); | |
1276 | reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1277 | pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); | |
1278 | } | |
1279 | ||
1280 | /* Restore the extended configuration access via 0xCF8 feature */ | |
1281 | static void amd64_teardown(struct amd64_pvt *pvt) | |
1282 | { | |
1283 | u32 reg; | |
1284 | ||
6ba5dcdc | 1285 | amd64_read_pci_cfg(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); |
1afd3c98 DT |
1286 | |
1287 | reg &= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1288 | if (pvt->flags.cf8_extcfg) | |
1289 | reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1290 | pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); | |
1291 | } | |
1292 | ||
1293 | static u64 f10_get_error_address(struct mem_ctl_info *mci, | |
ef44cc4c | 1294 | struct err_regs *info) |
1afd3c98 DT |
1295 | { |
1296 | return (((u64) (info->nbeah & 0xffff)) << 32) + | |
1297 | (info->nbeal & ~0x01); | |
1298 | } | |
1299 | ||
1300 | /* | |
1301 | * Read the Base and Limit registers for F10 based Memory controllers. Extract | |
1302 | * fields from the 'raw' reg into separate data fields. | |
1303 | * | |
1304 | * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN. | |
1305 | */ | |
1306 | static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram) | |
1307 | { | |
1308 | u32 high_offset, low_offset, high_base, low_base, high_limit, low_limit; | |
1309 | ||
1310 | low_offset = K8_DRAM_BASE_LOW + (dram << 3); | |
1311 | high_offset = F10_DRAM_BASE_HIGH + (dram << 3); | |
1312 | ||
1313 | /* read the 'raw' DRAM BASE Address register */ | |
6ba5dcdc | 1314 | amd64_read_pci_cfg(pvt->addr_f1_ctl, low_offset, &low_base); |
1afd3c98 DT |
1315 | |
1316 | /* Read from the ECS data register */ | |
6ba5dcdc | 1317 | amd64_read_pci_cfg(pvt->addr_f1_ctl, high_offset, &high_base); |
1afd3c98 DT |
1318 | |
1319 | /* Extract parts into separate data entries */ | |
1320 | pvt->dram_rw_en[dram] = (low_base & 0x3); | |
1321 | ||
1322 | if (pvt->dram_rw_en[dram] == 0) | |
1323 | return; | |
1324 | ||
1325 | pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7; | |
1326 | ||
66216a7a | 1327 | pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) | |
4997811e | 1328 | (((u64)low_base & 0xFFFF0000) << 8); |
1afd3c98 DT |
1329 | |
1330 | low_offset = K8_DRAM_LIMIT_LOW + (dram << 3); | |
1331 | high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3); | |
1332 | ||
1333 | /* read the 'raw' LIMIT registers */ | |
6ba5dcdc | 1334 | amd64_read_pci_cfg(pvt->addr_f1_ctl, low_offset, &low_limit); |
1afd3c98 DT |
1335 | |
1336 | /* Read from the ECS data register for the HIGH portion */ | |
6ba5dcdc | 1337 | amd64_read_pci_cfg(pvt->addr_f1_ctl, high_offset, &high_limit); |
1afd3c98 | 1338 | |
1afd3c98 DT |
1339 | pvt->dram_DstNode[dram] = (low_limit & 0x7); |
1340 | pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7; | |
1341 | ||
1342 | /* | |
1343 | * Extract address values and form a LIMIT address. Limit is the HIGHEST | |
1344 | * memory location of the region, so low 24 bits need to be all ones. | |
1345 | */ | |
66216a7a | 1346 | pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) | |
4997811e | 1347 | (((u64) low_limit & 0xFFFF0000) << 8) | |
66216a7a | 1348 | 0x00FFFFFF; |
1afd3c98 | 1349 | } |
6163b5d4 DT |
1350 | |
1351 | static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) | |
1352 | { | |
6163b5d4 | 1353 | |
6ba5dcdc BP |
1354 | if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW, |
1355 | &pvt->dram_ctl_select_low)) { | |
72381bd5 BP |
1356 | debugf0("F2x110 (DCTL Sel. Low): 0x%08x, " |
1357 | "High range addresses at: 0x%x\n", | |
1358 | pvt->dram_ctl_select_low, | |
1359 | dct_sel_baseaddr(pvt)); | |
1360 | ||
1361 | debugf0(" DCT mode: %s, All DCTs on: %s\n", | |
1362 | (dct_ganging_enabled(pvt) ? "ganged" : "unganged"), | |
1363 | (dct_dram_enabled(pvt) ? "yes" : "no")); | |
1364 | ||
1365 | if (!dct_ganging_enabled(pvt)) | |
1366 | debugf0(" Address range split per DCT: %s\n", | |
1367 | (dct_high_range_enabled(pvt) ? "yes" : "no")); | |
1368 | ||
1369 | debugf0(" DCT data interleave for ECC: %s, " | |
1370 | "DRAM cleared since last warm reset: %s\n", | |
1371 | (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), | |
1372 | (dct_memory_cleared(pvt) ? "yes" : "no")); | |
1373 | ||
1374 | debugf0(" DCT channel interleave: %s, " | |
1375 | "DCT interleave bits selector: 0x%x\n", | |
1376 | (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), | |
6163b5d4 DT |
1377 | dct_sel_interleave_addr(pvt)); |
1378 | } | |
1379 | ||
6ba5dcdc BP |
1380 | amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH, |
1381 | &pvt->dram_ctl_select_high); | |
6163b5d4 DT |
1382 | } |
1383 | ||
f71d0a05 DT |
1384 | /* |
1385 | * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory | |
1386 | * Interleaving Modes. | |
1387 | */ | |
6163b5d4 DT |
1388 | static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, |
1389 | int hi_range_sel, u32 intlv_en) | |
1390 | { | |
1391 | u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1; | |
1392 | ||
1393 | if (dct_ganging_enabled(pvt)) | |
1394 | cs = 0; | |
1395 | else if (hi_range_sel) | |
1396 | cs = dct_sel_high; | |
1397 | else if (dct_interleave_enabled(pvt)) { | |
f71d0a05 DT |
1398 | /* |
1399 | * see F2x110[DctSelIntLvAddr] - channel interleave mode | |
1400 | */ | |
6163b5d4 DT |
1401 | if (dct_sel_interleave_addr(pvt) == 0) |
1402 | cs = sys_addr >> 6 & 1; | |
1403 | else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) { | |
1404 | temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; | |
1405 | ||
1406 | if (dct_sel_interleave_addr(pvt) & 1) | |
1407 | cs = (sys_addr >> 9 & 1) ^ temp; | |
1408 | else | |
1409 | cs = (sys_addr >> 6 & 1) ^ temp; | |
1410 | } else if (intlv_en & 4) | |
1411 | cs = sys_addr >> 15 & 1; | |
1412 | else if (intlv_en & 2) | |
1413 | cs = sys_addr >> 14 & 1; | |
1414 | else if (intlv_en & 1) | |
1415 | cs = sys_addr >> 13 & 1; | |
1416 | else | |
1417 | cs = sys_addr >> 12 & 1; | |
1418 | } else if (dct_high_range_enabled(pvt) && !dct_ganging_enabled(pvt)) | |
1419 | cs = ~dct_sel_high & 1; | |
1420 | else | |
1421 | cs = 0; | |
1422 | ||
1423 | return cs; | |
1424 | } | |
1425 | ||
1426 | static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en) | |
1427 | { | |
1428 | if (intlv_en == 1) | |
1429 | return 1; | |
1430 | else if (intlv_en == 3) | |
1431 | return 2; | |
1432 | else if (intlv_en == 7) | |
1433 | return 3; | |
1434 | ||
1435 | return 0; | |
1436 | } | |
1437 | ||
f71d0a05 DT |
1438 | /* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */ |
1439 | static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel, | |
6163b5d4 DT |
1440 | u32 dct_sel_base_addr, |
1441 | u64 dct_sel_base_off, | |
f71d0a05 | 1442 | u32 hole_valid, u32 hole_off, |
6163b5d4 DT |
1443 | u64 dram_base) |
1444 | { | |
1445 | u64 chan_off; | |
1446 | ||
1447 | if (hi_range_sel) { | |
1448 | if (!(dct_sel_base_addr & 0xFFFFF800) && | |
f71d0a05 | 1449 | hole_valid && (sys_addr >= 0x100000000ULL)) |
6163b5d4 DT |
1450 | chan_off = hole_off << 16; |
1451 | else | |
1452 | chan_off = dct_sel_base_off; | |
1453 | } else { | |
f71d0a05 | 1454 | if (hole_valid && (sys_addr >= 0x100000000ULL)) |
6163b5d4 DT |
1455 | chan_off = hole_off << 16; |
1456 | else | |
1457 | chan_off = dram_base & 0xFFFFF8000000ULL; | |
1458 | } | |
1459 | ||
1460 | return (sys_addr & 0x0000FFFFFFFFFFC0ULL) - | |
1461 | (chan_off & 0x0000FFFFFF800000ULL); | |
1462 | } | |
1463 | ||
1464 | /* Hack for the time being - Can we get this from BIOS?? */ | |
1465 | #define CH0SPARE_RANK 0 | |
1466 | #define CH1SPARE_RANK 1 | |
1467 | ||
1468 | /* | |
1469 | * checks if the csrow passed in is marked as SPARED, if so returns the new | |
1470 | * spare row | |
1471 | */ | |
1472 | static inline int f10_process_possible_spare(int csrow, | |
1473 | u32 cs, struct amd64_pvt *pvt) | |
1474 | { | |
1475 | u32 swap_done; | |
1476 | u32 bad_dram_cs; | |
1477 | ||
1478 | /* Depending on channel, isolate respective SPARING info */ | |
1479 | if (cs) { | |
1480 | swap_done = F10_ONLINE_SPARE_SWAPDONE1(pvt->online_spare); | |
1481 | bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS1(pvt->online_spare); | |
1482 | if (swap_done && (csrow == bad_dram_cs)) | |
1483 | csrow = CH1SPARE_RANK; | |
1484 | } else { | |
1485 | swap_done = F10_ONLINE_SPARE_SWAPDONE0(pvt->online_spare); | |
1486 | bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS0(pvt->online_spare); | |
1487 | if (swap_done && (csrow == bad_dram_cs)) | |
1488 | csrow = CH0SPARE_RANK; | |
1489 | } | |
1490 | return csrow; | |
1491 | } | |
1492 | ||
1493 | /* | |
1494 | * Iterate over the DRAM DCT "base" and "mask" registers looking for a | |
1495 | * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' | |
1496 | * | |
1497 | * Return: | |
1498 | * -EINVAL: NOT FOUND | |
1499 | * 0..csrow = Chip-Select Row | |
1500 | */ | |
1501 | static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs) | |
1502 | { | |
1503 | struct mem_ctl_info *mci; | |
1504 | struct amd64_pvt *pvt; | |
1505 | u32 cs_base, cs_mask; | |
1506 | int cs_found = -EINVAL; | |
1507 | int csrow; | |
1508 | ||
1509 | mci = mci_lookup[nid]; | |
1510 | if (!mci) | |
1511 | return cs_found; | |
1512 | ||
1513 | pvt = mci->pvt_info; | |
1514 | ||
1515 | debugf1("InputAddr=0x%x channelselect=%d\n", in_addr, cs); | |
1516 | ||
9d858bb1 | 1517 | for (csrow = 0; csrow < pvt->cs_count; csrow++) { |
6163b5d4 DT |
1518 | |
1519 | cs_base = amd64_get_dct_base(pvt, cs, csrow); | |
1520 | if (!(cs_base & K8_DCSB_CS_ENABLE)) | |
1521 | continue; | |
1522 | ||
1523 | /* | |
1524 | * We have an ENABLED CSROW, Isolate just the MASK bits of the | |
1525 | * target: [28:19] and [13:5], which map to [36:27] and [21:13] | |
1526 | * of the actual address. | |
1527 | */ | |
1528 | cs_base &= REV_F_F1Xh_DCSB_BASE_BITS; | |
1529 | ||
1530 | /* | |
1531 | * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and | |
1532 | * [4:0] to become ON. Then mask off bits [28:0] ([36:8]) | |
1533 | */ | |
1534 | cs_mask = amd64_get_dct_mask(pvt, cs, csrow); | |
1535 | ||
1536 | debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n", | |
1537 | csrow, cs_base, cs_mask); | |
1538 | ||
1539 | cs_mask = (cs_mask | 0x0007C01F) & 0x1FFFFFFF; | |
1540 | ||
1541 | debugf1(" Final CSMask=0x%x\n", cs_mask); | |
1542 | debugf1(" (InputAddr & ~CSMask)=0x%x " | |
1543 | "(CSBase & ~CSMask)=0x%x\n", | |
1544 | (in_addr & ~cs_mask), (cs_base & ~cs_mask)); | |
1545 | ||
1546 | if ((in_addr & ~cs_mask) == (cs_base & ~cs_mask)) { | |
1547 | cs_found = f10_process_possible_spare(csrow, cs, pvt); | |
1548 | ||
1549 | debugf1(" MATCH csrow=%d\n", cs_found); | |
1550 | break; | |
1551 | } | |
1552 | } | |
1553 | return cs_found; | |
1554 | } | |
1555 | ||
f71d0a05 DT |
1556 | /* For a given @dram_range, check if @sys_addr falls within it. */ |
1557 | static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range, | |
1558 | u64 sys_addr, int *nid, int *chan_sel) | |
1559 | { | |
1560 | int node_id, cs_found = -EINVAL, high_range = 0; | |
1561 | u32 intlv_en, intlv_sel, intlv_shift, hole_off; | |
1562 | u32 hole_valid, tmp, dct_sel_base, channel; | |
1563 | u64 dram_base, chan_addr, dct_sel_base_off; | |
1564 | ||
1565 | dram_base = pvt->dram_base[dram_range]; | |
1566 | intlv_en = pvt->dram_IntlvEn[dram_range]; | |
1567 | ||
1568 | node_id = pvt->dram_DstNode[dram_range]; | |
1569 | intlv_sel = pvt->dram_IntlvSel[dram_range]; | |
1570 | ||
1571 | debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n", | |
1572 | dram_range, dram_base, sys_addr, pvt->dram_limit[dram_range]); | |
1573 | ||
1574 | /* | |
1575 | * This assumes that one node's DHAR is the same as all the other | |
1576 | * nodes' DHAR. | |
1577 | */ | |
1578 | hole_off = (pvt->dhar & 0x0000FF80); | |
1579 | hole_valid = (pvt->dhar & 0x1); | |
1580 | dct_sel_base_off = (pvt->dram_ctl_select_high & 0xFFFFFC00) << 16; | |
1581 | ||
1582 | debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n", | |
1583 | hole_off, hole_valid, intlv_sel); | |
1584 | ||
1585 | if (intlv_en || | |
1586 | (intlv_sel != ((sys_addr >> 12) & intlv_en))) | |
1587 | return -EINVAL; | |
1588 | ||
1589 | dct_sel_base = dct_sel_baseaddr(pvt); | |
1590 | ||
1591 | /* | |
1592 | * check whether addresses >= DctSelBaseAddr[47:27] are to be used to | |
1593 | * select between DCT0 and DCT1. | |
1594 | */ | |
1595 | if (dct_high_range_enabled(pvt) && | |
1596 | !dct_ganging_enabled(pvt) && | |
1597 | ((sys_addr >> 27) >= (dct_sel_base >> 11))) | |
1598 | high_range = 1; | |
1599 | ||
1600 | channel = f10_determine_channel(pvt, sys_addr, high_range, intlv_en); | |
1601 | ||
1602 | chan_addr = f10_get_base_addr_offset(sys_addr, high_range, dct_sel_base, | |
1603 | dct_sel_base_off, hole_valid, | |
1604 | hole_off, dram_base); | |
1605 | ||
1606 | intlv_shift = f10_map_intlv_en_to_shift(intlv_en); | |
1607 | ||
1608 | /* remove Node ID (in case of memory interleaving) */ | |
1609 | tmp = chan_addr & 0xFC0; | |
1610 | ||
1611 | chan_addr = ((chan_addr >> intlv_shift) & 0xFFFFFFFFF000ULL) | tmp; | |
1612 | ||
1613 | /* remove channel interleave and hash */ | |
1614 | if (dct_interleave_enabled(pvt) && | |
1615 | !dct_high_range_enabled(pvt) && | |
1616 | !dct_ganging_enabled(pvt)) { | |
1617 | if (dct_sel_interleave_addr(pvt) != 1) | |
1618 | chan_addr = (chan_addr >> 1) & 0xFFFFFFFFFFFFFFC0ULL; | |
1619 | else { | |
1620 | tmp = chan_addr & 0xFC0; | |
1621 | chan_addr = ((chan_addr & 0xFFFFFFFFFFFFC000ULL) >> 1) | |
1622 | | tmp; | |
1623 | } | |
1624 | } | |
1625 | ||
1626 | debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n", | |
1627 | chan_addr, (u32)(chan_addr >> 8)); | |
1628 | ||
1629 | cs_found = f10_lookup_addr_in_dct(chan_addr >> 8, node_id, channel); | |
1630 | ||
1631 | if (cs_found >= 0) { | |
1632 | *nid = node_id; | |
1633 | *chan_sel = channel; | |
1634 | } | |
1635 | return cs_found; | |
1636 | } | |
1637 | ||
1638 | static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr, | |
1639 | int *node, int *chan_sel) | |
1640 | { | |
1641 | int dram_range, cs_found = -EINVAL; | |
1642 | u64 dram_base, dram_limit; | |
1643 | ||
1644 | for (dram_range = 0; dram_range < DRAM_REG_COUNT; dram_range++) { | |
1645 | ||
1646 | if (!pvt->dram_rw_en[dram_range]) | |
1647 | continue; | |
1648 | ||
1649 | dram_base = pvt->dram_base[dram_range]; | |
1650 | dram_limit = pvt->dram_limit[dram_range]; | |
1651 | ||
1652 | if ((dram_base <= sys_addr) && (sys_addr <= dram_limit)) { | |
1653 | ||
1654 | cs_found = f10_match_to_this_node(pvt, dram_range, | |
1655 | sys_addr, node, | |
1656 | chan_sel); | |
1657 | if (cs_found >= 0) | |
1658 | break; | |
1659 | } | |
1660 | } | |
1661 | return cs_found; | |
1662 | } | |
1663 | ||
1664 | /* | |
1665 | * This the F10h reference code from AMD to map a @sys_addr to NodeID, | |
1666 | * CSROW, Channel. | |
1667 | * | |
1668 | * The @sys_addr is usually an error address received from the hardware. | |
1669 | */ | |
1670 | static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci, | |
ef44cc4c | 1671 | struct err_regs *info, |
f71d0a05 DT |
1672 | u64 sys_addr) |
1673 | { | |
1674 | struct amd64_pvt *pvt = mci->pvt_info; | |
1675 | u32 page, offset; | |
1676 | unsigned short syndrome; | |
1677 | int nid, csrow, chan = 0; | |
1678 | ||
1679 | csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan); | |
1680 | ||
1681 | if (csrow >= 0) { | |
1682 | error_address_to_page_and_offset(sys_addr, &page, &offset); | |
1683 | ||
b70ef010 BP |
1684 | syndrome = HIGH_SYNDROME(info->nbsl) << 8; |
1685 | syndrome |= LOW_SYNDROME(info->nbsh); | |
f71d0a05 DT |
1686 | |
1687 | /* | |
1688 | * Is CHIPKILL on? If so, then we can attempt to use the | |
1689 | * syndrome to isolate which channel the error was on. | |
1690 | */ | |
1691 | if (pvt->nbcfg & K8_NBCFG_CHIPKILL) | |
1692 | chan = get_channel_from_ecc_syndrome(syndrome); | |
1693 | ||
1694 | if (chan >= 0) { | |
1695 | edac_mc_handle_ce(mci, page, offset, syndrome, | |
1696 | csrow, chan, EDAC_MOD_STR); | |
1697 | } else { | |
1698 | /* | |
1699 | * Channel unknown, report all channels on this | |
1700 | * CSROW as failed. | |
1701 | */ | |
1702 | for (chan = 0; chan < mci->csrows[csrow].nr_channels; | |
1703 | chan++) { | |
1704 | edac_mc_handle_ce(mci, page, offset, | |
1705 | syndrome, | |
1706 | csrow, chan, | |
1707 | EDAC_MOD_STR); | |
1708 | } | |
1709 | } | |
1710 | ||
1711 | } else { | |
1712 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1713 | } | |
1714 | } | |
1715 | ||
f71d0a05 | 1716 | /* |
8566c4df | 1717 | * debug routine to display the memory sizes of all logical DIMMs and its |
f71d0a05 DT |
1718 | * CSROWs as well |
1719 | */ | |
8566c4df | 1720 | static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt) |
f71d0a05 DT |
1721 | { |
1722 | int dimm, size0, size1; | |
1723 | u32 dbam; | |
1724 | u32 *dcsb; | |
1725 | ||
8566c4df BP |
1726 | if (boot_cpu_data.x86 == 0xf) { |
1727 | /* K8 families < revF not supported yet */ | |
1433eb99 | 1728 | if (pvt->ext_model < K8_REV_F) |
8566c4df BP |
1729 | return; |
1730 | else | |
1731 | WARN_ON(ctrl != 0); | |
1732 | } | |
1733 | ||
1734 | debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", | |
1735 | ctrl, ctrl ? pvt->dbam1 : pvt->dbam0); | |
f71d0a05 DT |
1736 | |
1737 | dbam = ctrl ? pvt->dbam1 : pvt->dbam0; | |
1738 | dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0; | |
1739 | ||
8566c4df BP |
1740 | edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl); |
1741 | ||
f71d0a05 DT |
1742 | /* Dump memory sizes for DIMM and its CSROWs */ |
1743 | for (dimm = 0; dimm < 4; dimm++) { | |
1744 | ||
1745 | size0 = 0; | |
1746 | if (dcsb[dimm*2] & K8_DCSB_CS_ENABLE) | |
1433eb99 | 1747 | size0 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam)); |
f71d0a05 DT |
1748 | |
1749 | size1 = 0; | |
1750 | if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE) | |
1433eb99 | 1751 | size1 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam)); |
f71d0a05 | 1752 | |
8566c4df BP |
1753 | edac_printk(KERN_DEBUG, EDAC_MC, " %d: %5dMB %d: %5dMB\n", |
1754 | dimm * 2, size0, dimm * 2 + 1, size1); | |
f71d0a05 DT |
1755 | } |
1756 | } | |
1757 | ||
1758 | /* | |
1759 | * Very early hardware probe on pci_probe thread to determine if this module | |
1760 | * supports the hardware. | |
1761 | * | |
1762 | * Return: | |
1763 | * 0 for OK | |
1764 | * 1 for error | |
1765 | */ | |
1766 | static int f10_probe_valid_hardware(struct amd64_pvt *pvt) | |
1767 | { | |
1768 | int ret = 0; | |
1769 | ||
1770 | /* | |
1771 | * If we are on a DDR3 machine, we don't know yet if | |
1772 | * we support that properly at this time | |
1773 | */ | |
1433eb99 BP |
1774 | if ((pvt->dchr0 & DDR3_MODE) || |
1775 | (pvt->dchr1 & DDR3_MODE)) { | |
f71d0a05 DT |
1776 | |
1777 | amd64_printk(KERN_WARNING, | |
1778 | "%s() This machine is running with DDR3 memory. " | |
1779 | "This is not currently supported. " | |
1780 | "DCHR0=0x%x DCHR1=0x%x\n", | |
1781 | __func__, pvt->dchr0, pvt->dchr1); | |
1782 | ||
1783 | amd64_printk(KERN_WARNING, | |
1784 | " Contact '%s' module MAINTAINER to help add" | |
1785 | " support.\n", | |
1786 | EDAC_MOD_STR); | |
1787 | ||
1788 | ret = 1; | |
1789 | ||
1790 | } | |
1791 | return ret; | |
1792 | } | |
6163b5d4 | 1793 | |
4d37607a DT |
1794 | /* |
1795 | * There currently are 3 types type of MC devices for AMD Athlon/Opterons | |
1796 | * (as per PCI DEVICE_IDs): | |
1797 | * | |
1798 | * Family K8: That is the Athlon64 and Opteron CPUs. They all have the same PCI | |
1799 | * DEVICE ID, even though there is differences between the different Revisions | |
1800 | * (CG,D,E,F). | |
1801 | * | |
1802 | * Family F10h and F11h. | |
1803 | * | |
1804 | */ | |
1805 | static struct amd64_family_type amd64_family_types[] = { | |
1806 | [K8_CPUS] = { | |
1807 | .ctl_name = "RevF", | |
1808 | .addr_f1_ctl = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, | |
1809 | .misc_f3_ctl = PCI_DEVICE_ID_AMD_K8_NB_MISC, | |
1810 | .ops = { | |
1433eb99 BP |
1811 | .early_channel_count = k8_early_channel_count, |
1812 | .get_error_address = k8_get_error_address, | |
1813 | .read_dram_base_limit = k8_read_dram_base_limit, | |
1814 | .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, | |
1815 | .dbam_to_cs = k8_dbam_to_chip_select, | |
4d37607a DT |
1816 | } |
1817 | }, | |
1818 | [F10_CPUS] = { | |
1819 | .ctl_name = "Family 10h", | |
1820 | .addr_f1_ctl = PCI_DEVICE_ID_AMD_10H_NB_MAP, | |
1821 | .misc_f3_ctl = PCI_DEVICE_ID_AMD_10H_NB_MISC, | |
1822 | .ops = { | |
1433eb99 BP |
1823 | .probe_valid_hardware = f10_probe_valid_hardware, |
1824 | .early_channel_count = f10_early_channel_count, | |
1825 | .get_error_address = f10_get_error_address, | |
1826 | .read_dram_base_limit = f10_read_dram_base_limit, | |
1827 | .read_dram_ctl_register = f10_read_dram_ctl_register, | |
1828 | .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, | |
1829 | .dbam_to_cs = f10_dbam_to_chip_select, | |
4d37607a DT |
1830 | } |
1831 | }, | |
1832 | [F11_CPUS] = { | |
1833 | .ctl_name = "Family 11h", | |
1834 | .addr_f1_ctl = PCI_DEVICE_ID_AMD_11H_NB_MAP, | |
1835 | .misc_f3_ctl = PCI_DEVICE_ID_AMD_11H_NB_MISC, | |
1836 | .ops = { | |
1433eb99 BP |
1837 | .probe_valid_hardware = f10_probe_valid_hardware, |
1838 | .early_channel_count = f10_early_channel_count, | |
1839 | .get_error_address = f10_get_error_address, | |
1840 | .read_dram_base_limit = f10_read_dram_base_limit, | |
1841 | .read_dram_ctl_register = f10_read_dram_ctl_register, | |
1842 | .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, | |
1843 | .dbam_to_cs = f10_dbam_to_chip_select, | |
4d37607a DT |
1844 | } |
1845 | }, | |
1846 | }; | |
1847 | ||
1848 | static struct pci_dev *pci_get_related_function(unsigned int vendor, | |
1849 | unsigned int device, | |
1850 | struct pci_dev *related) | |
1851 | { | |
1852 | struct pci_dev *dev = NULL; | |
1853 | ||
1854 | dev = pci_get_device(vendor, device, dev); | |
1855 | while (dev) { | |
1856 | if ((dev->bus->number == related->bus->number) && | |
1857 | (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) | |
1858 | break; | |
1859 | dev = pci_get_device(vendor, device, dev); | |
1860 | } | |
1861 | ||
1862 | return dev; | |
1863 | } | |
1864 | ||
b1289d6f DT |
1865 | /* |
1866 | * syndrome mapping table for ECC ChipKill devices | |
1867 | * | |
1868 | * The comment in each row is the token (nibble) number that is in error. | |
1869 | * The least significant nibble of the syndrome is the mask for the bits | |
1870 | * that are in error (need to be toggled) for the particular nibble. | |
1871 | * | |
1872 | * Each row contains 16 entries. | |
1873 | * The first entry (0th) is the channel number for that row of syndromes. | |
1874 | * The remaining 15 entries are the syndromes for the respective Error | |
1875 | * bit mask index. | |
1876 | * | |
1877 | * 1st index entry is 0x0001 mask, indicating that the rightmost bit is the | |
1878 | * bit in error. | |
1879 | * The 2nd index entry is 0x0010 that the second bit is damaged. | |
1880 | * The 3rd index entry is 0x0011 indicating that the rightmost 2 bits | |
1881 | * are damaged. | |
1882 | * Thus so on until index 15, 0x1111, whose entry has the syndrome | |
1883 | * indicating that all 4 bits are damaged. | |
1884 | * | |
1885 | * A search is performed on this table looking for a given syndrome. | |
1886 | * | |
1887 | * See the AMD documentation for ECC syndromes. This ECC table is valid | |
1888 | * across all the versions of the AMD64 processors. | |
1889 | * | |
1890 | * A fast lookup is to use the LAST four bits of the 16-bit syndrome as a | |
1891 | * COLUMN index, then search all ROWS of that column, looking for a match | |
1892 | * with the input syndrome. The ROW value will be the token number. | |
1893 | * | |
1894 | * The 0'th entry on that row, can be returned as the CHANNEL (0 or 1) of this | |
1895 | * error. | |
1896 | */ | |
1897 | #define NUMBER_ECC_ROWS 36 | |
1898 | static const unsigned short ecc_chipkill_syndromes[NUMBER_ECC_ROWS][16] = { | |
1899 | /* Channel 0 syndromes */ | |
1900 | {/*0*/ 0, 0xe821, 0x7c32, 0x9413, 0xbb44, 0x5365, 0xc776, 0x2f57, | |
1901 | 0xdd88, 0x35a9, 0xa1ba, 0x499b, 0x66cc, 0x8eed, 0x1afe, 0xf2df }, | |
1902 | {/*1*/ 0, 0x5d31, 0xa612, 0xfb23, 0x9584, 0xc8b5, 0x3396, 0x6ea7, | |
1903 | 0xeac8, 0xb7f9, 0x4cda, 0x11eb, 0x7f4c, 0x227d, 0xd95e, 0x846f }, | |
1904 | {/*2*/ 0, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, | |
1905 | 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f }, | |
1906 | {/*3*/ 0, 0x2021, 0x3032, 0x1013, 0x4044, 0x6065, 0x7076, 0x5057, | |
1907 | 0x8088, 0xa0a9, 0xb0ba, 0x909b, 0xc0cc, 0xe0ed, 0xf0fe, 0xd0df }, | |
1908 | {/*4*/ 0, 0x5041, 0xa082, 0xf0c3, 0x9054, 0xc015, 0x30d6, 0x6097, | |
1909 | 0xe0a8, 0xb0e9, 0x402a, 0x106b, 0x70fc, 0x20bd, 0xd07e, 0x803f }, | |
1910 | {/*5*/ 0, 0xbe21, 0xd732, 0x6913, 0x2144, 0x9f65, 0xf676, 0x4857, | |
1911 | 0x3288, 0x8ca9, 0xe5ba, 0x5b9b, 0x13cc, 0xaded, 0xc4fe, 0x7adf }, | |
1912 | {/*6*/ 0, 0x4951, 0x8ea2, 0xc7f3, 0x5394, 0x1ac5, 0xdd36, 0x9467, | |
1913 | 0xa1e8, 0xe8b9, 0x2f4a, 0x661b, 0xf27c, 0xbb2d, 0x7cde, 0x358f }, | |
1914 | {/*7*/ 0, 0x74e1, 0x9872, 0xec93, 0xd6b4, 0xa255, 0x4ec6, 0x3a27, | |
1915 | 0x6bd8, 0x1f39, 0xf3aa, 0x874b, 0xbd6c, 0xc98d, 0x251e, 0x51ff }, | |
1916 | {/*8*/ 0, 0x15c1, 0x2a42, 0x3f83, 0xcef4, 0xdb35, 0xe4b6, 0xf177, | |
1917 | 0x4758, 0x5299, 0x6d1a, 0x78db, 0x89ac, 0x9c6d, 0xa3ee, 0xb62f }, | |
1918 | {/*9*/ 0, 0x3d01, 0x1602, 0x2b03, 0x8504, 0xb805, 0x9306, 0xae07, | |
1919 | 0xca08, 0xf709, 0xdc0a, 0xe10b, 0x4f0c, 0x720d, 0x590e, 0x640f }, | |
1920 | {/*a*/ 0, 0x9801, 0xec02, 0x7403, 0x6b04, 0xf305, 0x8706, 0x1f07, | |
1921 | 0xbd08, 0x2509, 0x510a, 0xc90b, 0xd60c, 0x4e0d, 0x3a0e, 0xa20f }, | |
1922 | {/*b*/ 0, 0xd131, 0x6212, 0xb323, 0x3884, 0xe9b5, 0x5a96, 0x8ba7, | |
1923 | 0x1cc8, 0xcdf9, 0x7eda, 0xafeb, 0x244c, 0xf57d, 0x465e, 0x976f }, | |
1924 | {/*c*/ 0, 0xe1d1, 0x7262, 0x93b3, 0xb834, 0x59e5, 0xca56, 0x2b87, | |
1925 | 0xdc18, 0x3dc9, 0xae7a, 0x4fab, 0x542c, 0x85fd, 0x164e, 0xf79f }, | |
1926 | {/*d*/ 0, 0x6051, 0xb0a2, 0xd0f3, 0x1094, 0x70c5, 0xa036, 0xc067, | |
1927 | 0x20e8, 0x40b9, 0x904a, 0x601b, 0x307c, 0x502d, 0x80de, 0xe08f }, | |
1928 | {/*e*/ 0, 0xa4c1, 0xf842, 0x5c83, 0xe6f4, 0x4235, 0x1eb6, 0xba77, | |
1929 | 0x7b58, 0xdf99, 0x831a, 0x27db, 0x9dac, 0x396d, 0x65ee, 0xc12f }, | |
1930 | {/*f*/ 0, 0x11c1, 0x2242, 0x3383, 0xc8f4, 0xd935, 0xeab6, 0xfb77, | |
1931 | 0x4c58, 0x5d99, 0x6e1a, 0x7fdb, 0x84ac, 0x956d, 0xa6ee, 0xb72f }, | |
1932 | ||
1933 | /* Channel 1 syndromes */ | |
1934 | {/*10*/ 1, 0x45d1, 0x8a62, 0xcfb3, 0x5e34, 0x1be5, 0xd456, 0x9187, | |
1935 | 0xa718, 0xe2c9, 0x2d7a, 0x68ab, 0xf92c, 0xbcfd, 0x734e, 0x369f }, | |
1936 | {/*11*/ 1, 0x63e1, 0xb172, 0xd293, 0x14b4, 0x7755, 0xa5c6, 0xc627, | |
1937 | 0x28d8, 0x4b39, 0x99aa, 0xfa4b, 0x3c6c, 0x5f8d, 0x8d1e, 0xeeff }, | |
1938 | {/*12*/ 1, 0xb741, 0xd982, 0x6ec3, 0x2254, 0x9515, 0xfbd6, 0x4c97, | |
1939 | 0x33a8, 0x84e9, 0xea2a, 0x5d6b, 0x11fc, 0xa6bd, 0xc87e, 0x7f3f }, | |
1940 | {/*13*/ 1, 0xdd41, 0x6682, 0xbbc3, 0x3554, 0xe815, 0x53d6, 0xce97, | |
1941 | 0x1aa8, 0xc7e9, 0x7c2a, 0xa1fb, 0x2ffc, 0xf2bd, 0x497e, 0x943f }, | |
1942 | {/*14*/ 1, 0x2bd1, 0x3d62, 0x16b3, 0x4f34, 0x64e5, 0x7256, 0x5987, | |
1943 | 0x8518, 0xaec9, 0xb87a, 0x93ab, 0xca2c, 0xe1fd, 0xf74e, 0xdc9f }, | |
1944 | {/*15*/ 1, 0x83c1, 0xc142, 0x4283, 0xa4f4, 0x2735, 0x65b6, 0xe677, | |
1945 | 0xf858, 0x7b99, 0x391a, 0xbadb, 0x5cac, 0xdf6d, 0x9dee, 0x1e2f }, | |
1946 | {/*16*/ 1, 0x8fd1, 0xc562, 0x4ab3, 0xa934, 0x26e5, 0x6c56, 0xe387, | |
1947 | 0xfe18, 0x71c9, 0x3b7a, 0xb4ab, 0x572c, 0xd8fd, 0x924e, 0x1d9f }, | |
1948 | {/*17*/ 1, 0x4791, 0x89e2, 0xce73, 0x5264, 0x15f5, 0xdb86, 0x9c17, | |
1949 | 0xa3b8, 0xe429, 0x2a5a, 0x6dcb, 0xf1dc, 0xb64d, 0x783e, 0x3faf }, | |
1950 | {/*18*/ 1, 0x5781, 0xa9c2, 0xfe43, 0x92a4, 0xc525, 0x3b66, 0x6ce7, | |
1951 | 0xe3f8, 0xb479, 0x4a3a, 0x1dbb, 0x715c, 0x26dd, 0xd89e, 0x8f1f }, | |
1952 | {/*19*/ 1, 0xbf41, 0xd582, 0x6ac3, 0x2954, 0x9615, 0xfcd6, 0x4397, | |
1953 | 0x3ea8, 0x81e9, 0xeb2a, 0x546b, 0x17fc, 0xa8bd, 0xc27e, 0x7d3f }, | |
1954 | {/*1a*/ 1, 0x9891, 0xe1e2, 0x7273, 0x6464, 0xf7f5, 0x8586, 0x1617, | |
1955 | 0xb8b8, 0x2b29, 0x595a, 0xcacb, 0xdcdc, 0x4f4d, 0x3d3e, 0xaeaf }, | |
1956 | {/*1b*/ 1, 0xcce1, 0x4472, 0x8893, 0xfdb4, 0x3f55, 0xb9c6, 0x7527, | |
1957 | 0x56d8, 0x9a39, 0x12aa, 0xde4b, 0xab6c, 0x678d, 0xef1e, 0x23ff }, | |
1958 | {/*1c*/ 1, 0xa761, 0xf9b2, 0x5ed3, 0xe214, 0x4575, 0x1ba6, 0xbcc7, | |
1959 | 0x7328, 0xd449, 0x8a9a, 0x2dfb, 0x913c, 0x365d, 0x688e, 0xcfef }, | |
1960 | {/*1d*/ 1, 0xff61, 0x55b2, 0xaad3, 0x7914, 0x8675, 0x2ca6, 0xd3c7, | |
1961 | 0x9e28, 0x6149, 0xcb9a, 0x34fb, 0xe73c, 0x185d, 0xb28e, 0x4def }, | |
1962 | {/*1e*/ 1, 0x5451, 0xa8a2, 0xfcf3, 0x9694, 0xc2c5, 0x3e36, 0x6a67, | |
1963 | 0xebe8, 0xbfb9, 0x434a, 0x171b, 0x7d7c, 0x292d, 0xd5de, 0x818f }, | |
1964 | {/*1f*/ 1, 0x6fc1, 0xb542, 0xda83, 0x19f4, 0x7635, 0xacb6, 0xc377, | |
1965 | 0x2e58, 0x4199, 0x9b1a, 0xf4db, 0x37ac, 0x586d, 0x82ee, 0xed2f }, | |
1966 | ||
1967 | /* ECC bits are also in the set of tokens and they too can go bad | |
1968 | * first 2 cover channel 0, while the second 2 cover channel 1 | |
1969 | */ | |
1970 | {/*20*/ 0, 0xbe01, 0xd702, 0x6903, 0x2104, 0x9f05, 0xf606, 0x4807, | |
1971 | 0x3208, 0x8c09, 0xe50a, 0x5b0b, 0x130c, 0xad0d, 0xc40e, 0x7a0f }, | |
1972 | {/*21*/ 0, 0x4101, 0x8202, 0xc303, 0x5804, 0x1905, 0xda06, 0x9b07, | |
1973 | 0xac08, 0xed09, 0x2e0a, 0x6f0b, 0x640c, 0xb50d, 0x760e, 0x370f }, | |
1974 | {/*22*/ 1, 0xc441, 0x4882, 0x8cc3, 0xf654, 0x3215, 0xbed6, 0x7a97, | |
1975 | 0x5ba8, 0x9fe9, 0x132a, 0xd76b, 0xadfc, 0x69bd, 0xe57e, 0x213f }, | |
1976 | {/*23*/ 1, 0x7621, 0x9b32, 0xed13, 0xda44, 0xac65, 0x4176, 0x3757, | |
1977 | 0x6f88, 0x19a9, 0xf4ba, 0x829b, 0xb5cc, 0xc3ed, 0x2efe, 0x58df } | |
1978 | }; | |
1979 | ||
1980 | /* | |
1981 | * Given the syndrome argument, scan each of the channel tables for a syndrome | |
1982 | * match. Depending on which table it is found, return the channel number. | |
1983 | */ | |
1984 | static int get_channel_from_ecc_syndrome(unsigned short syndrome) | |
1985 | { | |
1986 | int row; | |
1987 | int column; | |
4d37607a | 1988 | |
b1289d6f DT |
1989 | /* Determine column to scan */ |
1990 | column = syndrome & 0xF; | |
1991 | ||
1992 | /* Scan all rows, looking for syndrome, or end of table */ | |
1993 | for (row = 0; row < NUMBER_ECC_ROWS; row++) { | |
1994 | if (ecc_chipkill_syndromes[row][column] == syndrome) | |
1995 | return ecc_chipkill_syndromes[row][0]; | |
1996 | } | |
1997 | ||
1998 | debugf0("syndrome(%x) not found\n", syndrome); | |
1999 | return -1; | |
2000 | } | |
d27bf6fa DT |
2001 | |
2002 | /* | |
2003 | * Check for valid error in the NB Status High register. If so, proceed to read | |
2004 | * NB Status Low, NB Address Low and NB Address High registers and store data | |
2005 | * into error structure. | |
2006 | * | |
2007 | * Returns: | |
2008 | * - 1: if hardware regs contains valid error info | |
2009 | * - 0: if no valid error is indicated | |
2010 | */ | |
2011 | static int amd64_get_error_info_regs(struct mem_ctl_info *mci, | |
ef44cc4c | 2012 | struct err_regs *regs) |
d27bf6fa DT |
2013 | { |
2014 | struct amd64_pvt *pvt; | |
2015 | struct pci_dev *misc_f3_ctl; | |
d27bf6fa DT |
2016 | |
2017 | pvt = mci->pvt_info; | |
2018 | misc_f3_ctl = pvt->misc_f3_ctl; | |
2019 | ||
6ba5dcdc BP |
2020 | if (amd64_read_pci_cfg(misc_f3_ctl, K8_NBSH, ®s->nbsh)) |
2021 | return 0; | |
d27bf6fa DT |
2022 | |
2023 | if (!(regs->nbsh & K8_NBSH_VALID_BIT)) | |
2024 | return 0; | |
2025 | ||
2026 | /* valid error, read remaining error information registers */ | |
6ba5dcdc BP |
2027 | if (amd64_read_pci_cfg(misc_f3_ctl, K8_NBSL, ®s->nbsl) || |
2028 | amd64_read_pci_cfg(misc_f3_ctl, K8_NBEAL, ®s->nbeal) || | |
2029 | amd64_read_pci_cfg(misc_f3_ctl, K8_NBEAH, ®s->nbeah) || | |
2030 | amd64_read_pci_cfg(misc_f3_ctl, K8_NBCFG, ®s->nbcfg)) | |
2031 | return 0; | |
d27bf6fa DT |
2032 | |
2033 | return 1; | |
d27bf6fa DT |
2034 | } |
2035 | ||
2036 | /* | |
2037 | * This function is called to retrieve the error data from hardware and store it | |
2038 | * in the info structure. | |
2039 | * | |
2040 | * Returns: | |
2041 | * - 1: if a valid error is found | |
2042 | * - 0: if no error is found | |
2043 | */ | |
2044 | static int amd64_get_error_info(struct mem_ctl_info *mci, | |
ef44cc4c | 2045 | struct err_regs *info) |
d27bf6fa DT |
2046 | { |
2047 | struct amd64_pvt *pvt; | |
ef44cc4c | 2048 | struct err_regs regs; |
d27bf6fa DT |
2049 | |
2050 | pvt = mci->pvt_info; | |
2051 | ||
2052 | if (!amd64_get_error_info_regs(mci, info)) | |
2053 | return 0; | |
2054 | ||
2055 | /* | |
2056 | * Here's the problem with the K8's EDAC reporting: There are four | |
2057 | * registers which report pieces of error information. They are shared | |
2058 | * between CEs and UEs. Furthermore, contrary to what is stated in the | |
2059 | * BKDG, the overflow bit is never used! Every error always updates the | |
2060 | * reporting registers. | |
2061 | * | |
2062 | * Can you see the race condition? All four error reporting registers | |
2063 | * must be read before a new error updates them! There is no way to read | |
2064 | * all four registers atomically. The best than can be done is to detect | |
2065 | * that a race has occured and then report the error without any kind of | |
2066 | * precision. | |
2067 | * | |
2068 | * What is still positive is that errors are still reported and thus | |
2069 | * problems can still be detected - just not localized because the | |
2070 | * syndrome and address are spread out across registers. | |
2071 | * | |
2072 | * Grrrrr!!!!! Here's hoping that AMD fixes this in some future K8 rev. | |
2073 | * UEs and CEs should have separate register sets with proper overflow | |
2074 | * bits that are used! At very least the problem can be fixed by | |
2075 | * honoring the ErrValid bit in 'nbsh' and not updating registers - just | |
2076 | * set the overflow bit - unless the current error is CE and the new | |
2077 | * error is UE which would be the only situation for overwriting the | |
2078 | * current values. | |
2079 | */ | |
2080 | ||
2081 | regs = *info; | |
2082 | ||
2083 | /* Use info from the second read - most current */ | |
2084 | if (unlikely(!amd64_get_error_info_regs(mci, info))) | |
2085 | return 0; | |
2086 | ||
2087 | /* clear the error bits in hardware */ | |
2088 | pci_write_bits32(pvt->misc_f3_ctl, K8_NBSH, 0, K8_NBSH_VALID_BIT); | |
2089 | ||
2090 | /* Check for the possible race condition */ | |
2091 | if ((regs.nbsh != info->nbsh) || | |
2092 | (regs.nbsl != info->nbsl) || | |
2093 | (regs.nbeah != info->nbeah) || | |
2094 | (regs.nbeal != info->nbeal)) { | |
2095 | amd64_mc_printk(mci, KERN_WARNING, | |
2096 | "hardware STATUS read access race condition " | |
2097 | "detected!\n"); | |
2098 | return 0; | |
2099 | } | |
2100 | return 1; | |
2101 | } | |
2102 | ||
d27bf6fa DT |
2103 | /* |
2104 | * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR | |
2105 | * ADDRESS and process. | |
2106 | */ | |
2107 | static void amd64_handle_ce(struct mem_ctl_info *mci, | |
ef44cc4c | 2108 | struct err_regs *info) |
d27bf6fa DT |
2109 | { |
2110 | struct amd64_pvt *pvt = mci->pvt_info; | |
44e9e2ee | 2111 | u64 sys_addr; |
d27bf6fa DT |
2112 | |
2113 | /* Ensure that the Error Address is VALID */ | |
2114 | if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { | |
2115 | amd64_mc_printk(mci, KERN_ERR, | |
2116 | "HW has no ERROR_ADDRESS available\n"); | |
2117 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
2118 | return; | |
2119 | } | |
2120 | ||
44e9e2ee | 2121 | sys_addr = extract_error_address(mci, info); |
d27bf6fa DT |
2122 | |
2123 | amd64_mc_printk(mci, KERN_ERR, | |
44e9e2ee | 2124 | "CE ERROR_ADDRESS= 0x%llx\n", sys_addr); |
d27bf6fa | 2125 | |
44e9e2ee | 2126 | pvt->ops->map_sysaddr_to_csrow(mci, info, sys_addr); |
d27bf6fa DT |
2127 | } |
2128 | ||
2129 | /* Handle any Un-correctable Errors (UEs) */ | |
2130 | static void amd64_handle_ue(struct mem_ctl_info *mci, | |
ef44cc4c | 2131 | struct err_regs *info) |
d27bf6fa DT |
2132 | { |
2133 | int csrow; | |
44e9e2ee | 2134 | u64 sys_addr; |
d27bf6fa DT |
2135 | u32 page, offset; |
2136 | struct mem_ctl_info *log_mci, *src_mci = NULL; | |
2137 | ||
2138 | log_mci = mci; | |
2139 | ||
2140 | if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { | |
2141 | amd64_mc_printk(mci, KERN_CRIT, | |
2142 | "HW has no ERROR_ADDRESS available\n"); | |
2143 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); | |
2144 | return; | |
2145 | } | |
2146 | ||
44e9e2ee | 2147 | sys_addr = extract_error_address(mci, info); |
d27bf6fa DT |
2148 | |
2149 | /* | |
2150 | * Find out which node the error address belongs to. This may be | |
2151 | * different from the node that detected the error. | |
2152 | */ | |
44e9e2ee | 2153 | src_mci = find_mc_by_sys_addr(mci, sys_addr); |
d27bf6fa DT |
2154 | if (!src_mci) { |
2155 | amd64_mc_printk(mci, KERN_CRIT, | |
2156 | "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n", | |
44e9e2ee | 2157 | (unsigned long)sys_addr); |
d27bf6fa DT |
2158 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); |
2159 | return; | |
2160 | } | |
2161 | ||
2162 | log_mci = src_mci; | |
2163 | ||
44e9e2ee | 2164 | csrow = sys_addr_to_csrow(log_mci, sys_addr); |
d27bf6fa DT |
2165 | if (csrow < 0) { |
2166 | amd64_mc_printk(mci, KERN_CRIT, | |
2167 | "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n", | |
44e9e2ee | 2168 | (unsigned long)sys_addr); |
d27bf6fa DT |
2169 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); |
2170 | } else { | |
44e9e2ee | 2171 | error_address_to_page_and_offset(sys_addr, &page, &offset); |
d27bf6fa DT |
2172 | edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR); |
2173 | } | |
2174 | } | |
2175 | ||
549d042d | 2176 | static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, |
b69b29de | 2177 | struct err_regs *info) |
d27bf6fa | 2178 | { |
b70ef010 BP |
2179 | u32 ec = ERROR_CODE(info->nbsl); |
2180 | u32 xec = EXT_ERROR_CODE(info->nbsl); | |
17adea01 | 2181 | int ecc_type = (info->nbsh >> 13) & 0x3; |
d27bf6fa | 2182 | |
b70ef010 BP |
2183 | /* Bail early out if this was an 'observed' error */ |
2184 | if (PP(ec) == K8_NBSL_PP_OBS) | |
2185 | return; | |
d27bf6fa | 2186 | |
ecaf5606 BP |
2187 | /* Do only ECC errors */ |
2188 | if (xec && xec != F10_NBSL_EXT_ERR_ECC) | |
d27bf6fa | 2189 | return; |
d27bf6fa | 2190 | |
ecaf5606 | 2191 | if (ecc_type == 2) |
d27bf6fa | 2192 | amd64_handle_ce(mci, info); |
ecaf5606 | 2193 | else if (ecc_type == 1) |
d27bf6fa DT |
2194 | amd64_handle_ue(mci, info); |
2195 | ||
2196 | /* | |
2197 | * If main error is CE then overflow must be CE. If main error is UE | |
2198 | * then overflow is unknown. We'll call the overflow a CE - if | |
2199 | * panic_on_ue is set then we're already panic'ed and won't arrive | |
2200 | * here. Else, then apparently someone doesn't think that UE's are | |
2201 | * catastrophic. | |
2202 | */ | |
2203 | if (info->nbsh & K8_NBSH_OVERFLOW) | |
ecaf5606 | 2204 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR "Error Overflow"); |
d27bf6fa DT |
2205 | } |
2206 | ||
b69b29de | 2207 | void amd64_decode_bus_error(int node_id, struct err_regs *regs) |
d27bf6fa | 2208 | { |
549d042d | 2209 | struct mem_ctl_info *mci = mci_lookup[node_id]; |
d27bf6fa | 2210 | |
b69b29de | 2211 | __amd64_decode_bus_error(mci, regs); |
d27bf6fa | 2212 | |
d27bf6fa DT |
2213 | /* |
2214 | * Check the UE bit of the NB status high register, if set generate some | |
2215 | * logs. If NOT a GART error, then process the event as a NO-INFO event. | |
2216 | * If it was a GART error, skip that process. | |
549d042d BP |
2217 | * |
2218 | * FIXME: this should go somewhere else, if at all. | |
d27bf6fa | 2219 | */ |
5110dbde BP |
2220 | if (regs->nbsh & K8_NBSH_UC_ERR && !report_gart_errors) |
2221 | edac_mc_handle_ue_no_info(mci, "UE bit is set"); | |
549d042d | 2222 | |
d27bf6fa | 2223 | } |
d27bf6fa | 2224 | |
0ec449ee DT |
2225 | /* |
2226 | * The main polling 'check' function, called FROM the edac core to perform the | |
2227 | * error checking and if an error is encountered, error processing. | |
2228 | */ | |
2229 | static void amd64_check(struct mem_ctl_info *mci) | |
2230 | { | |
ef44cc4c | 2231 | struct err_regs regs; |
0ec449ee | 2232 | |
549d042d BP |
2233 | if (amd64_get_error_info(mci, ®s)) { |
2234 | struct amd64_pvt *pvt = mci->pvt_info; | |
2235 | amd_decode_nb_mce(pvt->mc_node_id, ®s, 1); | |
2236 | } | |
0ec449ee DT |
2237 | } |
2238 | ||
2239 | /* | |
2240 | * Input: | |
2241 | * 1) struct amd64_pvt which contains pvt->dram_f2_ctl pointer | |
2242 | * 2) AMD Family index value | |
2243 | * | |
2244 | * Ouput: | |
2245 | * Upon return of 0, the following filled in: | |
2246 | * | |
2247 | * struct pvt->addr_f1_ctl | |
2248 | * struct pvt->misc_f3_ctl | |
2249 | * | |
2250 | * Filled in with related device funcitions of 'dram_f2_ctl' | |
2251 | * These devices are "reserved" via the pci_get_device() | |
2252 | * | |
2253 | * Upon return of 1 (error status): | |
2254 | * | |
2255 | * Nothing reserved | |
2256 | */ | |
2257 | static int amd64_reserve_mc_sibling_devices(struct amd64_pvt *pvt, int mc_idx) | |
2258 | { | |
2259 | const struct amd64_family_type *amd64_dev = &amd64_family_types[mc_idx]; | |
2260 | ||
2261 | /* Reserve the ADDRESS MAP Device */ | |
2262 | pvt->addr_f1_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor, | |
2263 | amd64_dev->addr_f1_ctl, | |
2264 | pvt->dram_f2_ctl); | |
2265 | ||
2266 | if (!pvt->addr_f1_ctl) { | |
2267 | amd64_printk(KERN_ERR, "error address map device not found: " | |
2268 | "vendor %x device 0x%x (broken BIOS?)\n", | |
2269 | PCI_VENDOR_ID_AMD, amd64_dev->addr_f1_ctl); | |
2270 | return 1; | |
2271 | } | |
2272 | ||
2273 | /* Reserve the MISC Device */ | |
2274 | pvt->misc_f3_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor, | |
2275 | amd64_dev->misc_f3_ctl, | |
2276 | pvt->dram_f2_ctl); | |
2277 | ||
2278 | if (!pvt->misc_f3_ctl) { | |
2279 | pci_dev_put(pvt->addr_f1_ctl); | |
2280 | pvt->addr_f1_ctl = NULL; | |
2281 | ||
2282 | amd64_printk(KERN_ERR, "error miscellaneous device not found: " | |
2283 | "vendor %x device 0x%x (broken BIOS?)\n", | |
2284 | PCI_VENDOR_ID_AMD, amd64_dev->misc_f3_ctl); | |
2285 | return 1; | |
2286 | } | |
2287 | ||
2288 | debugf1(" Addr Map device PCI Bus ID:\t%s\n", | |
2289 | pci_name(pvt->addr_f1_ctl)); | |
2290 | debugf1(" DRAM MEM-CTL PCI Bus ID:\t%s\n", | |
2291 | pci_name(pvt->dram_f2_ctl)); | |
2292 | debugf1(" Misc device PCI Bus ID:\t%s\n", | |
2293 | pci_name(pvt->misc_f3_ctl)); | |
2294 | ||
2295 | return 0; | |
2296 | } | |
2297 | ||
2298 | static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt) | |
2299 | { | |
2300 | pci_dev_put(pvt->addr_f1_ctl); | |
2301 | pci_dev_put(pvt->misc_f3_ctl); | |
2302 | } | |
2303 | ||
2304 | /* | |
2305 | * Retrieve the hardware registers of the memory controller (this includes the | |
2306 | * 'Address Map' and 'Misc' device regs) | |
2307 | */ | |
2308 | static void amd64_read_mc_registers(struct amd64_pvt *pvt) | |
2309 | { | |
2310 | u64 msr_val; | |
6ba5dcdc | 2311 | int dram; |
0ec449ee DT |
2312 | |
2313 | /* | |
2314 | * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since | |
2315 | * those are Read-As-Zero | |
2316 | */ | |
e97f8bb8 BP |
2317 | rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); |
2318 | debugf0(" TOP_MEM: 0x%016llx\n", pvt->top_mem); | |
0ec449ee DT |
2319 | |
2320 | /* check first whether TOP_MEM2 is enabled */ | |
2321 | rdmsrl(MSR_K8_SYSCFG, msr_val); | |
2322 | if (msr_val & (1U << 21)) { | |
e97f8bb8 BP |
2323 | rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); |
2324 | debugf0(" TOP_MEM2: 0x%016llx\n", pvt->top_mem2); | |
0ec449ee DT |
2325 | } else |
2326 | debugf0(" TOP_MEM2 disabled.\n"); | |
2327 | ||
2328 | amd64_cpu_display_info(pvt); | |
2329 | ||
6ba5dcdc | 2330 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCAP, &pvt->nbcap); |
0ec449ee DT |
2331 | |
2332 | if (pvt->ops->read_dram_ctl_register) | |
2333 | pvt->ops->read_dram_ctl_register(pvt); | |
2334 | ||
2335 | for (dram = 0; dram < DRAM_REG_COUNT; dram++) { | |
2336 | /* | |
2337 | * Call CPU specific READ function to get the DRAM Base and | |
2338 | * Limit values from the DCT. | |
2339 | */ | |
2340 | pvt->ops->read_dram_base_limit(pvt, dram); | |
2341 | ||
2342 | /* | |
2343 | * Only print out debug info on rows with both R and W Enabled. | |
2344 | * Normal processing, compiler should optimize this whole 'if' | |
2345 | * debug output block away. | |
2346 | */ | |
2347 | if (pvt->dram_rw_en[dram] != 0) { | |
e97f8bb8 BP |
2348 | debugf1(" DRAM-BASE[%d]: 0x%016llx " |
2349 | "DRAM-LIMIT: 0x%016llx\n", | |
0ec449ee | 2350 | dram, |
e97f8bb8 BP |
2351 | pvt->dram_base[dram], |
2352 | pvt->dram_limit[dram]); | |
2353 | ||
0ec449ee DT |
2354 | debugf1(" IntlvEn=%s %s %s " |
2355 | "IntlvSel=%d DstNode=%d\n", | |
2356 | pvt->dram_IntlvEn[dram] ? | |
2357 | "Enabled" : "Disabled", | |
2358 | (pvt->dram_rw_en[dram] & 0x2) ? "W" : "!W", | |
2359 | (pvt->dram_rw_en[dram] & 0x1) ? "R" : "!R", | |
2360 | pvt->dram_IntlvSel[dram], | |
2361 | pvt->dram_DstNode[dram]); | |
2362 | } | |
2363 | } | |
2364 | ||
2365 | amd64_read_dct_base_mask(pvt); | |
2366 | ||
6ba5dcdc | 2367 | amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DHAR, &pvt->dhar); |
0ec449ee DT |
2368 | amd64_read_dbam_reg(pvt); |
2369 | ||
6ba5dcdc BP |
2370 | amd64_read_pci_cfg(pvt->misc_f3_ctl, |
2371 | F10_ONLINE_SPARE, &pvt->online_spare); | |
0ec449ee | 2372 | |
6ba5dcdc BP |
2373 | amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); |
2374 | amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_0, &pvt->dchr0); | |
0ec449ee DT |
2375 | |
2376 | if (!dct_ganging_enabled(pvt)) { | |
6ba5dcdc BP |
2377 | amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1); |
2378 | amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_1, &pvt->dchr1); | |
0ec449ee | 2379 | } |
0ec449ee | 2380 | amd64_dump_misc_regs(pvt); |
0ec449ee DT |
2381 | } |
2382 | ||
2383 | /* | |
2384 | * NOTE: CPU Revision Dependent code | |
2385 | * | |
2386 | * Input: | |
9d858bb1 | 2387 | * @csrow_nr ChipSelect Row Number (0..pvt->cs_count-1) |
0ec449ee DT |
2388 | * k8 private pointer to --> |
2389 | * DRAM Bank Address mapping register | |
2390 | * node_id | |
2391 | * DCL register where dual_channel_active is | |
2392 | * | |
2393 | * The DBAM register consists of 4 sets of 4 bits each definitions: | |
2394 | * | |
2395 | * Bits: CSROWs | |
2396 | * 0-3 CSROWs 0 and 1 | |
2397 | * 4-7 CSROWs 2 and 3 | |
2398 | * 8-11 CSROWs 4 and 5 | |
2399 | * 12-15 CSROWs 6 and 7 | |
2400 | * | |
2401 | * Values range from: 0 to 15 | |
2402 | * The meaning of the values depends on CPU revision and dual-channel state, | |
2403 | * see relevant BKDG more info. | |
2404 | * | |
2405 | * The memory controller provides for total of only 8 CSROWs in its current | |
2406 | * architecture. Each "pair" of CSROWs normally represents just one DIMM in | |
2407 | * single channel or two (2) DIMMs in dual channel mode. | |
2408 | * | |
2409 | * The following code logic collapses the various tables for CSROW based on CPU | |
2410 | * revision. | |
2411 | * | |
2412 | * Returns: | |
2413 | * The number of PAGE_SIZE pages on the specified CSROW number it | |
2414 | * encompasses | |
2415 | * | |
2416 | */ | |
2417 | static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt) | |
2418 | { | |
1433eb99 | 2419 | u32 cs_mode, nr_pages; |
0ec449ee DT |
2420 | |
2421 | /* | |
2422 | * The math on this doesn't look right on the surface because x/2*4 can | |
2423 | * be simplified to x*2 but this expression makes use of the fact that | |
2424 | * it is integral math where 1/2=0. This intermediate value becomes the | |
2425 | * number of bits to shift the DBAM register to extract the proper CSROW | |
2426 | * field. | |
2427 | */ | |
1433eb99 | 2428 | cs_mode = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF; |
0ec449ee | 2429 | |
1433eb99 | 2430 | nr_pages = pvt->ops->dbam_to_cs(pvt, cs_mode) << (20 - PAGE_SHIFT); |
0ec449ee DT |
2431 | |
2432 | /* | |
2433 | * If dual channel then double the memory size of single channel. | |
2434 | * Channel count is 1 or 2 | |
2435 | */ | |
2436 | nr_pages <<= (pvt->channel_count - 1); | |
2437 | ||
1433eb99 | 2438 | debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode); |
0ec449ee DT |
2439 | debugf0(" nr_pages= %u channel-count = %d\n", |
2440 | nr_pages, pvt->channel_count); | |
2441 | ||
2442 | return nr_pages; | |
2443 | } | |
2444 | ||
2445 | /* | |
2446 | * Initialize the array of csrow attribute instances, based on the values | |
2447 | * from pci config hardware registers. | |
2448 | */ | |
2449 | static int amd64_init_csrows(struct mem_ctl_info *mci) | |
2450 | { | |
2451 | struct csrow_info *csrow; | |
2452 | struct amd64_pvt *pvt; | |
2453 | u64 input_addr_min, input_addr_max, sys_addr; | |
6ba5dcdc | 2454 | int i, empty = 1; |
0ec449ee DT |
2455 | |
2456 | pvt = mci->pvt_info; | |
2457 | ||
6ba5dcdc | 2458 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &pvt->nbcfg); |
0ec449ee DT |
2459 | |
2460 | debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt->nbcfg, | |
2461 | (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", | |
2462 | (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled" | |
2463 | ); | |
2464 | ||
9d858bb1 | 2465 | for (i = 0; i < pvt->cs_count; i++) { |
0ec449ee DT |
2466 | csrow = &mci->csrows[i]; |
2467 | ||
2468 | if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) { | |
2469 | debugf1("----CSROW %d EMPTY for node %d\n", i, | |
2470 | pvt->mc_node_id); | |
2471 | continue; | |
2472 | } | |
2473 | ||
2474 | debugf1("----CSROW %d VALID for MC node %d\n", | |
2475 | i, pvt->mc_node_id); | |
2476 | ||
2477 | empty = 0; | |
2478 | csrow->nr_pages = amd64_csrow_nr_pages(i, pvt); | |
2479 | find_csrow_limits(mci, i, &input_addr_min, &input_addr_max); | |
2480 | sys_addr = input_addr_to_sys_addr(mci, input_addr_min); | |
2481 | csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT); | |
2482 | sys_addr = input_addr_to_sys_addr(mci, input_addr_max); | |
2483 | csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT); | |
2484 | csrow->page_mask = ~mask_from_dct_mask(pvt, i); | |
2485 | /* 8 bytes of resolution */ | |
2486 | ||
2487 | csrow->mtype = amd64_determine_memory_type(pvt); | |
2488 | ||
2489 | debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i); | |
2490 | debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n", | |
2491 | (unsigned long)input_addr_min, | |
2492 | (unsigned long)input_addr_max); | |
2493 | debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n", | |
2494 | (unsigned long)sys_addr, csrow->page_mask); | |
2495 | debugf1(" nr_pages: %u first_page: 0x%lx " | |
2496 | "last_page: 0x%lx\n", | |
2497 | (unsigned)csrow->nr_pages, | |
2498 | csrow->first_page, csrow->last_page); | |
2499 | ||
2500 | /* | |
2501 | * determine whether CHIPKILL or JUST ECC or NO ECC is operating | |
2502 | */ | |
2503 | if (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) | |
2504 | csrow->edac_mode = | |
2505 | (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? | |
2506 | EDAC_S4ECD4ED : EDAC_SECDED; | |
2507 | else | |
2508 | csrow->edac_mode = EDAC_NONE; | |
2509 | } | |
2510 | ||
2511 | return empty; | |
2512 | } | |
d27bf6fa | 2513 | |
f6d6ae96 BP |
2514 | /* get all cores on this DCT */ |
2515 | static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid) | |
2516 | { | |
2517 | int cpu; | |
2518 | ||
2519 | for_each_online_cpu(cpu) | |
2520 | if (amd_get_nb_id(cpu) == nid) | |
2521 | cpumask_set_cpu(cpu, mask); | |
2522 | } | |
2523 | ||
2524 | /* check MCG_CTL on all the cpus on this node */ | |
2525 | static bool amd64_nb_mce_bank_enabled_on_node(int nid) | |
2526 | { | |
2527 | cpumask_var_t mask; | |
2528 | struct msr *msrs; | |
2529 | int cpu, nbe, idx = 0; | |
2530 | bool ret = false; | |
2531 | ||
2532 | if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { | |
2533 | amd64_printk(KERN_WARNING, "%s: error allocating mask\n", | |
2534 | __func__); | |
2535 | return false; | |
2536 | } | |
2537 | ||
2538 | get_cpus_on_this_dct_cpumask(mask, nid); | |
2539 | ||
2540 | msrs = kzalloc(sizeof(struct msr) * cpumask_weight(mask), GFP_KERNEL); | |
2541 | if (!msrs) { | |
2542 | amd64_printk(KERN_WARNING, "%s: error allocating msrs\n", | |
2543 | __func__); | |
2544 | free_cpumask_var(mask); | |
2545 | return false; | |
2546 | } | |
2547 | ||
2548 | rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs); | |
2549 | ||
2550 | for_each_cpu(cpu, mask) { | |
2551 | nbe = msrs[idx].l & K8_MSR_MCGCTL_NBE; | |
2552 | ||
2553 | debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", | |
2554 | cpu, msrs[idx].q, | |
2555 | (nbe ? "enabled" : "disabled")); | |
2556 | ||
2557 | if (!nbe) | |
2558 | goto out; | |
2559 | ||
2560 | idx++; | |
2561 | } | |
2562 | ret = true; | |
2563 | ||
2564 | out: | |
2565 | kfree(msrs); | |
2566 | free_cpumask_var(mask); | |
2567 | return ret; | |
2568 | } | |
2569 | ||
2570 | static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on) | |
2571 | { | |
2572 | cpumask_var_t cmask; | |
2573 | struct msr *msrs = NULL; | |
2574 | int cpu, idx = 0; | |
2575 | ||
2576 | if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) { | |
2577 | amd64_printk(KERN_WARNING, "%s: error allocating mask\n", | |
2578 | __func__); | |
2579 | return false; | |
2580 | } | |
2581 | ||
2582 | get_cpus_on_this_dct_cpumask(cmask, pvt->mc_node_id); | |
2583 | ||
2584 | msrs = kzalloc(sizeof(struct msr) * cpumask_weight(cmask), GFP_KERNEL); | |
2585 | if (!msrs) { | |
2586 | amd64_printk(KERN_WARNING, "%s: error allocating msrs\n", | |
2587 | __func__); | |
2588 | return -ENOMEM; | |
2589 | } | |
2590 | ||
2591 | rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); | |
2592 | ||
2593 | for_each_cpu(cpu, cmask) { | |
2594 | ||
2595 | if (on) { | |
2596 | if (msrs[idx].l & K8_MSR_MCGCTL_NBE) | |
2597 | pvt->flags.ecc_report = 1; | |
2598 | ||
2599 | msrs[idx].l |= K8_MSR_MCGCTL_NBE; | |
2600 | } else { | |
2601 | /* | |
2602 | * Turn off ECC reporting only when it was off before | |
2603 | */ | |
2604 | if (!pvt->flags.ecc_report) | |
2605 | msrs[idx].l &= ~K8_MSR_MCGCTL_NBE; | |
2606 | } | |
2607 | idx++; | |
2608 | } | |
2609 | wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); | |
2610 | ||
2611 | kfree(msrs); | |
2612 | free_cpumask_var(cmask); | |
2613 | ||
2614 | return 0; | |
2615 | } | |
2616 | ||
f9431992 DT |
2617 | /* |
2618 | * Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we" | |
2619 | * enable it. | |
2620 | */ | |
2621 | static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci) | |
2622 | { | |
2623 | struct amd64_pvt *pvt = mci->pvt_info; | |
f6d6ae96 | 2624 | u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; |
f9431992 DT |
2625 | |
2626 | if (!ecc_enable_override) | |
2627 | return; | |
2628 | ||
f9431992 DT |
2629 | amd64_printk(KERN_WARNING, |
2630 | "'ecc_enable_override' parameter is active, " | |
2631 | "Enabling AMD ECC hardware now: CAUTION\n"); | |
2632 | ||
6ba5dcdc | 2633 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCTL, &value); |
f9431992 DT |
2634 | |
2635 | /* turn on UECCn and CECCEn bits */ | |
2636 | pvt->old_nbctl = value & mask; | |
2637 | pvt->nbctl_mcgctl_saved = 1; | |
2638 | ||
2639 | value |= mask; | |
2640 | pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value); | |
2641 | ||
f6d6ae96 BP |
2642 | if (amd64_toggle_ecc_err_reporting(pvt, ON)) |
2643 | amd64_printk(KERN_WARNING, "Error enabling ECC reporting over " | |
2644 | "MCGCTL!\n"); | |
f9431992 | 2645 | |
6ba5dcdc | 2646 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value); |
f9431992 DT |
2647 | |
2648 | debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value, | |
2649 | (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", | |
2650 | (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"); | |
2651 | ||
2652 | if (!(value & K8_NBCFG_ECC_ENABLE)) { | |
2653 | amd64_printk(KERN_WARNING, | |
2654 | "This node reports that DRAM ECC is " | |
2655 | "currently Disabled; ENABLING now\n"); | |
2656 | ||
2657 | /* Attempt to turn on DRAM ECC Enable */ | |
2658 | value |= K8_NBCFG_ECC_ENABLE; | |
2659 | pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value); | |
2660 | ||
6ba5dcdc | 2661 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value); |
f9431992 DT |
2662 | |
2663 | if (!(value & K8_NBCFG_ECC_ENABLE)) { | |
2664 | amd64_printk(KERN_WARNING, | |
2665 | "Hardware rejects Enabling DRAM ECC checking\n" | |
2666 | "Check memory DIMM configuration\n"); | |
2667 | } else { | |
2668 | amd64_printk(KERN_DEBUG, | |
2669 | "Hardware accepted DRAM ECC Enable\n"); | |
2670 | } | |
2671 | } | |
2672 | debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value, | |
2673 | (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", | |
2674 | (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"); | |
2675 | ||
2676 | pvt->ctl_error_info.nbcfg = value; | |
2677 | } | |
2678 | ||
2679 | static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt) | |
2680 | { | |
f6d6ae96 | 2681 | u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; |
f9431992 DT |
2682 | |
2683 | if (!pvt->nbctl_mcgctl_saved) | |
2684 | return; | |
2685 | ||
6ba5dcdc | 2686 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCTL, &value); |
f9431992 DT |
2687 | value &= ~mask; |
2688 | value |= pvt->old_nbctl; | |
2689 | ||
2690 | /* restore the NB Enable MCGCTL bit */ | |
2691 | pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value); | |
2692 | ||
f6d6ae96 BP |
2693 | if (amd64_toggle_ecc_err_reporting(pvt, OFF)) |
2694 | amd64_printk(KERN_WARNING, "Error restoring ECC reporting over " | |
2695 | "MCGCTL!\n"); | |
f9431992 DT |
2696 | } |
2697 | ||
2698 | /* | |
2699 | * EDAC requires that the BIOS have ECC enabled before taking over the | |
2700 | * processing of ECC errors. This is because the BIOS can properly initialize | |
2701 | * the memory system completely. A command line option allows to force-enable | |
2702 | * hardware ECC later in amd64_enable_ecc_error_reporting(). | |
2703 | */ | |
be3468e8 BP |
2704 | static const char *ecc_warning = |
2705 | "WARNING: ECC is disabled by BIOS. Module will NOT be loaded.\n" | |
2706 | " Either Enable ECC in the BIOS, or set 'ecc_enable_override'.\n" | |
2707 | " Also, use of the override can cause unknown side effects.\n"; | |
2708 | ||
f9431992 DT |
2709 | static int amd64_check_ecc_enabled(struct amd64_pvt *pvt) |
2710 | { | |
2711 | u32 value; | |
06724535 BP |
2712 | u8 ecc_enabled = 0; |
2713 | bool nb_mce_en = false; | |
f9431992 | 2714 | |
6ba5dcdc | 2715 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value); |
f9431992 DT |
2716 | |
2717 | ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE); | |
be3468e8 BP |
2718 | if (!ecc_enabled) |
2719 | amd64_printk(KERN_WARNING, "This node reports that Memory ECC " | |
2720 | "is currently disabled, set F3x%x[22] (%s).\n", | |
2721 | K8_NBCFG, pci_name(pvt->misc_f3_ctl)); | |
2722 | else | |
2723 | amd64_printk(KERN_INFO, "ECC is enabled by BIOS.\n"); | |
f9431992 | 2724 | |
06724535 BP |
2725 | nb_mce_en = amd64_nb_mce_bank_enabled_on_node(pvt->mc_node_id); |
2726 | if (!nb_mce_en) | |
be3468e8 BP |
2727 | amd64_printk(KERN_WARNING, "NB MCE bank disabled, set MSR " |
2728 | "0x%08x[4] on node %d to enable.\n", | |
2729 | MSR_IA32_MCG_CTL, pvt->mc_node_id); | |
f9431992 | 2730 | |
06724535 | 2731 | if (!ecc_enabled || !nb_mce_en) { |
f9431992 | 2732 | if (!ecc_enable_override) { |
be3468e8 BP |
2733 | amd64_printk(KERN_WARNING, "%s", ecc_warning); |
2734 | return -ENODEV; | |
2735 | } | |
2736 | } else | |
f9431992 DT |
2737 | /* CLEAR the override, since BIOS controlled it */ |
2738 | ecc_enable_override = 0; | |
f9431992 | 2739 | |
be3468e8 | 2740 | return 0; |
f9431992 DT |
2741 | } |
2742 | ||
7d6034d3 DT |
2743 | struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) + |
2744 | ARRAY_SIZE(amd64_inj_attrs) + | |
2745 | 1]; | |
2746 | ||
2747 | struct mcidev_sysfs_attribute terminator = { .attr = { .name = NULL } }; | |
2748 | ||
2749 | static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info *mci) | |
2750 | { | |
2751 | unsigned int i = 0, j = 0; | |
2752 | ||
2753 | for (; i < ARRAY_SIZE(amd64_dbg_attrs); i++) | |
2754 | sysfs_attrs[i] = amd64_dbg_attrs[i]; | |
2755 | ||
2756 | for (j = 0; j < ARRAY_SIZE(amd64_inj_attrs); j++, i++) | |
2757 | sysfs_attrs[i] = amd64_inj_attrs[j]; | |
2758 | ||
2759 | sysfs_attrs[i] = terminator; | |
2760 | ||
2761 | mci->mc_driver_sysfs_attributes = sysfs_attrs; | |
2762 | } | |
2763 | ||
2764 | static void amd64_setup_mci_misc_attributes(struct mem_ctl_info *mci) | |
2765 | { | |
2766 | struct amd64_pvt *pvt = mci->pvt_info; | |
2767 | ||
2768 | mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; | |
2769 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
7d6034d3 DT |
2770 | |
2771 | if (pvt->nbcap & K8_NBCAP_SECDED) | |
2772 | mci->edac_ctl_cap |= EDAC_FLAG_SECDED; | |
2773 | ||
2774 | if (pvt->nbcap & K8_NBCAP_CHIPKILL) | |
2775 | mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; | |
2776 | ||
2777 | mci->edac_cap = amd64_determine_edac_cap(pvt); | |
2778 | mci->mod_name = EDAC_MOD_STR; | |
2779 | mci->mod_ver = EDAC_AMD64_VERSION; | |
2780 | mci->ctl_name = get_amd_family_name(pvt->mc_type_index); | |
2781 | mci->dev_name = pci_name(pvt->dram_f2_ctl); | |
2782 | mci->ctl_page_to_phys = NULL; | |
2783 | ||
2784 | /* IMPORTANT: Set the polling 'check' function in this module */ | |
2785 | mci->edac_check = amd64_check; | |
2786 | ||
2787 | /* memory scrubber interface */ | |
2788 | mci->set_sdram_scrub_rate = amd64_set_scrub_rate; | |
2789 | mci->get_sdram_scrub_rate = amd64_get_scrub_rate; | |
2790 | } | |
2791 | ||
2792 | /* | |
2793 | * Init stuff for this DRAM Controller device. | |
2794 | * | |
2795 | * Due to a hardware feature on Fam10h CPUs, the Enable Extended Configuration | |
2796 | * Space feature MUST be enabled on ALL Processors prior to actually reading | |
2797 | * from the ECS registers. Since the loading of the module can occur on any | |
2798 | * 'core', and cores don't 'see' all the other processors ECS data when the | |
2799 | * others are NOT enabled. Our solution is to first enable ECS access in this | |
2800 | * routine on all processors, gather some data in a amd64_pvt structure and | |
2801 | * later come back in a finish-setup function to perform that final | |
2802 | * initialization. See also amd64_init_2nd_stage() for that. | |
2803 | */ | |
2804 | static int amd64_probe_one_instance(struct pci_dev *dram_f2_ctl, | |
2805 | int mc_type_index) | |
2806 | { | |
2807 | struct amd64_pvt *pvt = NULL; | |
2808 | int err = 0, ret; | |
2809 | ||
2810 | ret = -ENOMEM; | |
2811 | pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); | |
2812 | if (!pvt) | |
2813 | goto err_exit; | |
2814 | ||
37da0450 | 2815 | pvt->mc_node_id = get_node_id(dram_f2_ctl); |
7d6034d3 DT |
2816 | |
2817 | pvt->dram_f2_ctl = dram_f2_ctl; | |
2818 | pvt->ext_model = boot_cpu_data.x86_model >> 4; | |
2819 | pvt->mc_type_index = mc_type_index; | |
2820 | pvt->ops = family_ops(mc_type_index); | |
7d6034d3 DT |
2821 | |
2822 | /* | |
2823 | * We have the dram_f2_ctl device as an argument, now go reserve its | |
2824 | * sibling devices from the PCI system. | |
2825 | */ | |
2826 | ret = -ENODEV; | |
2827 | err = amd64_reserve_mc_sibling_devices(pvt, mc_type_index); | |
2828 | if (err) | |
2829 | goto err_free; | |
2830 | ||
2831 | ret = -EINVAL; | |
2832 | err = amd64_check_ecc_enabled(pvt); | |
2833 | if (err) | |
2834 | goto err_put; | |
2835 | ||
2836 | /* | |
2837 | * Key operation here: setup of HW prior to performing ops on it. Some | |
2838 | * setup is required to access ECS data. After this is performed, the | |
2839 | * 'teardown' function must be called upon error and normal exit paths. | |
2840 | */ | |
2841 | if (boot_cpu_data.x86 >= 0x10) | |
2842 | amd64_setup(pvt); | |
2843 | ||
2844 | /* | |
2845 | * Save the pointer to the private data for use in 2nd initialization | |
2846 | * stage | |
2847 | */ | |
2848 | pvt_lookup[pvt->mc_node_id] = pvt; | |
2849 | ||
2850 | return 0; | |
2851 | ||
2852 | err_put: | |
2853 | amd64_free_mc_sibling_devices(pvt); | |
2854 | ||
2855 | err_free: | |
2856 | kfree(pvt); | |
2857 | ||
2858 | err_exit: | |
2859 | return ret; | |
2860 | } | |
2861 | ||
2862 | /* | |
2863 | * This is the finishing stage of the init code. Needs to be performed after all | |
2864 | * MCs' hardware have been prepped for accessing extended config space. | |
2865 | */ | |
2866 | static int amd64_init_2nd_stage(struct amd64_pvt *pvt) | |
2867 | { | |
2868 | int node_id = pvt->mc_node_id; | |
2869 | struct mem_ctl_info *mci; | |
2870 | int ret, err = 0; | |
2871 | ||
2872 | amd64_read_mc_registers(pvt); | |
2873 | ||
2874 | ret = -ENODEV; | |
2875 | if (pvt->ops->probe_valid_hardware) { | |
2876 | err = pvt->ops->probe_valid_hardware(pvt); | |
2877 | if (err) | |
2878 | goto err_exit; | |
2879 | } | |
2880 | ||
2881 | /* | |
2882 | * We need to determine how many memory channels there are. Then use | |
2883 | * that information for calculating the size of the dynamic instance | |
2884 | * tables in the 'mci' structure | |
2885 | */ | |
2886 | pvt->channel_count = pvt->ops->early_channel_count(pvt); | |
2887 | if (pvt->channel_count < 0) | |
2888 | goto err_exit; | |
2889 | ||
2890 | ret = -ENOMEM; | |
9d858bb1 | 2891 | mci = edac_mc_alloc(0, pvt->cs_count, pvt->channel_count, node_id); |
7d6034d3 DT |
2892 | if (!mci) |
2893 | goto err_exit; | |
2894 | ||
2895 | mci->pvt_info = pvt; | |
2896 | ||
2897 | mci->dev = &pvt->dram_f2_ctl->dev; | |
2898 | amd64_setup_mci_misc_attributes(mci); | |
2899 | ||
2900 | if (amd64_init_csrows(mci)) | |
2901 | mci->edac_cap = EDAC_FLAG_NONE; | |
2902 | ||
2903 | amd64_enable_ecc_error_reporting(mci); | |
2904 | amd64_set_mc_sysfs_attributes(mci); | |
2905 | ||
2906 | ret = -ENODEV; | |
2907 | if (edac_mc_add_mc(mci)) { | |
2908 | debugf1("failed edac_mc_add_mc()\n"); | |
2909 | goto err_add_mc; | |
2910 | } | |
2911 | ||
2912 | mci_lookup[node_id] = mci; | |
2913 | pvt_lookup[node_id] = NULL; | |
549d042d BP |
2914 | |
2915 | /* register stuff with EDAC MCE */ | |
2916 | if (report_gart_errors) | |
2917 | amd_report_gart_errors(true); | |
2918 | ||
2919 | amd_register_ecc_decoder(amd64_decode_bus_error); | |
2920 | ||
7d6034d3 DT |
2921 | return 0; |
2922 | ||
2923 | err_add_mc: | |
2924 | edac_mc_free(mci); | |
2925 | ||
2926 | err_exit: | |
2927 | debugf0("failure to init 2nd stage: ret=%d\n", ret); | |
2928 | ||
2929 | amd64_restore_ecc_error_reporting(pvt); | |
2930 | ||
2931 | if (boot_cpu_data.x86 > 0xf) | |
2932 | amd64_teardown(pvt); | |
2933 | ||
2934 | amd64_free_mc_sibling_devices(pvt); | |
2935 | ||
2936 | kfree(pvt_lookup[pvt->mc_node_id]); | |
2937 | pvt_lookup[node_id] = NULL; | |
2938 | ||
2939 | return ret; | |
2940 | } | |
2941 | ||
2942 | ||
2943 | static int __devinit amd64_init_one_instance(struct pci_dev *pdev, | |
2944 | const struct pci_device_id *mc_type) | |
2945 | { | |
2946 | int ret = 0; | |
2947 | ||
37da0450 | 2948 | debugf0("(MC node=%d,mc_type='%s')\n", get_node_id(pdev), |
7d6034d3 DT |
2949 | get_amd_family_name(mc_type->driver_data)); |
2950 | ||
2951 | ret = pci_enable_device(pdev); | |
2952 | if (ret < 0) | |
2953 | ret = -EIO; | |
2954 | else | |
2955 | ret = amd64_probe_one_instance(pdev, mc_type->driver_data); | |
2956 | ||
2957 | if (ret < 0) | |
2958 | debugf0("ret=%d\n", ret); | |
2959 | ||
2960 | return ret; | |
2961 | } | |
2962 | ||
2963 | static void __devexit amd64_remove_one_instance(struct pci_dev *pdev) | |
2964 | { | |
2965 | struct mem_ctl_info *mci; | |
2966 | struct amd64_pvt *pvt; | |
2967 | ||
2968 | /* Remove from EDAC CORE tracking list */ | |
2969 | mci = edac_mc_del_mc(&pdev->dev); | |
2970 | if (!mci) | |
2971 | return; | |
2972 | ||
2973 | pvt = mci->pvt_info; | |
2974 | ||
2975 | amd64_restore_ecc_error_reporting(pvt); | |
2976 | ||
2977 | if (boot_cpu_data.x86 > 0xf) | |
2978 | amd64_teardown(pvt); | |
2979 | ||
2980 | amd64_free_mc_sibling_devices(pvt); | |
2981 | ||
2982 | kfree(pvt); | |
2983 | mci->pvt_info = NULL; | |
2984 | ||
2985 | mci_lookup[pvt->mc_node_id] = NULL; | |
2986 | ||
549d042d BP |
2987 | /* unregister from EDAC MCE */ |
2988 | amd_report_gart_errors(false); | |
2989 | amd_unregister_ecc_decoder(amd64_decode_bus_error); | |
2990 | ||
7d6034d3 DT |
2991 | /* Free the EDAC CORE resources */ |
2992 | edac_mc_free(mci); | |
2993 | } | |
2994 | ||
2995 | /* | |
2996 | * This table is part of the interface for loading drivers for PCI devices. The | |
2997 | * PCI core identifies what devices are on a system during boot, and then | |
2998 | * inquiry this table to see if this driver is for a given device found. | |
2999 | */ | |
3000 | static const struct pci_device_id amd64_pci_table[] __devinitdata = { | |
3001 | { | |
3002 | .vendor = PCI_VENDOR_ID_AMD, | |
3003 | .device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL, | |
3004 | .subvendor = PCI_ANY_ID, | |
3005 | .subdevice = PCI_ANY_ID, | |
3006 | .class = 0, | |
3007 | .class_mask = 0, | |
3008 | .driver_data = K8_CPUS | |
3009 | }, | |
3010 | { | |
3011 | .vendor = PCI_VENDOR_ID_AMD, | |
3012 | .device = PCI_DEVICE_ID_AMD_10H_NB_DRAM, | |
3013 | .subvendor = PCI_ANY_ID, | |
3014 | .subdevice = PCI_ANY_ID, | |
3015 | .class = 0, | |
3016 | .class_mask = 0, | |
3017 | .driver_data = F10_CPUS | |
3018 | }, | |
3019 | { | |
3020 | .vendor = PCI_VENDOR_ID_AMD, | |
3021 | .device = PCI_DEVICE_ID_AMD_11H_NB_DRAM, | |
3022 | .subvendor = PCI_ANY_ID, | |
3023 | .subdevice = PCI_ANY_ID, | |
3024 | .class = 0, | |
3025 | .class_mask = 0, | |
3026 | .driver_data = F11_CPUS | |
3027 | }, | |
3028 | {0, } | |
3029 | }; | |
3030 | MODULE_DEVICE_TABLE(pci, amd64_pci_table); | |
3031 | ||
3032 | static struct pci_driver amd64_pci_driver = { | |
3033 | .name = EDAC_MOD_STR, | |
3034 | .probe = amd64_init_one_instance, | |
3035 | .remove = __devexit_p(amd64_remove_one_instance), | |
3036 | .id_table = amd64_pci_table, | |
3037 | }; | |
3038 | ||
3039 | static void amd64_setup_pci_device(void) | |
3040 | { | |
3041 | struct mem_ctl_info *mci; | |
3042 | struct amd64_pvt *pvt; | |
3043 | ||
3044 | if (amd64_ctl_pci) | |
3045 | return; | |
3046 | ||
3047 | mci = mci_lookup[0]; | |
3048 | if (mci) { | |
3049 | ||
3050 | pvt = mci->pvt_info; | |
3051 | amd64_ctl_pci = | |
3052 | edac_pci_create_generic_ctl(&pvt->dram_f2_ctl->dev, | |
3053 | EDAC_MOD_STR); | |
3054 | ||
3055 | if (!amd64_ctl_pci) { | |
3056 | pr_warning("%s(): Unable to create PCI control\n", | |
3057 | __func__); | |
3058 | ||
3059 | pr_warning("%s(): PCI error report via EDAC not set\n", | |
3060 | __func__); | |
3061 | } | |
3062 | } | |
3063 | } | |
3064 | ||
3065 | static int __init amd64_edac_init(void) | |
3066 | { | |
3067 | int nb, err = -ENODEV; | |
3068 | ||
3069 | edac_printk(KERN_INFO, EDAC_MOD_STR, EDAC_AMD64_VERSION "\n"); | |
3070 | ||
3071 | opstate_init(); | |
3072 | ||
3073 | if (cache_k8_northbridges() < 0) | |
a3c4c580 | 3074 | return err; |
7d6034d3 DT |
3075 | |
3076 | err = pci_register_driver(&amd64_pci_driver); | |
3077 | if (err) | |
3078 | return err; | |
3079 | ||
3080 | /* | |
3081 | * At this point, the array 'pvt_lookup[]' contains pointers to alloc'd | |
3082 | * amd64_pvt structs. These will be used in the 2nd stage init function | |
3083 | * to finish initialization of the MC instances. | |
3084 | */ | |
3085 | for (nb = 0; nb < num_k8_northbridges; nb++) { | |
3086 | if (!pvt_lookup[nb]) | |
3087 | continue; | |
3088 | ||
3089 | err = amd64_init_2nd_stage(pvt_lookup[nb]); | |
3090 | if (err) | |
37da0450 | 3091 | goto err_2nd_stage; |
7d6034d3 DT |
3092 | } |
3093 | ||
3094 | amd64_setup_pci_device(); | |
3095 | ||
3096 | return 0; | |
3097 | ||
37da0450 BP |
3098 | err_2nd_stage: |
3099 | debugf0("2nd stage failed\n"); | |
7d6034d3 DT |
3100 | pci_unregister_driver(&amd64_pci_driver); |
3101 | ||
3102 | return err; | |
3103 | } | |
3104 | ||
3105 | static void __exit amd64_edac_exit(void) | |
3106 | { | |
3107 | if (amd64_ctl_pci) | |
3108 | edac_pci_release_generic_ctl(amd64_ctl_pci); | |
3109 | ||
3110 | pci_unregister_driver(&amd64_pci_driver); | |
3111 | } | |
3112 | ||
3113 | module_init(amd64_edac_init); | |
3114 | module_exit(amd64_edac_exit); | |
3115 | ||
3116 | MODULE_LICENSE("GPL"); | |
3117 | MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, " | |
3118 | "Dave Peterson, Thayne Harbaugh"); | |
3119 | MODULE_DESCRIPTION("MC support for AMD64 memory controllers - " | |
3120 | EDAC_AMD64_VERSION); | |
3121 | ||
3122 | module_param(edac_op_state, int, 0444); | |
3123 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |