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Commit | Line | Data |
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2bc65418 | 1 | #include "amd64_edac.h" |
23ac4ae8 | 2 | #include <asm/amd_nb.h> |
2bc65418 DT |
3 | |
4 | static struct edac_pci_ctl_info *amd64_ctl_pci; | |
5 | ||
6 | static int report_gart_errors; | |
7 | module_param(report_gart_errors, int, 0644); | |
8 | ||
9 | /* | |
10 | * Set by command line parameter. If BIOS has enabled the ECC, this override is | |
11 | * cleared to prevent re-enabling the hardware by this driver. | |
12 | */ | |
13 | static int ecc_enable_override; | |
14 | module_param(ecc_enable_override, int, 0644); | |
15 | ||
a29d8b8e | 16 | static struct msr __percpu *msrs; |
50542251 | 17 | |
360b7f3c BP |
18 | /* |
19 | * count successfully initialized driver instances for setup_pci_device() | |
20 | */ | |
21 | static atomic_t drv_instances = ATOMIC_INIT(0); | |
22 | ||
cc4d8860 BP |
23 | /* Per-node driver instances */ |
24 | static struct mem_ctl_info **mcis; | |
ae7bb7c6 | 25 | static struct ecc_settings **ecc_stngs; |
2bc65418 | 26 | |
b70ef010 BP |
27 | /* |
28 | * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing | |
29 | * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching- | |
30 | * or higher value'. | |
31 | * | |
32 | *FIXME: Produce a better mapping/linearisation. | |
33 | */ | |
39094443 BP |
34 | struct scrubrate { |
35 | u32 scrubval; /* bit pattern for scrub rate */ | |
36 | u32 bandwidth; /* bandwidth consumed (bytes/sec) */ | |
37 | } scrubrates[] = { | |
b70ef010 BP |
38 | { 0x01, 1600000000UL}, |
39 | { 0x02, 800000000UL}, | |
40 | { 0x03, 400000000UL}, | |
41 | { 0x04, 200000000UL}, | |
42 | { 0x05, 100000000UL}, | |
43 | { 0x06, 50000000UL}, | |
44 | { 0x07, 25000000UL}, | |
45 | { 0x08, 12284069UL}, | |
46 | { 0x09, 6274509UL}, | |
47 | { 0x0A, 3121951UL}, | |
48 | { 0x0B, 1560975UL}, | |
49 | { 0x0C, 781440UL}, | |
50 | { 0x0D, 390720UL}, | |
51 | { 0x0E, 195300UL}, | |
52 | { 0x0F, 97650UL}, | |
53 | { 0x10, 48854UL}, | |
54 | { 0x11, 24427UL}, | |
55 | { 0x12, 12213UL}, | |
56 | { 0x13, 6101UL}, | |
57 | { 0x14, 3051UL}, | |
58 | { 0x15, 1523UL}, | |
59 | { 0x16, 761UL}, | |
60 | { 0x00, 0UL}, /* scrubbing off */ | |
61 | }; | |
62 | ||
b2b0c605 BP |
63 | static int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, |
64 | u32 *val, const char *func) | |
65 | { | |
66 | int err = 0; | |
67 | ||
68 | err = pci_read_config_dword(pdev, offset, val); | |
69 | if (err) | |
70 | amd64_warn("%s: error reading F%dx%03x.\n", | |
71 | func, PCI_FUNC(pdev->devfn), offset); | |
72 | ||
73 | return err; | |
74 | } | |
75 | ||
76 | int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, | |
77 | u32 val, const char *func) | |
78 | { | |
79 | int err = 0; | |
80 | ||
81 | err = pci_write_config_dword(pdev, offset, val); | |
82 | if (err) | |
83 | amd64_warn("%s: error writing to F%dx%03x.\n", | |
84 | func, PCI_FUNC(pdev->devfn), offset); | |
85 | ||
86 | return err; | |
87 | } | |
88 | ||
89 | /* | |
90 | * | |
91 | * Depending on the family, F2 DCT reads need special handling: | |
92 | * | |
93 | * K8: has a single DCT only | |
94 | * | |
95 | * F10h: each DCT has its own set of regs | |
96 | * DCT0 -> F2x040.. | |
97 | * DCT1 -> F2x140.. | |
98 | * | |
99 | * F15h: we select which DCT we access using F1x10C[DctCfgSel] | |
100 | * | |
101 | */ | |
102 | static int k8_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val, | |
103 | const char *func) | |
104 | { | |
105 | if (addr >= 0x100) | |
106 | return -EINVAL; | |
107 | ||
108 | return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); | |
109 | } | |
110 | ||
111 | static int f10_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val, | |
112 | const char *func) | |
113 | { | |
114 | return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); | |
115 | } | |
116 | ||
73ba8593 BP |
117 | /* |
118 | * Select DCT to which PCI cfg accesses are routed | |
119 | */ | |
120 | static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) | |
121 | { | |
122 | u32 reg = 0; | |
123 | ||
124 | amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); | |
125 | reg &= 0xfffffffe; | |
126 | reg |= dct; | |
127 | amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); | |
128 | } | |
129 | ||
b2b0c605 BP |
130 | static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val, |
131 | const char *func) | |
132 | { | |
b2b0c605 BP |
133 | u8 dct = 0; |
134 | ||
135 | if (addr >= 0x140 && addr <= 0x1a0) { | |
136 | dct = 1; | |
137 | addr -= 0x100; | |
138 | } | |
139 | ||
73ba8593 | 140 | f15h_select_dct(pvt, dct); |
b2b0c605 BP |
141 | |
142 | return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); | |
143 | } | |
144 | ||
2bc65418 DT |
145 | /* |
146 | * Memory scrubber control interface. For K8, memory scrubbing is handled by | |
147 | * hardware and can involve L2 cache, dcache as well as the main memory. With | |
148 | * F10, this is extended to L3 cache scrubbing on CPU models sporting that | |
149 | * functionality. | |
150 | * | |
151 | * This causes the "units" for the scrubbing speed to vary from 64 byte blocks | |
152 | * (dram) over to cache lines. This is nasty, so we will use bandwidth in | |
153 | * bytes/sec for the setting. | |
154 | * | |
155 | * Currently, we only do dram scrubbing. If the scrubbing is done in software on | |
156 | * other archs, we might not have access to the caches directly. | |
157 | */ | |
158 | ||
159 | /* | |
160 | * scan the scrub rate mapping table for a close or matching bandwidth value to | |
161 | * issue. If requested is too big, then use last maximum value found. | |
162 | */ | |
395ae783 | 163 | static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate) |
2bc65418 DT |
164 | { |
165 | u32 scrubval; | |
166 | int i; | |
167 | ||
168 | /* | |
169 | * map the configured rate (new_bw) to a value specific to the AMD64 | |
170 | * memory controller and apply to register. Search for the first | |
171 | * bandwidth entry that is greater or equal than the setting requested | |
172 | * and program that. If at last entry, turn off DRAM scrubbing. | |
173 | */ | |
174 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { | |
175 | /* | |
176 | * skip scrub rates which aren't recommended | |
177 | * (see F10 BKDG, F3x58) | |
178 | */ | |
395ae783 | 179 | if (scrubrates[i].scrubval < min_rate) |
2bc65418 DT |
180 | continue; |
181 | ||
182 | if (scrubrates[i].bandwidth <= new_bw) | |
183 | break; | |
184 | ||
185 | /* | |
186 | * if no suitable bandwidth found, turn off DRAM scrubbing | |
187 | * entirely by falling back to the last element in the | |
188 | * scrubrates array. | |
189 | */ | |
190 | } | |
191 | ||
192 | scrubval = scrubrates[i].scrubval; | |
2bc65418 | 193 | |
5980bb9c | 194 | pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F); |
2bc65418 | 195 | |
39094443 BP |
196 | if (scrubval) |
197 | return scrubrates[i].bandwidth; | |
198 | ||
2bc65418 DT |
199 | return 0; |
200 | } | |
201 | ||
395ae783 | 202 | static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw) |
2bc65418 DT |
203 | { |
204 | struct amd64_pvt *pvt = mci->pvt_info; | |
87b3e0e6 | 205 | u32 min_scrubrate = 0x5; |
2bc65418 | 206 | |
87b3e0e6 BP |
207 | if (boot_cpu_data.x86 == 0xf) |
208 | min_scrubrate = 0x0; | |
209 | ||
73ba8593 BP |
210 | /* F15h Erratum #505 */ |
211 | if (boot_cpu_data.x86 == 0x15) | |
212 | f15h_select_dct(pvt, 0); | |
213 | ||
87b3e0e6 | 214 | return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate); |
2bc65418 DT |
215 | } |
216 | ||
39094443 | 217 | static int amd64_get_scrub_rate(struct mem_ctl_info *mci) |
2bc65418 DT |
218 | { |
219 | struct amd64_pvt *pvt = mci->pvt_info; | |
220 | u32 scrubval = 0; | |
39094443 | 221 | int i, retval = -EINVAL; |
2bc65418 | 222 | |
73ba8593 BP |
223 | /* F15h Erratum #505 */ |
224 | if (boot_cpu_data.x86 == 0x15) | |
225 | f15h_select_dct(pvt, 0); | |
226 | ||
5980bb9c | 227 | amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); |
2bc65418 DT |
228 | |
229 | scrubval = scrubval & 0x001F; | |
230 | ||
926311fd | 231 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { |
2bc65418 | 232 | if (scrubrates[i].scrubval == scrubval) { |
39094443 | 233 | retval = scrubrates[i].bandwidth; |
2bc65418 DT |
234 | break; |
235 | } | |
236 | } | |
39094443 | 237 | return retval; |
2bc65418 DT |
238 | } |
239 | ||
6775763a | 240 | /* |
7f19bf75 BP |
241 | * returns true if the SysAddr given by sys_addr matches the |
242 | * DRAM base/limit associated with node_id | |
6775763a | 243 | */ |
b487c33e BP |
244 | static bool amd64_base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, |
245 | unsigned nid) | |
6775763a | 246 | { |
7f19bf75 | 247 | u64 addr; |
6775763a DT |
248 | |
249 | /* The K8 treats this as a 40-bit value. However, bits 63-40 will be | |
250 | * all ones if the most significant implemented address bit is 1. | |
251 | * Here we discard bits 63-40. See section 3.4.2 of AMD publication | |
252 | * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 | |
253 | * Application Programming. | |
254 | */ | |
255 | addr = sys_addr & 0x000000ffffffffffull; | |
256 | ||
7f19bf75 BP |
257 | return ((addr >= get_dram_base(pvt, nid)) && |
258 | (addr <= get_dram_limit(pvt, nid))); | |
6775763a DT |
259 | } |
260 | ||
261 | /* | |
262 | * Attempt to map a SysAddr to a node. On success, return a pointer to the | |
263 | * mem_ctl_info structure for the node that the SysAddr maps to. | |
264 | * | |
265 | * On failure, return NULL. | |
266 | */ | |
267 | static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, | |
268 | u64 sys_addr) | |
269 | { | |
270 | struct amd64_pvt *pvt; | |
b487c33e | 271 | unsigned node_id; |
6775763a DT |
272 | u32 intlv_en, bits; |
273 | ||
274 | /* | |
275 | * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section | |
276 | * 3.4.4.2) registers to map the SysAddr to a node ID. | |
277 | */ | |
278 | pvt = mci->pvt_info; | |
279 | ||
280 | /* | |
281 | * The value of this field should be the same for all DRAM Base | |
282 | * registers. Therefore we arbitrarily choose to read it from the | |
283 | * register for node 0. | |
284 | */ | |
7f19bf75 | 285 | intlv_en = dram_intlv_en(pvt, 0); |
6775763a DT |
286 | |
287 | if (intlv_en == 0) { | |
7f19bf75 | 288 | for (node_id = 0; node_id < DRAM_RANGES; node_id++) { |
6775763a | 289 | if (amd64_base_limit_match(pvt, sys_addr, node_id)) |
8edc5445 | 290 | goto found; |
6775763a | 291 | } |
8edc5445 | 292 | goto err_no_match; |
6775763a DT |
293 | } |
294 | ||
72f158fe BP |
295 | if (unlikely((intlv_en != 0x01) && |
296 | (intlv_en != 0x03) && | |
297 | (intlv_en != 0x07))) { | |
24f9a7fe | 298 | amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en); |
6775763a DT |
299 | return NULL; |
300 | } | |
301 | ||
302 | bits = (((u32) sys_addr) >> 12) & intlv_en; | |
303 | ||
304 | for (node_id = 0; ; ) { | |
7f19bf75 | 305 | if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) |
6775763a DT |
306 | break; /* intlv_sel field matches */ |
307 | ||
7f19bf75 | 308 | if (++node_id >= DRAM_RANGES) |
6775763a DT |
309 | goto err_no_match; |
310 | } | |
311 | ||
312 | /* sanity test for sys_addr */ | |
313 | if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) { | |
24f9a7fe BP |
314 | amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address" |
315 | "range for node %d with node interleaving enabled.\n", | |
316 | __func__, sys_addr, node_id); | |
6775763a DT |
317 | return NULL; |
318 | } | |
319 | ||
320 | found: | |
b487c33e | 321 | return edac_mc_find((int)node_id); |
6775763a DT |
322 | |
323 | err_no_match: | |
324 | debugf2("sys_addr 0x%lx doesn't match any node\n", | |
325 | (unsigned long)sys_addr); | |
326 | ||
327 | return NULL; | |
328 | } | |
e2ce7255 DT |
329 | |
330 | /* | |
11c75ead BP |
331 | * compute the CS base address of the @csrow on the DRAM controller @dct. |
332 | * For details see F2x[5C:40] in the processor's BKDG | |
e2ce7255 | 333 | */ |
11c75ead BP |
334 | static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, |
335 | u64 *base, u64 *mask) | |
e2ce7255 | 336 | { |
11c75ead BP |
337 | u64 csbase, csmask, base_bits, mask_bits; |
338 | u8 addr_shift; | |
e2ce7255 | 339 | |
11c75ead BP |
340 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) { |
341 | csbase = pvt->csels[dct].csbases[csrow]; | |
342 | csmask = pvt->csels[dct].csmasks[csrow]; | |
343 | base_bits = GENMASK(21, 31) | GENMASK(9, 15); | |
344 | mask_bits = GENMASK(21, 29) | GENMASK(9, 15); | |
345 | addr_shift = 4; | |
346 | } else { | |
347 | csbase = pvt->csels[dct].csbases[csrow]; | |
348 | csmask = pvt->csels[dct].csmasks[csrow >> 1]; | |
349 | addr_shift = 8; | |
e2ce7255 | 350 | |
11c75ead BP |
351 | if (boot_cpu_data.x86 == 0x15) |
352 | base_bits = mask_bits = GENMASK(19,30) | GENMASK(5,13); | |
353 | else | |
354 | base_bits = mask_bits = GENMASK(19,28) | GENMASK(5,13); | |
355 | } | |
e2ce7255 | 356 | |
11c75ead | 357 | *base = (csbase & base_bits) << addr_shift; |
e2ce7255 | 358 | |
11c75ead BP |
359 | *mask = ~0ULL; |
360 | /* poke holes for the csmask */ | |
361 | *mask &= ~(mask_bits << addr_shift); | |
362 | /* OR them in */ | |
363 | *mask |= (csmask & mask_bits) << addr_shift; | |
e2ce7255 DT |
364 | } |
365 | ||
11c75ead BP |
366 | #define for_each_chip_select(i, dct, pvt) \ |
367 | for (i = 0; i < pvt->csels[dct].b_cnt; i++) | |
368 | ||
614ec9d8 BP |
369 | #define chip_select_base(i, dct, pvt) \ |
370 | pvt->csels[dct].csbases[i] | |
371 | ||
11c75ead BP |
372 | #define for_each_chip_select_mask(i, dct, pvt) \ |
373 | for (i = 0; i < pvt->csels[dct].m_cnt; i++) | |
374 | ||
e2ce7255 DT |
375 | /* |
376 | * @input_addr is an InputAddr associated with the node given by mci. Return the | |
377 | * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). | |
378 | */ | |
379 | static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) | |
380 | { | |
381 | struct amd64_pvt *pvt; | |
382 | int csrow; | |
383 | u64 base, mask; | |
384 | ||
385 | pvt = mci->pvt_info; | |
386 | ||
11c75ead BP |
387 | for_each_chip_select(csrow, 0, pvt) { |
388 | if (!csrow_enabled(csrow, 0, pvt)) | |
e2ce7255 DT |
389 | continue; |
390 | ||
11c75ead BP |
391 | get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); |
392 | ||
393 | mask = ~mask; | |
e2ce7255 DT |
394 | |
395 | if ((input_addr & mask) == (base & mask)) { | |
396 | debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n", | |
397 | (unsigned long)input_addr, csrow, | |
398 | pvt->mc_node_id); | |
399 | ||
400 | return csrow; | |
401 | } | |
402 | } | |
e2ce7255 DT |
403 | debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n", |
404 | (unsigned long)input_addr, pvt->mc_node_id); | |
405 | ||
406 | return -1; | |
407 | } | |
408 | ||
e2ce7255 DT |
409 | /* |
410 | * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) | |
411 | * for the node represented by mci. Info is passed back in *hole_base, | |
412 | * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if | |
413 | * info is invalid. Info may be invalid for either of the following reasons: | |
414 | * | |
415 | * - The revision of the node is not E or greater. In this case, the DRAM Hole | |
416 | * Address Register does not exist. | |
417 | * | |
418 | * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, | |
419 | * indicating that its contents are not valid. | |
420 | * | |
421 | * The values passed back in *hole_base, *hole_offset, and *hole_size are | |
422 | * complete 32-bit values despite the fact that the bitfields in the DHAR | |
423 | * only represent bits 31-24 of the base and offset values. | |
424 | */ | |
425 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, | |
426 | u64 *hole_offset, u64 *hole_size) | |
427 | { | |
428 | struct amd64_pvt *pvt = mci->pvt_info; | |
429 | u64 base; | |
430 | ||
431 | /* only revE and later have the DRAM Hole Address Register */ | |
1433eb99 | 432 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) { |
e2ce7255 DT |
433 | debugf1(" revision %d for node %d does not support DHAR\n", |
434 | pvt->ext_model, pvt->mc_node_id); | |
435 | return 1; | |
436 | } | |
437 | ||
bc21fa57 | 438 | /* valid for Fam10h and above */ |
c8e518d5 | 439 | if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) { |
e2ce7255 DT |
440 | debugf1(" Dram Memory Hoisting is DISABLED on this system\n"); |
441 | return 1; | |
442 | } | |
443 | ||
c8e518d5 | 444 | if (!dhar_valid(pvt)) { |
e2ce7255 DT |
445 | debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n", |
446 | pvt->mc_node_id); | |
447 | return 1; | |
448 | } | |
449 | ||
450 | /* This node has Memory Hoisting */ | |
451 | ||
452 | /* +------------------+--------------------+--------------------+----- | |
453 | * | memory | DRAM hole | relocated | | |
454 | * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | | |
455 | * | | | DRAM hole | | |
456 | * | | | [0x100000000, | | |
457 | * | | | (0x100000000+ | | |
458 | * | | | (0xffffffff-x))] | | |
459 | * +------------------+--------------------+--------------------+----- | |
460 | * | |
461 | * Above is a diagram of physical memory showing the DRAM hole and the | |
462 | * relocated addresses from the DRAM hole. As shown, the DRAM hole | |
463 | * starts at address x (the base address) and extends through address | |
464 | * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the | |
465 | * addresses in the hole so that they start at 0x100000000. | |
466 | */ | |
467 | ||
bc21fa57 | 468 | base = dhar_base(pvt); |
e2ce7255 DT |
469 | |
470 | *hole_base = base; | |
471 | *hole_size = (0x1ull << 32) - base; | |
472 | ||
473 | if (boot_cpu_data.x86 > 0xf) | |
bc21fa57 | 474 | *hole_offset = f10_dhar_offset(pvt); |
e2ce7255 | 475 | else |
bc21fa57 | 476 | *hole_offset = k8_dhar_offset(pvt); |
e2ce7255 DT |
477 | |
478 | debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", | |
479 | pvt->mc_node_id, (unsigned long)*hole_base, | |
480 | (unsigned long)*hole_offset, (unsigned long)*hole_size); | |
481 | ||
482 | return 0; | |
483 | } | |
484 | EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); | |
485 | ||
93c2df58 DT |
486 | /* |
487 | * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is | |
488 | * assumed that sys_addr maps to the node given by mci. | |
489 | * | |
490 | * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section | |
491 | * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a | |
492 | * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, | |
493 | * then it is also involved in translating a SysAddr to a DramAddr. Sections | |
494 | * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. | |
495 | * These parts of the documentation are unclear. I interpret them as follows: | |
496 | * | |
497 | * When node n receives a SysAddr, it processes the SysAddr as follows: | |
498 | * | |
499 | * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM | |
500 | * Limit registers for node n. If the SysAddr is not within the range | |
501 | * specified by the base and limit values, then node n ignores the Sysaddr | |
502 | * (since it does not map to node n). Otherwise continue to step 2 below. | |
503 | * | |
504 | * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is | |
505 | * disabled so skip to step 3 below. Otherwise see if the SysAddr is within | |
506 | * the range of relocated addresses (starting at 0x100000000) from the DRAM | |
507 | * hole. If not, skip to step 3 below. Else get the value of the | |
508 | * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the | |
509 | * offset defined by this value from the SysAddr. | |
510 | * | |
511 | * 3. Obtain the base address for node n from the DRAMBase field of the DRAM | |
512 | * Base register for node n. To obtain the DramAddr, subtract the base | |
513 | * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). | |
514 | */ | |
515 | static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
516 | { | |
7f19bf75 | 517 | struct amd64_pvt *pvt = mci->pvt_info; |
93c2df58 DT |
518 | u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; |
519 | int ret = 0; | |
520 | ||
7f19bf75 | 521 | dram_base = get_dram_base(pvt, pvt->mc_node_id); |
93c2df58 DT |
522 | |
523 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
524 | &hole_size); | |
525 | if (!ret) { | |
526 | if ((sys_addr >= (1ull << 32)) && | |
527 | (sys_addr < ((1ull << 32) + hole_size))) { | |
528 | /* use DHAR to translate SysAddr to DramAddr */ | |
529 | dram_addr = sys_addr - hole_offset; | |
530 | ||
531 | debugf2("using DHAR to translate SysAddr 0x%lx to " | |
532 | "DramAddr 0x%lx\n", | |
533 | (unsigned long)sys_addr, | |
534 | (unsigned long)dram_addr); | |
535 | ||
536 | return dram_addr; | |
537 | } | |
538 | } | |
539 | ||
540 | /* | |
541 | * Translate the SysAddr to a DramAddr as shown near the start of | |
542 | * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 | |
543 | * only deals with 40-bit values. Therefore we discard bits 63-40 of | |
544 | * sys_addr below. If bit 39 of sys_addr is 1 then the bits we | |
545 | * discard are all 1s. Otherwise the bits we discard are all 0s. See | |
546 | * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture | |
547 | * Programmer's Manual Volume 1 Application Programming. | |
548 | */ | |
f678b8cc | 549 | dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base; |
93c2df58 DT |
550 | |
551 | debugf2("using DRAM Base register to translate SysAddr 0x%lx to " | |
552 | "DramAddr 0x%lx\n", (unsigned long)sys_addr, | |
553 | (unsigned long)dram_addr); | |
554 | return dram_addr; | |
555 | } | |
556 | ||
557 | /* | |
558 | * @intlv_en is the value of the IntlvEn field from a DRAM Base register | |
559 | * (section 3.4.4.1). Return the number of bits from a SysAddr that are used | |
560 | * for node interleaving. | |
561 | */ | |
562 | static int num_node_interleave_bits(unsigned intlv_en) | |
563 | { | |
564 | static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; | |
565 | int n; | |
566 | ||
567 | BUG_ON(intlv_en > 7); | |
568 | n = intlv_shift_table[intlv_en]; | |
569 | return n; | |
570 | } | |
571 | ||
572 | /* Translate the DramAddr given by @dram_addr to an InputAddr. */ | |
573 | static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
574 | { | |
575 | struct amd64_pvt *pvt; | |
576 | int intlv_shift; | |
577 | u64 input_addr; | |
578 | ||
579 | pvt = mci->pvt_info; | |
580 | ||
581 | /* | |
582 | * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
583 | * concerning translating a DramAddr to an InputAddr. | |
584 | */ | |
7f19bf75 | 585 | intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); |
f678b8cc BP |
586 | input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) + |
587 | (dram_addr & 0xfff); | |
93c2df58 DT |
588 | |
589 | debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", | |
590 | intlv_shift, (unsigned long)dram_addr, | |
591 | (unsigned long)input_addr); | |
592 | ||
593 | return input_addr; | |
594 | } | |
595 | ||
596 | /* | |
597 | * Translate the SysAddr represented by @sys_addr to an InputAddr. It is | |
598 | * assumed that @sys_addr maps to the node given by mci. | |
599 | */ | |
600 | static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
601 | { | |
602 | u64 input_addr; | |
603 | ||
604 | input_addr = | |
605 | dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); | |
606 | ||
607 | debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n", | |
608 | (unsigned long)sys_addr, (unsigned long)input_addr); | |
609 | ||
610 | return input_addr; | |
611 | } | |
612 | ||
613 | ||
614 | /* | |
615 | * @input_addr is an InputAddr associated with the node represented by mci. | |
616 | * Translate @input_addr to a DramAddr and return the result. | |
617 | */ | |
618 | static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr) | |
619 | { | |
620 | struct amd64_pvt *pvt; | |
b487c33e | 621 | unsigned node_id, intlv_shift; |
93c2df58 DT |
622 | u64 bits, dram_addr; |
623 | u32 intlv_sel; | |
624 | ||
625 | /* | |
626 | * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
627 | * shows how to translate a DramAddr to an InputAddr. Here we reverse | |
628 | * this procedure. When translating from a DramAddr to an InputAddr, the | |
629 | * bits used for node interleaving are discarded. Here we recover these | |
630 | * bits from the IntlvSel field of the DRAM Limit register (section | |
631 | * 3.4.4.2) for the node that input_addr is associated with. | |
632 | */ | |
633 | pvt = mci->pvt_info; | |
634 | node_id = pvt->mc_node_id; | |
b487c33e BP |
635 | |
636 | BUG_ON(node_id > 7); | |
93c2df58 | 637 | |
7f19bf75 | 638 | intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); |
93c2df58 DT |
639 | if (intlv_shift == 0) { |
640 | debugf1(" InputAddr 0x%lx translates to DramAddr of " | |
641 | "same value\n", (unsigned long)input_addr); | |
642 | ||
643 | return input_addr; | |
644 | } | |
645 | ||
f678b8cc BP |
646 | bits = ((input_addr & GENMASK(12, 35)) << intlv_shift) + |
647 | (input_addr & 0xfff); | |
93c2df58 | 648 | |
7f19bf75 | 649 | intlv_sel = dram_intlv_sel(pvt, node_id) & ((1 << intlv_shift) - 1); |
93c2df58 DT |
650 | dram_addr = bits + (intlv_sel << 12); |
651 | ||
652 | debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx " | |
653 | "(%d node interleave bits)\n", (unsigned long)input_addr, | |
654 | (unsigned long)dram_addr, intlv_shift); | |
655 | ||
656 | return dram_addr; | |
657 | } | |
658 | ||
659 | /* | |
660 | * @dram_addr is a DramAddr that maps to the node represented by mci. Convert | |
661 | * @dram_addr to a SysAddr. | |
662 | */ | |
663 | static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
664 | { | |
665 | struct amd64_pvt *pvt = mci->pvt_info; | |
7f19bf75 | 666 | u64 hole_base, hole_offset, hole_size, base, sys_addr; |
93c2df58 DT |
667 | int ret = 0; |
668 | ||
669 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
670 | &hole_size); | |
671 | if (!ret) { | |
672 | if ((dram_addr >= hole_base) && | |
673 | (dram_addr < (hole_base + hole_size))) { | |
674 | sys_addr = dram_addr + hole_offset; | |
675 | ||
676 | debugf1("using DHAR to translate DramAddr 0x%lx to " | |
677 | "SysAddr 0x%lx\n", (unsigned long)dram_addr, | |
678 | (unsigned long)sys_addr); | |
679 | ||
680 | return sys_addr; | |
681 | } | |
682 | } | |
683 | ||
7f19bf75 | 684 | base = get_dram_base(pvt, pvt->mc_node_id); |
93c2df58 DT |
685 | sys_addr = dram_addr + base; |
686 | ||
687 | /* | |
688 | * The sys_addr we have computed up to this point is a 40-bit value | |
689 | * because the k8 deals with 40-bit values. However, the value we are | |
690 | * supposed to return is a full 64-bit physical address. The AMD | |
691 | * x86-64 architecture specifies that the most significant implemented | |
692 | * address bit through bit 63 of a physical address must be either all | |
693 | * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a | |
694 | * 64-bit value below. See section 3.4.2 of AMD publication 24592: | |
695 | * AMD x86-64 Architecture Programmer's Manual Volume 1 Application | |
696 | * Programming. | |
697 | */ | |
698 | sys_addr |= ~((sys_addr & (1ull << 39)) - 1); | |
699 | ||
700 | debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", | |
701 | pvt->mc_node_id, (unsigned long)dram_addr, | |
702 | (unsigned long)sys_addr); | |
703 | ||
704 | return sys_addr; | |
705 | } | |
706 | ||
707 | /* | |
708 | * @input_addr is an InputAddr associated with the node given by mci. Translate | |
709 | * @input_addr to a SysAddr. | |
710 | */ | |
711 | static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci, | |
712 | u64 input_addr) | |
713 | { | |
714 | return dram_addr_to_sys_addr(mci, | |
715 | input_addr_to_dram_addr(mci, input_addr)); | |
716 | } | |
717 | ||
718 | /* | |
719 | * Find the minimum and maximum InputAddr values that map to the given @csrow. | |
720 | * Pass back these values in *input_addr_min and *input_addr_max. | |
721 | */ | |
722 | static void find_csrow_limits(struct mem_ctl_info *mci, int csrow, | |
723 | u64 *input_addr_min, u64 *input_addr_max) | |
724 | { | |
725 | struct amd64_pvt *pvt; | |
726 | u64 base, mask; | |
727 | ||
728 | pvt = mci->pvt_info; | |
11c75ead | 729 | BUG_ON((csrow < 0) || (csrow >= pvt->csels[0].b_cnt)); |
93c2df58 | 730 | |
11c75ead | 731 | get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); |
93c2df58 DT |
732 | |
733 | *input_addr_min = base & ~mask; | |
11c75ead | 734 | *input_addr_max = base | mask; |
93c2df58 DT |
735 | } |
736 | ||
93c2df58 DT |
737 | /* Map the Error address to a PAGE and PAGE OFFSET. */ |
738 | static inline void error_address_to_page_and_offset(u64 error_address, | |
739 | u32 *page, u32 *offset) | |
740 | { | |
741 | *page = (u32) (error_address >> PAGE_SHIFT); | |
742 | *offset = ((u32) error_address) & ~PAGE_MASK; | |
743 | } | |
744 | ||
745 | /* | |
746 | * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address | |
747 | * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers | |
748 | * of a node that detected an ECC memory error. mci represents the node that | |
749 | * the error address maps to (possibly different from the node that detected | |
750 | * the error). Return the number of the csrow that sys_addr maps to, or -1 on | |
751 | * error. | |
752 | */ | |
753 | static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) | |
754 | { | |
755 | int csrow; | |
756 | ||
757 | csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); | |
758 | ||
759 | if (csrow == -1) | |
24f9a7fe BP |
760 | amd64_mc_err(mci, "Failed to translate InputAddr to csrow for " |
761 | "address 0x%lx\n", (unsigned long)sys_addr); | |
93c2df58 DT |
762 | return csrow; |
763 | } | |
e2ce7255 | 764 | |
bfc04aec | 765 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); |
2da11654 | 766 | |
2da11654 DT |
767 | /* |
768 | * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs | |
769 | * are ECC capable. | |
770 | */ | |
1f6189ed | 771 | static unsigned long amd64_determine_edac_cap(struct amd64_pvt *pvt) |
2da11654 | 772 | { |
cb328507 | 773 | u8 bit; |
1f6189ed | 774 | unsigned long edac_cap = EDAC_FLAG_NONE; |
2da11654 | 775 | |
1433eb99 | 776 | bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F) |
2da11654 DT |
777 | ? 19 |
778 | : 17; | |
779 | ||
584fcff4 | 780 | if (pvt->dclr0 & BIT(bit)) |
2da11654 DT |
781 | edac_cap = EDAC_FLAG_SECDED; |
782 | ||
783 | return edac_cap; | |
784 | } | |
785 | ||
8c671751 | 786 | static void amd64_debug_display_dimm_sizes(struct amd64_pvt *, u8); |
2da11654 | 787 | |
68798e17 BP |
788 | static void amd64_dump_dramcfg_low(u32 dclr, int chan) |
789 | { | |
790 | debugf1("F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr); | |
791 | ||
792 | debugf1(" DIMM type: %sbuffered; all DIMMs support ECC: %s\n", | |
793 | (dclr & BIT(16)) ? "un" : "", | |
794 | (dclr & BIT(19)) ? "yes" : "no"); | |
795 | ||
796 | debugf1(" PAR/ERR parity: %s\n", | |
797 | (dclr & BIT(8)) ? "enabled" : "disabled"); | |
798 | ||
cb328507 BP |
799 | if (boot_cpu_data.x86 == 0x10) |
800 | debugf1(" DCT 128bit mode width: %s\n", | |
801 | (dclr & BIT(11)) ? "128b" : "64b"); | |
68798e17 BP |
802 | |
803 | debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", | |
804 | (dclr & BIT(12)) ? "yes" : "no", | |
805 | (dclr & BIT(13)) ? "yes" : "no", | |
806 | (dclr & BIT(14)) ? "yes" : "no", | |
807 | (dclr & BIT(15)) ? "yes" : "no"); | |
808 | } | |
809 | ||
2da11654 | 810 | /* Display and decode various NB registers for debug purposes. */ |
b2b0c605 | 811 | static void dump_misc_regs(struct amd64_pvt *pvt) |
2da11654 | 812 | { |
68798e17 BP |
813 | debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); |
814 | ||
815 | debugf1(" NB two channel DRAM capable: %s\n", | |
5980bb9c | 816 | (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); |
2da11654 | 817 | |
68798e17 | 818 | debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n", |
5980bb9c BP |
819 | (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", |
820 | (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); | |
68798e17 BP |
821 | |
822 | amd64_dump_dramcfg_low(pvt->dclr0, 0); | |
2da11654 | 823 | |
8de1d91e | 824 | debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); |
2da11654 | 825 | |
8de1d91e BP |
826 | debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, " |
827 | "offset: 0x%08x\n", | |
bc21fa57 BP |
828 | pvt->dhar, dhar_base(pvt), |
829 | (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt) | |
830 | : f10_dhar_offset(pvt)); | |
2da11654 | 831 | |
c8e518d5 | 832 | debugf1(" DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); |
2da11654 | 833 | |
8c671751 | 834 | amd64_debug_display_dimm_sizes(pvt, 0); |
4d796364 | 835 | |
8de1d91e | 836 | /* everything below this point is Fam10h and above */ |
4d796364 | 837 | if (boot_cpu_data.x86 == 0xf) |
2da11654 | 838 | return; |
4d796364 | 839 | |
8c671751 | 840 | amd64_debug_display_dimm_sizes(pvt, 1); |
2da11654 | 841 | |
a3b7db09 | 842 | amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4")); |
ad6a32e9 | 843 | |
8de1d91e | 844 | /* Only if NOT ganged does dclr1 have valid info */ |
68798e17 BP |
845 | if (!dct_ganging_enabled(pvt)) |
846 | amd64_dump_dramcfg_low(pvt->dclr1, 1); | |
2da11654 DT |
847 | } |
848 | ||
94be4bff | 849 | /* |
11c75ead | 850 | * see BKDG, F2x[1,0][5C:40], F2[1,0][6C:60] |
94be4bff | 851 | */ |
11c75ead | 852 | static void prep_chip_selects(struct amd64_pvt *pvt) |
94be4bff | 853 | { |
1433eb99 | 854 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) { |
11c75ead BP |
855 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; |
856 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; | |
9d858bb1 | 857 | } else { |
11c75ead BP |
858 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; |
859 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; | |
94be4bff DT |
860 | } |
861 | } | |
862 | ||
863 | /* | |
11c75ead | 864 | * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers |
94be4bff | 865 | */ |
b2b0c605 | 866 | static void read_dct_base_mask(struct amd64_pvt *pvt) |
94be4bff | 867 | { |
11c75ead | 868 | int cs; |
94be4bff | 869 | |
11c75ead | 870 | prep_chip_selects(pvt); |
94be4bff | 871 | |
11c75ead | 872 | for_each_chip_select(cs, 0, pvt) { |
71d2a32e BP |
873 | int reg0 = DCSB0 + (cs * 4); |
874 | int reg1 = DCSB1 + (cs * 4); | |
11c75ead BP |
875 | u32 *base0 = &pvt->csels[0].csbases[cs]; |
876 | u32 *base1 = &pvt->csels[1].csbases[cs]; | |
b2b0c605 | 877 | |
11c75ead | 878 | if (!amd64_read_dct_pci_cfg(pvt, reg0, base0)) |
94be4bff | 879 | debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n", |
11c75ead | 880 | cs, *base0, reg0); |
94be4bff | 881 | |
11c75ead BP |
882 | if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt)) |
883 | continue; | |
b2b0c605 | 884 | |
11c75ead BP |
885 | if (!amd64_read_dct_pci_cfg(pvt, reg1, base1)) |
886 | debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n", | |
887 | cs, *base1, reg1); | |
94be4bff DT |
888 | } |
889 | ||
11c75ead | 890 | for_each_chip_select_mask(cs, 0, pvt) { |
71d2a32e BP |
891 | int reg0 = DCSM0 + (cs * 4); |
892 | int reg1 = DCSM1 + (cs * 4); | |
11c75ead BP |
893 | u32 *mask0 = &pvt->csels[0].csmasks[cs]; |
894 | u32 *mask1 = &pvt->csels[1].csmasks[cs]; | |
b2b0c605 | 895 | |
11c75ead | 896 | if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0)) |
94be4bff | 897 | debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n", |
11c75ead | 898 | cs, *mask0, reg0); |
94be4bff | 899 | |
11c75ead BP |
900 | if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt)) |
901 | continue; | |
b2b0c605 | 902 | |
11c75ead BP |
903 | if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1)) |
904 | debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n", | |
905 | cs, *mask1, reg1); | |
94be4bff DT |
906 | } |
907 | } | |
908 | ||
24f9a7fe | 909 | static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt, int cs) |
94be4bff DT |
910 | { |
911 | enum mem_type type; | |
912 | ||
cb328507 BP |
913 | /* F15h supports only DDR3 */ |
914 | if (boot_cpu_data.x86 >= 0x15) | |
915 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; | |
916 | else if (boot_cpu_data.x86 == 0x10 || pvt->ext_model >= K8_REV_F) { | |
6b4c0bde BP |
917 | if (pvt->dchr0 & DDR3_MODE) |
918 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; | |
919 | else | |
920 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; | |
94be4bff | 921 | } else { |
94be4bff DT |
922 | type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; |
923 | } | |
924 | ||
24f9a7fe | 925 | amd64_info("CS%d: %s\n", cs, edac_mem_types[type]); |
94be4bff DT |
926 | |
927 | return type; | |
928 | } | |
929 | ||
cb328507 | 930 | /* Get the number of DCT channels the memory controller is using. */ |
ddff876d DT |
931 | static int k8_early_channel_count(struct amd64_pvt *pvt) |
932 | { | |
cb328507 | 933 | int flag; |
ddff876d | 934 | |
9f56da0e | 935 | if (pvt->ext_model >= K8_REV_F) |
ddff876d | 936 | /* RevF (NPT) and later */ |
41d8bfab | 937 | flag = pvt->dclr0 & WIDTH_128; |
9f56da0e | 938 | else |
ddff876d DT |
939 | /* RevE and earlier */ |
940 | flag = pvt->dclr0 & REVE_WIDTH_128; | |
ddff876d DT |
941 | |
942 | /* not used */ | |
943 | pvt->dclr1 = 0; | |
944 | ||
945 | return (flag) ? 2 : 1; | |
946 | } | |
947 | ||
70046624 BP |
948 | /* On F10h and later ErrAddr is MC4_ADDR[47:1] */ |
949 | static u64 get_error_address(struct mce *m) | |
ddff876d | 950 | { |
c1ae6830 BP |
951 | struct cpuinfo_x86 *c = &boot_cpu_data; |
952 | u64 addr; | |
70046624 BP |
953 | u8 start_bit = 1; |
954 | u8 end_bit = 47; | |
955 | ||
c1ae6830 | 956 | if (c->x86 == 0xf) { |
70046624 BP |
957 | start_bit = 3; |
958 | end_bit = 39; | |
959 | } | |
960 | ||
c1ae6830 BP |
961 | addr = m->addr & GENMASK(start_bit, end_bit); |
962 | ||
963 | /* | |
964 | * Erratum 637 workaround | |
965 | */ | |
966 | if (c->x86 == 0x15) { | |
967 | struct amd64_pvt *pvt; | |
968 | u64 cc6_base, tmp_addr; | |
969 | u32 tmp; | |
970 | u8 mce_nid, intlv_en; | |
971 | ||
972 | if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7) | |
973 | return addr; | |
974 | ||
975 | mce_nid = amd_get_nb_id(m->extcpu); | |
976 | pvt = mcis[mce_nid]->pvt_info; | |
977 | ||
978 | amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); | |
979 | intlv_en = tmp >> 21 & 0x7; | |
980 | ||
981 | /* add [47:27] + 3 trailing bits */ | |
982 | cc6_base = (tmp & GENMASK(0, 20)) << 3; | |
983 | ||
984 | /* reverse and add DramIntlvEn */ | |
985 | cc6_base |= intlv_en ^ 0x7; | |
986 | ||
987 | /* pin at [47:24] */ | |
988 | cc6_base <<= 24; | |
989 | ||
990 | if (!intlv_en) | |
991 | return cc6_base | (addr & GENMASK(0, 23)); | |
992 | ||
993 | amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); | |
994 | ||
995 | /* faster log2 */ | |
996 | tmp_addr = (addr & GENMASK(12, 23)) << __fls(intlv_en + 1); | |
997 | ||
998 | /* OR DramIntlvSel into bits [14:12] */ | |
999 | tmp_addr |= (tmp & GENMASK(21, 23)) >> 9; | |
1000 | ||
1001 | /* add remaining [11:0] bits from original MC4_ADDR */ | |
1002 | tmp_addr |= addr & GENMASK(0, 11); | |
1003 | ||
1004 | return cc6_base | tmp_addr; | |
1005 | } | |
1006 | ||
1007 | return addr; | |
ddff876d DT |
1008 | } |
1009 | ||
7f19bf75 | 1010 | static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) |
ddff876d | 1011 | { |
f08e457c | 1012 | struct cpuinfo_x86 *c = &boot_cpu_data; |
71d2a32e | 1013 | int off = range << 3; |
ddff876d | 1014 | |
7f19bf75 BP |
1015 | amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); |
1016 | amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); | |
ddff876d | 1017 | |
f08e457c | 1018 | if (c->x86 == 0xf) |
7f19bf75 | 1019 | return; |
ddff876d | 1020 | |
7f19bf75 BP |
1021 | if (!dram_rw(pvt, range)) |
1022 | return; | |
ddff876d | 1023 | |
7f19bf75 BP |
1024 | amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); |
1025 | amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); | |
f08e457c BP |
1026 | |
1027 | /* Factor in CC6 save area by reading dst node's limit reg */ | |
1028 | if (c->x86 == 0x15) { | |
1029 | struct pci_dev *f1 = NULL; | |
1030 | u8 nid = dram_dst_node(pvt, range); | |
1031 | u32 llim; | |
1032 | ||
1033 | f1 = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0x18 + nid, 1)); | |
1034 | if (WARN_ON(!f1)) | |
1035 | return; | |
1036 | ||
1037 | amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim); | |
1038 | ||
1039 | pvt->ranges[range].lim.lo &= GENMASK(0, 15); | |
1040 | ||
1041 | /* {[39:27],111b} */ | |
1042 | pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; | |
1043 | ||
1044 | pvt->ranges[range].lim.hi &= GENMASK(0, 7); | |
1045 | ||
1046 | /* [47:40] */ | |
1047 | pvt->ranges[range].lim.hi |= llim >> 13; | |
1048 | ||
1049 | pci_dev_put(f1); | |
1050 | } | |
ddff876d DT |
1051 | } |
1052 | ||
f192c7b1 BP |
1053 | static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, |
1054 | u16 syndrome) | |
ddff876d DT |
1055 | { |
1056 | struct mem_ctl_info *src_mci; | |
f192c7b1 | 1057 | struct amd64_pvt *pvt = mci->pvt_info; |
ddff876d DT |
1058 | int channel, csrow; |
1059 | u32 page, offset; | |
ddff876d DT |
1060 | |
1061 | /* CHIPKILL enabled */ | |
f192c7b1 | 1062 | if (pvt->nbcfg & NBCFG_CHIPKILL) { |
bfc04aec | 1063 | channel = get_channel_from_ecc_syndrome(mci, syndrome); |
ddff876d DT |
1064 | if (channel < 0) { |
1065 | /* | |
1066 | * Syndrome didn't map, so we don't know which of the | |
1067 | * 2 DIMMs is in error. So we need to ID 'both' of them | |
1068 | * as suspect. | |
1069 | */ | |
24f9a7fe BP |
1070 | amd64_mc_warn(mci, "unknown syndrome 0x%04x - possible " |
1071 | "error reporting race\n", syndrome); | |
ddff876d DT |
1072 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); |
1073 | return; | |
1074 | } | |
1075 | } else { | |
1076 | /* | |
1077 | * non-chipkill ecc mode | |
1078 | * | |
1079 | * The k8 documentation is unclear about how to determine the | |
1080 | * channel number when using non-chipkill memory. This method | |
1081 | * was obtained from email communication with someone at AMD. | |
1082 | * (Wish the email was placed in this comment - norsk) | |
1083 | */ | |
44e9e2ee | 1084 | channel = ((sys_addr & BIT(3)) != 0); |
ddff876d DT |
1085 | } |
1086 | ||
1087 | /* | |
1088 | * Find out which node the error address belongs to. This may be | |
1089 | * different from the node that detected the error. | |
1090 | */ | |
44e9e2ee | 1091 | src_mci = find_mc_by_sys_addr(mci, sys_addr); |
2cff18c2 | 1092 | if (!src_mci) { |
24f9a7fe | 1093 | amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n", |
44e9e2ee | 1094 | (unsigned long)sys_addr); |
ddff876d DT |
1095 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); |
1096 | return; | |
1097 | } | |
1098 | ||
44e9e2ee BP |
1099 | /* Now map the sys_addr to a CSROW */ |
1100 | csrow = sys_addr_to_csrow(src_mci, sys_addr); | |
ddff876d DT |
1101 | if (csrow < 0) { |
1102 | edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR); | |
1103 | } else { | |
44e9e2ee | 1104 | error_address_to_page_and_offset(sys_addr, &page, &offset); |
ddff876d DT |
1105 | |
1106 | edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow, | |
1107 | channel, EDAC_MOD_STR); | |
1108 | } | |
1109 | } | |
1110 | ||
41d8bfab | 1111 | static int ddr2_cs_size(unsigned i, bool dct_width) |
ddff876d | 1112 | { |
41d8bfab | 1113 | unsigned shift = 0; |
ddff876d | 1114 | |
41d8bfab BP |
1115 | if (i <= 2) |
1116 | shift = i; | |
1117 | else if (!(i & 0x1)) | |
1118 | shift = i >> 1; | |
1433eb99 | 1119 | else |
41d8bfab | 1120 | shift = (i + 1) >> 1; |
ddff876d | 1121 | |
41d8bfab BP |
1122 | return 128 << (shift + !!dct_width); |
1123 | } | |
1124 | ||
1125 | static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
1126 | unsigned cs_mode) | |
1127 | { | |
1128 | u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; | |
1129 | ||
1130 | if (pvt->ext_model >= K8_REV_F) { | |
1131 | WARN_ON(cs_mode > 11); | |
1132 | return ddr2_cs_size(cs_mode, dclr & WIDTH_128); | |
1133 | } | |
1134 | else if (pvt->ext_model >= K8_REV_D) { | |
1135 | WARN_ON(cs_mode > 10); | |
1136 | ||
1137 | if (cs_mode == 3 || cs_mode == 8) | |
1138 | return 32 << (cs_mode - 1); | |
1139 | else | |
1140 | return 32 << cs_mode; | |
1141 | } | |
1142 | else { | |
1143 | WARN_ON(cs_mode > 6); | |
1144 | return 32 << cs_mode; | |
1145 | } | |
ddff876d DT |
1146 | } |
1147 | ||
1afd3c98 DT |
1148 | /* |
1149 | * Get the number of DCT channels in use. | |
1150 | * | |
1151 | * Return: | |
1152 | * number of Memory Channels in operation | |
1153 | * Pass back: | |
1154 | * contents of the DCL0_LOW register | |
1155 | */ | |
7d20d14d | 1156 | static int f1x_early_channel_count(struct amd64_pvt *pvt) |
1afd3c98 | 1157 | { |
6ba5dcdc | 1158 | int i, j, channels = 0; |
1afd3c98 | 1159 | |
7d20d14d | 1160 | /* On F10h, if we are in 128 bit mode, then we are using 2 channels */ |
41d8bfab | 1161 | if (boot_cpu_data.x86 == 0x10 && (pvt->dclr0 & WIDTH_128)) |
7d20d14d | 1162 | return 2; |
1afd3c98 DT |
1163 | |
1164 | /* | |
d16149e8 BP |
1165 | * Need to check if in unganged mode: In such, there are 2 channels, |
1166 | * but they are not in 128 bit mode and thus the above 'dclr0' status | |
1167 | * bit will be OFF. | |
1afd3c98 DT |
1168 | * |
1169 | * Need to check DCT0[0] and DCT1[0] to see if only one of them has | |
1170 | * their CSEnable bit on. If so, then SINGLE DIMM case. | |
1171 | */ | |
d16149e8 | 1172 | debugf0("Data width is not 128 bits - need more decoding\n"); |
ddff876d | 1173 | |
1afd3c98 DT |
1174 | /* |
1175 | * Check DRAM Bank Address Mapping values for each DIMM to see if there | |
1176 | * is more than just one DIMM present in unganged mode. Need to check | |
1177 | * both controllers since DIMMs can be placed in either one. | |
1178 | */ | |
525a1b20 BP |
1179 | for (i = 0; i < 2; i++) { |
1180 | u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); | |
1afd3c98 | 1181 | |
57a30854 WW |
1182 | for (j = 0; j < 4; j++) { |
1183 | if (DBAM_DIMM(j, dbam) > 0) { | |
1184 | channels++; | |
1185 | break; | |
1186 | } | |
1187 | } | |
1afd3c98 DT |
1188 | } |
1189 | ||
d16149e8 BP |
1190 | if (channels > 2) |
1191 | channels = 2; | |
1192 | ||
24f9a7fe | 1193 | amd64_info("MCT channel count: %d\n", channels); |
1afd3c98 DT |
1194 | |
1195 | return channels; | |
1afd3c98 DT |
1196 | } |
1197 | ||
41d8bfab | 1198 | static int ddr3_cs_size(unsigned i, bool dct_width) |
1afd3c98 | 1199 | { |
41d8bfab BP |
1200 | unsigned shift = 0; |
1201 | int cs_size = 0; | |
1202 | ||
1203 | if (i == 0 || i == 3 || i == 4) | |
1204 | cs_size = -1; | |
1205 | else if (i <= 2) | |
1206 | shift = i; | |
1207 | else if (i == 12) | |
1208 | shift = 7; | |
1209 | else if (!(i & 0x1)) | |
1210 | shift = i >> 1; | |
1211 | else | |
1212 | shift = (i + 1) >> 1; | |
1213 | ||
1214 | if (cs_size != -1) | |
1215 | cs_size = (128 * (1 << !!dct_width)) << shift; | |
1216 | ||
1217 | return cs_size; | |
1218 | } | |
1219 | ||
1220 | static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
1221 | unsigned cs_mode) | |
1222 | { | |
1223 | u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; | |
1224 | ||
1225 | WARN_ON(cs_mode > 11); | |
1433eb99 BP |
1226 | |
1227 | if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) | |
41d8bfab | 1228 | return ddr3_cs_size(cs_mode, dclr & WIDTH_128); |
1433eb99 | 1229 | else |
41d8bfab BP |
1230 | return ddr2_cs_size(cs_mode, dclr & WIDTH_128); |
1231 | } | |
1232 | ||
1233 | /* | |
1234 | * F15h supports only 64bit DCT interfaces | |
1235 | */ | |
1236 | static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
1237 | unsigned cs_mode) | |
1238 | { | |
1239 | WARN_ON(cs_mode > 12); | |
1433eb99 | 1240 | |
41d8bfab | 1241 | return ddr3_cs_size(cs_mode, false); |
1afd3c98 DT |
1242 | } |
1243 | ||
5a5d2371 | 1244 | static void read_dram_ctl_register(struct amd64_pvt *pvt) |
6163b5d4 | 1245 | { |
6163b5d4 | 1246 | |
5a5d2371 BP |
1247 | if (boot_cpu_data.x86 == 0xf) |
1248 | return; | |
1249 | ||
78da121e BP |
1250 | if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) { |
1251 | debugf0("F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n", | |
1252 | pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); | |
72381bd5 | 1253 | |
5a5d2371 BP |
1254 | debugf0(" DCTs operate in %s mode.\n", |
1255 | (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); | |
72381bd5 BP |
1256 | |
1257 | if (!dct_ganging_enabled(pvt)) | |
1258 | debugf0(" Address range split per DCT: %s\n", | |
1259 | (dct_high_range_enabled(pvt) ? "yes" : "no")); | |
1260 | ||
78da121e | 1261 | debugf0(" data interleave for ECC: %s, " |
72381bd5 BP |
1262 | "DRAM cleared since last warm reset: %s\n", |
1263 | (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), | |
1264 | (dct_memory_cleared(pvt) ? "yes" : "no")); | |
1265 | ||
78da121e BP |
1266 | debugf0(" channel interleave: %s, " |
1267 | "interleave bits selector: 0x%x\n", | |
72381bd5 | 1268 | (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), |
6163b5d4 DT |
1269 | dct_sel_interleave_addr(pvt)); |
1270 | } | |
1271 | ||
78da121e | 1272 | amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi); |
6163b5d4 DT |
1273 | } |
1274 | ||
f71d0a05 | 1275 | /* |
229a7a11 | 1276 | * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory |
f71d0a05 DT |
1277 | * Interleaving Modes. |
1278 | */ | |
b15f0fca | 1279 | static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, |
229a7a11 | 1280 | bool hi_range_sel, u8 intlv_en) |
6163b5d4 | 1281 | { |
151fa71c | 1282 | u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; |
6163b5d4 DT |
1283 | |
1284 | if (dct_ganging_enabled(pvt)) | |
229a7a11 | 1285 | return 0; |
6163b5d4 | 1286 | |
229a7a11 BP |
1287 | if (hi_range_sel) |
1288 | return dct_sel_high; | |
6163b5d4 | 1289 | |
229a7a11 BP |
1290 | /* |
1291 | * see F2x110[DctSelIntLvAddr] - channel interleave mode | |
1292 | */ | |
1293 | if (dct_interleave_enabled(pvt)) { | |
1294 | u8 intlv_addr = dct_sel_interleave_addr(pvt); | |
1295 | ||
1296 | /* return DCT select function: 0=DCT0, 1=DCT1 */ | |
1297 | if (!intlv_addr) | |
1298 | return sys_addr >> 6 & 1; | |
1299 | ||
1300 | if (intlv_addr & 0x2) { | |
1301 | u8 shift = intlv_addr & 0x1 ? 9 : 6; | |
1302 | u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; | |
1303 | ||
1304 | return ((sys_addr >> shift) & 1) ^ temp; | |
1305 | } | |
1306 | ||
1307 | return (sys_addr >> (12 + hweight8(intlv_en))) & 1; | |
1308 | } | |
1309 | ||
1310 | if (dct_high_range_enabled(pvt)) | |
1311 | return ~dct_sel_high & 1; | |
6163b5d4 DT |
1312 | |
1313 | return 0; | |
1314 | } | |
1315 | ||
c8e518d5 | 1316 | /* Convert the sys_addr to the normalized DCT address */ |
e761359a | 1317 | static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, unsigned range, |
c8e518d5 BP |
1318 | u64 sys_addr, bool hi_rng, |
1319 | u32 dct_sel_base_addr) | |
6163b5d4 DT |
1320 | { |
1321 | u64 chan_off; | |
c8e518d5 BP |
1322 | u64 dram_base = get_dram_base(pvt, range); |
1323 | u64 hole_off = f10_dhar_offset(pvt); | |
c8e518d5 | 1324 | u64 dct_sel_base_off = (pvt->dct_sel_hi & 0xFFFFFC00) << 16; |
6163b5d4 | 1325 | |
c8e518d5 BP |
1326 | if (hi_rng) { |
1327 | /* | |
1328 | * if | |
1329 | * base address of high range is below 4Gb | |
1330 | * (bits [47:27] at [31:11]) | |
1331 | * DRAM address space on this DCT is hoisted above 4Gb && | |
1332 | * sys_addr > 4Gb | |
1333 | * | |
1334 | * remove hole offset from sys_addr | |
1335 | * else | |
1336 | * remove high range offset from sys_addr | |
1337 | */ | |
1338 | if ((!(dct_sel_base_addr >> 16) || | |
1339 | dct_sel_base_addr < dhar_base(pvt)) && | |
972ea17a | 1340 | dhar_valid(pvt) && |
c8e518d5 | 1341 | (sys_addr >= BIT_64(32))) |
bc21fa57 | 1342 | chan_off = hole_off; |
6163b5d4 DT |
1343 | else |
1344 | chan_off = dct_sel_base_off; | |
1345 | } else { | |
c8e518d5 BP |
1346 | /* |
1347 | * if | |
1348 | * we have a valid hole && | |
1349 | * sys_addr > 4Gb | |
1350 | * | |
1351 | * remove hole | |
1352 | * else | |
1353 | * remove dram base to normalize to DCT address | |
1354 | */ | |
972ea17a | 1355 | if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) |
bc21fa57 | 1356 | chan_off = hole_off; |
6163b5d4 | 1357 | else |
c8e518d5 | 1358 | chan_off = dram_base; |
6163b5d4 DT |
1359 | } |
1360 | ||
c8e518d5 | 1361 | return (sys_addr & GENMASK(6,47)) - (chan_off & GENMASK(23,47)); |
6163b5d4 DT |
1362 | } |
1363 | ||
6163b5d4 DT |
1364 | /* |
1365 | * checks if the csrow passed in is marked as SPARED, if so returns the new | |
1366 | * spare row | |
1367 | */ | |
11c75ead | 1368 | static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) |
6163b5d4 | 1369 | { |
614ec9d8 BP |
1370 | int tmp_cs; |
1371 | ||
1372 | if (online_spare_swap_done(pvt, dct) && | |
1373 | csrow == online_spare_bad_dramcs(pvt, dct)) { | |
1374 | ||
1375 | for_each_chip_select(tmp_cs, dct, pvt) { | |
1376 | if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { | |
1377 | csrow = tmp_cs; | |
1378 | break; | |
1379 | } | |
1380 | } | |
6163b5d4 DT |
1381 | } |
1382 | return csrow; | |
1383 | } | |
1384 | ||
1385 | /* | |
1386 | * Iterate over the DRAM DCT "base" and "mask" registers looking for a | |
1387 | * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' | |
1388 | * | |
1389 | * Return: | |
1390 | * -EINVAL: NOT FOUND | |
1391 | * 0..csrow = Chip-Select Row | |
1392 | */ | |
b15f0fca | 1393 | static int f1x_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct) |
6163b5d4 DT |
1394 | { |
1395 | struct mem_ctl_info *mci; | |
1396 | struct amd64_pvt *pvt; | |
11c75ead | 1397 | u64 cs_base, cs_mask; |
6163b5d4 DT |
1398 | int cs_found = -EINVAL; |
1399 | int csrow; | |
1400 | ||
cc4d8860 | 1401 | mci = mcis[nid]; |
6163b5d4 DT |
1402 | if (!mci) |
1403 | return cs_found; | |
1404 | ||
1405 | pvt = mci->pvt_info; | |
1406 | ||
11c75ead | 1407 | debugf1("input addr: 0x%llx, DCT: %d\n", in_addr, dct); |
6163b5d4 | 1408 | |
11c75ead BP |
1409 | for_each_chip_select(csrow, dct, pvt) { |
1410 | if (!csrow_enabled(csrow, dct, pvt)) | |
6163b5d4 DT |
1411 | continue; |
1412 | ||
11c75ead | 1413 | get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); |
6163b5d4 | 1414 | |
11c75ead BP |
1415 | debugf1(" CSROW=%d CSBase=0x%llx CSMask=0x%llx\n", |
1416 | csrow, cs_base, cs_mask); | |
6163b5d4 | 1417 | |
11c75ead | 1418 | cs_mask = ~cs_mask; |
6163b5d4 | 1419 | |
11c75ead BP |
1420 | debugf1(" (InputAddr & ~CSMask)=0x%llx " |
1421 | "(CSBase & ~CSMask)=0x%llx\n", | |
1422 | (in_addr & cs_mask), (cs_base & cs_mask)); | |
6163b5d4 | 1423 | |
11c75ead BP |
1424 | if ((in_addr & cs_mask) == (cs_base & cs_mask)) { |
1425 | cs_found = f10_process_possible_spare(pvt, dct, csrow); | |
6163b5d4 DT |
1426 | |
1427 | debugf1(" MATCH csrow=%d\n", cs_found); | |
1428 | break; | |
1429 | } | |
1430 | } | |
1431 | return cs_found; | |
1432 | } | |
1433 | ||
95b0ef55 BP |
1434 | /* |
1435 | * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is | |
1436 | * swapped with a region located at the bottom of memory so that the GPU can use | |
1437 | * the interleaved region and thus two channels. | |
1438 | */ | |
b15f0fca | 1439 | static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) |
95b0ef55 BP |
1440 | { |
1441 | u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr; | |
1442 | ||
1443 | if (boot_cpu_data.x86 == 0x10) { | |
1444 | /* only revC3 and revE have that feature */ | |
1445 | if (boot_cpu_data.x86_model < 4 || | |
1446 | (boot_cpu_data.x86_model < 0xa && | |
1447 | boot_cpu_data.x86_mask < 3)) | |
1448 | return sys_addr; | |
1449 | } | |
1450 | ||
1451 | amd64_read_dct_pci_cfg(pvt, SWAP_INTLV_REG, &swap_reg); | |
1452 | ||
1453 | if (!(swap_reg & 0x1)) | |
1454 | return sys_addr; | |
1455 | ||
1456 | swap_base = (swap_reg >> 3) & 0x7f; | |
1457 | swap_limit = (swap_reg >> 11) & 0x7f; | |
1458 | rgn_size = (swap_reg >> 20) & 0x7f; | |
1459 | tmp_addr = sys_addr >> 27; | |
1460 | ||
1461 | if (!(sys_addr >> 34) && | |
1462 | (((tmp_addr >= swap_base) && | |
1463 | (tmp_addr <= swap_limit)) || | |
1464 | (tmp_addr < rgn_size))) | |
1465 | return sys_addr ^ (u64)swap_base << 27; | |
1466 | ||
1467 | return sys_addr; | |
1468 | } | |
1469 | ||
f71d0a05 | 1470 | /* For a given @dram_range, check if @sys_addr falls within it. */ |
e761359a | 1471 | static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, |
f71d0a05 DT |
1472 | u64 sys_addr, int *nid, int *chan_sel) |
1473 | { | |
229a7a11 | 1474 | int cs_found = -EINVAL; |
c8e518d5 | 1475 | u64 chan_addr; |
5d4b58e8 | 1476 | u32 dct_sel_base; |
11c75ead | 1477 | u8 channel; |
229a7a11 | 1478 | bool high_range = false; |
f71d0a05 | 1479 | |
7f19bf75 | 1480 | u8 node_id = dram_dst_node(pvt, range); |
229a7a11 | 1481 | u8 intlv_en = dram_intlv_en(pvt, range); |
7f19bf75 | 1482 | u32 intlv_sel = dram_intlv_sel(pvt, range); |
f71d0a05 | 1483 | |
c8e518d5 BP |
1484 | debugf1("(range %d) SystemAddr= 0x%llx Limit=0x%llx\n", |
1485 | range, sys_addr, get_dram_limit(pvt, range)); | |
f71d0a05 | 1486 | |
355fba60 BP |
1487 | if (dhar_valid(pvt) && |
1488 | dhar_base(pvt) <= sys_addr && | |
1489 | sys_addr < BIT_64(32)) { | |
1490 | amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n", | |
1491 | sys_addr); | |
1492 | return -EINVAL; | |
1493 | } | |
1494 | ||
f030ddfb | 1495 | if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en))) |
f71d0a05 DT |
1496 | return -EINVAL; |
1497 | ||
b15f0fca | 1498 | sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); |
95b0ef55 | 1499 | |
f71d0a05 DT |
1500 | dct_sel_base = dct_sel_baseaddr(pvt); |
1501 | ||
1502 | /* | |
1503 | * check whether addresses >= DctSelBaseAddr[47:27] are to be used to | |
1504 | * select between DCT0 and DCT1. | |
1505 | */ | |
1506 | if (dct_high_range_enabled(pvt) && | |
1507 | !dct_ganging_enabled(pvt) && | |
1508 | ((sys_addr >> 27) >= (dct_sel_base >> 11))) | |
229a7a11 | 1509 | high_range = true; |
f71d0a05 | 1510 | |
b15f0fca | 1511 | channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); |
f71d0a05 | 1512 | |
b15f0fca | 1513 | chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, |
c8e518d5 | 1514 | high_range, dct_sel_base); |
f71d0a05 | 1515 | |
e2f79dbd BP |
1516 | /* Remove node interleaving, see F1x120 */ |
1517 | if (intlv_en) | |
1518 | chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) | | |
1519 | (chan_addr & 0xfff); | |
f71d0a05 | 1520 | |
5d4b58e8 | 1521 | /* remove channel interleave */ |
f71d0a05 DT |
1522 | if (dct_interleave_enabled(pvt) && |
1523 | !dct_high_range_enabled(pvt) && | |
1524 | !dct_ganging_enabled(pvt)) { | |
5d4b58e8 BP |
1525 | |
1526 | if (dct_sel_interleave_addr(pvt) != 1) { | |
1527 | if (dct_sel_interleave_addr(pvt) == 0x3) | |
1528 | /* hash 9 */ | |
1529 | chan_addr = ((chan_addr >> 10) << 9) | | |
1530 | (chan_addr & 0x1ff); | |
1531 | else | |
1532 | /* A[6] or hash 6 */ | |
1533 | chan_addr = ((chan_addr >> 7) << 6) | | |
1534 | (chan_addr & 0x3f); | |
1535 | } else | |
1536 | /* A[12] */ | |
1537 | chan_addr = ((chan_addr >> 13) << 12) | | |
1538 | (chan_addr & 0xfff); | |
f71d0a05 DT |
1539 | } |
1540 | ||
5d4b58e8 | 1541 | debugf1(" Normalized DCT addr: 0x%llx\n", chan_addr); |
f71d0a05 | 1542 | |
b15f0fca | 1543 | cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel); |
f71d0a05 DT |
1544 | |
1545 | if (cs_found >= 0) { | |
1546 | *nid = node_id; | |
1547 | *chan_sel = channel; | |
1548 | } | |
1549 | return cs_found; | |
1550 | } | |
1551 | ||
b15f0fca | 1552 | static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr, |
f71d0a05 DT |
1553 | int *node, int *chan_sel) |
1554 | { | |
e761359a BP |
1555 | int cs_found = -EINVAL; |
1556 | unsigned range; | |
f71d0a05 | 1557 | |
7f19bf75 | 1558 | for (range = 0; range < DRAM_RANGES; range++) { |
f71d0a05 | 1559 | |
7f19bf75 | 1560 | if (!dram_rw(pvt, range)) |
f71d0a05 DT |
1561 | continue; |
1562 | ||
7f19bf75 BP |
1563 | if ((get_dram_base(pvt, range) <= sys_addr) && |
1564 | (get_dram_limit(pvt, range) >= sys_addr)) { | |
f71d0a05 | 1565 | |
b15f0fca | 1566 | cs_found = f1x_match_to_this_node(pvt, range, |
f71d0a05 DT |
1567 | sys_addr, node, |
1568 | chan_sel); | |
1569 | if (cs_found >= 0) | |
1570 | break; | |
1571 | } | |
1572 | } | |
1573 | return cs_found; | |
1574 | } | |
1575 | ||
1576 | /* | |
bdc30a0c BP |
1577 | * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps |
1578 | * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW). | |
f71d0a05 | 1579 | * |
bdc30a0c BP |
1580 | * The @sys_addr is usually an error address received from the hardware |
1581 | * (MCX_ADDR). | |
f71d0a05 | 1582 | */ |
b15f0fca | 1583 | static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, |
f192c7b1 | 1584 | u16 syndrome) |
f71d0a05 DT |
1585 | { |
1586 | struct amd64_pvt *pvt = mci->pvt_info; | |
1587 | u32 page, offset; | |
f71d0a05 DT |
1588 | int nid, csrow, chan = 0; |
1589 | ||
b15f0fca | 1590 | csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan); |
f71d0a05 | 1591 | |
bdc30a0c BP |
1592 | if (csrow < 0) { |
1593 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1594 | return; | |
1595 | } | |
1596 | ||
1597 | error_address_to_page_and_offset(sys_addr, &page, &offset); | |
f71d0a05 | 1598 | |
bdc30a0c BP |
1599 | /* |
1600 | * We need the syndromes for channel detection only when we're | |
1601 | * ganged. Otherwise @chan should already contain the channel at | |
1602 | * this point. | |
1603 | */ | |
a97fa68e | 1604 | if (dct_ganging_enabled(pvt)) |
bdc30a0c | 1605 | chan = get_channel_from_ecc_syndrome(mci, syndrome); |
f71d0a05 | 1606 | |
bdc30a0c BP |
1607 | if (chan >= 0) |
1608 | edac_mc_handle_ce(mci, page, offset, syndrome, csrow, chan, | |
1609 | EDAC_MOD_STR); | |
1610 | else | |
f71d0a05 | 1611 | /* |
bdc30a0c | 1612 | * Channel unknown, report all channels on this CSROW as failed. |
f71d0a05 | 1613 | */ |
bdc30a0c | 1614 | for (chan = 0; chan < mci->csrows[csrow].nr_channels; chan++) |
f71d0a05 | 1615 | edac_mc_handle_ce(mci, page, offset, syndrome, |
bdc30a0c | 1616 | csrow, chan, EDAC_MOD_STR); |
f71d0a05 DT |
1617 | } |
1618 | ||
f71d0a05 | 1619 | /* |
8566c4df | 1620 | * debug routine to display the memory sizes of all logical DIMMs and its |
cb328507 | 1621 | * CSROWs |
f71d0a05 | 1622 | */ |
8c671751 | 1623 | static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) |
f71d0a05 | 1624 | { |
603adaf6 | 1625 | int dimm, size0, size1, factor = 0; |
525a1b20 BP |
1626 | u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; |
1627 | u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; | |
f71d0a05 | 1628 | |
8566c4df | 1629 | if (boot_cpu_data.x86 == 0xf) { |
41d8bfab | 1630 | if (pvt->dclr0 & WIDTH_128) |
603adaf6 BP |
1631 | factor = 1; |
1632 | ||
8566c4df | 1633 | /* K8 families < revF not supported yet */ |
1433eb99 | 1634 | if (pvt->ext_model < K8_REV_F) |
8566c4df BP |
1635 | return; |
1636 | else | |
1637 | WARN_ON(ctrl != 0); | |
1638 | } | |
1639 | ||
4d796364 | 1640 | dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 : pvt->dbam0; |
11c75ead BP |
1641 | dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases |
1642 | : pvt->csels[0].csbases; | |
f71d0a05 | 1643 | |
4d796364 | 1644 | debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", ctrl, dbam); |
f71d0a05 | 1645 | |
8566c4df BP |
1646 | edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl); |
1647 | ||
f71d0a05 DT |
1648 | /* Dump memory sizes for DIMM and its CSROWs */ |
1649 | for (dimm = 0; dimm < 4; dimm++) { | |
1650 | ||
1651 | size0 = 0; | |
11c75ead | 1652 | if (dcsb[dimm*2] & DCSB_CS_ENABLE) |
41d8bfab BP |
1653 | size0 = pvt->ops->dbam_to_cs(pvt, ctrl, |
1654 | DBAM_DIMM(dimm, dbam)); | |
f71d0a05 DT |
1655 | |
1656 | size1 = 0; | |
11c75ead | 1657 | if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE) |
41d8bfab BP |
1658 | size1 = pvt->ops->dbam_to_cs(pvt, ctrl, |
1659 | DBAM_DIMM(dimm, dbam)); | |
f71d0a05 | 1660 | |
24f9a7fe BP |
1661 | amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n", |
1662 | dimm * 2, size0 << factor, | |
1663 | dimm * 2 + 1, size1 << factor); | |
f71d0a05 DT |
1664 | } |
1665 | } | |
1666 | ||
4d37607a DT |
1667 | static struct amd64_family_type amd64_family_types[] = { |
1668 | [K8_CPUS] = { | |
0092b20d | 1669 | .ctl_name = "K8", |
8d5b5d9c BP |
1670 | .f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, |
1671 | .f3_id = PCI_DEVICE_ID_AMD_K8_NB_MISC, | |
4d37607a | 1672 | .ops = { |
1433eb99 | 1673 | .early_channel_count = k8_early_channel_count, |
1433eb99 BP |
1674 | .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, |
1675 | .dbam_to_cs = k8_dbam_to_chip_select, | |
b2b0c605 | 1676 | .read_dct_pci_cfg = k8_read_dct_pci_cfg, |
4d37607a DT |
1677 | } |
1678 | }, | |
1679 | [F10_CPUS] = { | |
0092b20d | 1680 | .ctl_name = "F10h", |
8d5b5d9c BP |
1681 | .f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP, |
1682 | .f3_id = PCI_DEVICE_ID_AMD_10H_NB_MISC, | |
4d37607a | 1683 | .ops = { |
7d20d14d | 1684 | .early_channel_count = f1x_early_channel_count, |
b15f0fca | 1685 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, |
1433eb99 | 1686 | .dbam_to_cs = f10_dbam_to_chip_select, |
b2b0c605 BP |
1687 | .read_dct_pci_cfg = f10_read_dct_pci_cfg, |
1688 | } | |
1689 | }, | |
1690 | [F15_CPUS] = { | |
1691 | .ctl_name = "F15h", | |
df71a053 BP |
1692 | .f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1, |
1693 | .f3_id = PCI_DEVICE_ID_AMD_15H_NB_F3, | |
b2b0c605 | 1694 | .ops = { |
7d20d14d | 1695 | .early_channel_count = f1x_early_channel_count, |
b15f0fca | 1696 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, |
41d8bfab | 1697 | .dbam_to_cs = f15_dbam_to_chip_select, |
b2b0c605 | 1698 | .read_dct_pci_cfg = f15_read_dct_pci_cfg, |
4d37607a DT |
1699 | } |
1700 | }, | |
4d37607a DT |
1701 | }; |
1702 | ||
1703 | static struct pci_dev *pci_get_related_function(unsigned int vendor, | |
1704 | unsigned int device, | |
1705 | struct pci_dev *related) | |
1706 | { | |
1707 | struct pci_dev *dev = NULL; | |
1708 | ||
1709 | dev = pci_get_device(vendor, device, dev); | |
1710 | while (dev) { | |
1711 | if ((dev->bus->number == related->bus->number) && | |
1712 | (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) | |
1713 | break; | |
1714 | dev = pci_get_device(vendor, device, dev); | |
1715 | } | |
1716 | ||
1717 | return dev; | |
1718 | } | |
1719 | ||
b1289d6f | 1720 | /* |
bfc04aec BP |
1721 | * These are tables of eigenvectors (one per line) which can be used for the |
1722 | * construction of the syndrome tables. The modified syndrome search algorithm | |
1723 | * uses those to find the symbol in error and thus the DIMM. | |
b1289d6f | 1724 | * |
bfc04aec | 1725 | * Algorithm courtesy of Ross LaFetra from AMD. |
b1289d6f | 1726 | */ |
bfc04aec BP |
1727 | static u16 x4_vectors[] = { |
1728 | 0x2f57, 0x1afe, 0x66cc, 0xdd88, | |
1729 | 0x11eb, 0x3396, 0x7f4c, 0xeac8, | |
1730 | 0x0001, 0x0002, 0x0004, 0x0008, | |
1731 | 0x1013, 0x3032, 0x4044, 0x8088, | |
1732 | 0x106b, 0x30d6, 0x70fc, 0xe0a8, | |
1733 | 0x4857, 0xc4fe, 0x13cc, 0x3288, | |
1734 | 0x1ac5, 0x2f4a, 0x5394, 0xa1e8, | |
1735 | 0x1f39, 0x251e, 0xbd6c, 0x6bd8, | |
1736 | 0x15c1, 0x2a42, 0x89ac, 0x4758, | |
1737 | 0x2b03, 0x1602, 0x4f0c, 0xca08, | |
1738 | 0x1f07, 0x3a0e, 0x6b04, 0xbd08, | |
1739 | 0x8ba7, 0x465e, 0x244c, 0x1cc8, | |
1740 | 0x2b87, 0x164e, 0x642c, 0xdc18, | |
1741 | 0x40b9, 0x80de, 0x1094, 0x20e8, | |
1742 | 0x27db, 0x1eb6, 0x9dac, 0x7b58, | |
1743 | 0x11c1, 0x2242, 0x84ac, 0x4c58, | |
1744 | 0x1be5, 0x2d7a, 0x5e34, 0xa718, | |
1745 | 0x4b39, 0x8d1e, 0x14b4, 0x28d8, | |
1746 | 0x4c97, 0xc87e, 0x11fc, 0x33a8, | |
1747 | 0x8e97, 0x497e, 0x2ffc, 0x1aa8, | |
1748 | 0x16b3, 0x3d62, 0x4f34, 0x8518, | |
1749 | 0x1e2f, 0x391a, 0x5cac, 0xf858, | |
1750 | 0x1d9f, 0x3b7a, 0x572c, 0xfe18, | |
1751 | 0x15f5, 0x2a5a, 0x5264, 0xa3b8, | |
1752 | 0x1dbb, 0x3b66, 0x715c, 0xe3f8, | |
1753 | 0x4397, 0xc27e, 0x17fc, 0x3ea8, | |
1754 | 0x1617, 0x3d3e, 0x6464, 0xb8b8, | |
1755 | 0x23ff, 0x12aa, 0xab6c, 0x56d8, | |
1756 | 0x2dfb, 0x1ba6, 0x913c, 0x7328, | |
1757 | 0x185d, 0x2ca6, 0x7914, 0x9e28, | |
1758 | 0x171b, 0x3e36, 0x7d7c, 0xebe8, | |
1759 | 0x4199, 0x82ee, 0x19f4, 0x2e58, | |
1760 | 0x4807, 0xc40e, 0x130c, 0x3208, | |
1761 | 0x1905, 0x2e0a, 0x5804, 0xac08, | |
1762 | 0x213f, 0x132a, 0xadfc, 0x5ba8, | |
1763 | 0x19a9, 0x2efe, 0xb5cc, 0x6f88, | |
b1289d6f DT |
1764 | }; |
1765 | ||
bfc04aec BP |
1766 | static u16 x8_vectors[] = { |
1767 | 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480, | |
1768 | 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80, | |
1769 | 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80, | |
1770 | 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80, | |
1771 | 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780, | |
1772 | 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080, | |
1773 | 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080, | |
1774 | 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080, | |
1775 | 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80, | |
1776 | 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580, | |
1777 | 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880, | |
1778 | 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280, | |
1779 | 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180, | |
1780 | 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580, | |
1781 | 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280, | |
1782 | 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180, | |
1783 | 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080, | |
1784 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
1785 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, | |
1786 | }; | |
1787 | ||
d34a6ecd BP |
1788 | static int decode_syndrome(u16 syndrome, u16 *vectors, unsigned num_vecs, |
1789 | unsigned v_dim) | |
b1289d6f | 1790 | { |
bfc04aec BP |
1791 | unsigned int i, err_sym; |
1792 | ||
1793 | for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) { | |
1794 | u16 s = syndrome; | |
d34a6ecd BP |
1795 | unsigned v_idx = err_sym * v_dim; |
1796 | unsigned v_end = (err_sym + 1) * v_dim; | |
bfc04aec BP |
1797 | |
1798 | /* walk over all 16 bits of the syndrome */ | |
1799 | for (i = 1; i < (1U << 16); i <<= 1) { | |
1800 | ||
1801 | /* if bit is set in that eigenvector... */ | |
1802 | if (v_idx < v_end && vectors[v_idx] & i) { | |
1803 | u16 ev_comp = vectors[v_idx++]; | |
1804 | ||
1805 | /* ... and bit set in the modified syndrome, */ | |
1806 | if (s & i) { | |
1807 | /* remove it. */ | |
1808 | s ^= ev_comp; | |
4d37607a | 1809 | |
bfc04aec BP |
1810 | if (!s) |
1811 | return err_sym; | |
1812 | } | |
b1289d6f | 1813 | |
bfc04aec BP |
1814 | } else if (s & i) |
1815 | /* can't get to zero, move to next symbol */ | |
1816 | break; | |
1817 | } | |
b1289d6f DT |
1818 | } |
1819 | ||
1820 | debugf0("syndrome(%x) not found\n", syndrome); | |
1821 | return -1; | |
1822 | } | |
d27bf6fa | 1823 | |
bfc04aec BP |
1824 | static int map_err_sym_to_channel(int err_sym, int sym_size) |
1825 | { | |
1826 | if (sym_size == 4) | |
1827 | switch (err_sym) { | |
1828 | case 0x20: | |
1829 | case 0x21: | |
1830 | return 0; | |
1831 | break; | |
1832 | case 0x22: | |
1833 | case 0x23: | |
1834 | return 1; | |
1835 | break; | |
1836 | default: | |
1837 | return err_sym >> 4; | |
1838 | break; | |
1839 | } | |
1840 | /* x8 symbols */ | |
1841 | else | |
1842 | switch (err_sym) { | |
1843 | /* imaginary bits not in a DIMM */ | |
1844 | case 0x10: | |
1845 | WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n", | |
1846 | err_sym); | |
1847 | return -1; | |
1848 | break; | |
1849 | ||
1850 | case 0x11: | |
1851 | return 0; | |
1852 | break; | |
1853 | case 0x12: | |
1854 | return 1; | |
1855 | break; | |
1856 | default: | |
1857 | return err_sym >> 3; | |
1858 | break; | |
1859 | } | |
1860 | return -1; | |
1861 | } | |
1862 | ||
1863 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome) | |
1864 | { | |
1865 | struct amd64_pvt *pvt = mci->pvt_info; | |
ad6a32e9 BP |
1866 | int err_sym = -1; |
1867 | ||
a3b7db09 | 1868 | if (pvt->ecc_sym_sz == 8) |
ad6a32e9 BP |
1869 | err_sym = decode_syndrome(syndrome, x8_vectors, |
1870 | ARRAY_SIZE(x8_vectors), | |
a3b7db09 BP |
1871 | pvt->ecc_sym_sz); |
1872 | else if (pvt->ecc_sym_sz == 4) | |
ad6a32e9 BP |
1873 | err_sym = decode_syndrome(syndrome, x4_vectors, |
1874 | ARRAY_SIZE(x4_vectors), | |
a3b7db09 | 1875 | pvt->ecc_sym_sz); |
ad6a32e9 | 1876 | else { |
a3b7db09 | 1877 | amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); |
ad6a32e9 | 1878 | return err_sym; |
bfc04aec | 1879 | } |
ad6a32e9 | 1880 | |
a3b7db09 | 1881 | return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); |
bfc04aec BP |
1882 | } |
1883 | ||
d27bf6fa DT |
1884 | /* |
1885 | * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR | |
1886 | * ADDRESS and process. | |
1887 | */ | |
f192c7b1 | 1888 | static void amd64_handle_ce(struct mem_ctl_info *mci, struct mce *m) |
d27bf6fa DT |
1889 | { |
1890 | struct amd64_pvt *pvt = mci->pvt_info; | |
44e9e2ee | 1891 | u64 sys_addr; |
f192c7b1 | 1892 | u16 syndrome; |
d27bf6fa DT |
1893 | |
1894 | /* Ensure that the Error Address is VALID */ | |
f192c7b1 | 1895 | if (!(m->status & MCI_STATUS_ADDRV)) { |
24f9a7fe | 1896 | amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n"); |
d27bf6fa DT |
1897 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); |
1898 | return; | |
1899 | } | |
1900 | ||
70046624 | 1901 | sys_addr = get_error_address(m); |
f192c7b1 | 1902 | syndrome = extract_syndrome(m->status); |
d27bf6fa | 1903 | |
24f9a7fe | 1904 | amd64_mc_err(mci, "CE ERROR_ADDRESS= 0x%llx\n", sys_addr); |
d27bf6fa | 1905 | |
f192c7b1 | 1906 | pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, syndrome); |
d27bf6fa DT |
1907 | } |
1908 | ||
1909 | /* Handle any Un-correctable Errors (UEs) */ | |
f192c7b1 | 1910 | static void amd64_handle_ue(struct mem_ctl_info *mci, struct mce *m) |
d27bf6fa | 1911 | { |
1f6bcee7 | 1912 | struct mem_ctl_info *log_mci, *src_mci = NULL; |
d27bf6fa | 1913 | int csrow; |
44e9e2ee | 1914 | u64 sys_addr; |
d27bf6fa | 1915 | u32 page, offset; |
d27bf6fa DT |
1916 | |
1917 | log_mci = mci; | |
1918 | ||
f192c7b1 | 1919 | if (!(m->status & MCI_STATUS_ADDRV)) { |
24f9a7fe | 1920 | amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n"); |
d27bf6fa DT |
1921 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); |
1922 | return; | |
1923 | } | |
1924 | ||
70046624 | 1925 | sys_addr = get_error_address(m); |
d27bf6fa DT |
1926 | |
1927 | /* | |
1928 | * Find out which node the error address belongs to. This may be | |
1929 | * different from the node that detected the error. | |
1930 | */ | |
44e9e2ee | 1931 | src_mci = find_mc_by_sys_addr(mci, sys_addr); |
d27bf6fa | 1932 | if (!src_mci) { |
24f9a7fe BP |
1933 | amd64_mc_err(mci, "ERROR ADDRESS (0x%lx) NOT mapped to a MC\n", |
1934 | (unsigned long)sys_addr); | |
d27bf6fa DT |
1935 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); |
1936 | return; | |
1937 | } | |
1938 | ||
1939 | log_mci = src_mci; | |
1940 | ||
44e9e2ee | 1941 | csrow = sys_addr_to_csrow(log_mci, sys_addr); |
d27bf6fa | 1942 | if (csrow < 0) { |
24f9a7fe BP |
1943 | amd64_mc_err(mci, "ERROR_ADDRESS (0x%lx) NOT mapped to CS\n", |
1944 | (unsigned long)sys_addr); | |
d27bf6fa DT |
1945 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); |
1946 | } else { | |
44e9e2ee | 1947 | error_address_to_page_and_offset(sys_addr, &page, &offset); |
d27bf6fa DT |
1948 | edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR); |
1949 | } | |
1950 | } | |
1951 | ||
549d042d | 1952 | static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, |
f192c7b1 | 1953 | struct mce *m) |
d27bf6fa | 1954 | { |
f192c7b1 BP |
1955 | u16 ec = EC(m->status); |
1956 | u8 xec = XEC(m->status, 0x1f); | |
1957 | u8 ecc_type = (m->status >> 45) & 0x3; | |
d27bf6fa | 1958 | |
b70ef010 | 1959 | /* Bail early out if this was an 'observed' error */ |
5980bb9c | 1960 | if (PP(ec) == NBSL_PP_OBS) |
b70ef010 | 1961 | return; |
d27bf6fa | 1962 | |
ecaf5606 BP |
1963 | /* Do only ECC errors */ |
1964 | if (xec && xec != F10_NBSL_EXT_ERR_ECC) | |
d27bf6fa | 1965 | return; |
d27bf6fa | 1966 | |
ecaf5606 | 1967 | if (ecc_type == 2) |
f192c7b1 | 1968 | amd64_handle_ce(mci, m); |
ecaf5606 | 1969 | else if (ecc_type == 1) |
f192c7b1 | 1970 | amd64_handle_ue(mci, m); |
d27bf6fa DT |
1971 | } |
1972 | ||
b0b07a2b | 1973 | void amd64_decode_bus_error(int node_id, struct mce *m) |
d27bf6fa | 1974 | { |
b0b07a2b | 1975 | __amd64_decode_bus_error(mcis[node_id], m); |
d27bf6fa | 1976 | } |
d27bf6fa | 1977 | |
0ec449ee | 1978 | /* |
8d5b5d9c | 1979 | * Use pvt->F2 which contains the F2 CPU PCI device to get the related |
bbd0c1f6 | 1980 | * F1 (AddrMap) and F3 (Misc) devices. Return negative value on error. |
0ec449ee | 1981 | */ |
360b7f3c | 1982 | static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id) |
0ec449ee | 1983 | { |
0ec449ee | 1984 | /* Reserve the ADDRESS MAP Device */ |
8d5b5d9c BP |
1985 | pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2); |
1986 | if (!pvt->F1) { | |
24f9a7fe BP |
1987 | amd64_err("error address map device not found: " |
1988 | "vendor %x device 0x%x (broken BIOS?)\n", | |
1989 | PCI_VENDOR_ID_AMD, f1_id); | |
bbd0c1f6 | 1990 | return -ENODEV; |
0ec449ee DT |
1991 | } |
1992 | ||
1993 | /* Reserve the MISC Device */ | |
8d5b5d9c BP |
1994 | pvt->F3 = pci_get_related_function(pvt->F2->vendor, f3_id, pvt->F2); |
1995 | if (!pvt->F3) { | |
1996 | pci_dev_put(pvt->F1); | |
1997 | pvt->F1 = NULL; | |
0ec449ee | 1998 | |
24f9a7fe BP |
1999 | amd64_err("error F3 device not found: " |
2000 | "vendor %x device 0x%x (broken BIOS?)\n", | |
2001 | PCI_VENDOR_ID_AMD, f3_id); | |
0ec449ee | 2002 | |
bbd0c1f6 | 2003 | return -ENODEV; |
0ec449ee | 2004 | } |
8d5b5d9c BP |
2005 | debugf1("F1: %s\n", pci_name(pvt->F1)); |
2006 | debugf1("F2: %s\n", pci_name(pvt->F2)); | |
2007 | debugf1("F3: %s\n", pci_name(pvt->F3)); | |
0ec449ee DT |
2008 | |
2009 | return 0; | |
2010 | } | |
2011 | ||
360b7f3c | 2012 | static void free_mc_sibling_devs(struct amd64_pvt *pvt) |
0ec449ee | 2013 | { |
8d5b5d9c BP |
2014 | pci_dev_put(pvt->F1); |
2015 | pci_dev_put(pvt->F3); | |
0ec449ee DT |
2016 | } |
2017 | ||
2018 | /* | |
2019 | * Retrieve the hardware registers of the memory controller (this includes the | |
2020 | * 'Address Map' and 'Misc' device regs) | |
2021 | */ | |
360b7f3c | 2022 | static void read_mc_regs(struct amd64_pvt *pvt) |
0ec449ee | 2023 | { |
a3b7db09 | 2024 | struct cpuinfo_x86 *c = &boot_cpu_data; |
0ec449ee | 2025 | u64 msr_val; |
ad6a32e9 | 2026 | u32 tmp; |
e761359a | 2027 | unsigned range; |
0ec449ee DT |
2028 | |
2029 | /* | |
2030 | * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since | |
2031 | * those are Read-As-Zero | |
2032 | */ | |
e97f8bb8 BP |
2033 | rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); |
2034 | debugf0(" TOP_MEM: 0x%016llx\n", pvt->top_mem); | |
0ec449ee DT |
2035 | |
2036 | /* check first whether TOP_MEM2 is enabled */ | |
2037 | rdmsrl(MSR_K8_SYSCFG, msr_val); | |
2038 | if (msr_val & (1U << 21)) { | |
e97f8bb8 BP |
2039 | rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); |
2040 | debugf0(" TOP_MEM2: 0x%016llx\n", pvt->top_mem2); | |
0ec449ee DT |
2041 | } else |
2042 | debugf0(" TOP_MEM2 disabled.\n"); | |
2043 | ||
5980bb9c | 2044 | amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); |
0ec449ee | 2045 | |
5a5d2371 | 2046 | read_dram_ctl_register(pvt); |
0ec449ee | 2047 | |
7f19bf75 BP |
2048 | for (range = 0; range < DRAM_RANGES; range++) { |
2049 | u8 rw; | |
0ec449ee | 2050 | |
7f19bf75 BP |
2051 | /* read settings for this DRAM range */ |
2052 | read_dram_base_limit_regs(pvt, range); | |
2053 | ||
2054 | rw = dram_rw(pvt, range); | |
2055 | if (!rw) | |
2056 | continue; | |
2057 | ||
2058 | debugf1(" DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n", | |
2059 | range, | |
2060 | get_dram_base(pvt, range), | |
2061 | get_dram_limit(pvt, range)); | |
2062 | ||
2063 | debugf1(" IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n", | |
2064 | dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", | |
2065 | (rw & 0x1) ? "R" : "-", | |
2066 | (rw & 0x2) ? "W" : "-", | |
2067 | dram_intlv_sel(pvt, range), | |
2068 | dram_dst_node(pvt, range)); | |
0ec449ee DT |
2069 | } |
2070 | ||
b2b0c605 | 2071 | read_dct_base_mask(pvt); |
0ec449ee | 2072 | |
bc21fa57 | 2073 | amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); |
525a1b20 | 2074 | amd64_read_dct_pci_cfg(pvt, DBAM0, &pvt->dbam0); |
0ec449ee | 2075 | |
8d5b5d9c | 2076 | amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); |
0ec449ee | 2077 | |
cb328507 BP |
2078 | amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0); |
2079 | amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0); | |
0ec449ee | 2080 | |
78da121e | 2081 | if (!dct_ganging_enabled(pvt)) { |
cb328507 BP |
2082 | amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1); |
2083 | amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1); | |
0ec449ee | 2084 | } |
ad6a32e9 | 2085 | |
a3b7db09 BP |
2086 | pvt->ecc_sym_sz = 4; |
2087 | ||
2088 | if (c->x86 >= 0x10) { | |
b2b0c605 | 2089 | amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); |
525a1b20 | 2090 | amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1); |
ad6a32e9 | 2091 | |
a3b7db09 BP |
2092 | /* F10h, revD and later can do x8 ECC too */ |
2093 | if ((c->x86 > 0x10 || c->x86_model > 7) && tmp & BIT(25)) | |
2094 | pvt->ecc_sym_sz = 8; | |
2095 | } | |
b2b0c605 | 2096 | dump_misc_regs(pvt); |
0ec449ee DT |
2097 | } |
2098 | ||
2099 | /* | |
2100 | * NOTE: CPU Revision Dependent code | |
2101 | * | |
2102 | * Input: | |
11c75ead | 2103 | * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1) |
0ec449ee DT |
2104 | * k8 private pointer to --> |
2105 | * DRAM Bank Address mapping register | |
2106 | * node_id | |
2107 | * DCL register where dual_channel_active is | |
2108 | * | |
2109 | * The DBAM register consists of 4 sets of 4 bits each definitions: | |
2110 | * | |
2111 | * Bits: CSROWs | |
2112 | * 0-3 CSROWs 0 and 1 | |
2113 | * 4-7 CSROWs 2 and 3 | |
2114 | * 8-11 CSROWs 4 and 5 | |
2115 | * 12-15 CSROWs 6 and 7 | |
2116 | * | |
2117 | * Values range from: 0 to 15 | |
2118 | * The meaning of the values depends on CPU revision and dual-channel state, | |
2119 | * see relevant BKDG more info. | |
2120 | * | |
2121 | * The memory controller provides for total of only 8 CSROWs in its current | |
2122 | * architecture. Each "pair" of CSROWs normally represents just one DIMM in | |
2123 | * single channel or two (2) DIMMs in dual channel mode. | |
2124 | * | |
2125 | * The following code logic collapses the various tables for CSROW based on CPU | |
2126 | * revision. | |
2127 | * | |
2128 | * Returns: | |
2129 | * The number of PAGE_SIZE pages on the specified CSROW number it | |
2130 | * encompasses | |
2131 | * | |
2132 | */ | |
41d8bfab | 2133 | static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) |
0ec449ee | 2134 | { |
1433eb99 | 2135 | u32 cs_mode, nr_pages; |
f92cae45 | 2136 | u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; |
0ec449ee DT |
2137 | |
2138 | /* | |
2139 | * The math on this doesn't look right on the surface because x/2*4 can | |
2140 | * be simplified to x*2 but this expression makes use of the fact that | |
2141 | * it is integral math where 1/2=0. This intermediate value becomes the | |
2142 | * number of bits to shift the DBAM register to extract the proper CSROW | |
2143 | * field. | |
2144 | */ | |
f92cae45 | 2145 | cs_mode = (dbam >> ((csrow_nr / 2) * 4)) & 0xF; |
0ec449ee | 2146 | |
41d8bfab | 2147 | nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT); |
0ec449ee | 2148 | |
1433eb99 | 2149 | debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode); |
0ec449ee DT |
2150 | debugf0(" nr_pages= %u channel-count = %d\n", |
2151 | nr_pages, pvt->channel_count); | |
2152 | ||
2153 | return nr_pages; | |
2154 | } | |
2155 | ||
2156 | /* | |
2157 | * Initialize the array of csrow attribute instances, based on the values | |
2158 | * from pci config hardware registers. | |
2159 | */ | |
360b7f3c | 2160 | static int init_csrows(struct mem_ctl_info *mci) |
0ec449ee DT |
2161 | { |
2162 | struct csrow_info *csrow; | |
2299ef71 | 2163 | struct amd64_pvt *pvt = mci->pvt_info; |
11c75ead | 2164 | u64 input_addr_min, input_addr_max, sys_addr, base, mask; |
2299ef71 | 2165 | u32 val; |
6ba5dcdc | 2166 | int i, empty = 1; |
0ec449ee | 2167 | |
a97fa68e | 2168 | amd64_read_pci_cfg(pvt->F3, NBCFG, &val); |
0ec449ee | 2169 | |
2299ef71 | 2170 | pvt->nbcfg = val; |
0ec449ee | 2171 | |
2299ef71 BP |
2172 | debugf0("node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n", |
2173 | pvt->mc_node_id, val, | |
a97fa68e | 2174 | !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE)); |
0ec449ee | 2175 | |
11c75ead | 2176 | for_each_chip_select(i, 0, pvt) { |
0ec449ee DT |
2177 | csrow = &mci->csrows[i]; |
2178 | ||
f92cae45 | 2179 | if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) { |
0ec449ee DT |
2180 | debugf1("----CSROW %d EMPTY for node %d\n", i, |
2181 | pvt->mc_node_id); | |
2182 | continue; | |
2183 | } | |
2184 | ||
2185 | debugf1("----CSROW %d VALID for MC node %d\n", | |
2186 | i, pvt->mc_node_id); | |
2187 | ||
2188 | empty = 0; | |
f92cae45 AS |
2189 | if (csrow_enabled(i, 0, pvt)) |
2190 | csrow->nr_pages = amd64_csrow_nr_pages(pvt, 0, i); | |
2191 | if (csrow_enabled(i, 1, pvt)) | |
2192 | csrow->nr_pages += amd64_csrow_nr_pages(pvt, 1, i); | |
0ec449ee DT |
2193 | find_csrow_limits(mci, i, &input_addr_min, &input_addr_max); |
2194 | sys_addr = input_addr_to_sys_addr(mci, input_addr_min); | |
2195 | csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT); | |
2196 | sys_addr = input_addr_to_sys_addr(mci, input_addr_max); | |
2197 | csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT); | |
11c75ead BP |
2198 | |
2199 | get_cs_base_and_mask(pvt, i, 0, &base, &mask); | |
2200 | csrow->page_mask = ~mask; | |
0ec449ee DT |
2201 | /* 8 bytes of resolution */ |
2202 | ||
24f9a7fe | 2203 | csrow->mtype = amd64_determine_memory_type(pvt, i); |
0ec449ee DT |
2204 | |
2205 | debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i); | |
2206 | debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n", | |
2207 | (unsigned long)input_addr_min, | |
2208 | (unsigned long)input_addr_max); | |
2209 | debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n", | |
2210 | (unsigned long)sys_addr, csrow->page_mask); | |
2211 | debugf1(" nr_pages: %u first_page: 0x%lx " | |
2212 | "last_page: 0x%lx\n", | |
2213 | (unsigned)csrow->nr_pages, | |
2214 | csrow->first_page, csrow->last_page); | |
2215 | ||
2216 | /* | |
2217 | * determine whether CHIPKILL or JUST ECC or NO ECC is operating | |
2218 | */ | |
a97fa68e | 2219 | if (pvt->nbcfg & NBCFG_ECC_ENABLE) |
0ec449ee | 2220 | csrow->edac_mode = |
a97fa68e | 2221 | (pvt->nbcfg & NBCFG_CHIPKILL) ? |
0ec449ee DT |
2222 | EDAC_S4ECD4ED : EDAC_SECDED; |
2223 | else | |
2224 | csrow->edac_mode = EDAC_NONE; | |
2225 | } | |
2226 | ||
2227 | return empty; | |
2228 | } | |
d27bf6fa | 2229 | |
f6d6ae96 | 2230 | /* get all cores on this DCT */ |
b487c33e | 2231 | static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, unsigned nid) |
f6d6ae96 BP |
2232 | { |
2233 | int cpu; | |
2234 | ||
2235 | for_each_online_cpu(cpu) | |
2236 | if (amd_get_nb_id(cpu) == nid) | |
2237 | cpumask_set_cpu(cpu, mask); | |
2238 | } | |
2239 | ||
2240 | /* check MCG_CTL on all the cpus on this node */ | |
b487c33e | 2241 | static bool amd64_nb_mce_bank_enabled_on_node(unsigned nid) |
f6d6ae96 BP |
2242 | { |
2243 | cpumask_var_t mask; | |
50542251 | 2244 | int cpu, nbe; |
f6d6ae96 BP |
2245 | bool ret = false; |
2246 | ||
2247 | if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { | |
24f9a7fe | 2248 | amd64_warn("%s: Error allocating mask\n", __func__); |
f6d6ae96 BP |
2249 | return false; |
2250 | } | |
2251 | ||
2252 | get_cpus_on_this_dct_cpumask(mask, nid); | |
2253 | ||
f6d6ae96 BP |
2254 | rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs); |
2255 | ||
2256 | for_each_cpu(cpu, mask) { | |
50542251 | 2257 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
5980bb9c | 2258 | nbe = reg->l & MSR_MCGCTL_NBE; |
f6d6ae96 BP |
2259 | |
2260 | debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", | |
50542251 | 2261 | cpu, reg->q, |
f6d6ae96 BP |
2262 | (nbe ? "enabled" : "disabled")); |
2263 | ||
2264 | if (!nbe) | |
2265 | goto out; | |
f6d6ae96 BP |
2266 | } |
2267 | ret = true; | |
2268 | ||
2269 | out: | |
f6d6ae96 BP |
2270 | free_cpumask_var(mask); |
2271 | return ret; | |
2272 | } | |
2273 | ||
2299ef71 | 2274 | static int toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on) |
f6d6ae96 BP |
2275 | { |
2276 | cpumask_var_t cmask; | |
50542251 | 2277 | int cpu; |
f6d6ae96 BP |
2278 | |
2279 | if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) { | |
24f9a7fe | 2280 | amd64_warn("%s: error allocating mask\n", __func__); |
f6d6ae96 BP |
2281 | return false; |
2282 | } | |
2283 | ||
ae7bb7c6 | 2284 | get_cpus_on_this_dct_cpumask(cmask, nid); |
f6d6ae96 | 2285 | |
f6d6ae96 BP |
2286 | rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); |
2287 | ||
2288 | for_each_cpu(cpu, cmask) { | |
2289 | ||
50542251 BP |
2290 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
2291 | ||
f6d6ae96 | 2292 | if (on) { |
5980bb9c | 2293 | if (reg->l & MSR_MCGCTL_NBE) |
ae7bb7c6 | 2294 | s->flags.nb_mce_enable = 1; |
f6d6ae96 | 2295 | |
5980bb9c | 2296 | reg->l |= MSR_MCGCTL_NBE; |
f6d6ae96 BP |
2297 | } else { |
2298 | /* | |
d95cf4de | 2299 | * Turn off NB MCE reporting only when it was off before |
f6d6ae96 | 2300 | */ |
ae7bb7c6 | 2301 | if (!s->flags.nb_mce_enable) |
5980bb9c | 2302 | reg->l &= ~MSR_MCGCTL_NBE; |
f6d6ae96 | 2303 | } |
f6d6ae96 BP |
2304 | } |
2305 | wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); | |
2306 | ||
f6d6ae96 BP |
2307 | free_cpumask_var(cmask); |
2308 | ||
2309 | return 0; | |
2310 | } | |
2311 | ||
2299ef71 BP |
2312 | static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid, |
2313 | struct pci_dev *F3) | |
f9431992 | 2314 | { |
2299ef71 | 2315 | bool ret = true; |
c9f4f26e | 2316 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
f9431992 | 2317 | |
2299ef71 BP |
2318 | if (toggle_ecc_err_reporting(s, nid, ON)) { |
2319 | amd64_warn("Error enabling ECC reporting over MCGCTL!\n"); | |
2320 | return false; | |
2321 | } | |
2322 | ||
c9f4f26e | 2323 | amd64_read_pci_cfg(F3, NBCTL, &value); |
f9431992 | 2324 | |
ae7bb7c6 BP |
2325 | s->old_nbctl = value & mask; |
2326 | s->nbctl_valid = true; | |
f9431992 DT |
2327 | |
2328 | value |= mask; | |
c9f4f26e | 2329 | amd64_write_pci_cfg(F3, NBCTL, value); |
f9431992 | 2330 | |
a97fa68e | 2331 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2332 | |
a97fa68e BP |
2333 | debugf0("1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", |
2334 | nid, value, !!(value & NBCFG_ECC_ENABLE)); | |
f9431992 | 2335 | |
a97fa68e | 2336 | if (!(value & NBCFG_ECC_ENABLE)) { |
24f9a7fe | 2337 | amd64_warn("DRAM ECC disabled on this node, enabling...\n"); |
f9431992 | 2338 | |
ae7bb7c6 | 2339 | s->flags.nb_ecc_prev = 0; |
d95cf4de | 2340 | |
f9431992 | 2341 | /* Attempt to turn on DRAM ECC Enable */ |
a97fa68e BP |
2342 | value |= NBCFG_ECC_ENABLE; |
2343 | amd64_write_pci_cfg(F3, NBCFG, value); | |
f9431992 | 2344 | |
a97fa68e | 2345 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2346 | |
a97fa68e | 2347 | if (!(value & NBCFG_ECC_ENABLE)) { |
24f9a7fe BP |
2348 | amd64_warn("Hardware rejected DRAM ECC enable," |
2349 | "check memory DIMM configuration.\n"); | |
2299ef71 | 2350 | ret = false; |
f9431992 | 2351 | } else { |
24f9a7fe | 2352 | amd64_info("Hardware accepted DRAM ECC Enable\n"); |
f9431992 | 2353 | } |
d95cf4de | 2354 | } else { |
ae7bb7c6 | 2355 | s->flags.nb_ecc_prev = 1; |
f9431992 | 2356 | } |
d95cf4de | 2357 | |
a97fa68e BP |
2358 | debugf0("2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", |
2359 | nid, value, !!(value & NBCFG_ECC_ENABLE)); | |
f9431992 | 2360 | |
2299ef71 | 2361 | return ret; |
f9431992 DT |
2362 | } |
2363 | ||
360b7f3c BP |
2364 | static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid, |
2365 | struct pci_dev *F3) | |
f9431992 | 2366 | { |
c9f4f26e BP |
2367 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
2368 | ||
f9431992 | 2369 | |
ae7bb7c6 | 2370 | if (!s->nbctl_valid) |
f9431992 DT |
2371 | return; |
2372 | ||
c9f4f26e | 2373 | amd64_read_pci_cfg(F3, NBCTL, &value); |
f9431992 | 2374 | value &= ~mask; |
ae7bb7c6 | 2375 | value |= s->old_nbctl; |
f9431992 | 2376 | |
c9f4f26e | 2377 | amd64_write_pci_cfg(F3, NBCTL, value); |
f9431992 | 2378 | |
ae7bb7c6 BP |
2379 | /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ |
2380 | if (!s->flags.nb_ecc_prev) { | |
a97fa68e BP |
2381 | amd64_read_pci_cfg(F3, NBCFG, &value); |
2382 | value &= ~NBCFG_ECC_ENABLE; | |
2383 | amd64_write_pci_cfg(F3, NBCFG, value); | |
d95cf4de BP |
2384 | } |
2385 | ||
2386 | /* restore the NB Enable MCGCTL bit */ | |
2299ef71 | 2387 | if (toggle_ecc_err_reporting(s, nid, OFF)) |
24f9a7fe | 2388 | amd64_warn("Error restoring NB MCGCTL settings!\n"); |
f9431992 DT |
2389 | } |
2390 | ||
2391 | /* | |
2299ef71 BP |
2392 | * EDAC requires that the BIOS have ECC enabled before |
2393 | * taking over the processing of ECC errors. A command line | |
2394 | * option allows to force-enable hardware ECC later in | |
2395 | * enable_ecc_error_reporting(). | |
f9431992 | 2396 | */ |
cab4d277 BP |
2397 | static const char *ecc_msg = |
2398 | "ECC disabled in the BIOS or no ECC capability, module will not load.\n" | |
2399 | " Either enable ECC checking or force module loading by setting " | |
2400 | "'ecc_enable_override'.\n" | |
2401 | " (Note that use of the override may cause unknown side effects.)\n"; | |
be3468e8 | 2402 | |
2299ef71 | 2403 | static bool ecc_enabled(struct pci_dev *F3, u8 nid) |
f9431992 DT |
2404 | { |
2405 | u32 value; | |
2299ef71 | 2406 | u8 ecc_en = 0; |
06724535 | 2407 | bool nb_mce_en = false; |
f9431992 | 2408 | |
a97fa68e | 2409 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2410 | |
a97fa68e | 2411 | ecc_en = !!(value & NBCFG_ECC_ENABLE); |
2299ef71 | 2412 | amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled")); |
f9431992 | 2413 | |
2299ef71 | 2414 | nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid); |
06724535 | 2415 | if (!nb_mce_en) |
2299ef71 BP |
2416 | amd64_notice("NB MCE bank disabled, set MSR " |
2417 | "0x%08x[4] on node %d to enable.\n", | |
2418 | MSR_IA32_MCG_CTL, nid); | |
f9431992 | 2419 | |
2299ef71 BP |
2420 | if (!ecc_en || !nb_mce_en) { |
2421 | amd64_notice("%s", ecc_msg); | |
2422 | return false; | |
2423 | } | |
2424 | return true; | |
f9431992 DT |
2425 | } |
2426 | ||
7d6034d3 DT |
2427 | struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) + |
2428 | ARRAY_SIZE(amd64_inj_attrs) + | |
2429 | 1]; | |
2430 | ||
2431 | struct mcidev_sysfs_attribute terminator = { .attr = { .name = NULL } }; | |
2432 | ||
360b7f3c | 2433 | static void set_mc_sysfs_attrs(struct mem_ctl_info *mci) |
7d6034d3 DT |
2434 | { |
2435 | unsigned int i = 0, j = 0; | |
2436 | ||
2437 | for (; i < ARRAY_SIZE(amd64_dbg_attrs); i++) | |
2438 | sysfs_attrs[i] = amd64_dbg_attrs[i]; | |
2439 | ||
a135cef7 BP |
2440 | if (boot_cpu_data.x86 >= 0x10) |
2441 | for (j = 0; j < ARRAY_SIZE(amd64_inj_attrs); j++, i++) | |
2442 | sysfs_attrs[i] = amd64_inj_attrs[j]; | |
7d6034d3 DT |
2443 | |
2444 | sysfs_attrs[i] = terminator; | |
2445 | ||
2446 | mci->mc_driver_sysfs_attributes = sysfs_attrs; | |
2447 | } | |
2448 | ||
df71a053 BP |
2449 | static void setup_mci_misc_attrs(struct mem_ctl_info *mci, |
2450 | struct amd64_family_type *fam) | |
7d6034d3 DT |
2451 | { |
2452 | struct amd64_pvt *pvt = mci->pvt_info; | |
2453 | ||
2454 | mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; | |
2455 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
7d6034d3 | 2456 | |
5980bb9c | 2457 | if (pvt->nbcap & NBCAP_SECDED) |
7d6034d3 DT |
2458 | mci->edac_ctl_cap |= EDAC_FLAG_SECDED; |
2459 | ||
5980bb9c | 2460 | if (pvt->nbcap & NBCAP_CHIPKILL) |
7d6034d3 DT |
2461 | mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; |
2462 | ||
2463 | mci->edac_cap = amd64_determine_edac_cap(pvt); | |
2464 | mci->mod_name = EDAC_MOD_STR; | |
2465 | mci->mod_ver = EDAC_AMD64_VERSION; | |
df71a053 | 2466 | mci->ctl_name = fam->ctl_name; |
8d5b5d9c | 2467 | mci->dev_name = pci_name(pvt->F2); |
7d6034d3 DT |
2468 | mci->ctl_page_to_phys = NULL; |
2469 | ||
7d6034d3 DT |
2470 | /* memory scrubber interface */ |
2471 | mci->set_sdram_scrub_rate = amd64_set_scrub_rate; | |
2472 | mci->get_sdram_scrub_rate = amd64_get_scrub_rate; | |
2473 | } | |
2474 | ||
0092b20d BP |
2475 | /* |
2476 | * returns a pointer to the family descriptor on success, NULL otherwise. | |
2477 | */ | |
2478 | static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt) | |
395ae783 | 2479 | { |
0092b20d BP |
2480 | u8 fam = boot_cpu_data.x86; |
2481 | struct amd64_family_type *fam_type = NULL; | |
2482 | ||
2483 | switch (fam) { | |
395ae783 | 2484 | case 0xf: |
0092b20d | 2485 | fam_type = &amd64_family_types[K8_CPUS]; |
b8cfa02f | 2486 | pvt->ops = &amd64_family_types[K8_CPUS].ops; |
395ae783 | 2487 | break; |
df71a053 | 2488 | |
395ae783 | 2489 | case 0x10: |
0092b20d | 2490 | fam_type = &amd64_family_types[F10_CPUS]; |
b8cfa02f | 2491 | pvt->ops = &amd64_family_types[F10_CPUS].ops; |
df71a053 BP |
2492 | break; |
2493 | ||
2494 | case 0x15: | |
2495 | fam_type = &amd64_family_types[F15_CPUS]; | |
2496 | pvt->ops = &amd64_family_types[F15_CPUS].ops; | |
395ae783 BP |
2497 | break; |
2498 | ||
2499 | default: | |
24f9a7fe | 2500 | amd64_err("Unsupported family!\n"); |
0092b20d | 2501 | return NULL; |
395ae783 | 2502 | } |
0092b20d | 2503 | |
b8cfa02f BP |
2504 | pvt->ext_model = boot_cpu_data.x86_model >> 4; |
2505 | ||
df71a053 | 2506 | amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name, |
0092b20d | 2507 | (fam == 0xf ? |
24f9a7fe BP |
2508 | (pvt->ext_model >= K8_REV_F ? "revF or later " |
2509 | : "revE or earlier ") | |
2510 | : ""), pvt->mc_node_id); | |
0092b20d | 2511 | return fam_type; |
395ae783 BP |
2512 | } |
2513 | ||
2299ef71 | 2514 | static int amd64_init_one_instance(struct pci_dev *F2) |
7d6034d3 DT |
2515 | { |
2516 | struct amd64_pvt *pvt = NULL; | |
0092b20d | 2517 | struct amd64_family_type *fam_type = NULL; |
360b7f3c | 2518 | struct mem_ctl_info *mci = NULL; |
7d6034d3 | 2519 | int err = 0, ret; |
360b7f3c | 2520 | u8 nid = get_node_id(F2); |
7d6034d3 DT |
2521 | |
2522 | ret = -ENOMEM; | |
2523 | pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); | |
2524 | if (!pvt) | |
360b7f3c | 2525 | goto err_ret; |
7d6034d3 | 2526 | |
360b7f3c | 2527 | pvt->mc_node_id = nid; |
8d5b5d9c | 2528 | pvt->F2 = F2; |
7d6034d3 | 2529 | |
395ae783 | 2530 | ret = -EINVAL; |
0092b20d BP |
2531 | fam_type = amd64_per_family_init(pvt); |
2532 | if (!fam_type) | |
395ae783 BP |
2533 | goto err_free; |
2534 | ||
7d6034d3 | 2535 | ret = -ENODEV; |
360b7f3c | 2536 | err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id); |
7d6034d3 DT |
2537 | if (err) |
2538 | goto err_free; | |
2539 | ||
360b7f3c | 2540 | read_mc_regs(pvt); |
7d6034d3 | 2541 | |
7d6034d3 DT |
2542 | /* |
2543 | * We need to determine how many memory channels there are. Then use | |
2544 | * that information for calculating the size of the dynamic instance | |
360b7f3c | 2545 | * tables in the 'mci' structure. |
7d6034d3 | 2546 | */ |
360b7f3c | 2547 | ret = -EINVAL; |
7d6034d3 DT |
2548 | pvt->channel_count = pvt->ops->early_channel_count(pvt); |
2549 | if (pvt->channel_count < 0) | |
360b7f3c | 2550 | goto err_siblings; |
7d6034d3 DT |
2551 | |
2552 | ret = -ENOMEM; | |
11c75ead | 2553 | mci = edac_mc_alloc(0, pvt->csels[0].b_cnt, pvt->channel_count, nid); |
7d6034d3 | 2554 | if (!mci) |
360b7f3c | 2555 | goto err_siblings; |
7d6034d3 DT |
2556 | |
2557 | mci->pvt_info = pvt; | |
8d5b5d9c | 2558 | mci->dev = &pvt->F2->dev; |
7d6034d3 | 2559 | |
df71a053 | 2560 | setup_mci_misc_attrs(mci, fam_type); |
360b7f3c BP |
2561 | |
2562 | if (init_csrows(mci)) | |
7d6034d3 DT |
2563 | mci->edac_cap = EDAC_FLAG_NONE; |
2564 | ||
360b7f3c | 2565 | set_mc_sysfs_attrs(mci); |
7d6034d3 DT |
2566 | |
2567 | ret = -ENODEV; | |
2568 | if (edac_mc_add_mc(mci)) { | |
2569 | debugf1("failed edac_mc_add_mc()\n"); | |
2570 | goto err_add_mc; | |
2571 | } | |
2572 | ||
549d042d BP |
2573 | /* register stuff with EDAC MCE */ |
2574 | if (report_gart_errors) | |
2575 | amd_report_gart_errors(true); | |
2576 | ||
2577 | amd_register_ecc_decoder(amd64_decode_bus_error); | |
2578 | ||
360b7f3c BP |
2579 | mcis[nid] = mci; |
2580 | ||
2581 | atomic_inc(&drv_instances); | |
2582 | ||
7d6034d3 DT |
2583 | return 0; |
2584 | ||
2585 | err_add_mc: | |
2586 | edac_mc_free(mci); | |
2587 | ||
360b7f3c BP |
2588 | err_siblings: |
2589 | free_mc_sibling_devs(pvt); | |
7d6034d3 | 2590 | |
360b7f3c BP |
2591 | err_free: |
2592 | kfree(pvt); | |
7d6034d3 | 2593 | |
360b7f3c | 2594 | err_ret: |
7d6034d3 DT |
2595 | return ret; |
2596 | } | |
2597 | ||
2299ef71 | 2598 | static int __devinit amd64_probe_one_instance(struct pci_dev *pdev, |
b8cfa02f | 2599 | const struct pci_device_id *mc_type) |
7d6034d3 | 2600 | { |
ae7bb7c6 | 2601 | u8 nid = get_node_id(pdev); |
2299ef71 | 2602 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; |
ae7bb7c6 | 2603 | struct ecc_settings *s; |
2299ef71 | 2604 | int ret = 0; |
7d6034d3 | 2605 | |
7d6034d3 | 2606 | ret = pci_enable_device(pdev); |
b8cfa02f BP |
2607 | if (ret < 0) { |
2608 | debugf0("ret=%d\n", ret); | |
2609 | return -EIO; | |
2610 | } | |
7d6034d3 | 2611 | |
ae7bb7c6 BP |
2612 | ret = -ENOMEM; |
2613 | s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL); | |
2614 | if (!s) | |
2299ef71 | 2615 | goto err_out; |
ae7bb7c6 BP |
2616 | |
2617 | ecc_stngs[nid] = s; | |
2618 | ||
2299ef71 BP |
2619 | if (!ecc_enabled(F3, nid)) { |
2620 | ret = -ENODEV; | |
2621 | ||
2622 | if (!ecc_enable_override) | |
2623 | goto err_enable; | |
2624 | ||
2625 | amd64_warn("Forcing ECC on!\n"); | |
2626 | ||
2627 | if (!enable_ecc_error_reporting(s, nid, F3)) | |
2628 | goto err_enable; | |
2629 | } | |
2630 | ||
2631 | ret = amd64_init_one_instance(pdev); | |
360b7f3c | 2632 | if (ret < 0) { |
ae7bb7c6 | 2633 | amd64_err("Error probing instance: %d\n", nid); |
360b7f3c BP |
2634 | restore_ecc_error_reporting(s, nid, F3); |
2635 | } | |
7d6034d3 DT |
2636 | |
2637 | return ret; | |
2299ef71 BP |
2638 | |
2639 | err_enable: | |
2640 | kfree(s); | |
2641 | ecc_stngs[nid] = NULL; | |
2642 | ||
2643 | err_out: | |
2644 | return ret; | |
7d6034d3 DT |
2645 | } |
2646 | ||
2647 | static void __devexit amd64_remove_one_instance(struct pci_dev *pdev) | |
2648 | { | |
2649 | struct mem_ctl_info *mci; | |
2650 | struct amd64_pvt *pvt; | |
360b7f3c BP |
2651 | u8 nid = get_node_id(pdev); |
2652 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; | |
2653 | struct ecc_settings *s = ecc_stngs[nid]; | |
7d6034d3 DT |
2654 | |
2655 | /* Remove from EDAC CORE tracking list */ | |
2656 | mci = edac_mc_del_mc(&pdev->dev); | |
2657 | if (!mci) | |
2658 | return; | |
2659 | ||
2660 | pvt = mci->pvt_info; | |
2661 | ||
360b7f3c | 2662 | restore_ecc_error_reporting(s, nid, F3); |
7d6034d3 | 2663 | |
360b7f3c | 2664 | free_mc_sibling_devs(pvt); |
7d6034d3 | 2665 | |
549d042d BP |
2666 | /* unregister from EDAC MCE */ |
2667 | amd_report_gart_errors(false); | |
2668 | amd_unregister_ecc_decoder(amd64_decode_bus_error); | |
2669 | ||
360b7f3c BP |
2670 | kfree(ecc_stngs[nid]); |
2671 | ecc_stngs[nid] = NULL; | |
ae7bb7c6 | 2672 | |
7d6034d3 | 2673 | /* Free the EDAC CORE resources */ |
8f68ed97 | 2674 | mci->pvt_info = NULL; |
360b7f3c | 2675 | mcis[nid] = NULL; |
8f68ed97 BP |
2676 | |
2677 | kfree(pvt); | |
7d6034d3 DT |
2678 | edac_mc_free(mci); |
2679 | } | |
2680 | ||
2681 | /* | |
2682 | * This table is part of the interface for loading drivers for PCI devices. The | |
2683 | * PCI core identifies what devices are on a system during boot, and then | |
2684 | * inquiry this table to see if this driver is for a given device found. | |
2685 | */ | |
2686 | static const struct pci_device_id amd64_pci_table[] __devinitdata = { | |
2687 | { | |
2688 | .vendor = PCI_VENDOR_ID_AMD, | |
2689 | .device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL, | |
2690 | .subvendor = PCI_ANY_ID, | |
2691 | .subdevice = PCI_ANY_ID, | |
2692 | .class = 0, | |
2693 | .class_mask = 0, | |
7d6034d3 DT |
2694 | }, |
2695 | { | |
2696 | .vendor = PCI_VENDOR_ID_AMD, | |
2697 | .device = PCI_DEVICE_ID_AMD_10H_NB_DRAM, | |
2698 | .subvendor = PCI_ANY_ID, | |
2699 | .subdevice = PCI_ANY_ID, | |
2700 | .class = 0, | |
2701 | .class_mask = 0, | |
7d6034d3 | 2702 | }, |
df71a053 BP |
2703 | { |
2704 | .vendor = PCI_VENDOR_ID_AMD, | |
2705 | .device = PCI_DEVICE_ID_AMD_15H_NB_F2, | |
2706 | .subvendor = PCI_ANY_ID, | |
2707 | .subdevice = PCI_ANY_ID, | |
2708 | .class = 0, | |
2709 | .class_mask = 0, | |
2710 | }, | |
2711 | ||
7d6034d3 DT |
2712 | {0, } |
2713 | }; | |
2714 | MODULE_DEVICE_TABLE(pci, amd64_pci_table); | |
2715 | ||
2716 | static struct pci_driver amd64_pci_driver = { | |
2717 | .name = EDAC_MOD_STR, | |
2299ef71 | 2718 | .probe = amd64_probe_one_instance, |
7d6034d3 DT |
2719 | .remove = __devexit_p(amd64_remove_one_instance), |
2720 | .id_table = amd64_pci_table, | |
2721 | }; | |
2722 | ||
360b7f3c | 2723 | static void setup_pci_device(void) |
7d6034d3 DT |
2724 | { |
2725 | struct mem_ctl_info *mci; | |
2726 | struct amd64_pvt *pvt; | |
2727 | ||
2728 | if (amd64_ctl_pci) | |
2729 | return; | |
2730 | ||
cc4d8860 | 2731 | mci = mcis[0]; |
7d6034d3 DT |
2732 | if (mci) { |
2733 | ||
2734 | pvt = mci->pvt_info; | |
2735 | amd64_ctl_pci = | |
8d5b5d9c | 2736 | edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR); |
7d6034d3 DT |
2737 | |
2738 | if (!amd64_ctl_pci) { | |
2739 | pr_warning("%s(): Unable to create PCI control\n", | |
2740 | __func__); | |
2741 | ||
2742 | pr_warning("%s(): PCI error report via EDAC not set\n", | |
2743 | __func__); | |
2744 | } | |
2745 | } | |
2746 | } | |
2747 | ||
2748 | static int __init amd64_edac_init(void) | |
2749 | { | |
360b7f3c | 2750 | int err = -ENODEV; |
7d6034d3 | 2751 | |
df71a053 | 2752 | printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION); |
7d6034d3 DT |
2753 | |
2754 | opstate_init(); | |
2755 | ||
9653a5c7 | 2756 | if (amd_cache_northbridges() < 0) |
56b34b91 | 2757 | goto err_ret; |
7d6034d3 | 2758 | |
cc4d8860 | 2759 | err = -ENOMEM; |
ae7bb7c6 BP |
2760 | mcis = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL); |
2761 | ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL); | |
360b7f3c | 2762 | if (!(mcis && ecc_stngs)) |
a9f0fbe2 | 2763 | goto err_free; |
cc4d8860 | 2764 | |
50542251 | 2765 | msrs = msrs_alloc(); |
56b34b91 | 2766 | if (!msrs) |
360b7f3c | 2767 | goto err_free; |
50542251 | 2768 | |
7d6034d3 DT |
2769 | err = pci_register_driver(&amd64_pci_driver); |
2770 | if (err) | |
56b34b91 | 2771 | goto err_pci; |
7d6034d3 | 2772 | |
56b34b91 | 2773 | err = -ENODEV; |
360b7f3c BP |
2774 | if (!atomic_read(&drv_instances)) |
2775 | goto err_no_instances; | |
7d6034d3 | 2776 | |
360b7f3c BP |
2777 | setup_pci_device(); |
2778 | return 0; | |
7d6034d3 | 2779 | |
360b7f3c | 2780 | err_no_instances: |
7d6034d3 | 2781 | pci_unregister_driver(&amd64_pci_driver); |
cc4d8860 | 2782 | |
56b34b91 BP |
2783 | err_pci: |
2784 | msrs_free(msrs); | |
2785 | msrs = NULL; | |
cc4d8860 | 2786 | |
360b7f3c BP |
2787 | err_free: |
2788 | kfree(mcis); | |
2789 | mcis = NULL; | |
2790 | ||
2791 | kfree(ecc_stngs); | |
2792 | ecc_stngs = NULL; | |
2793 | ||
56b34b91 | 2794 | err_ret: |
7d6034d3 DT |
2795 | return err; |
2796 | } | |
2797 | ||
2798 | static void __exit amd64_edac_exit(void) | |
2799 | { | |
2800 | if (amd64_ctl_pci) | |
2801 | edac_pci_release_generic_ctl(amd64_ctl_pci); | |
2802 | ||
2803 | pci_unregister_driver(&amd64_pci_driver); | |
50542251 | 2804 | |
ae7bb7c6 BP |
2805 | kfree(ecc_stngs); |
2806 | ecc_stngs = NULL; | |
2807 | ||
cc4d8860 BP |
2808 | kfree(mcis); |
2809 | mcis = NULL; | |
2810 | ||
50542251 BP |
2811 | msrs_free(msrs); |
2812 | msrs = NULL; | |
7d6034d3 DT |
2813 | } |
2814 | ||
2815 | module_init(amd64_edac_init); | |
2816 | module_exit(amd64_edac_exit); | |
2817 | ||
2818 | MODULE_LICENSE("GPL"); | |
2819 | MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, " | |
2820 | "Dave Peterson, Thayne Harbaugh"); | |
2821 | MODULE_DESCRIPTION("MC support for AMD64 memory controllers - " | |
2822 | EDAC_AMD64_VERSION); | |
2823 | ||
2824 | module_param(edac_op_state, int, 0444); | |
2825 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |