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cfe40fdb DT |
1 | /* |
2 | * AMD64 class Memory Controller kernel module | |
3 | * | |
4 | * Copyright (c) 2009 SoftwareBitMaker. | |
5 | * Copyright (c) 2009 Advanced Micro Devices, Inc. | |
6 | * | |
7 | * This file may be distributed under the terms of the | |
8 | * GNU General Public License. | |
9 | * | |
10 | * Originally Written by Thayne Harbaugh | |
11 | * | |
12 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
13 | * - K8 CPU Revision D and greater support | |
14 | * | |
15 | * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>: | |
16 | * - Module largely rewritten, with new (and hopefully correct) | |
17 | * code for dealing with node and chip select interleaving, | |
18 | * various code cleanup, and bug fixes | |
19 | * - Added support for memory hoisting using DRAM hole address | |
20 | * register | |
21 | * | |
22 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
23 | * -K8 Rev (1207) revision support added, required Revision | |
24 | * specific mini-driver code to support Rev F as well as | |
25 | * prior revisions | |
26 | * | |
27 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
28 | * -Family 10h revision support added. New PCI Device IDs, | |
29 | * indicating new changes. Actual registers modified | |
30 | * were slight, less than the Rev E to Rev F transition | |
31 | * but changing the PCI Device ID was the proper thing to | |
32 | * do, as it provides for almost automactic family | |
33 | * detection. The mods to Rev F required more family | |
34 | * information detection. | |
35 | * | |
36 | * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>: | |
37 | * - misc fixes and code cleanups | |
38 | * | |
39 | * This module is based on the following documents | |
40 | * (available from http://www.amd.com/): | |
41 | * | |
42 | * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD | |
43 | * Opteron Processors | |
44 | * AMD publication #: 26094 | |
45 | *` Revision: 3.26 | |
46 | * | |
47 | * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh | |
48 | * Processors | |
49 | * AMD publication #: 32559 | |
50 | * Revision: 3.00 | |
51 | * Issue Date: May 2006 | |
52 | * | |
53 | * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h | |
54 | * Processors | |
55 | * AMD publication #: 31116 | |
56 | * Revision: 3.00 | |
57 | * Issue Date: September 07, 2007 | |
58 | * | |
59 | * Sections in the first 2 documents are no longer in sync with each other. | |
60 | * The Family 10h BKDG was totally re-written from scratch with a new | |
61 | * presentation model. | |
62 | * Therefore, comments that refer to a Document section might be off. | |
63 | */ | |
64 | ||
65 | #include <linux/module.h> | |
66 | #include <linux/ctype.h> | |
67 | #include <linux/init.h> | |
68 | #include <linux/pci.h> | |
69 | #include <linux/pci_ids.h> | |
70 | #include <linux/slab.h> | |
71 | #include <linux/mmzone.h> | |
72 | #include <linux/edac.h> | |
f9431992 | 73 | #include <asm/msr.h> |
cfe40fdb | 74 | #include "edac_core.h" |
47ca08a4 | 75 | #include "mce_amd.h" |
cfe40fdb | 76 | |
24f9a7fe BP |
77 | #define amd64_debug(fmt, arg...) \ |
78 | edac_printk(KERN_DEBUG, "amd64", fmt, ##arg) | |
cfe40fdb | 79 | |
24f9a7fe BP |
80 | #define amd64_info(fmt, arg...) \ |
81 | edac_printk(KERN_INFO, "amd64", fmt, ##arg) | |
82 | ||
83 | #define amd64_notice(fmt, arg...) \ | |
84 | edac_printk(KERN_NOTICE, "amd64", fmt, ##arg) | |
85 | ||
86 | #define amd64_warn(fmt, arg...) \ | |
87 | edac_printk(KERN_WARNING, "amd64", fmt, ##arg) | |
88 | ||
89 | #define amd64_err(fmt, arg...) \ | |
90 | edac_printk(KERN_ERR, "amd64", fmt, ##arg) | |
91 | ||
92 | #define amd64_mc_warn(mci, fmt, arg...) \ | |
93 | edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) | |
94 | ||
95 | #define amd64_mc_err(mci, fmt, arg...) \ | |
96 | edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) | |
cfe40fdb DT |
97 | |
98 | /* | |
99 | * Throughout the comments in this code, the following terms are used: | |
100 | * | |
101 | * SysAddr, DramAddr, and InputAddr | |
102 | * | |
103 | * These terms come directly from the amd64 documentation | |
104 | * (AMD publication #26094). They are defined as follows: | |
105 | * | |
106 | * SysAddr: | |
107 | * This is a physical address generated by a CPU core or a device | |
108 | * doing DMA. If generated by a CPU core, a SysAddr is the result of | |
109 | * a virtual to physical address translation by the CPU core's address | |
110 | * translation mechanism (MMU). | |
111 | * | |
112 | * DramAddr: | |
113 | * A DramAddr is derived from a SysAddr by subtracting an offset that | |
114 | * depends on which node the SysAddr maps to and whether the SysAddr | |
115 | * is within a range affected by memory hoisting. The DRAM Base | |
116 | * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers | |
117 | * determine which node a SysAddr maps to. | |
118 | * | |
119 | * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr | |
120 | * is within the range of addresses specified by this register, then | |
121 | * a value x from the DHAR is subtracted from the SysAddr to produce a | |
122 | * DramAddr. Here, x represents the base address for the node that | |
123 | * the SysAddr maps to plus an offset due to memory hoisting. See | |
124 | * section 3.4.8 and the comments in amd64_get_dram_hole_info() and | |
125 | * sys_addr_to_dram_addr() below for more information. | |
126 | * | |
127 | * If the SysAddr is not affected by the DHAR then a value y is | |
128 | * subtracted from the SysAddr to produce a DramAddr. Here, y is the | |
129 | * base address for the node that the SysAddr maps to. See section | |
130 | * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more | |
131 | * information. | |
132 | * | |
133 | * InputAddr: | |
134 | * A DramAddr is translated to an InputAddr before being passed to the | |
135 | * memory controller for the node that the DramAddr is associated | |
136 | * with. The memory controller then maps the InputAddr to a csrow. | |
137 | * If node interleaving is not in use, then the InputAddr has the same | |
138 | * value as the DramAddr. Otherwise, the InputAddr is produced by | |
139 | * discarding the bits used for node interleaving from the DramAddr. | |
140 | * See section 3.4.4 for more information. | |
141 | * | |
142 | * The memory controller for a given node uses its DRAM CS Base and | |
143 | * DRAM CS Mask registers to map an InputAddr to a csrow. See | |
144 | * sections 3.5.4 and 3.5.5 for more information. | |
145 | */ | |
146 | ||
24f9a7fe | 147 | #define EDAC_AMD64_VERSION "v3.3.0" |
cfe40fdb DT |
148 | #define EDAC_MOD_STR "amd64_edac" |
149 | ||
150 | /* Extended Model from CPUID, for CPU Revision numbers */ | |
1433eb99 BP |
151 | #define K8_REV_D 1 |
152 | #define K8_REV_E 2 | |
153 | #define K8_REV_F 4 | |
cfe40fdb DT |
154 | |
155 | /* Hardware limit on ChipSelect rows per MC and processors per system */ | |
7f19bf75 BP |
156 | #define NUM_CHIPSELECTS 8 |
157 | #define DRAM_RANGES 8 | |
cfe40fdb | 158 | |
f6d6ae96 BP |
159 | #define ON true |
160 | #define OFF false | |
cfe40fdb | 161 | |
11c75ead BP |
162 | /* |
163 | * Create a contiguous bitmask starting at bit position @lo and ending at | |
164 | * position @hi. For example | |
165 | * | |
166 | * GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000. | |
167 | */ | |
168 | #define GENMASK(lo, hi) (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) | |
169 | ||
cfe40fdb DT |
170 | /* |
171 | * PCI-defined configuration space registers | |
172 | */ | |
173 | ||
174 | ||
175 | /* | |
176 | * Function 1 - Address Map | |
177 | */ | |
7f19bf75 BP |
178 | #define DRAM_BASE_LO 0x40 |
179 | #define DRAM_LIMIT_LO 0x44 | |
180 | ||
181 | #define dram_intlv_en(pvt, i) ((pvt->ranges[i].base.lo >> 8) & 0x7) | |
182 | #define dram_rw(pvt, i) (pvt->ranges[i].base.lo & 0x3) | |
183 | #define dram_intlv_sel(pvt, i) ((pvt->ranges[i].lim.lo >> 8) & 0x7) | |
184 | #define dram_dst_node(pvt, i) (pvt->ranges[i].lim.lo & 0x7) | |
185 | ||
bc21fa57 | 186 | #define DHAR 0xf0 |
c8e518d5 BP |
187 | #define dhar_valid(pvt) ((pvt)->dhar & BIT(0)) |
188 | #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) | |
189 | #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) | |
190 | #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) | |
cfe40fdb | 191 | |
cfe40fdb | 192 | /* NOTE: Extra mask bit vs K8 */ |
c8e518d5 | 193 | #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) |
cfe40fdb | 194 | |
b2b0c605 | 195 | #define DCT_CFG_SEL 0x10C |
cfe40fdb | 196 | |
7f19bf75 BP |
197 | #define DRAM_BASE_HI 0x140 |
198 | #define DRAM_LIMIT_HI 0x144 | |
cfe40fdb DT |
199 | |
200 | ||
201 | /* | |
202 | * Function 2 - DRAM controller | |
203 | */ | |
11c75ead BP |
204 | #define DCSB0 0x40 |
205 | #define DCSB1 0x140 | |
206 | #define DCSB_CS_ENABLE BIT(0) | |
cfe40fdb | 207 | |
11c75ead BP |
208 | #define DCSM0 0x60 |
209 | #define DCSM1 0x160 | |
cfe40fdb | 210 | |
11c75ead | 211 | #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) |
cfe40fdb DT |
212 | |
213 | #define DBAM0 0x80 | |
214 | #define DBAM1 0x180 | |
215 | ||
216 | /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ | |
217 | #define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF) | |
218 | ||
219 | #define DBAM_MAX_VALUE 11 | |
220 | ||
221 | ||
222 | #define F10_DCLR_0 0x90 | |
223 | #define F10_DCLR_1 0x190 | |
224 | #define REVE_WIDTH_128 BIT(16) | |
225 | #define F10_WIDTH_128 BIT(11) | |
226 | ||
227 | ||
228 | #define F10_DCHR_0 0x94 | |
229 | #define F10_DCHR_1 0x194 | |
230 | ||
231 | #define F10_DCHR_FOUR_RANK_DIMM BIT(18) | |
1433eb99 | 232 | #define DDR3_MODE BIT(8) |
cfe40fdb DT |
233 | #define F10_DCHR_MblMode BIT(6) |
234 | ||
235 | ||
236 | #define F10_DCTL_SEL_LOW 0x110 | |
b2b0c605 BP |
237 | #define dct_sel_baseaddr(pvt) ((pvt->dct_sel_low) & 0xFFFFF800) |
238 | #define dct_sel_interleave_addr(pvt) (((pvt->dct_sel_low) >> 6) & 0x3) | |
239 | #define dct_high_range_enabled(pvt) (pvt->dct_sel_low & BIT(0)) | |
240 | #define dct_interleave_enabled(pvt) (pvt->dct_sel_low & BIT(2)) | |
241 | #define dct_ganging_enabled(pvt) (pvt->dct_sel_low & BIT(4)) | |
242 | #define dct_data_intlv_enabled(pvt) (pvt->dct_sel_low & BIT(5)) | |
243 | #define dct_dram_enabled(pvt) (pvt->dct_sel_low & BIT(8)) | |
244 | #define dct_memory_cleared(pvt) (pvt->dct_sel_low & BIT(10)) | |
cfe40fdb DT |
245 | |
246 | #define F10_DCTL_SEL_HIGH 0x114 | |
247 | ||
cfe40fdb DT |
248 | /* |
249 | * Function 3 - Misc Control | |
250 | */ | |
251 | #define K8_NBCTL 0x40 | |
252 | ||
253 | /* Correctable ECC error reporting enable */ | |
254 | #define K8_NBCTL_CECCEn BIT(0) | |
255 | ||
256 | /* UnCorrectable ECC error reporting enable */ | |
257 | #define K8_NBCTL_UECCEn BIT(1) | |
258 | ||
259 | #define K8_NBCFG 0x44 | |
260 | #define K8_NBCFG_CHIPKILL BIT(23) | |
261 | #define K8_NBCFG_ECC_ENABLE BIT(22) | |
262 | ||
263 | #define K8_NBSL 0x48 | |
264 | ||
265 | ||
cfe40fdb DT |
266 | /* Family F10h: Normalized Extended Error Codes */ |
267 | #define F10_NBSL_EXT_ERR_RES 0x0 | |
cfe40fdb | 268 | #define F10_NBSL_EXT_ERR_ECC 0x8 |
cfe40fdb DT |
269 | |
270 | /* Next two are overloaded values */ | |
271 | #define F10_NBSL_EXT_ERR_LINK_PROTO 0xB | |
272 | #define F10_NBSL_EXT_ERR_L3_PROTO 0xB | |
273 | ||
274 | #define F10_NBSL_EXT_ERR_NB_ARRAY 0xC | |
275 | #define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD | |
276 | #define F10_NBSL_EXT_ERR_LINK_RETRY 0xE | |
277 | ||
278 | /* Next two are overloaded values */ | |
279 | #define F10_NBSL_EXT_ERR_GART_WALK 0xF | |
280 | #define F10_NBSL_EXT_ERR_DEV_WALK 0xF | |
281 | ||
282 | /* 0x10 to 0x1B: Reserved */ | |
283 | #define F10_NBSL_EXT_ERR_L3_DATA 0x1C | |
284 | #define F10_NBSL_EXT_ERR_L3_TAG 0x1D | |
285 | #define F10_NBSL_EXT_ERR_L3_LRU 0x1E | |
286 | ||
287 | /* K8: Normalized Extended Error Codes */ | |
288 | #define K8_NBSL_EXT_ERR_ECC 0x0 | |
289 | #define K8_NBSL_EXT_ERR_CRC 0x1 | |
290 | #define K8_NBSL_EXT_ERR_SYNC 0x2 | |
291 | #define K8_NBSL_EXT_ERR_MST 0x3 | |
292 | #define K8_NBSL_EXT_ERR_TGT 0x4 | |
293 | #define K8_NBSL_EXT_ERR_GART 0x5 | |
294 | #define K8_NBSL_EXT_ERR_RMW 0x6 | |
295 | #define K8_NBSL_EXT_ERR_WDT 0x7 | |
296 | #define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8 | |
297 | #define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD | |
298 | ||
cfe40fdb DT |
299 | /* |
300 | * The following are for BUS type errors AFTER values have been normalized by | |
301 | * shifting right | |
302 | */ | |
303 | #define K8_NBSL_PP_SRC 0x0 | |
304 | #define K8_NBSL_PP_RES 0x1 | |
305 | #define K8_NBSL_PP_OBS 0x2 | |
306 | #define K8_NBSL_PP_GENERIC 0x3 | |
307 | ||
cfe40fdb | 308 | #define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF) |
cfe40fdb | 309 | |
cfe40fdb DT |
310 | #define K8_NBEAL 0x50 |
311 | #define K8_NBEAH 0x54 | |
312 | #define K8_SCRCTRL 0x58 | |
313 | ||
314 | #define F10_NB_CFG_LOW 0x88 | |
cfe40fdb DT |
315 | |
316 | #define F10_ONLINE_SPARE 0xB0 | |
317 | #define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1)) | |
318 | #define F10_ONLINE_SPARE_SWAPDONE1(x) ((x) & BIT(3)) | |
319 | #define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007) | |
320 | #define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007) | |
321 | ||
322 | #define F10_NB_ARRAY_ADDR 0xB8 | |
323 | ||
324 | #define F10_NB_ARRAY_DRAM_ECC 0x80000000 | |
325 | ||
326 | /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ | |
327 | #define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1) | |
328 | ||
329 | #define F10_NB_ARRAY_DATA 0xBC | |
330 | ||
331 | #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ | |
332 | (BIT(((word) & 0xF) + 20) | \ | |
94baaee4 | 333 | BIT(17) | bits) |
cfe40fdb DT |
334 | |
335 | #define SET_NB_DRAM_INJECTION_READ(word, bits) \ | |
336 | (BIT(((word) & 0xF) + 20) | \ | |
94baaee4 | 337 | BIT(16) | bits) |
cfe40fdb DT |
338 | |
339 | #define K8_NBCAP 0xE8 | |
340 | #define K8_NBCAP_CORES (BIT(12)|BIT(13)) | |
341 | #define K8_NBCAP_CHIPKILL BIT(4) | |
342 | #define K8_NBCAP_SECDED BIT(3) | |
cfe40fdb DT |
343 | #define K8_NBCAP_DCT_DUAL BIT(0) |
344 | ||
ad6a32e9 BP |
345 | #define EXT_NB_MCA_CFG 0x180 |
346 | ||
f6d6ae96 | 347 | /* MSRs */ |
cfe40fdb DT |
348 | #define K8_MSR_MCGCTL_NBE BIT(4) |
349 | ||
350 | #define K8_MSR_MC4CTL 0x0410 | |
351 | #define K8_MSR_MC4STAT 0x0411 | |
352 | #define K8_MSR_MC4ADDR 0x0412 | |
353 | ||
354 | /* AMD sets the first MC device at device ID 0x18. */ | |
37da0450 | 355 | static inline int get_node_id(struct pci_dev *pdev) |
cfe40fdb DT |
356 | { |
357 | return PCI_SLOT(pdev->devfn) - 0x18; | |
358 | } | |
359 | ||
b2b0c605 | 360 | enum amd_families { |
cfe40fdb DT |
361 | K8_CPUS = 0, |
362 | F10_CPUS, | |
b2b0c605 BP |
363 | F15_CPUS, |
364 | NUM_FAMILIES, | |
cfe40fdb DT |
365 | }; |
366 | ||
cfe40fdb DT |
367 | /* Error injection control structure */ |
368 | struct error_injection { | |
369 | u32 section; | |
370 | u32 word; | |
371 | u32 bit_map; | |
372 | }; | |
373 | ||
7f19bf75 BP |
374 | /* low and high part of PCI config space regs */ |
375 | struct reg_pair { | |
376 | u32 lo, hi; | |
377 | }; | |
378 | ||
379 | /* | |
380 | * See F1x[1, 0][7C:40] DRAM Base/Limit Registers | |
381 | */ | |
382 | struct dram_range { | |
383 | struct reg_pair base; | |
384 | struct reg_pair lim; | |
385 | }; | |
386 | ||
11c75ead BP |
387 | /* A DCT chip selects collection */ |
388 | struct chip_select { | |
389 | u32 csbases[NUM_CHIPSELECTS]; | |
390 | u8 b_cnt; | |
391 | ||
392 | u32 csmasks[NUM_CHIPSELECTS]; | |
393 | u8 m_cnt; | |
394 | }; | |
395 | ||
cfe40fdb | 396 | struct amd64_pvt { |
b8cfa02f BP |
397 | struct low_ops *ops; |
398 | ||
cfe40fdb | 399 | /* pci_device handles which we utilize */ |
8d5b5d9c | 400 | struct pci_dev *F1, *F2, *F3; |
cfe40fdb DT |
401 | |
402 | int mc_node_id; /* MC index of this MC node */ | |
403 | int ext_model; /* extended model value of this node */ | |
cfe40fdb DT |
404 | int channel_count; |
405 | ||
406 | /* Raw registers */ | |
407 | u32 dclr0; /* DRAM Configuration Low DCT0 reg */ | |
408 | u32 dclr1; /* DRAM Configuration Low DCT1 reg */ | |
409 | u32 dchr0; /* DRAM Configuration High DCT0 reg */ | |
410 | u32 dchr1; /* DRAM Configuration High DCT1 reg */ | |
411 | u32 nbcap; /* North Bridge Capabilities */ | |
412 | u32 nbcfg; /* F10 North Bridge Configuration */ | |
413 | u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ | |
414 | u32 dhar; /* DRAM Hoist reg */ | |
415 | u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ | |
416 | u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ | |
417 | ||
11c75ead BP |
418 | /* one for each DCT */ |
419 | struct chip_select csels[2]; | |
cfe40fdb | 420 | |
7f19bf75 BP |
421 | /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ |
422 | struct dram_range ranges[DRAM_RANGES]; | |
cfe40fdb | 423 | |
cfe40fdb DT |
424 | u64 top_mem; /* top of memory below 4GB */ |
425 | u64 top_mem2; /* top of memory above 4GB */ | |
426 | ||
b2b0c605 BP |
427 | u32 dct_sel_low; /* DRAM Controller Select Low Reg */ |
428 | u32 dct_sel_hi; /* DRAM Controller Select High Reg */ | |
429 | u32 online_spare; /* On-Line spare Reg */ | |
cfe40fdb | 430 | |
ad6a32e9 BP |
431 | /* x4 or x8 syndromes in use */ |
432 | u8 syn_type; | |
433 | ||
cfe40fdb | 434 | /* temp storage for when input is received from sysfs */ |
ef44cc4c | 435 | struct err_regs ctl_error_info; |
cfe40fdb DT |
436 | |
437 | /* place to store error injection parameters prior to issue */ | |
438 | struct error_injection injection; | |
439 | ||
395ae783 BP |
440 | /* DCT per-family scrubrate setting */ |
441 | u32 min_scrubrate; | |
442 | ||
0092b20d BP |
443 | /* family name this instance is running on */ |
444 | const char *ctl_name; | |
445 | ||
ae7bb7c6 BP |
446 | }; |
447 | ||
7f19bf75 BP |
448 | static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i) |
449 | { | |
450 | u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; | |
451 | ||
452 | if (boot_cpu_data.x86 == 0xf) | |
453 | return addr; | |
454 | ||
455 | return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; | |
456 | } | |
457 | ||
458 | static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i) | |
459 | { | |
460 | u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; | |
461 | ||
462 | if (boot_cpu_data.x86 == 0xf) | |
463 | return lim; | |
464 | ||
465 | return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; | |
466 | } | |
467 | ||
ae7bb7c6 BP |
468 | /* |
469 | * per-node ECC settings descriptor | |
470 | */ | |
471 | struct ecc_settings { | |
472 | u32 old_nbctl; | |
473 | bool nbctl_valid; | |
474 | ||
cfe40fdb | 475 | struct flags { |
d95cf4de BP |
476 | unsigned long nb_mce_enable:1; |
477 | unsigned long nb_ecc_prev:1; | |
cfe40fdb DT |
478 | } flags; |
479 | }; | |
480 | ||
cfe40fdb DT |
481 | extern const char *tt_msgs[4]; |
482 | extern const char *ll_msgs[4]; | |
483 | extern const char *rrrr_msgs[16]; | |
484 | extern const char *to_msgs[2]; | |
485 | extern const char *pp_msgs[4]; | |
486 | extern const char *ii_msgs[4]; | |
cfe40fdb DT |
487 | extern const char *htlink_msgs[8]; |
488 | ||
7d6034d3 | 489 | #ifdef CONFIG_EDAC_DEBUG |
9cdeb404 | 490 | #define NUM_DBG_ATTRS 5 |
7d6034d3 DT |
491 | #else |
492 | #define NUM_DBG_ATTRS 0 | |
493 | #endif | |
494 | ||
495 | #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION | |
496 | #define NUM_INJ_ATTRS 5 | |
497 | #else | |
498 | #define NUM_INJ_ATTRS 0 | |
499 | #endif | |
500 | ||
501 | extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS], | |
502 | amd64_inj_attrs[NUM_INJ_ATTRS]; | |
503 | ||
cfe40fdb DT |
504 | /* |
505 | * Each of the PCI Device IDs types have their own set of hardware accessor | |
506 | * functions and per device encoding/decoding logic. | |
507 | */ | |
508 | struct low_ops { | |
1433eb99 BP |
509 | int (*early_channel_count) (struct amd64_pvt *pvt); |
510 | ||
511 | u64 (*get_error_address) (struct mem_ctl_info *mci, | |
512 | struct err_regs *info); | |
1433eb99 BP |
513 | void (*read_dram_ctl_register) (struct amd64_pvt *pvt); |
514 | void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, | |
515 | struct err_regs *info, u64 SystemAddr); | |
516 | int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode); | |
b2b0c605 BP |
517 | int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset, |
518 | u32 *val, const char *func); | |
cfe40fdb DT |
519 | }; |
520 | ||
521 | struct amd64_family_type { | |
522 | const char *ctl_name; | |
8d5b5d9c | 523 | u16 f1_id, f3_id; |
cfe40fdb DT |
524 | struct low_ops ops; |
525 | }; | |
526 | ||
b2b0c605 BP |
527 | int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, |
528 | u32 val, const char *func); | |
6ba5dcdc | 529 | |
b2b0c605 BP |
530 | #define amd64_read_pci_cfg(pdev, offset, val) \ |
531 | __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) | |
6ba5dcdc | 532 | |
b2b0c605 BP |
533 | #define amd64_write_pci_cfg(pdev, offset, val) \ |
534 | __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) | |
6ba5dcdc | 535 | |
b2b0c605 BP |
536 | #define amd64_read_dct_pci_cfg(pvt, offset, val) \ |
537 | pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__) | |
6ba5dcdc | 538 | |
cfe40fdb DT |
539 | /* |
540 | * For future CPU versions, verify the following as new 'slow' rates appear and | |
541 | * modify the necessary skip values for the supported CPU. | |
542 | */ | |
543 | #define K8_MIN_SCRUB_RATE_BITS 0x0 | |
544 | #define F10_MIN_SCRUB_RATE_BITS 0x5 | |
cfe40fdb | 545 | |
cfe40fdb DT |
546 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, |
547 | u64 *hole_offset, u64 *hole_size); |