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Commit | Line | Data |
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fd3d6780 DT |
1 | #include "amd64_edac.h" |
2 | ||
3 | /* | |
4 | * accept a hex value and store it into the virtual error register file, field: | |
5 | * nbeal and nbeah. Assume virtual error values have already been set for: NBSL, | |
6 | * NBSH and NBCFG. Then proceed to map the error values to a MC, CSROW and | |
7 | * CHANNEL | |
8 | */ | |
9 | static ssize_t amd64_nbea_store(struct mem_ctl_info *mci, const char *data, | |
10 | size_t count) | |
11 | { | |
12 | struct amd64_pvt *pvt = mci->pvt_info; | |
7cfd4a87 | 13 | u64 value; |
fd3d6780 | 14 | int ret = 0; |
7cfd4a87 | 15 | struct mce m; |
fd3d6780 DT |
16 | |
17 | ret = strict_strtoull(data, 16, &value); | |
18 | if (ret != -EINVAL) { | |
7cfd4a87 BP |
19 | struct err_regs *regs = &pvt->ctl_error_info; |
20 | ||
fd3d6780 DT |
21 | debugf0("received NBEA= 0x%llx\n", value); |
22 | ||
23 | /* place the value into the virtual error packet */ | |
24 | pvt->ctl_error_info.nbeal = (u32) value; | |
25 | value >>= 32; | |
26 | pvt->ctl_error_info.nbeah = (u32) value; | |
27 | ||
7cfd4a87 BP |
28 | m.addr = value; |
29 | m.status = regs->nbsl | ((u64)regs->nbsh << 32); | |
30 | ||
fd3d6780 DT |
31 | /* Process the Mapping request */ |
32 | /* TODO: Add race prevention */ | |
7cfd4a87 | 33 | amd_decode_nb_mce(pvt->mc_node_id, &m, regs->nbcfg); |
fd3d6780 DT |
34 | |
35 | return count; | |
36 | } | |
37 | return ret; | |
38 | } | |
39 | ||
40 | /* display back what the last NBEA (MCA NB Address (MC4_ADDR)) was written */ | |
41 | static ssize_t amd64_nbea_show(struct mem_ctl_info *mci, char *data) | |
42 | { | |
43 | struct amd64_pvt *pvt = mci->pvt_info; | |
44 | u64 value; | |
45 | ||
46 | value = pvt->ctl_error_info.nbeah; | |
47 | value <<= 32; | |
48 | value |= pvt->ctl_error_info.nbeal; | |
49 | ||
50 | return sprintf(data, "%llx\n", value); | |
51 | } | |
52 | ||
53 | /* store the NBSL (MCA NB Status Low (MC4_STATUS)) value user desires */ | |
54 | static ssize_t amd64_nbsl_store(struct mem_ctl_info *mci, const char *data, | |
55 | size_t count) | |
56 | { | |
57 | struct amd64_pvt *pvt = mci->pvt_info; | |
58 | unsigned long value; | |
59 | int ret = 0; | |
60 | ||
61 | ret = strict_strtoul(data, 16, &value); | |
62 | if (ret != -EINVAL) { | |
63 | debugf0("received NBSL= 0x%lx\n", value); | |
64 | ||
65 | pvt->ctl_error_info.nbsl = (u32) value; | |
66 | ||
67 | return count; | |
68 | } | |
69 | return ret; | |
70 | } | |
71 | ||
72 | /* display back what the last NBSL value written */ | |
73 | static ssize_t amd64_nbsl_show(struct mem_ctl_info *mci, char *data) | |
74 | { | |
75 | struct amd64_pvt *pvt = mci->pvt_info; | |
76 | u32 value; | |
77 | ||
78 | value = pvt->ctl_error_info.nbsl; | |
79 | ||
80 | return sprintf(data, "%x\n", value); | |
81 | } | |
82 | ||
83 | /* store the NBSH (MCA NB Status High) value user desires */ | |
84 | static ssize_t amd64_nbsh_store(struct mem_ctl_info *mci, const char *data, | |
85 | size_t count) | |
86 | { | |
87 | struct amd64_pvt *pvt = mci->pvt_info; | |
88 | unsigned long value; | |
89 | int ret = 0; | |
90 | ||
91 | ret = strict_strtoul(data, 16, &value); | |
92 | if (ret != -EINVAL) { | |
93 | debugf0("received NBSH= 0x%lx\n", value); | |
94 | ||
95 | pvt->ctl_error_info.nbsh = (u32) value; | |
96 | ||
97 | return count; | |
98 | } | |
99 | return ret; | |
100 | } | |
101 | ||
102 | /* display back what the last NBSH value written */ | |
103 | static ssize_t amd64_nbsh_show(struct mem_ctl_info *mci, char *data) | |
104 | { | |
105 | struct amd64_pvt *pvt = mci->pvt_info; | |
106 | u32 value; | |
107 | ||
108 | value = pvt->ctl_error_info.nbsh; | |
109 | ||
110 | return sprintf(data, "%x\n", value); | |
111 | } | |
112 | ||
113 | /* accept and store the NBCFG (MCA NB Configuration) value user desires */ | |
114 | static ssize_t amd64_nbcfg_store(struct mem_ctl_info *mci, | |
115 | const char *data, size_t count) | |
116 | { | |
117 | struct amd64_pvt *pvt = mci->pvt_info; | |
118 | unsigned long value; | |
119 | int ret = 0; | |
120 | ||
121 | ret = strict_strtoul(data, 16, &value); | |
122 | if (ret != -EINVAL) { | |
123 | debugf0("received NBCFG= 0x%lx\n", value); | |
124 | ||
125 | pvt->ctl_error_info.nbcfg = (u32) value; | |
126 | ||
127 | return count; | |
128 | } | |
129 | return ret; | |
130 | } | |
131 | ||
132 | /* various show routines for the controls of a MCI */ | |
133 | static ssize_t amd64_nbcfg_show(struct mem_ctl_info *mci, char *data) | |
134 | { | |
135 | struct amd64_pvt *pvt = mci->pvt_info; | |
136 | ||
137 | return sprintf(data, "%x\n", pvt->ctl_error_info.nbcfg); | |
138 | } | |
139 | ||
140 | ||
141 | static ssize_t amd64_dhar_show(struct mem_ctl_info *mci, char *data) | |
142 | { | |
143 | struct amd64_pvt *pvt = mci->pvt_info; | |
144 | ||
145 | return sprintf(data, "%x\n", pvt->dhar); | |
146 | } | |
147 | ||
148 | ||
149 | static ssize_t amd64_dbam_show(struct mem_ctl_info *mci, char *data) | |
150 | { | |
151 | struct amd64_pvt *pvt = mci->pvt_info; | |
152 | ||
153 | return sprintf(data, "%x\n", pvt->dbam0); | |
154 | } | |
155 | ||
156 | ||
157 | static ssize_t amd64_topmem_show(struct mem_ctl_info *mci, char *data) | |
158 | { | |
159 | struct amd64_pvt *pvt = mci->pvt_info; | |
160 | ||
161 | return sprintf(data, "%llx\n", pvt->top_mem); | |
162 | } | |
163 | ||
164 | ||
165 | static ssize_t amd64_topmem2_show(struct mem_ctl_info *mci, char *data) | |
166 | { | |
167 | struct amd64_pvt *pvt = mci->pvt_info; | |
168 | ||
169 | return sprintf(data, "%llx\n", pvt->top_mem2); | |
170 | } | |
171 | ||
172 | static ssize_t amd64_hole_show(struct mem_ctl_info *mci, char *data) | |
173 | { | |
174 | u64 hole_base = 0; | |
175 | u64 hole_offset = 0; | |
176 | u64 hole_size = 0; | |
177 | ||
178 | amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size); | |
179 | ||
180 | return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset, | |
181 | hole_size); | |
182 | } | |
183 | ||
184 | /* | |
185 | * update NUM_DBG_ATTRS in case you add new members | |
186 | */ | |
187 | struct mcidev_sysfs_attribute amd64_dbg_attrs[] = { | |
188 | ||
189 | { | |
190 | .attr = { | |
191 | .name = "nbea_ctl", | |
192 | .mode = (S_IRUGO | S_IWUSR) | |
193 | }, | |
194 | .show = amd64_nbea_show, | |
195 | .store = amd64_nbea_store, | |
196 | }, | |
197 | { | |
198 | .attr = { | |
199 | .name = "nbsl_ctl", | |
200 | .mode = (S_IRUGO | S_IWUSR) | |
201 | }, | |
202 | .show = amd64_nbsl_show, | |
203 | .store = amd64_nbsl_store, | |
204 | }, | |
205 | { | |
206 | .attr = { | |
207 | .name = "nbsh_ctl", | |
208 | .mode = (S_IRUGO | S_IWUSR) | |
209 | }, | |
210 | .show = amd64_nbsh_show, | |
211 | .store = amd64_nbsh_store, | |
212 | }, | |
213 | { | |
214 | .attr = { | |
215 | .name = "nbcfg_ctl", | |
216 | .mode = (S_IRUGO | S_IWUSR) | |
217 | }, | |
218 | .show = amd64_nbcfg_show, | |
219 | .store = amd64_nbcfg_store, | |
220 | }, | |
221 | { | |
222 | .attr = { | |
223 | .name = "dhar", | |
224 | .mode = (S_IRUGO) | |
225 | }, | |
226 | .show = amd64_dhar_show, | |
227 | .store = NULL, | |
228 | }, | |
229 | { | |
230 | .attr = { | |
231 | .name = "dbam", | |
232 | .mode = (S_IRUGO) | |
233 | }, | |
234 | .show = amd64_dbam_show, | |
235 | .store = NULL, | |
236 | }, | |
237 | { | |
238 | .attr = { | |
239 | .name = "topmem", | |
240 | .mode = (S_IRUGO) | |
241 | }, | |
242 | .show = amd64_topmem_show, | |
243 | .store = NULL, | |
244 | }, | |
245 | { | |
246 | .attr = { | |
247 | .name = "topmem2", | |
248 | .mode = (S_IRUGO) | |
249 | }, | |
250 | .show = amd64_topmem2_show, | |
251 | .store = NULL, | |
252 | }, | |
253 | { | |
254 | .attr = { | |
255 | .name = "dram_hole", | |
256 | .mode = (S_IRUGO) | |
257 | }, | |
258 | .show = amd64_hole_show, | |
259 | .store = NULL, | |
260 | }, | |
261 | }; |