[mirror_ubuntu-artful-kernel.git] / drivers / edac / amd76x_edac.c

/*
 * AMD 76x Memory Controller kernel module
 * (C) 2003 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Thayne Harbaugh
 * Based on work by Dan Hollis <goemon at anime dot net> and others.
 *	http://www.anime.net/~goemon/linux-ecc/
 *
 * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_module.h"

#define AMD76X_REVISION	" Ver: 2.0.2"
#define EDAC_MOD_STR	"amd76x_edac"

#define amd76x_printk(level, fmt, arg...) \
	edac_printk(level, "amd76x", fmt, ##arg)

#define amd76x_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)

#define AMD76X_NR_CSROWS 8
#define AMD76X_NR_DIMMS  4

/* AMD 76x register addresses - device 0 function 0 - PCI bridge */

#define AMD76X_ECC_MODE_STATUS	0x48	/* Mode and status of ECC (32b)
					 *
					 * 31:16 reserved
					 * 15:14 SERR enabled: x1=ue 1x=ce
					 * 13    reserved
					 * 12    diag: disabled, enabled
					 * 11:10 mode: dis, EC, ECC, ECC+scrub
					 *  9:8  status: x1=ue 1x=ce
					 *  7:4  UE cs row
					 *  3:0  CE cs row
					 */

#define AMD76X_DRAM_MODE_STATUS	0x58	/* DRAM Mode and status (32b)
					 *
					 * 31:26 clock disable 5 - 0
					 * 25    SDRAM init
					 * 24    reserved
					 * 23    mode register service
					 * 22:21 suspend to RAM
					 * 20    burst refresh enable
					 * 19    refresh disable
					 * 18    reserved
					 * 17:16 cycles-per-refresh
					 * 15:8  reserved
					 *  7:0  x4 mode enable 7 - 0
					 */

#define AMD76X_MEM_BASE_ADDR	0xC0	/* Memory base address (8 x 32b)
					 *
					 * 31:23 chip-select base
					 * 22:16 reserved
					 * 15:7  chip-select mask
					 *  6:3  reserved
					 *  2:1  address mode
					 *  0    chip-select enable
					 */

struct amd76x_error_info {
	u32 ecc_mode_status;
};

enum amd76x_chips {
	AMD761 = 0,
	AMD762
};

struct amd76x_dev_info {
	const char *ctl_name;
};

static const struct amd76x_dev_info amd76x_devs[] = {
	[AMD761] = {
		.ctl_name = "AMD761"},
	[AMD762] = {
		.ctl_name = "AMD762"},
};

static struct edac_pci_ctl_info *amd76x_pci;

/**
 *	amd76x_get_error_info	-	fetch error information
 *	@mci: Memory controller
 *	@info: Info to fill in
 *
 *	Fetch and store the AMD76x ECC status. Clear pending status
 *	on the chip so that further errors will be reported
 */
static void amd76x_get_error_info(struct mem_ctl_info *mci,
				struct amd76x_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->pdev);
	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
			&info->ecc_mode_status);

	if (info->ecc_mode_status & BIT(8))
		pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
				 (u32) BIT(8), (u32) BIT(8));

	if (info->ecc_mode_status & BIT(9))
		pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
				 (u32) BIT(9), (u32) BIT(9));
}

/**
 *	amd76x_process_error_info	-	Error check
 *	@mci: Memory controller
 *	@info: Previously fetched information from chip
 *	@handle_errors: 1 if we should do recovery
 *
 *	Process the chip state and decide if an error has occurred.
 *	A return of 1 indicates an error. Also if handle_errors is true
 *	then attempt to handle and clean up after the error
 */
static int amd76x_process_error_info(struct mem_ctl_info *mci,
				struct amd76x_error_info *info,
				int handle_errors)
{
	int error_found;
	u32 row;

	error_found = 0;

	/*
	 *      Check for an uncorrectable error
	 */
	if (info->ecc_mode_status & BIT(8)) {
		error_found = 1;

		if (handle_errors) {
			row = (info->ecc_mode_status >> 4) & 0xf;
			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
					     mci->csrows[row]->first_page, 0, 0,
					     row, 0, -1,
					     mci->ctl_name, "");
		}
	}

	/*
	 *      Check for a correctable error
	 */
	if (info->ecc_mode_status & BIT(9)) {
		error_found = 1;

		if (handle_errors) {
			row = info->ecc_mode_status & 0xf;
			edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
					     mci->csrows[row]->first_page, 0, 0,
					     row, 0, -1,
					     mci->ctl_name, "");
		}
	}

	return error_found;
}

/**
 *	amd76x_check	-	Poll the controller
 *	@mci: Memory controller
 *
 *	Called by the poll handlers this function reads the status
 *	from the controller and checks for errors.
 */
static void amd76x_check(struct mem_ctl_info *mci)
{
	struct amd76x_error_info info;
	edac_dbg(3, "\n");
	amd76x_get_error_info(mci, &info);
	amd76x_process_error_info(mci, &info, 1);
}

static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
			enum edac_type edac_mode)
{
	struct csrow_info *csrow;
	struct dimm_info *dimm;
	u32 mba, mba_base, mba_mask, dms;
	int index;

	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = mci->csrows[index];
		dimm = csrow->channels[0]->dimm;

		/* find the DRAM Chip Select Base address and mask */
		pci_read_config_dword(pdev,
				AMD76X_MEM_BASE_ADDR + (index * 4), &mba);

		if (!(mba & BIT(0)))
			continue;

		mba_base = mba & 0xff800000UL;
		mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
		pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
		csrow->first_page = mba_base >> PAGE_SHIFT;
		dimm->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
		csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
		csrow->page_mask = mba_mask >> PAGE_SHIFT;
		dimm->grain = dimm->nr_pages << PAGE_SHIFT;
		dimm->mtype = MEM_RDDR;
		dimm->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
		dimm->edac_mode = edac_mode;
	}
}

/**
 *	amd76x_probe1	-	Perform set up for detected device
 *	@pdev; PCI device detected
 *	@dev_idx: Device type index
 *
 *	We have found an AMD76x and now need to set up the memory
 *	controller status reporting. We configure and set up the
 *	memory controller reporting and claim the device.
 */
static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
{
	static const enum edac_type ems_modes[] = {
		EDAC_NONE,
		EDAC_EC,
		EDAC_SECDED,
		EDAC_SECDED
	};
	struct mem_ctl_info *mci;
	struct edac_mc_layer layers[2];
	u32 ems;
	u32 ems_mode;
	struct amd76x_error_info discard;

	edac_dbg(0, "\n");
	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
	ems_mode = (ems >> 10) & 0x3;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = AMD76X_NR_CSROWS;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = 1;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);

	if (mci == NULL)
		return -ENOMEM;

	edac_dbg(0, "mci = %p\n", mci);
	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_RDDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
	mci->edac_cap = ems_mode ?
		(EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = AMD76X_REVISION;
	mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = amd76x_check;
	mci->ctl_page_to_phys = NULL;

	amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
	amd76x_get_error_info(mci, &discard);	/* clear counters */

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "failed edac_mc_add_mc()\n");
		goto fail;
	}

	/* allocating generic PCI control info */
	amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!amd76x_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	/* get this far and it's successful */
	edac_dbg(3, "success\n");
	return 0;

fail:
	edac_mc_free(mci);
	return -ENODEV;
}

/* returns count (>= 0), or negative on error */
static int amd76x_init_one(struct pci_dev *pdev,
			   const struct pci_device_id *ent)
{
	edac_dbg(0, "\n");

	/* don't need to call pci_enable_device() */
	return amd76x_probe1(pdev, ent->driver_data);
}

/**
 *	amd76x_remove_one	-	driver shutdown
 *	@pdev: PCI device being handed back
 *
 *	Called when the driver is unloaded. Find the matching mci
 *	structure for the device then delete the mci and free the
 *	resources.
 */
static void amd76x_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	edac_dbg(0, "\n");

	if (amd76x_pci)
		edac_pci_release_generic_ctl(amd76x_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id amd76x_pci_tbl[] = {
	{
	 PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 AMD762},
	{
	 PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 AMD761},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);

static struct pci_driver amd76x_driver = {
	.name = EDAC_MOD_STR,
	.probe = amd76x_init_one,
	.remove = amd76x_remove_one,
	.id_table = amd76x_pci_tbl,
};

static int __init amd76x_init(void)
{
       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	return pci_register_driver(&amd76x_driver);
}

static void __exit amd76x_exit(void)
{
	pci_unregister_driver(&amd76x_driver);
}

module_init(amd76x_init);
module_exit(amd76x_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
806c35f5 AC	1	/*
	2	* AMD 76x Memory Controller kernel module
	3	* (C) 2003 Linux Networx (http://lnxi.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Thayne Harbaugh
	8	* Based on work by Dan Hollis <goemon at anime dot net> and others.
	9	* http://www.anime.net/~goemon/linux-ecc/
	10	*
	11	* $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
	12	*
	13	*/
	14
806c35f5 AC	15	#include <linux/module.h>
806c35f5 AC	16	#include <linux/init.h>
806c35f5 AC	17	#include <linux/pci.h>
806c35f5 AC	18	#include <linux/pci_ids.h>
c3c52bce	19	#include <linux/edac.h>
78d88e8a	20	#include "edac_module.h"
806c35f5	21
152ba394	22	#define AMD76X_REVISION " Ver: 2.0.2"
929a40ec	23	#define EDAC_MOD_STR "amd76x_edac"
37f04581	24
537fba28	25	#define amd76x_printk(level, fmt, arg...) \
e7ecd891	26	edac_printk(level, "amd76x", fmt, ##arg)
537fba28 DP	27
537fba28 DP	28	#define amd76x_mc_printk(mci, level, fmt, arg...) \
e7ecd891	29	edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
537fba28	30
806c35f5	31	#define AMD76X_NR_CSROWS 8
806c35f5 AC	32	#define AMD76X_NR_DIMMS 4
806c35f5 AC	33
806c35f5	34	/* AMD 76x register addresses - device 0 function 0 - PCI bridge */
e7ecd891	35
806c35f5 AC	36	#define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
	37	*
	38	* 31:16 reserved
	39	* 15:14 SERR enabled: x1=ue 1x=ce
	40	* 13 reserved
	41	* 12 diag: disabled, enabled
	42	* 11:10 mode: dis, EC, ECC, ECC+scrub
	43	* 9:8 status: x1=ue 1x=ce
	44	* 7:4 UE cs row
	45	* 3:0 CE cs row
	46	*/
e7ecd891	47
806c35f5 AC	48	#define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
	49	*
	50	* 31:26 clock disable 5 - 0
	51	* 25 SDRAM init
	52	* 24 reserved
	53	* 23 mode register service
	54	* 22:21 suspend to RAM
	55	* 20 burst refresh enable
	56	* 19 refresh disable
	57	* 18 reserved
	58	* 17:16 cycles-per-refresh
	59	* 15:8 reserved
	60	* 7:0 x4 mode enable 7 - 0
	61	*/
e7ecd891	62
806c35f5 AC	63	#define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
	64	*
	65	* 31:23 chip-select base
	66	* 22:16 reserved
	67	* 15:7 chip-select mask
	68	* 6:3 reserved
	69	* 2:1 address mode
	70	* 0 chip-select enable
	71	*/
	72
806c35f5 AC	73	struct amd76x_error_info {
	74	u32 ecc_mode_status;
	75	};
	76
806c35f5 AC	77	enum amd76x_chips {
	78	AMD761 = 0,
	79	AMD762
	80	};
	81
806c35f5 AC	82	struct amd76x_dev_info {
	83	const char *ctl_name;
	84	};
	85
806c35f5	86	static const struct amd76x_dev_info amd76x_devs[] = {
e7ecd891	87	[AMD761] = {
052dfb45	88	.ctl_name = "AMD761"},
e7ecd891	89	[AMD762] = {
052dfb45	90	.ctl_name = "AMD762"},
806c35f5 AC	91	};
806c35f5 AC	92
456a2f95 DJ	93	static struct edac_pci_ctl_info *amd76x_pci;
456a2f95 DJ	94
806c35f5 AC	95	/**
	96	* amd76x_get_error_info - fetch error information
	97	* @mci: Memory controller
	98	* @info: Info to fill in
	99	*
	100	* Fetch and store the AMD76x ECC status. Clear pending status
	101	* on the chip so that further errors will be reported
	102	*/
e7ecd891	103	static void amd76x_get_error_info(struct mem_ctl_info *mci,
052dfb45	104	struct amd76x_error_info *info)
806c35f5	105	{
37f04581 DT	106	struct pci_dev *pdev;
37f04581 DT	107
fd687502	108	pdev = to_pci_dev(mci->pdev);
37f04581	109	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
052dfb45	110	&info->ecc_mode_status);
806c35f5 AC	111
806c35f5 AC	112	if (info->ecc_mode_status & BIT(8))
37f04581	113	pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
67cb2b61	114	(u32) BIT(8), (u32) BIT(8));
806c35f5 AC	115
806c35f5 AC	116	if (info->ecc_mode_status & BIT(9))
37f04581	117	pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
67cb2b61	118	(u32) BIT(9), (u32) BIT(9));
806c35f5 AC	119	}
806c35f5 AC	120
806c35f5 AC	121	/**
	122	* amd76x_process_error_info - Error check
	123	* @mci: Memory controller
	124	* @info: Previously fetched information from chip
	125	* @handle_errors: 1 if we should do recovery
	126	*
	127	* Process the chip state and decide if an error has occurred.
	128	* A return of 1 indicates an error. Also if handle_errors is true
	129	* then attempt to handle and clean up after the error
	130	*/
e7ecd891	131	static int amd76x_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	132	struct amd76x_error_info *info,
052dfb45 DT	133	int handle_errors)
806c35f5 AC	134	{
	135	int error_found;
	136	u32 row;
	137
	138	error_found = 0;
	139
	140	/*
67cb2b61	141	* Check for an uncorrectable error
806c35f5 AC	142	*/
	143	if (info->ecc_mode_status & BIT(8)) {
	144	error_found = 1;
	145
	146	if (handle_errors) {
	147	row = (info->ecc_mode_status >> 4) & 0xf;
9eb07a7f	148	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
de3910eb	149	mci->csrows[row]->first_page, 0, 0,
d8c34af4	150	row, 0, -1,
03f7eae8	151	mci->ctl_name, "");
806c35f5 AC	152	}
	153	}
	154
	155	/*
67cb2b61	156	* Check for a correctable error
806c35f5 AC	157	*/
	158	if (info->ecc_mode_status & BIT(9)) {
	159	error_found = 1;
	160
	161	if (handle_errors) {
	162	row = info->ecc_mode_status & 0xf;
9eb07a7f	163	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
de3910eb	164	mci->csrows[row]->first_page, 0, 0,
d8c34af4	165	row, 0, -1,
03f7eae8	166	mci->ctl_name, "");
806c35f5 AC	167	}
806c35f5 AC	168	}
e7ecd891	169
806c35f5 AC	170	return error_found;
	171	}
	172
	173	/**
	174	* amd76x_check - Poll the controller
	175	* @mci: Memory controller
	176	*
	177	* Called by the poll handlers this function reads the status
	178	* from the controller and checks for errors.
	179	*/
806c35f5 AC	180	static void amd76x_check(struct mem_ctl_info *mci)
	181	{
	182	struct amd76x_error_info info;
956b9ba1	183	edac_dbg(3, "\n");
806c35f5 AC	184	amd76x_get_error_info(mci, &info);
	185	amd76x_process_error_info(mci, &info, 1);
	186	}
	187
13189525	188	static void amd76x_init_csrows(struct mem_ctl_info mci, struct pci_dev pdev,
052dfb45	189	enum edac_type edac_mode)
13189525 DT	190	{
13189525 DT	191	struct csrow_info *csrow;
084a4fcc	192	struct dimm_info *dimm;
13189525 DT	193	u32 mba, mba_base, mba_mask, dms;
	194	int index;
	195
	196	for (index = 0; index < mci->nr_csrows; index++) {
de3910eb MCC	197	csrow = mci->csrows[index];
de3910eb MCC	198	dimm = csrow->channels[0]->dimm;
13189525 DT	199
	200	/* find the DRAM Chip Select Base address and mask */
	201	pci_read_config_dword(pdev,
052dfb45	202	AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
13189525 DT	203
	204	if (!(mba & BIT(0)))
	205	continue;
	206
	207	mba_base = mba & 0xff800000UL;
	208	mba_mask = ((mba & 0xff80) << 16) \| 0x7fffffUL;
	209	pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
	210	csrow->first_page = mba_base >> PAGE_SHIFT;
a895bf8b MCC	211	dimm->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
a895bf8b MCC	212	csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
13189525	213	csrow->page_mask = mba_mask >> PAGE_SHIFT;
a895bf8b	214	dimm->grain = dimm->nr_pages << PAGE_SHIFT;
084a4fcc MCC	215	dimm->mtype = MEM_RDDR;
	216	dimm->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
	217	dimm->edac_mode = edac_mode;
13189525 DT	218	}
	219	}
	220
806c35f5 AC	221	/**
	222	* amd76x_probe1 - Perform set up for detected device
	223	* @pdev; PCI device detected
	224	* @dev_idx: Device type index
	225	*
	226	* We have found an AMD76x and now need to set up the memory
	227	* controller status reporting. We configure and set up the
	228	* memory controller reporting and claim the device.
	229	*/
806c35f5 AC	230	static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
806c35f5 AC	231	{
13189525	232	static const enum edac_type ems_modes[] = {
806c35f5 AC	233	EDAC_NONE,
	234	EDAC_EC,
	235	EDAC_SECDED,
	236	EDAC_SECDED
	237	};
d8c34af4 MCC	238	struct mem_ctl_info *mci;
d8c34af4 MCC	239	struct edac_mc_layer layers[2];
806c35f5 AC	240	u32 ems;
806c35f5 AC	241	u32 ems_mode;
749ede57	242	struct amd76x_error_info discard;
806c35f5	243
956b9ba1	244	edac_dbg(0, "\n");
806c35f5 AC	245	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
806c35f5 AC	246	ems_mode = (ems >> 10) & 0x3;
806c35f5	247
d8c34af4 MCC	248	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	249	layers[0].size = AMD76X_NR_CSROWS;
	250	layers[0].is_virt_csrow = true;
	251	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	252	layers[1].size = 1;
	253	layers[1].is_virt_csrow = false;
ca0907b9	254	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
d8c34af4 MCC	255
d8c34af4 MCC	256	if (mci == NULL)
13189525	257	return -ENOMEM;
806c35f5	258
956b9ba1	259	edac_dbg(0, "mci = %p\n", mci);
fd687502	260	mci->pdev = &pdev->dev;
806c35f5	261	mci->mtype_cap = MEM_FLAG_RDDR;
806c35f5 AC	262	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;
806c35f5 AC	263	mci->edac_cap = ems_mode ?
052dfb45	264	(EDAC_FLAG_EC \| EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
680cbbbb	265	mci->mod_name = EDAC_MOD_STR;
37f04581	266	mci->mod_ver = AMD76X_REVISION;
806c35f5	267	mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
c4192705	268	mci->dev_name = pci_name(pdev);
806c35f5 AC	269	mci->edac_check = amd76x_check;
	270	mci->ctl_page_to_phys = NULL;
	271
13189525	272	amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
67cb2b61	273	amd76x_get_error_info(mci, &discard); /* clear counters */
806c35f5	274
2d7bbb91 DT	275	/* Here we assume that we will never see multiple instances of this
	276	* type of memory controller. The ID is therefore hardcoded to 0.
	277	*/
b8f6f975	278	if (edac_mc_add_mc(mci)) {
956b9ba1	279	edac_dbg(3, "failed edac_mc_add_mc()\n");
806c35f5 AC	280	goto fail;
	281	}
	282
456a2f95 DJ	283	/* allocating generic PCI control info */
	284	amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	285	if (!amd76x_pci) {
	286	printk(KERN_WARNING
	287	"%s(): Unable to create PCI control\n",
	288	__func__);
	289	printk(KERN_WARNING
	290	"%s(): PCI error report via EDAC not setup\n",
	291	__func__);
	292	}
	293
806c35f5	294	/* get this far and it's successful */
956b9ba1	295	edac_dbg(3, "success\n");
806c35f5 AC	296	return 0;
806c35f5 AC	297
052dfb45	298	fail:
13189525 DT	299	edac_mc_free(mci);
13189525 DT	300	return -ENODEV;
806c35f5 AC	301	}
	302
	303	/* returns count (>= 0), or negative on error */
9b3c6e85 GKH	304	static int amd76x_init_one(struct pci_dev *pdev,
9b3c6e85 GKH	305	const struct pci_device_id *ent)
806c35f5	306	{
956b9ba1	307	edac_dbg(0, "\n");
806c35f5	308
ee6583f6	309	/* don't need to call pci_enable_device() */
806c35f5 AC	310	return amd76x_probe1(pdev, ent->driver_data);
	311	}
	312
806c35f5 AC	313	/**
	314	* amd76x_remove_one - driver shutdown
	315	* @pdev: PCI device being handed back
	316	*
	317	* Called when the driver is unloaded. Find the matching mci
	318	* structure for the device then delete the mci and free the
	319	* resources.
	320	*/
9b3c6e85	321	static void amd76x_remove_one(struct pci_dev *pdev)
806c35f5 AC	322	{
	323	struct mem_ctl_info *mci;
	324
956b9ba1	325	edac_dbg(0, "\n");
806c35f5	326
456a2f95 DJ	327	if (amd76x_pci)
	328	edac_pci_release_generic_ctl(amd76x_pci);
	329
37f04581	330	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
806c35f5	331	return;
18dbc337	332
806c35f5 AC	333	edac_mc_free(mci);
	334	}
	335
ba935f40	336	static const struct pci_device_id amd76x_pci_tbl[] = {
e7ecd891	337	{
67cb2b61 DT	338	PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
67cb2b61 DT	339	AMD762},
e7ecd891	340	{
67cb2b61 DT	341	PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
67cb2b61 DT	342	AMD761},
e7ecd891	343	{
67cb2b61 DT	344	0,
67cb2b61 DT	345	} /* 0 terminated list. */
806c35f5 AC	346	};
	347
	348	MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
	349
806c35f5	350	static struct pci_driver amd76x_driver = {
680cbbbb	351	.name = EDAC_MOD_STR,
806c35f5	352	.probe = amd76x_init_one,
9b3c6e85	353	.remove = amd76x_remove_one,
806c35f5 AC	354	.id_table = amd76x_pci_tbl,
	355	};
	356
da9bb1d2	357	static int __init amd76x_init(void)
806c35f5	358	{
c3c52bce HM	359	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	360	opstate_init();
	361
806c35f5 AC	362	return pci_register_driver(&amd76x_driver);
	363	}
	364
	365	static void __exit amd76x_exit(void)
	366	{
	367	pci_unregister_driver(&amd76x_driver);
	368	}
	369
	370	module_init(amd76x_init);
	371	module_exit(amd76x_exit);
	372
	373	MODULE_LICENSE("GPL");
	374	MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
	375	MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");
c3c52bce HM	376
	377	module_param(edac_op_state, int, 0444);
	378	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");