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Commit | Line | Data |
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da9bb1d2 AC |
1 | /* |
2 | * edac_mc kernel module | |
49c0dab7 | 3 | * (C) 2005, 2006 Linux Networx (http://lnxi.com) |
da9bb1d2 AC |
4 | * This file may be distributed under the terms of the |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
9 | * http://www.anime.net/~goemon/linux-ecc/ | |
10 | * | |
11 | * Modified by Dave Peterson and Doug Thompson | |
12 | * | |
13 | */ | |
14 | ||
da9bb1d2 AC |
15 | #include <linux/module.h> |
16 | #include <linux/proc_fs.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/sysctl.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/timer.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/jiffies.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/list.h> | |
da9bb1d2 | 28 | #include <linux/ctype.h> |
c0d12172 | 29 | #include <linux/edac.h> |
53f2d028 | 30 | #include <linux/bitops.h> |
7c0f6ba6 | 31 | #include <linux/uaccess.h> |
da9bb1d2 | 32 | #include <asm/page.h> |
78d88e8a | 33 | #include "edac_mc.h" |
7c9281d7 | 34 | #include "edac_module.h" |
53f2d028 MCC |
35 | #include <ras/ras_event.h> |
36 | ||
b01aec9b BP |
37 | #ifdef CONFIG_EDAC_ATOMIC_SCRUB |
38 | #include <asm/edac.h> | |
39 | #else | |
40 | #define edac_atomic_scrub(va, size) do { } while (0) | |
41 | #endif | |
42 | ||
8c22b4fe BP |
43 | int edac_op_state = EDAC_OPSTATE_INVAL; |
44 | EXPORT_SYMBOL_GPL(edac_op_state); | |
45 | ||
fee27d7d BP |
46 | static int edac_report = EDAC_REPORTING_ENABLED; |
47 | ||
da9bb1d2 | 48 | /* lock to memory controller's control array */ |
63b7df91 | 49 | static DEFINE_MUTEX(mem_ctls_mutex); |
ff6ac2a6 | 50 | static LIST_HEAD(mc_devices); |
da9bb1d2 | 51 | |
80cc7d87 MCC |
52 | /* |
53 | * Used to lock EDAC MC to just one module, avoiding two drivers e. g. | |
54 | * apei/ghes and i7core_edac to be used at the same time. | |
55 | */ | |
3877c7d1 | 56 | static const char *edac_mc_owner; |
80cc7d87 | 57 | |
88d84ac9 BP |
58 | static struct bus_type mc_bus[EDAC_MAX_MCS]; |
59 | ||
bffc7dec | 60 | int edac_get_report_status(void) |
fee27d7d BP |
61 | { |
62 | return edac_report; | |
63 | } | |
bffc7dec | 64 | EXPORT_SYMBOL_GPL(edac_get_report_status); |
fee27d7d | 65 | |
bffc7dec | 66 | void edac_set_report_status(int new) |
fee27d7d BP |
67 | { |
68 | if (new == EDAC_REPORTING_ENABLED || | |
69 | new == EDAC_REPORTING_DISABLED || | |
70 | new == EDAC_REPORTING_FORCE) | |
71 | edac_report = new; | |
72 | } | |
bffc7dec | 73 | EXPORT_SYMBOL_GPL(edac_set_report_status); |
fee27d7d BP |
74 | |
75 | static int edac_report_set(const char *str, const struct kernel_param *kp) | |
76 | { | |
77 | if (!str) | |
78 | return -EINVAL; | |
79 | ||
80 | if (!strncmp(str, "on", 2)) | |
81 | edac_report = EDAC_REPORTING_ENABLED; | |
82 | else if (!strncmp(str, "off", 3)) | |
83 | edac_report = EDAC_REPORTING_DISABLED; | |
84 | else if (!strncmp(str, "force", 5)) | |
85 | edac_report = EDAC_REPORTING_FORCE; | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
90 | static int edac_report_get(char *buffer, const struct kernel_param *kp) | |
91 | { | |
92 | int ret = 0; | |
93 | ||
94 | switch (edac_report) { | |
95 | case EDAC_REPORTING_ENABLED: | |
96 | ret = sprintf(buffer, "on"); | |
97 | break; | |
98 | case EDAC_REPORTING_DISABLED: | |
99 | ret = sprintf(buffer, "off"); | |
100 | break; | |
101 | case EDAC_REPORTING_FORCE: | |
102 | ret = sprintf(buffer, "force"); | |
103 | break; | |
104 | default: | |
105 | ret = -EINVAL; | |
106 | break; | |
107 | } | |
108 | ||
109 | return ret; | |
110 | } | |
111 | ||
112 | static const struct kernel_param_ops edac_report_ops = { | |
113 | .set = edac_report_set, | |
114 | .get = edac_report_get, | |
115 | }; | |
116 | ||
117 | module_param_cb(edac_report, &edac_report_ops, &edac_report, 0644); | |
118 | ||
6e84d359 MCC |
119 | unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf, |
120 | unsigned len) | |
121 | { | |
122 | struct mem_ctl_info *mci = dimm->mci; | |
123 | int i, n, count = 0; | |
124 | char *p = buf; | |
125 | ||
126 | for (i = 0; i < mci->n_layers; i++) { | |
127 | n = snprintf(p, len, "%s %d ", | |
128 | edac_layer_name[mci->layers[i].type], | |
129 | dimm->location[i]); | |
130 | p += n; | |
131 | len -= n; | |
132 | count += n; | |
133 | if (!len) | |
134 | break; | |
135 | } | |
136 | ||
137 | return count; | |
138 | } | |
139 | ||
da9bb1d2 AC |
140 | #ifdef CONFIG_EDAC_DEBUG |
141 | ||
a4b4be3f | 142 | static void edac_mc_dump_channel(struct rank_info *chan) |
da9bb1d2 | 143 | { |
6e84d359 MCC |
144 | edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx); |
145 | edac_dbg(4, " channel = %p\n", chan); | |
146 | edac_dbg(4, " channel->csrow = %p\n", chan->csrow); | |
147 | edac_dbg(4, " channel->dimm = %p\n", chan->dimm); | |
4275be63 MCC |
148 | } |
149 | ||
6e84d359 | 150 | static void edac_mc_dump_dimm(struct dimm_info *dimm, int number) |
4275be63 | 151 | { |
6e84d359 MCC |
152 | char location[80]; |
153 | ||
154 | edac_dimm_info_location(dimm, location, sizeof(location)); | |
155 | ||
156 | edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n", | |
9713faec | 157 | dimm->mci->csbased ? "rank" : "dimm", |
6e84d359 MCC |
158 | number, location, dimm->csrow, dimm->cschannel); |
159 | edac_dbg(4, " dimm = %p\n", dimm); | |
160 | edac_dbg(4, " dimm->label = '%s'\n", dimm->label); | |
161 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
162 | edac_dbg(4, " dimm->grain = %d\n", dimm->grain); | |
163 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
da9bb1d2 AC |
164 | } |
165 | ||
2da1c119 | 166 | static void edac_mc_dump_csrow(struct csrow_info *csrow) |
da9bb1d2 | 167 | { |
6e84d359 MCC |
168 | edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx); |
169 | edac_dbg(4, " csrow = %p\n", csrow); | |
170 | edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page); | |
171 | edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page); | |
172 | edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask); | |
173 | edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels); | |
174 | edac_dbg(4, " csrow->channels = %p\n", csrow->channels); | |
175 | edac_dbg(4, " csrow->mci = %p\n", csrow->mci); | |
da9bb1d2 AC |
176 | } |
177 | ||
2da1c119 | 178 | static void edac_mc_dump_mci(struct mem_ctl_info *mci) |
da9bb1d2 | 179 | { |
956b9ba1 JP |
180 | edac_dbg(3, "\tmci = %p\n", mci); |
181 | edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap); | |
182 | edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap); | |
183 | edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap); | |
184 | edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check); | |
185 | edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n", | |
186 | mci->nr_csrows, mci->csrows); | |
187 | edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n", | |
188 | mci->tot_dimms, mci->dimms); | |
189 | edac_dbg(3, "\tdev = %p\n", mci->pdev); | |
190 | edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n", | |
191 | mci->mod_name, mci->ctl_name); | |
192 | edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info); | |
da9bb1d2 AC |
193 | } |
194 | ||
24f9a7fe BP |
195 | #endif /* CONFIG_EDAC_DEBUG */ |
196 | ||
f4ce6eca | 197 | const char * const edac_mem_types[] = { |
4cfc3a40 BP |
198 | [MEM_EMPTY] = "Empty csrow", |
199 | [MEM_RESERVED] = "Reserved csrow type", | |
200 | [MEM_UNKNOWN] = "Unknown csrow type", | |
201 | [MEM_FPM] = "Fast page mode RAM", | |
202 | [MEM_EDO] = "Extended data out RAM", | |
203 | [MEM_BEDO] = "Burst Extended data out RAM", | |
204 | [MEM_SDR] = "Single data rate SDRAM", | |
205 | [MEM_RDR] = "Registered single data rate SDRAM", | |
206 | [MEM_DDR] = "Double data rate SDRAM", | |
207 | [MEM_RDDR] = "Registered Double data rate SDRAM", | |
208 | [MEM_RMBS] = "Rambus DRAM", | |
209 | [MEM_DDR2] = "Unbuffered DDR2 RAM", | |
210 | [MEM_FB_DDR2] = "Fully buffered DDR2", | |
211 | [MEM_RDDR2] = "Registered DDR2 RAM", | |
212 | [MEM_XDR] = "Rambus XDR", | |
213 | [MEM_DDR3] = "Unbuffered DDR3 RAM", | |
214 | [MEM_RDDR3] = "Registered DDR3 RAM", | |
215 | [MEM_LRDDR3] = "Load-Reduced DDR3 RAM", | |
216 | [MEM_DDR4] = "Unbuffered DDR4 RAM", | |
217 | [MEM_RDDR4] = "Registered DDR4 RAM", | |
239642fe BP |
218 | }; |
219 | EXPORT_SYMBOL_GPL(edac_mem_types); | |
220 | ||
93e4fe64 MCC |
221 | /** |
222 | * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation | |
223 | * @p: pointer to a pointer with the memory offset to be used. At | |
224 | * return, this will be incremented to point to the next offset | |
225 | * @size: Size of the data structure to be reserved | |
226 | * @n_elems: Number of elements that should be reserved | |
da9bb1d2 AC |
227 | * |
228 | * If 'size' is a constant, the compiler will optimize this whole function | |
93e4fe64 MCC |
229 | * down to either a no-op or the addition of a constant to the value of '*p'. |
230 | * | |
231 | * The 'p' pointer is absolutely needed to keep the proper advancing | |
232 | * further in memory to the proper offsets when allocating the struct along | |
233 | * with its embedded structs, as edac_device_alloc_ctl_info() does it | |
234 | * above, for example. | |
235 | * | |
236 | * At return, the pointer 'p' will be incremented to be used on a next call | |
237 | * to this function. | |
da9bb1d2 | 238 | */ |
93e4fe64 | 239 | void *edac_align_ptr(void **p, unsigned size, int n_elems) |
da9bb1d2 AC |
240 | { |
241 | unsigned align, r; | |
93e4fe64 | 242 | void *ptr = *p; |
da9bb1d2 | 243 | |
93e4fe64 MCC |
244 | *p += size * n_elems; |
245 | ||
246 | /* | |
247 | * 'p' can possibly be an unaligned item X such that sizeof(X) is | |
248 | * 'size'. Adjust 'p' so that its alignment is at least as | |
249 | * stringent as what the compiler would provide for X and return | |
250 | * the aligned result. | |
251 | * Here we assume that the alignment of a "long long" is the most | |
da9bb1d2 AC |
252 | * stringent alignment that the compiler will ever provide by default. |
253 | * As far as I know, this is a reasonable assumption. | |
254 | */ | |
255 | if (size > sizeof(long)) | |
256 | align = sizeof(long long); | |
257 | else if (size > sizeof(int)) | |
258 | align = sizeof(long); | |
259 | else if (size > sizeof(short)) | |
260 | align = sizeof(int); | |
261 | else if (size > sizeof(char)) | |
262 | align = sizeof(short); | |
263 | else | |
079708b9 | 264 | return (char *)ptr; |
da9bb1d2 | 265 | |
8447c4d1 | 266 | r = (unsigned long)p % align; |
da9bb1d2 AC |
267 | |
268 | if (r == 0) | |
079708b9 | 269 | return (char *)ptr; |
da9bb1d2 | 270 | |
93e4fe64 MCC |
271 | *p += align - r; |
272 | ||
7391c6dc | 273 | return (void *)(((unsigned long)ptr) + align - r); |
da9bb1d2 AC |
274 | } |
275 | ||
faa2ad09 SR |
276 | static void _edac_mc_free(struct mem_ctl_info *mci) |
277 | { | |
278 | int i, chn, row; | |
279 | struct csrow_info *csr; | |
280 | const unsigned int tot_dimms = mci->tot_dimms; | |
281 | const unsigned int tot_channels = mci->num_cschannel; | |
282 | const unsigned int tot_csrows = mci->nr_csrows; | |
283 | ||
284 | if (mci->dimms) { | |
285 | for (i = 0; i < tot_dimms; i++) | |
286 | kfree(mci->dimms[i]); | |
287 | kfree(mci->dimms); | |
288 | } | |
289 | if (mci->csrows) { | |
290 | for (row = 0; row < tot_csrows; row++) { | |
291 | csr = mci->csrows[row]; | |
292 | if (csr) { | |
293 | if (csr->channels) { | |
294 | for (chn = 0; chn < tot_channels; chn++) | |
295 | kfree(csr->channels[chn]); | |
296 | kfree(csr->channels); | |
297 | } | |
298 | kfree(csr); | |
299 | } | |
300 | } | |
301 | kfree(mci->csrows); | |
302 | } | |
303 | kfree(mci); | |
304 | } | |
305 | ||
ca0907b9 MCC |
306 | struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, |
307 | unsigned n_layers, | |
308 | struct edac_mc_layer *layers, | |
309 | unsigned sz_pvt) | |
da9bb1d2 AC |
310 | { |
311 | struct mem_ctl_info *mci; | |
4275be63 | 312 | struct edac_mc_layer *layer; |
de3910eb MCC |
313 | struct csrow_info *csr; |
314 | struct rank_info *chan; | |
a7d7d2e1 | 315 | struct dimm_info *dimm; |
4275be63 MCC |
316 | u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; |
317 | unsigned pos[EDAC_MAX_LAYERS]; | |
4275be63 MCC |
318 | unsigned size, tot_dimms = 1, count = 1; |
319 | unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0; | |
5926ff50 | 320 | void *pvt, *p, *ptr = NULL; |
de3910eb | 321 | int i, j, row, chn, n, len, off; |
4275be63 MCC |
322 | bool per_rank = false; |
323 | ||
324 | BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0); | |
325 | /* | |
326 | * Calculate the total amount of dimms and csrows/cschannels while | |
327 | * in the old API emulation mode | |
328 | */ | |
329 | for (i = 0; i < n_layers; i++) { | |
330 | tot_dimms *= layers[i].size; | |
331 | if (layers[i].is_virt_csrow) | |
332 | tot_csrows *= layers[i].size; | |
333 | else | |
334 | tot_channels *= layers[i].size; | |
335 | ||
336 | if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) | |
337 | per_rank = true; | |
338 | } | |
da9bb1d2 AC |
339 | |
340 | /* Figure out the offsets of the various items from the start of an mc | |
341 | * structure. We want the alignment of each item to be at least as | |
342 | * stringent as what the compiler would provide if we could simply | |
343 | * hardcode everything into a single struct. | |
344 | */ | |
93e4fe64 | 345 | mci = edac_align_ptr(&ptr, sizeof(*mci), 1); |
4275be63 | 346 | layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); |
4275be63 MCC |
347 | for (i = 0; i < n_layers; i++) { |
348 | count *= layers[i].size; | |
956b9ba1 | 349 | edac_dbg(4, "errcount layer %d size %d\n", i, count); |
4275be63 MCC |
350 | ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); |
351 | ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); | |
352 | tot_errcount += 2 * count; | |
353 | } | |
354 | ||
956b9ba1 | 355 | edac_dbg(4, "allocating %d error counters\n", tot_errcount); |
93e4fe64 | 356 | pvt = edac_align_ptr(&ptr, sz_pvt, 1); |
079708b9 | 357 | size = ((unsigned long)pvt) + sz_pvt; |
da9bb1d2 | 358 | |
956b9ba1 JP |
359 | edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", |
360 | size, | |
361 | tot_dimms, | |
362 | per_rank ? "ranks" : "dimms", | |
363 | tot_csrows * tot_channels); | |
de3910eb | 364 | |
8096cfaf DT |
365 | mci = kzalloc(size, GFP_KERNEL); |
366 | if (mci == NULL) | |
da9bb1d2 AC |
367 | return NULL; |
368 | ||
369 | /* Adjust pointers so they point within the memory we just allocated | |
370 | * rather than an imaginary chunk of memory located at address 0. | |
371 | */ | |
4275be63 | 372 | layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); |
4275be63 MCC |
373 | for (i = 0; i < n_layers; i++) { |
374 | mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i])); | |
375 | mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i])); | |
376 | } | |
079708b9 | 377 | pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; |
da9bb1d2 | 378 | |
b8f6f975 | 379 | /* setup index and various internal pointers */ |
4275be63 | 380 | mci->mc_idx = mc_num; |
4275be63 | 381 | mci->tot_dimms = tot_dimms; |
da9bb1d2 | 382 | mci->pvt_info = pvt; |
4275be63 MCC |
383 | mci->n_layers = n_layers; |
384 | mci->layers = layer; | |
385 | memcpy(mci->layers, layers, sizeof(*layer) * n_layers); | |
386 | mci->nr_csrows = tot_csrows; | |
387 | mci->num_cschannel = tot_channels; | |
9713faec | 388 | mci->csbased = per_rank; |
da9bb1d2 | 389 | |
a7d7d2e1 | 390 | /* |
de3910eb | 391 | * Alocate and fill the csrow/channels structs |
a7d7d2e1 | 392 | */ |
d3d09e18 | 393 | mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); |
de3910eb MCC |
394 | if (!mci->csrows) |
395 | goto error; | |
4275be63 | 396 | for (row = 0; row < tot_csrows; row++) { |
de3910eb MCC |
397 | csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); |
398 | if (!csr) | |
399 | goto error; | |
400 | mci->csrows[row] = csr; | |
4275be63 MCC |
401 | csr->csrow_idx = row; |
402 | csr->mci = mci; | |
403 | csr->nr_channels = tot_channels; | |
d3d09e18 | 404 | csr->channels = kcalloc(tot_channels, sizeof(*csr->channels), |
de3910eb MCC |
405 | GFP_KERNEL); |
406 | if (!csr->channels) | |
407 | goto error; | |
4275be63 MCC |
408 | |
409 | for (chn = 0; chn < tot_channels; chn++) { | |
de3910eb MCC |
410 | chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL); |
411 | if (!chan) | |
412 | goto error; | |
413 | csr->channels[chn] = chan; | |
da9bb1d2 | 414 | chan->chan_idx = chn; |
4275be63 MCC |
415 | chan->csrow = csr; |
416 | } | |
417 | } | |
418 | ||
419 | /* | |
de3910eb | 420 | * Allocate and fill the dimm structs |
4275be63 | 421 | */ |
d3d09e18 | 422 | mci->dimms = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL); |
de3910eb MCC |
423 | if (!mci->dimms) |
424 | goto error; | |
425 | ||
4275be63 MCC |
426 | memset(&pos, 0, sizeof(pos)); |
427 | row = 0; | |
428 | chn = 0; | |
4275be63 | 429 | for (i = 0; i < tot_dimms; i++) { |
de3910eb MCC |
430 | chan = mci->csrows[row]->channels[chn]; |
431 | off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]); | |
432 | if (off < 0 || off >= tot_dimms) { | |
433 | edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n"); | |
434 | goto error; | |
435 | } | |
4275be63 | 436 | |
de3910eb | 437 | dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); |
08a4a136 DC |
438 | if (!dimm) |
439 | goto error; | |
de3910eb | 440 | mci->dimms[off] = dimm; |
4275be63 | 441 | dimm->mci = mci; |
4275be63 | 442 | |
5926ff50 MCC |
443 | /* |
444 | * Copy DIMM location and initialize it. | |
445 | */ | |
446 | len = sizeof(dimm->label); | |
447 | p = dimm->label; | |
448 | n = snprintf(p, len, "mc#%u", mc_num); | |
449 | p += n; | |
450 | len -= n; | |
451 | for (j = 0; j < n_layers; j++) { | |
452 | n = snprintf(p, len, "%s#%u", | |
453 | edac_layer_name[layers[j].type], | |
454 | pos[j]); | |
455 | p += n; | |
456 | len -= n; | |
4275be63 MCC |
457 | dimm->location[j] = pos[j]; |
458 | ||
5926ff50 MCC |
459 | if (len <= 0) |
460 | break; | |
461 | } | |
462 | ||
4275be63 MCC |
463 | /* Link it to the csrows old API data */ |
464 | chan->dimm = dimm; | |
465 | dimm->csrow = row; | |
466 | dimm->cschannel = chn; | |
467 | ||
468 | /* Increment csrow location */ | |
24bef66e | 469 | if (layers[0].is_virt_csrow) { |
4275be63 | 470 | chn++; |
24bef66e MCC |
471 | if (chn == tot_channels) { |
472 | chn = 0; | |
473 | row++; | |
474 | } | |
475 | } else { | |
476 | row++; | |
477 | if (row == tot_csrows) { | |
478 | row = 0; | |
479 | chn++; | |
480 | } | |
4275be63 | 481 | } |
a7d7d2e1 | 482 | |
4275be63 MCC |
483 | /* Increment dimm location */ |
484 | for (j = n_layers - 1; j >= 0; j--) { | |
485 | pos[j]++; | |
486 | if (pos[j] < layers[j].size) | |
487 | break; | |
488 | pos[j] = 0; | |
da9bb1d2 AC |
489 | } |
490 | } | |
491 | ||
81d87cb1 | 492 | mci->op_state = OP_ALLOC; |
8096cfaf | 493 | |
da9bb1d2 | 494 | return mci; |
de3910eb MCC |
495 | |
496 | error: | |
faa2ad09 | 497 | _edac_mc_free(mci); |
de3910eb MCC |
498 | |
499 | return NULL; | |
4275be63 | 500 | } |
9110540f | 501 | EXPORT_SYMBOL_GPL(edac_mc_alloc); |
da9bb1d2 | 502 | |
da9bb1d2 AC |
503 | void edac_mc_free(struct mem_ctl_info *mci) |
504 | { | |
956b9ba1 | 505 | edac_dbg(1, "\n"); |
bbc560ae | 506 | |
faa2ad09 SR |
507 | /* If we're not yet registered with sysfs free only what was allocated |
508 | * in edac_mc_alloc(). | |
509 | */ | |
510 | if (!device_is_registered(&mci->dev)) { | |
511 | _edac_mc_free(mci); | |
512 | return; | |
513 | } | |
514 | ||
de3910eb | 515 | /* the mci instance is freed here, when the sysfs object is dropped */ |
7a623c03 | 516 | edac_unregister_sysfs(mci); |
da9bb1d2 | 517 | } |
9110540f | 518 | EXPORT_SYMBOL_GPL(edac_mc_free); |
da9bb1d2 | 519 | |
d7fc9d77 YG |
520 | bool edac_has_mcs(void) |
521 | { | |
522 | bool ret; | |
523 | ||
524 | mutex_lock(&mem_ctls_mutex); | |
525 | ||
526 | ret = list_empty(&mc_devices); | |
527 | ||
528 | mutex_unlock(&mem_ctls_mutex); | |
529 | ||
530 | return !ret; | |
531 | } | |
532 | EXPORT_SYMBOL_GPL(edac_has_mcs); | |
533 | ||
c73e8833 BP |
534 | /* Caller must hold mem_ctls_mutex */ |
535 | static struct mem_ctl_info *__find_mci_by_dev(struct device *dev) | |
da9bb1d2 AC |
536 | { |
537 | struct mem_ctl_info *mci; | |
538 | struct list_head *item; | |
539 | ||
956b9ba1 | 540 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
541 | |
542 | list_for_each(item, &mc_devices) { | |
543 | mci = list_entry(item, struct mem_ctl_info, link); | |
544 | ||
fd687502 | 545 | if (mci->pdev == dev) |
da9bb1d2 AC |
546 | return mci; |
547 | } | |
548 | ||
549 | return NULL; | |
550 | } | |
c73e8833 BP |
551 | |
552 | /** | |
553 | * find_mci_by_dev | |
554 | * | |
555 | * scan list of controllers looking for the one that manages | |
556 | * the 'dev' device | |
557 | * @dev: pointer to a struct device related with the MCI | |
558 | */ | |
559 | struct mem_ctl_info *find_mci_by_dev(struct device *dev) | |
560 | { | |
561 | struct mem_ctl_info *ret; | |
562 | ||
563 | mutex_lock(&mem_ctls_mutex); | |
564 | ret = __find_mci_by_dev(dev); | |
565 | mutex_unlock(&mem_ctls_mutex); | |
566 | ||
567 | return ret; | |
568 | } | |
939747bd | 569 | EXPORT_SYMBOL_GPL(find_mci_by_dev); |
da9bb1d2 | 570 | |
81d87cb1 DJ |
571 | /* |
572 | * edac_mc_workq_function | |
573 | * performs the operation scheduled by a workq request | |
574 | */ | |
81d87cb1 DJ |
575 | static void edac_mc_workq_function(struct work_struct *work_req) |
576 | { | |
fbeb4384 | 577 | struct delayed_work *d_work = to_delayed_work(work_req); |
81d87cb1 | 578 | struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work); |
81d87cb1 DJ |
579 | |
580 | mutex_lock(&mem_ctls_mutex); | |
581 | ||
06e912d4 | 582 | if (mci->op_state != OP_RUNNING_POLL) { |
bf52fa4a DT |
583 | mutex_unlock(&mem_ctls_mutex); |
584 | return; | |
585 | } | |
586 | ||
d3116a08 | 587 | if (edac_op_state == EDAC_OPSTATE_POLL) |
81d87cb1 DJ |
588 | mci->edac_check(mci); |
589 | ||
81d87cb1 DJ |
590 | mutex_unlock(&mem_ctls_mutex); |
591 | ||
06e912d4 | 592 | /* Queue ourselves again. */ |
c4cf3b45 | 593 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); |
81d87cb1 DJ |
594 | } |
595 | ||
81d87cb1 | 596 | /* |
bce19683 DT |
597 | * edac_mc_reset_delay_period(unsigned long value) |
598 | * | |
599 | * user space has updated our poll period value, need to | |
600 | * reset our workq delays | |
81d87cb1 | 601 | */ |
9da21b15 | 602 | void edac_mc_reset_delay_period(unsigned long value) |
81d87cb1 | 603 | { |
bce19683 DT |
604 | struct mem_ctl_info *mci; |
605 | struct list_head *item; | |
606 | ||
607 | mutex_lock(&mem_ctls_mutex); | |
608 | ||
bce19683 DT |
609 | list_for_each(item, &mc_devices) { |
610 | mci = list_entry(item, struct mem_ctl_info, link); | |
611 | ||
fbedcaf4 NK |
612 | if (mci->op_state == OP_RUNNING_POLL) |
613 | edac_mod_work(&mci->work, value); | |
bce19683 | 614 | } |
81d87cb1 DJ |
615 | mutex_unlock(&mem_ctls_mutex); |
616 | } | |
617 | ||
bce19683 DT |
618 | |
619 | ||
2d7bbb91 DT |
620 | /* Return 0 on success, 1 on failure. |
621 | * Before calling this function, caller must | |
622 | * assign a unique value to mci->mc_idx. | |
bf52fa4a DT |
623 | * |
624 | * locking model: | |
625 | * | |
626 | * called with the mem_ctls_mutex lock held | |
2d7bbb91 | 627 | */ |
079708b9 | 628 | static int add_mc_to_global_list(struct mem_ctl_info *mci) |
da9bb1d2 AC |
629 | { |
630 | struct list_head *item, *insert_before; | |
631 | struct mem_ctl_info *p; | |
da9bb1d2 | 632 | |
2d7bbb91 | 633 | insert_before = &mc_devices; |
da9bb1d2 | 634 | |
c73e8833 | 635 | p = __find_mci_by_dev(mci->pdev); |
bf52fa4a | 636 | if (unlikely(p != NULL)) |
2d7bbb91 | 637 | goto fail0; |
da9bb1d2 | 638 | |
2d7bbb91 DT |
639 | list_for_each(item, &mc_devices) { |
640 | p = list_entry(item, struct mem_ctl_info, link); | |
da9bb1d2 | 641 | |
2d7bbb91 DT |
642 | if (p->mc_idx >= mci->mc_idx) { |
643 | if (unlikely(p->mc_idx == mci->mc_idx)) | |
644 | goto fail1; | |
da9bb1d2 | 645 | |
2d7bbb91 DT |
646 | insert_before = item; |
647 | break; | |
da9bb1d2 | 648 | } |
da9bb1d2 AC |
649 | } |
650 | ||
651 | list_add_tail_rcu(&mci->link, insert_before); | |
652 | return 0; | |
2d7bbb91 | 653 | |
052dfb45 | 654 | fail0: |
2d7bbb91 | 655 | edac_printk(KERN_WARNING, EDAC_MC, |
fd687502 | 656 | "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev), |
17aa7e03 | 657 | edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx); |
2d7bbb91 DT |
658 | return 1; |
659 | ||
052dfb45 | 660 | fail1: |
2d7bbb91 | 661 | edac_printk(KERN_WARNING, EDAC_MC, |
052dfb45 DT |
662 | "bug in low-level driver: attempt to assign\n" |
663 | " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__); | |
2d7bbb91 | 664 | return 1; |
da9bb1d2 AC |
665 | } |
666 | ||
80cc7d87 | 667 | static int del_mc_from_global_list(struct mem_ctl_info *mci) |
a1d03fcc DP |
668 | { |
669 | list_del_rcu(&mci->link); | |
e2e77098 LJ |
670 | |
671 | /* these are for safe removal of devices from global list while | |
672 | * NMI handlers may be traversing list | |
673 | */ | |
674 | synchronize_rcu(); | |
675 | INIT_LIST_HEAD(&mci->link); | |
80cc7d87 | 676 | |
97bb6c17 | 677 | return list_empty(&mc_devices); |
a1d03fcc DP |
678 | } |
679 | ||
079708b9 | 680 | struct mem_ctl_info *edac_mc_find(int idx) |
5da0831c | 681 | { |
c73e8833 | 682 | struct mem_ctl_info *mci = NULL; |
5da0831c | 683 | struct list_head *item; |
c73e8833 BP |
684 | |
685 | mutex_lock(&mem_ctls_mutex); | |
5da0831c DT |
686 | |
687 | list_for_each(item, &mc_devices) { | |
688 | mci = list_entry(item, struct mem_ctl_info, link); | |
689 | ||
690 | if (mci->mc_idx >= idx) { | |
c73e8833 BP |
691 | if (mci->mc_idx == idx) { |
692 | goto unlock; | |
693 | } | |
5da0831c DT |
694 | break; |
695 | } | |
696 | } | |
697 | ||
c73e8833 BP |
698 | unlock: |
699 | mutex_unlock(&mem_ctls_mutex); | |
700 | return mci; | |
5da0831c DT |
701 | } |
702 | EXPORT_SYMBOL(edac_mc_find); | |
703 | ||
3877c7d1 TK |
704 | const char *edac_get_owner(void) |
705 | { | |
706 | return edac_mc_owner; | |
707 | } | |
708 | EXPORT_SYMBOL_GPL(edac_get_owner); | |
da9bb1d2 AC |
709 | |
710 | /* FIXME - should a warning be printed if no error detection? correction? */ | |
4e8d230d TI |
711 | int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, |
712 | const struct attribute_group **groups) | |
da9bb1d2 | 713 | { |
80cc7d87 | 714 | int ret = -EINVAL; |
956b9ba1 | 715 | edac_dbg(0, "\n"); |
b8f6f975 | 716 | |
88d84ac9 BP |
717 | if (mci->mc_idx >= EDAC_MAX_MCS) { |
718 | pr_warn_once("Too many memory controllers: %d\n", mci->mc_idx); | |
719 | return -ENODEV; | |
720 | } | |
721 | ||
da9bb1d2 AC |
722 | #ifdef CONFIG_EDAC_DEBUG |
723 | if (edac_debug_level >= 3) | |
724 | edac_mc_dump_mci(mci); | |
e7ecd891 | 725 | |
da9bb1d2 AC |
726 | if (edac_debug_level >= 4) { |
727 | int i; | |
728 | ||
729 | for (i = 0; i < mci->nr_csrows; i++) { | |
6e84d359 MCC |
730 | struct csrow_info *csrow = mci->csrows[i]; |
731 | u32 nr_pages = 0; | |
da9bb1d2 | 732 | int j; |
e7ecd891 | 733 | |
6e84d359 MCC |
734 | for (j = 0; j < csrow->nr_channels; j++) |
735 | nr_pages += csrow->channels[j]->dimm->nr_pages; | |
736 | if (!nr_pages) | |
737 | continue; | |
738 | edac_mc_dump_csrow(csrow); | |
739 | for (j = 0; j < csrow->nr_channels; j++) | |
740 | if (csrow->channels[j]->dimm->nr_pages) | |
741 | edac_mc_dump_channel(csrow->channels[j]); | |
da9bb1d2 | 742 | } |
4275be63 | 743 | for (i = 0; i < mci->tot_dimms; i++) |
6e84d359 MCC |
744 | if (mci->dimms[i]->nr_pages) |
745 | edac_mc_dump_dimm(mci->dimms[i], i); | |
da9bb1d2 AC |
746 | } |
747 | #endif | |
63b7df91 | 748 | mutex_lock(&mem_ctls_mutex); |
da9bb1d2 | 749 | |
80cc7d87 MCC |
750 | if (edac_mc_owner && edac_mc_owner != mci->mod_name) { |
751 | ret = -EPERM; | |
752 | goto fail0; | |
753 | } | |
754 | ||
da9bb1d2 | 755 | if (add_mc_to_global_list(mci)) |
028a7b6d | 756 | goto fail0; |
da9bb1d2 AC |
757 | |
758 | /* set load time so that error rate can be tracked */ | |
759 | mci->start_time = jiffies; | |
760 | ||
88d84ac9 BP |
761 | mci->bus = &mc_bus[mci->mc_idx]; |
762 | ||
4e8d230d | 763 | if (edac_create_sysfs_mci_device(mci, groups)) { |
9794f33d | 764 | edac_mc_printk(mci, KERN_WARNING, |
052dfb45 | 765 | "failed to create sysfs device\n"); |
9794f33d | 766 | goto fail1; |
767 | } | |
da9bb1d2 | 768 | |
09667606 | 769 | if (mci->edac_check) { |
81d87cb1 DJ |
770 | mci->op_state = OP_RUNNING_POLL; |
771 | ||
626a7a4d BP |
772 | INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function); |
773 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); | |
774 | ||
81d87cb1 DJ |
775 | } else { |
776 | mci->op_state = OP_RUNNING_INTERRUPT; | |
777 | } | |
778 | ||
da9bb1d2 | 779 | /* Report action taken */ |
7270a608 RR |
780 | edac_mc_printk(mci, KERN_INFO, |
781 | "Giving out device to module %s controller %s: DEV %s (%s)\n", | |
782 | mci->mod_name, mci->ctl_name, mci->dev_name, | |
783 | edac_op_state_to_string(mci->op_state)); | |
da9bb1d2 | 784 | |
80cc7d87 MCC |
785 | edac_mc_owner = mci->mod_name; |
786 | ||
63b7df91 | 787 | mutex_unlock(&mem_ctls_mutex); |
028a7b6d | 788 | return 0; |
da9bb1d2 | 789 | |
052dfb45 | 790 | fail1: |
028a7b6d DP |
791 | del_mc_from_global_list(mci); |
792 | ||
052dfb45 | 793 | fail0: |
63b7df91 | 794 | mutex_unlock(&mem_ctls_mutex); |
80cc7d87 | 795 | return ret; |
da9bb1d2 | 796 | } |
4e8d230d | 797 | EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups); |
da9bb1d2 | 798 | |
079708b9 | 799 | struct mem_ctl_info *edac_mc_del_mc(struct device *dev) |
da9bb1d2 | 800 | { |
18dbc337 | 801 | struct mem_ctl_info *mci; |
da9bb1d2 | 802 | |
956b9ba1 | 803 | edac_dbg(0, "\n"); |
bf52fa4a | 804 | |
63b7df91 | 805 | mutex_lock(&mem_ctls_mutex); |
18dbc337 | 806 | |
bf52fa4a | 807 | /* find the requested mci struct in the global list */ |
c73e8833 | 808 | mci = __find_mci_by_dev(dev); |
bf52fa4a | 809 | if (mci == NULL) { |
63b7df91 | 810 | mutex_unlock(&mem_ctls_mutex); |
18dbc337 DP |
811 | return NULL; |
812 | } | |
813 | ||
09667606 BP |
814 | /* mark MCI offline: */ |
815 | mci->op_state = OP_OFFLINE; | |
816 | ||
97bb6c17 | 817 | if (del_mc_from_global_list(mci)) |
80cc7d87 | 818 | edac_mc_owner = NULL; |
bf52fa4a | 819 | |
09667606 | 820 | mutex_unlock(&mem_ctls_mutex); |
bb31b312 | 821 | |
09667606 | 822 | if (mci->edac_check) |
626a7a4d | 823 | edac_stop_work(&mci->work); |
bb31b312 BP |
824 | |
825 | /* remove from sysfs */ | |
bf52fa4a DT |
826 | edac_remove_sysfs_mci_device(mci); |
827 | ||
537fba28 | 828 | edac_printk(KERN_INFO, EDAC_MC, |
052dfb45 | 829 | "Removed device %d for %s %s: DEV %s\n", mci->mc_idx, |
17aa7e03 | 830 | mci->mod_name, mci->ctl_name, edac_dev_name(mci)); |
bf52fa4a | 831 | |
18dbc337 | 832 | return mci; |
da9bb1d2 | 833 | } |
9110540f | 834 | EXPORT_SYMBOL_GPL(edac_mc_del_mc); |
da9bb1d2 | 835 | |
2da1c119 AB |
836 | static void edac_mc_scrub_block(unsigned long page, unsigned long offset, |
837 | u32 size) | |
da9bb1d2 AC |
838 | { |
839 | struct page *pg; | |
840 | void *virt_addr; | |
841 | unsigned long flags = 0; | |
842 | ||
956b9ba1 | 843 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
844 | |
845 | /* ECC error page was not in our memory. Ignore it. */ | |
079708b9 | 846 | if (!pfn_valid(page)) |
da9bb1d2 AC |
847 | return; |
848 | ||
849 | /* Find the actual page structure then map it and fix */ | |
850 | pg = pfn_to_page(page); | |
851 | ||
852 | if (PageHighMem(pg)) | |
853 | local_irq_save(flags); | |
854 | ||
4e5df7ca | 855 | virt_addr = kmap_atomic(pg); |
da9bb1d2 AC |
856 | |
857 | /* Perform architecture specific atomic scrub operation */ | |
b01aec9b | 858 | edac_atomic_scrub(virt_addr + offset, size); |
da9bb1d2 AC |
859 | |
860 | /* Unmap and complete */ | |
4e5df7ca | 861 | kunmap_atomic(virt_addr); |
da9bb1d2 AC |
862 | |
863 | if (PageHighMem(pg)) | |
864 | local_irq_restore(flags); | |
865 | } | |
866 | ||
da9bb1d2 | 867 | /* FIXME - should return -1 */ |
e7ecd891 | 868 | int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page) |
da9bb1d2 | 869 | { |
de3910eb | 870 | struct csrow_info **csrows = mci->csrows; |
a895bf8b | 871 | int row, i, j, n; |
da9bb1d2 | 872 | |
956b9ba1 | 873 | edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page); |
da9bb1d2 AC |
874 | row = -1; |
875 | ||
876 | for (i = 0; i < mci->nr_csrows; i++) { | |
de3910eb | 877 | struct csrow_info *csrow = csrows[i]; |
a895bf8b MCC |
878 | n = 0; |
879 | for (j = 0; j < csrow->nr_channels; j++) { | |
de3910eb | 880 | struct dimm_info *dimm = csrow->channels[j]->dimm; |
a895bf8b MCC |
881 | n += dimm->nr_pages; |
882 | } | |
883 | if (n == 0) | |
da9bb1d2 AC |
884 | continue; |
885 | ||
956b9ba1 JP |
886 | edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n", |
887 | mci->mc_idx, | |
888 | csrow->first_page, page, csrow->last_page, | |
889 | csrow->page_mask); | |
da9bb1d2 AC |
890 | |
891 | if ((page >= csrow->first_page) && | |
892 | (page <= csrow->last_page) && | |
893 | ((page & csrow->page_mask) == | |
894 | (csrow->first_page & csrow->page_mask))) { | |
895 | row = i; | |
896 | break; | |
897 | } | |
898 | } | |
899 | ||
900 | if (row == -1) | |
537fba28 | 901 | edac_mc_printk(mci, KERN_ERR, |
052dfb45 DT |
902 | "could not look up page error address %lx\n", |
903 | (unsigned long)page); | |
da9bb1d2 AC |
904 | |
905 | return row; | |
906 | } | |
9110540f | 907 | EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page); |
da9bb1d2 | 908 | |
4275be63 MCC |
909 | const char *edac_layer_name[] = { |
910 | [EDAC_MC_LAYER_BRANCH] = "branch", | |
911 | [EDAC_MC_LAYER_CHANNEL] = "channel", | |
912 | [EDAC_MC_LAYER_SLOT] = "slot", | |
913 | [EDAC_MC_LAYER_CHIP_SELECT] = "csrow", | |
c66b5a79 | 914 | [EDAC_MC_LAYER_ALL_MEM] = "memory", |
4275be63 MCC |
915 | }; |
916 | EXPORT_SYMBOL_GPL(edac_layer_name); | |
917 | ||
918 | static void edac_inc_ce_error(struct mem_ctl_info *mci, | |
9eb07a7f MCC |
919 | bool enable_per_layer_report, |
920 | const int pos[EDAC_MAX_LAYERS], | |
921 | const u16 count) | |
da9bb1d2 | 922 | { |
4275be63 | 923 | int i, index = 0; |
da9bb1d2 | 924 | |
9eb07a7f | 925 | mci->ce_mc += count; |
da9bb1d2 | 926 | |
4275be63 | 927 | if (!enable_per_layer_report) { |
9eb07a7f | 928 | mci->ce_noinfo_count += count; |
da9bb1d2 AC |
929 | return; |
930 | } | |
e7ecd891 | 931 | |
4275be63 MCC |
932 | for (i = 0; i < mci->n_layers; i++) { |
933 | if (pos[i] < 0) | |
934 | break; | |
935 | index += pos[i]; | |
9eb07a7f | 936 | mci->ce_per_layer[i][index] += count; |
4275be63 MCC |
937 | |
938 | if (i < mci->n_layers - 1) | |
939 | index *= mci->layers[i + 1].size; | |
940 | } | |
941 | } | |
942 | ||
943 | static void edac_inc_ue_error(struct mem_ctl_info *mci, | |
944 | bool enable_per_layer_report, | |
9eb07a7f MCC |
945 | const int pos[EDAC_MAX_LAYERS], |
946 | const u16 count) | |
4275be63 MCC |
947 | { |
948 | int i, index = 0; | |
949 | ||
9eb07a7f | 950 | mci->ue_mc += count; |
4275be63 MCC |
951 | |
952 | if (!enable_per_layer_report) { | |
993f88f1 | 953 | mci->ue_noinfo_count += count; |
da9bb1d2 AC |
954 | return; |
955 | } | |
956 | ||
4275be63 MCC |
957 | for (i = 0; i < mci->n_layers; i++) { |
958 | if (pos[i] < 0) | |
959 | break; | |
960 | index += pos[i]; | |
9eb07a7f | 961 | mci->ue_per_layer[i][index] += count; |
a7d7d2e1 | 962 | |
4275be63 MCC |
963 | if (i < mci->n_layers - 1) |
964 | index *= mci->layers[i + 1].size; | |
965 | } | |
966 | } | |
da9bb1d2 | 967 | |
4275be63 | 968 | static void edac_ce_error(struct mem_ctl_info *mci, |
9eb07a7f | 969 | const u16 error_count, |
4275be63 MCC |
970 | const int pos[EDAC_MAX_LAYERS], |
971 | const char *msg, | |
972 | const char *location, | |
973 | const char *label, | |
974 | const char *detail, | |
975 | const char *other_detail, | |
976 | const bool enable_per_layer_report, | |
977 | const unsigned long page_frame_number, | |
978 | const unsigned long offset_in_page, | |
53f2d028 | 979 | long grain) |
4275be63 MCC |
980 | { |
981 | unsigned long remapped_page; | |
f430d570 BP |
982 | char *msg_aux = ""; |
983 | ||
984 | if (*msg) | |
985 | msg_aux = " "; | |
4275be63 MCC |
986 | |
987 | if (edac_mc_get_log_ce()) { | |
988 | if (other_detail && *other_detail) | |
989 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
990 | "%d CE %s%son %s (%s %s - %s)\n", |
991 | error_count, msg, msg_aux, label, | |
992 | location, detail, other_detail); | |
4275be63 MCC |
993 | else |
994 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
995 | "%d CE %s%son %s (%s %s)\n", |
996 | error_count, msg, msg_aux, label, | |
997 | location, detail); | |
4275be63 | 998 | } |
9eb07a7f | 999 | edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count); |
da9bb1d2 | 1000 | |
aa2064d7 | 1001 | if (mci->scrub_mode == SCRUB_SW_SRC) { |
da9bb1d2 | 1002 | /* |
4275be63 MCC |
1003 | * Some memory controllers (called MCs below) can remap |
1004 | * memory so that it is still available at a different | |
1005 | * address when PCI devices map into memory. | |
1006 | * MC's that can't do this, lose the memory where PCI | |
1007 | * devices are mapped. This mapping is MC-dependent | |
1008 | * and so we call back into the MC driver for it to | |
1009 | * map the MC page to a physical (CPU) page which can | |
1010 | * then be mapped to a virtual page - which can then | |
1011 | * be scrubbed. | |
1012 | */ | |
da9bb1d2 | 1013 | remapped_page = mci->ctl_page_to_phys ? |
052dfb45 DT |
1014 | mci->ctl_page_to_phys(mci, page_frame_number) : |
1015 | page_frame_number; | |
da9bb1d2 | 1016 | |
4275be63 MCC |
1017 | edac_mc_scrub_block(remapped_page, |
1018 | offset_in_page, grain); | |
da9bb1d2 AC |
1019 | } |
1020 | } | |
1021 | ||
4275be63 | 1022 | static void edac_ue_error(struct mem_ctl_info *mci, |
9eb07a7f | 1023 | const u16 error_count, |
4275be63 MCC |
1024 | const int pos[EDAC_MAX_LAYERS], |
1025 | const char *msg, | |
1026 | const char *location, | |
1027 | const char *label, | |
1028 | const char *detail, | |
1029 | const char *other_detail, | |
1030 | const bool enable_per_layer_report) | |
da9bb1d2 | 1031 | { |
f430d570 BP |
1032 | char *msg_aux = ""; |
1033 | ||
1034 | if (*msg) | |
1035 | msg_aux = " "; | |
1036 | ||
4275be63 MCC |
1037 | if (edac_mc_get_log_ue()) { |
1038 | if (other_detail && *other_detail) | |
1039 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
1040 | "%d UE %s%son %s (%s %s - %s)\n", |
1041 | error_count, msg, msg_aux, label, | |
1042 | location, detail, other_detail); | |
4275be63 MCC |
1043 | else |
1044 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
1045 | "%d UE %s%son %s (%s %s)\n", |
1046 | error_count, msg, msg_aux, label, | |
1047 | location, detail); | |
4275be63 | 1048 | } |
e7ecd891 | 1049 | |
4275be63 MCC |
1050 | if (edac_mc_get_panic_on_ue()) { |
1051 | if (other_detail && *other_detail) | |
f430d570 BP |
1052 | panic("UE %s%son %s (%s%s - %s)\n", |
1053 | msg, msg_aux, label, location, detail, other_detail); | |
4275be63 | 1054 | else |
f430d570 BP |
1055 | panic("UE %s%son %s (%s%s)\n", |
1056 | msg, msg_aux, label, location, detail); | |
4275be63 MCC |
1057 | } |
1058 | ||
9eb07a7f | 1059 | edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count); |
da9bb1d2 AC |
1060 | } |
1061 | ||
e7e24830 MCC |
1062 | void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, |
1063 | struct mem_ctl_info *mci, | |
1064 | struct edac_raw_error_desc *e) | |
1065 | { | |
1066 | char detail[80]; | |
1067 | int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; | |
1068 | ||
1069 | /* Memory type dependent details about the error */ | |
1070 | if (type == HW_EVENT_ERR_CORRECTED) { | |
1071 | snprintf(detail, sizeof(detail), | |
1072 | "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", | |
1073 | e->page_frame_number, e->offset_in_page, | |
1074 | e->grain, e->syndrome); | |
1075 | edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label, | |
1076 | detail, e->other_detail, e->enable_per_layer_report, | |
1077 | e->page_frame_number, e->offset_in_page, e->grain); | |
1078 | } else { | |
1079 | snprintf(detail, sizeof(detail), | |
1080 | "page:0x%lx offset:0x%lx grain:%ld", | |
1081 | e->page_frame_number, e->offset_in_page, e->grain); | |
1082 | ||
1083 | edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label, | |
1084 | detail, e->other_detail, e->enable_per_layer_report); | |
1085 | } | |
1086 | ||
1087 | ||
1088 | } | |
1089 | EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error); | |
53f2d028 | 1090 | |
4275be63 MCC |
1091 | void edac_mc_handle_error(const enum hw_event_mc_err_type type, |
1092 | struct mem_ctl_info *mci, | |
9eb07a7f | 1093 | const u16 error_count, |
4275be63 MCC |
1094 | const unsigned long page_frame_number, |
1095 | const unsigned long offset_in_page, | |
1096 | const unsigned long syndrome, | |
53f2d028 MCC |
1097 | const int top_layer, |
1098 | const int mid_layer, | |
1099 | const int low_layer, | |
4275be63 | 1100 | const char *msg, |
03f7eae8 | 1101 | const char *other_detail) |
da9bb1d2 | 1102 | { |
4275be63 MCC |
1103 | char *p; |
1104 | int row = -1, chan = -1; | |
53f2d028 | 1105 | int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; |
c7ef7645 | 1106 | int i, n_labels = 0; |
53f2d028 | 1107 | u8 grain_bits; |
c7ef7645 | 1108 | struct edac_raw_error_desc *e = &mci->error_desc; |
da9bb1d2 | 1109 | |
956b9ba1 | 1110 | edac_dbg(3, "MC%d\n", mci->mc_idx); |
da9bb1d2 | 1111 | |
c7ef7645 MCC |
1112 | /* Fills the error report buffer */ |
1113 | memset(e, 0, sizeof (*e)); | |
1114 | e->error_count = error_count; | |
1115 | e->top_layer = top_layer; | |
1116 | e->mid_layer = mid_layer; | |
1117 | e->low_layer = low_layer; | |
1118 | e->page_frame_number = page_frame_number; | |
1119 | e->offset_in_page = offset_in_page; | |
1120 | e->syndrome = syndrome; | |
1121 | e->msg = msg; | |
1122 | e->other_detail = other_detail; | |
1123 | ||
4275be63 MCC |
1124 | /* |
1125 | * Check if the event report is consistent and if the memory | |
1126 | * location is known. If it is known, enable_per_layer_report will be | |
1127 | * true, the DIMM(s) label info will be filled and the per-layer | |
1128 | * error counters will be incremented. | |
1129 | */ | |
1130 | for (i = 0; i < mci->n_layers; i++) { | |
1131 | if (pos[i] >= (int)mci->layers[i].size) { | |
4275be63 MCC |
1132 | |
1133 | edac_mc_printk(mci, KERN_ERR, | |
1134 | "INTERNAL ERROR: %s value is out of range (%d >= %d)\n", | |
1135 | edac_layer_name[mci->layers[i].type], | |
1136 | pos[i], mci->layers[i].size); | |
1137 | /* | |
1138 | * Instead of just returning it, let's use what's | |
1139 | * known about the error. The increment routines and | |
1140 | * the DIMM filter logic will do the right thing by | |
1141 | * pointing the likely damaged DIMMs. | |
1142 | */ | |
1143 | pos[i] = -1; | |
1144 | } | |
1145 | if (pos[i] >= 0) | |
c7ef7645 | 1146 | e->enable_per_layer_report = true; |
da9bb1d2 AC |
1147 | } |
1148 | ||
4275be63 MCC |
1149 | /* |
1150 | * Get the dimm label/grain that applies to the match criteria. | |
1151 | * As the error algorithm may not be able to point to just one memory | |
1152 | * stick, the logic here will get all possible labels that could | |
1153 | * pottentially be affected by the error. | |
1154 | * On FB-DIMM memory controllers, for uncorrected errors, it is common | |
1155 | * to have only the MC channel and the MC dimm (also called "branch") | |
1156 | * but the channel is not known, as the memory is arranged in pairs, | |
1157 | * where each memory belongs to a separate channel within the same | |
1158 | * branch. | |
1159 | */ | |
c7ef7645 | 1160 | p = e->label; |
4275be63 | 1161 | *p = '\0'; |
4da1b7bf | 1162 | |
4275be63 | 1163 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1164 | struct dimm_info *dimm = mci->dimms[i]; |
da9bb1d2 | 1165 | |
53f2d028 | 1166 | if (top_layer >= 0 && top_layer != dimm->location[0]) |
4275be63 | 1167 | continue; |
53f2d028 | 1168 | if (mid_layer >= 0 && mid_layer != dimm->location[1]) |
4275be63 | 1169 | continue; |
53f2d028 | 1170 | if (low_layer >= 0 && low_layer != dimm->location[2]) |
4275be63 | 1171 | continue; |
da9bb1d2 | 1172 | |
4275be63 | 1173 | /* get the max grain, over the error match range */ |
c7ef7645 MCC |
1174 | if (dimm->grain > e->grain) |
1175 | e->grain = dimm->grain; | |
9794f33d | 1176 | |
4275be63 MCC |
1177 | /* |
1178 | * If the error is memory-controller wide, there's no need to | |
1179 | * seek for the affected DIMMs because the whole | |
1180 | * channel/memory controller/... may be affected. | |
1181 | * Also, don't show errors for empty DIMM slots. | |
1182 | */ | |
c7ef7645 MCC |
1183 | if (e->enable_per_layer_report && dimm->nr_pages) { |
1184 | if (n_labels >= EDAC_MAX_LABELS) { | |
1185 | e->enable_per_layer_report = false; | |
1186 | break; | |
1187 | } | |
1188 | n_labels++; | |
1189 | if (p != e->label) { | |
4275be63 MCC |
1190 | strcpy(p, OTHER_LABEL); |
1191 | p += strlen(OTHER_LABEL); | |
1192 | } | |
1193 | strcpy(p, dimm->label); | |
1194 | p += strlen(p); | |
1195 | *p = '\0'; | |
1196 | ||
1197 | /* | |
1198 | * get csrow/channel of the DIMM, in order to allow | |
1199 | * incrementing the compat API counters | |
1200 | */ | |
956b9ba1 | 1201 | edac_dbg(4, "%s csrows map: (%d,%d)\n", |
9713faec | 1202 | mci->csbased ? "rank" : "dimm", |
956b9ba1 | 1203 | dimm->csrow, dimm->cschannel); |
4275be63 MCC |
1204 | if (row == -1) |
1205 | row = dimm->csrow; | |
1206 | else if (row >= 0 && row != dimm->csrow) | |
1207 | row = -2; | |
1208 | ||
1209 | if (chan == -1) | |
1210 | chan = dimm->cschannel; | |
1211 | else if (chan >= 0 && chan != dimm->cschannel) | |
1212 | chan = -2; | |
1213 | } | |
9794f33d | 1214 | } |
1215 | ||
c7ef7645 MCC |
1216 | if (!e->enable_per_layer_report) { |
1217 | strcpy(e->label, "any memory"); | |
4275be63 | 1218 | } else { |
956b9ba1 | 1219 | edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); |
c7ef7645 MCC |
1220 | if (p == e->label) |
1221 | strcpy(e->label, "unknown memory"); | |
4275be63 MCC |
1222 | if (type == HW_EVENT_ERR_CORRECTED) { |
1223 | if (row >= 0) { | |
9eb07a7f | 1224 | mci->csrows[row]->ce_count += error_count; |
4275be63 | 1225 | if (chan >= 0) |
9eb07a7f | 1226 | mci->csrows[row]->channels[chan]->ce_count += error_count; |
4275be63 MCC |
1227 | } |
1228 | } else | |
1229 | if (row >= 0) | |
9eb07a7f | 1230 | mci->csrows[row]->ue_count += error_count; |
9794f33d | 1231 | } |
1232 | ||
4275be63 | 1233 | /* Fill the RAM location data */ |
c7ef7645 | 1234 | p = e->location; |
4da1b7bf | 1235 | |
4275be63 MCC |
1236 | for (i = 0; i < mci->n_layers; i++) { |
1237 | if (pos[i] < 0) | |
1238 | continue; | |
9794f33d | 1239 | |
4275be63 MCC |
1240 | p += sprintf(p, "%s:%d ", |
1241 | edac_layer_name[mci->layers[i].type], | |
1242 | pos[i]); | |
9794f33d | 1243 | } |
c7ef7645 | 1244 | if (p > e->location) |
53f2d028 MCC |
1245 | *(p - 1) = '\0'; |
1246 | ||
1247 | /* Report the error via the trace interface */ | |
c7ef7645 | 1248 | grain_bits = fls_long(e->grain) + 1; |
be1d1629 BP |
1249 | |
1250 | if (IS_ENABLED(CONFIG_RAS)) | |
1251 | trace_mc_event(type, e->msg, e->label, e->error_count, | |
1252 | mci->mc_idx, e->top_layer, e->mid_layer, | |
1253 | e->low_layer, | |
1254 | (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, | |
1255 | grain_bits, e->syndrome, e->other_detail); | |
a7d7d2e1 | 1256 | |
e7e24830 | 1257 | edac_raw_mc_handle_error(type, mci, e); |
9794f33d | 1258 | } |
4275be63 | 1259 | EXPORT_SYMBOL_GPL(edac_mc_handle_error); |